SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "drm_crtc_helper.h"
  32 #include "drm_fb_helper.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37
  38 /* Really want an OS-independent resettable timer.  Would like to have
  39  * this loop run for (eg) 3 sec, but have the timer reset every time
  40  * the head pointer changes, so that EBUSY only happens if the ring
  41  * actually stalls for (eg) 3 seconds.
  42  */
  43 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
  44 {
  45         drm_i915_private_t *dev_priv = dev->dev_private;
  46         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  47         u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
  48         u32 last_acthd = I915_READ(acthd_reg);
  49         u32 acthd;
  50         u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  51         int i;
  52
  53         trace_i915_ring_wait_begin (dev);
  54
  55         for (i = 0; i < 100000; i++) {
  56                 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  57                 acthd = I915_READ(acthd_reg);
  58                 ring->space = ring->head - (ring->tail + 8);
  59                 if (ring->space < 0)
  60                         ring->space += ring->Size;
  61                 if (ring->space >= n) {
  62                         trace_i915_ring_wait_end (dev);
  63                         return 0;
  64                 }
  65
  66                 if (dev->primary->master) {
  67                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  68                         if (master_priv->sarea_priv)
  69                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
  70                 }
  71
  72
  73                 if (ring->head != last_head)
  74                         i = 0;
  75                 if (acthd != last_acthd)
  76                         i = 0;
  77
  78                 last_head = ring->head;
  79                 last_acthd = acthd;
  80                 msleep_interruptible(10);
  81
  82         }
  83
  84         trace_i915_ring_wait_end (dev);
  85         return -EBUSY;
  86 }
  87
  88 /* As a ringbuffer is only allowed to wrap between instructions, fill
  89  * the tail with NOOPs.
  90  */
  91 int i915_wrap_ring(struct drm_device *dev)
  92 {
  93         drm_i915_private_t *dev_priv = dev->dev_private;
  94         volatile unsigned int *virt;
  95         int rem;
  96
  97         rem = dev_priv->ring.Size - dev_priv->ring.tail;
  98         if (dev_priv->ring.space < rem) {
  99                 int ret = i915_wait_ring(dev, rem, __func__);
 100                 if (ret)
 101                         return ret;
 102         }
 103         dev_priv->ring.space -= rem;
 104
 105         virt = (unsigned int *)
 106                 (dev_priv->ring.virtual_start + dev_priv->ring.tail);
 107         rem /= 4;
 108         while (rem--)
 109                 *virt++ = MI_NOOP;
 110
 111         dev_priv->ring.tail = 0;
 112
 113         return 0;
 114 }
 115
 116 /**
 117  * Sets up the hardware status page for devices that need a physical address
 118  * in the register.
 119  */
 120 static int i915_init_phys_hws(struct drm_device *dev)
 121 {
 122         drm_i915_private_t *dev_priv = dev->dev_private;
 123         /* Program Hardware Status Page */
 124         dev_priv->status_page_dmah =
 125                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
 126
 127         if (!dev_priv->status_page_dmah) {
 128                 DRM_ERROR("Can not allocate hardware status page\n");
 129                 return -ENOMEM;
 130         }
 131         dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
 132         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
 133
 134         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 135
 136         I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
 137         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 138         return 0;
 139 }
 140
 141 /**
 142  * Frees the hardware status page, whether it's a physical address or a virtual
 143  * address set up by the X Server.
 144  */
 145 static void i915_free_hws(struct drm_device *dev)
 146 {
 147         drm_i915_private_t *dev_priv = dev->dev_private;
 148         if (dev_priv->status_page_dmah) {
 149                 drm_pci_free(dev, dev_priv->status_page_dmah);
 150                 dev_priv->status_page_dmah = NULL;
 151         }
 152
 153         if (dev_priv->status_gfx_addr) {
 154                 dev_priv->status_gfx_addr = 0;
 155                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 156         }
 157
 158         /* Need to rewrite hardware status page */
 159         I915_WRITE(HWS_PGA, 0x1ffff000);
 160 }
 161
 162 void i915_kernel_lost_context(struct drm_device * dev)
 163 {
 164         drm_i915_private_t *dev_priv = dev->dev_private;
 165         struct drm_i915_master_private *master_priv;
 166         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
 167
 168         /*
 169          * We should never lose context on the ring with modesetting
 170          * as we don't expose it to userspace
 171          */
 172         if (drm_core_check_feature(dev, DRIVER_MODESET))
 173                 return;
 174
 175         ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 176         ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
 177         ring->space = ring->head - (ring->tail + 8);
 178         if (ring->space < 0)
 179                 ring->space += ring->Size;
 180
 181         if (!dev->primary->master)
 182                 return;
 183
 184         master_priv = dev->primary->master->driver_priv;
 185         if (ring->head == ring->tail && master_priv->sarea_priv)
 186                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 187 }
 188
 189 static int i915_dma_cleanup(struct drm_device * dev)
 190 {
 191         drm_i915_private_t *dev_priv = dev->dev_private;
 192         /* Make sure interrupts are disabled here because the uninstall ioctl
 193          * may not have been called from userspace and after dev_private
 194          * is freed, it's too late.
 195          */
 196         if (dev->irq_enabled)
 197                 drm_irq_uninstall(dev);
 198
 199         if (dev_priv->ring.virtual_start) {
 200                 drm_core_ioremapfree(&dev_priv->ring.map, dev);
 201                 dev_priv->ring.virtual_start = NULL;
 202                 dev_priv->ring.map.handle = NULL;
 203                 dev_priv->ring.map.size = 0;
 204         }
 205
 206         /* Clear the HWS virtual address at teardown */
 207         if (I915_NEED_GFX_HWS(dev))
 208                 i915_free_hws(dev);
 209
 210         return 0;
 211 }
 212
 213 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 214 {
 215         drm_i915_private_t *dev_priv = dev->dev_private;
 216         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 217
 218         master_priv->sarea = drm_getsarea(dev);
 219         if (master_priv->sarea) {
 220                 master_priv->sarea_priv = (drm_i915_sarea_t *)
 221                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
 222         } else {
 223                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
 224         }
 225
 226         if (init->ring_size != 0) {
 227                 if (dev_priv->ring.ring_obj != NULL) {
 228                         i915_dma_cleanup(dev);
 229                         DRM_ERROR("Client tried to initialize ringbuffer in "
 230                                   "GEM mode\n");
 231                         return -EINVAL;
 232                 }
 233
 234                 dev_priv->ring.Size = init->ring_size;
 235
 236                 dev_priv->ring.map.offset = init->ring_start;
 237                 dev_priv->ring.map.size = init->ring_size;
 238                 dev_priv->ring.map.type = 0;
 239                 dev_priv->ring.map.flags = 0;
 240                 dev_priv->ring.map.mtrr = 0;
 241
 242                 drm_core_ioremap_wc(&dev_priv->ring.map, dev);
 243
 244                 if (dev_priv->ring.map.handle == NULL) {
 245                         i915_dma_cleanup(dev);
 246                         DRM_ERROR("can not ioremap virtual address for"
 247                                   " ring buffer\n");
 248                         return -ENOMEM;
 249                 }
 250         }
 251
 252         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 253
 254         dev_priv->cpp = init->cpp;
 255         dev_priv->back_offset = init->back_offset;
 256         dev_priv->front_offset = init->front_offset;
 257         dev_priv->current_page = 0;
 258         if (master_priv->sarea_priv)
 259                 master_priv->sarea_priv->pf_current_page = 0;
 260
 261         /* Allow hardware batchbuffers unless told otherwise.
 262          */
 263         dev_priv->allow_batchbuffer = 1;
 264
 265         return 0;
 266 }
 267
 268 static int i915_dma_resume(struct drm_device * dev)
 269 {
 270         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 271
 272         DRM_DEBUG_DRIVER("%s\n", __func__);
 273
 274         if (dev_priv->ring.map.handle == NULL) {
 275                 DRM_ERROR("can not ioremap virtual address for"
 276                           " ring buffer\n");
 277                 return -ENOMEM;
 278         }
 279
 280         /* Program Hardware Status Page */
 281         if (!dev_priv->hw_status_page) {
 282                 DRM_ERROR("Can not find hardware status page\n");
 283                 return -EINVAL;
 284         }
 285         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 286                                 dev_priv->hw_status_page);
 287
 288         if (dev_priv->status_gfx_addr != 0)
 289                 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
 290         else
 291                 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
 292         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 293
 294         return 0;
 295 }
 296
 297 static int i915_dma_init(struct drm_device *dev, void *data,
 298                          struct drm_file *file_priv)
 299 {
 300         drm_i915_init_t *init = data;
 301         int retcode = 0;
 302
 303         switch (init->func) {
 304         case I915_INIT_DMA:
 305                 retcode = i915_initialize(dev, init);
 306                 break;
 307         case I915_CLEANUP_DMA:
 308                 retcode = i915_dma_cleanup(dev);
 309                 break;
 310         case I915_RESUME_DMA:
 311                 retcode = i915_dma_resume(dev);
 312                 break;
 313         default:
 314                 retcode = -EINVAL;
 315                 break;
 316         }
 317
 318         return retcode;
 319 }
 320
 321 /* Implement basically the same security restrictions as hardware does
 322  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 323  *
 324  * Most of the calculations below involve calculating the size of a
 325  * particular instruction.  It's important to get the size right as
 326  * that tells us where the next instruction to check is.  Any illegal
 327  * instruction detected will be given a size of zero, which is a
 328  * signal to abort the rest of the buffer.
 329  */
 330 static int do_validate_cmd(int cmd)
 331 {
 332         switch (((cmd >> 29) & 0x7)) {
 333         case 0x0:
 334                 switch ((cmd >> 23) & 0x3f) {
 335                 case 0x0:
 336                         return 1;       /* MI_NOOP */
 337                 case 0x4:
 338                         return 1;       /* MI_FLUSH */
 339                 default:
 340                         return 0;       /* disallow everything else */
 341                 }
 342                 break;
 343         case 0x1:
 344                 return 0;       /* reserved */
 345         case 0x2:
 346                 return (cmd & 0xff) + 2;        /* 2d commands */
 347         case 0x3:
 348                 if (((cmd >> 24) & 0x1f) <= 0x18)
 349                         return 1;
 350
 351                 switch ((cmd >> 24) & 0x1f) {
 352                 case 0x1c:
 353                         return 1;
 354                 case 0x1d:
 355                         switch ((cmd >> 16) & 0xff) {
 356                         case 0x3:
 357                                 return (cmd & 0x1f) + 2;
 358                         case 0x4:
 359                                 return (cmd & 0xf) + 2;
 360                         default:
 361                                 return (cmd & 0xffff) + 2;
 362                         }
 363                 case 0x1e:
 364                         if (cmd & (1 << 23))
 365                                 return (cmd & 0xffff) + 1;
 366                         else
 367                                 return 1;
 368                 case 0x1f:
 369                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 370                                 return (cmd & 0x1ffff) + 2;
 371                         else if (cmd & (1 << 17))       /* indirect random */
 372                                 if ((cmd & 0xffff) == 0)
 373                                         return 0;       /* unknown length, too hard */
 374                                 else
 375                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 376                         else
 377                                 return 2;       /* indirect sequential */
 378                 default:
 379                         return 0;
 380                 }
 381         default:
 382                 return 0;
 383         }
 384
 385         return 0;
 386 }
 387
 388 static int validate_cmd(int cmd)
 389 {
 390         int ret = do_validate_cmd(cmd);
 391
 392 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 393
 394         return ret;
 395 }
 396
 397 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 398 {
 399         drm_i915_private_t *dev_priv = dev->dev_private;
 400         int i;
 401         RING_LOCALS;
 402
 403         if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
 404                 return -EINVAL;
 405
 406         BEGIN_LP_RING((dwords+1)&~1);
 407
 408         for (i = 0; i < dwords;) {
 409                 int cmd, sz;
 410
 411                 cmd = buffer[i];
 412
 413                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 414                         return -EINVAL;
 415
 416                 OUT_RING(cmd);
 417
 418                 while (++i, --sz) {
 419                         OUT_RING(buffer[i]);
 420                 }
 421         }
 422
 423         if (dwords & 1)
 424                 OUT_RING(0);
 425
 426         ADVANCE_LP_RING();
 427
 428         return 0;
 429 }
 430
 431 int
 432 i915_emit_box(struct drm_device *dev,
 433               struct drm_clip_rect *boxes,
 434               int i, int DR1, int DR4)
 435 {
 436         drm_i915_private_t *dev_priv = dev->dev_private;
 437         struct drm_clip_rect box = boxes[i];
 438         RING_LOCALS;
 439
 440         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 441                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 442                           box.x1, box.y1, box.x2, box.y2);
 443                 return -EINVAL;
 444         }
 445
 446         if (IS_I965G(dev)) {
 447                 BEGIN_LP_RING(4);
 448                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 449                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 450                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 451                 OUT_RING(DR4);
 452                 ADVANCE_LP_RING();
 453         } else {
 454                 BEGIN_LP_RING(6);
 455                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 456                 OUT_RING(DR1);
 457                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 458                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 459                 OUT_RING(DR4);
 460                 OUT_RING(0);
 461                 ADVANCE_LP_RING();
 462         }
 463
 464         return 0;
 465 }
 466
 467 /* XXX: Emitting the counter should really be moved to part of the IRQ
 468  * emit. For now, do it in both places:
 469  */
 470
 471 static void i915_emit_breadcrumb(struct drm_device *dev)
 472 {
 473         drm_i915_private_t *dev_priv = dev->dev_private;
 474         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 475         RING_LOCALS;
 476
 477         dev_priv->counter++;
 478         if (dev_priv->counter > 0x7FFFFFFFUL)
 479                 dev_priv->counter = 0;
 480         if (master_priv->sarea_priv)
 481                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 482
 483         BEGIN_LP_RING(4);
 484         OUT_RING(MI_STORE_DWORD_INDEX);
 485         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 486         OUT_RING(dev_priv->counter);
 487         OUT_RING(0);
 488         ADVANCE_LP_RING();
 489 }
 490
 491 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 492                                    drm_i915_cmdbuffer_t *cmd,
 493                                    struct drm_clip_rect *cliprects,
 494                                    void *cmdbuf)
 495 {
 496         int nbox = cmd->num_cliprects;
 497         int i = 0, count, ret;
 498
 499         if (cmd->sz & 0x3) {
 500                 DRM_ERROR("alignment");
 501                 return -EINVAL;
 502         }
 503
 504         i915_kernel_lost_context(dev);
 505
 506         count = nbox ? nbox : 1;
 507
 508         for (i = 0; i < count; i++) {
 509                 if (i < nbox) {
 510                         ret = i915_emit_box(dev, cliprects, i,
 511                                             cmd->DR1, cmd->DR4);
 512                         if (ret)
 513                                 return ret;
 514                 }
 515
 516                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 517                 if (ret)
 518                         return ret;
 519         }
 520
 521         i915_emit_breadcrumb(dev);
 522         return 0;
 523 }
 524
 525 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 526                                      drm_i915_batchbuffer_t * batch,
 527                                      struct drm_clip_rect *cliprects)
 528 {
 529         drm_i915_private_t *dev_priv = dev->dev_private;
 530         int nbox = batch->num_cliprects;
 531         int i = 0, count;
 532         RING_LOCALS;
 533
 534         if ((batch->start | batch->used) & 0x7) {
 535                 DRM_ERROR("alignment");
 536                 return -EINVAL;
 537         }
 538
 539         i915_kernel_lost_context(dev);
 540
 541         count = nbox ? nbox : 1;
 542
 543         for (i = 0; i < count; i++) {
 544                 if (i < nbox) {
 545                         int ret = i915_emit_box(dev, cliprects, i,
 546                                                 batch->DR1, batch->DR4);
 547                         if (ret)
 548                                 return ret;
 549                 }
 550
 551                 if (!IS_I830(dev) && !IS_845G(dev)) {
 552                         BEGIN_LP_RING(2);
 553                         if (IS_I965G(dev)) {
 554                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 555                                 OUT_RING(batch->start);
 556                         } else {
 557                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 558                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 559                         }
 560                         ADVANCE_LP_RING();
 561                 } else {
 562                         BEGIN_LP_RING(4);
 563                         OUT_RING(MI_BATCH_BUFFER);
 564                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 565                         OUT_RING(batch->start + batch->used - 4);
 566                         OUT_RING(0);
 567                         ADVANCE_LP_RING();
 568                 }
 569         }
 570
 571         i915_emit_breadcrumb(dev);
 572
 573         return 0;
 574 }
 575
 576 static int i915_dispatch_flip(struct drm_device * dev)
 577 {
 578         drm_i915_private_t *dev_priv = dev->dev_private;
 579         struct drm_i915_master_private *master_priv =
 580                 dev->primary->master->driver_priv;
 581         RING_LOCALS;
 582
 583         if (!master_priv->sarea_priv)
 584                 return -EINVAL;
 585
 586         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 587                           __func__,
 588                          dev_priv->current_page,
 589                          master_priv->sarea_priv->pf_current_page);
 590
 591         i915_kernel_lost_context(dev);
 592
 593         BEGIN_LP_RING(2);
 594         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 595         OUT_RING(0);
 596         ADVANCE_LP_RING();
 597
 598         BEGIN_LP_RING(6);
 599         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 600         OUT_RING(0);
 601         if (dev_priv->current_page == 0) {
 602                 OUT_RING(dev_priv->back_offset);
 603                 dev_priv->current_page = 1;
 604         } else {
 605                 OUT_RING(dev_priv->front_offset);
 606                 dev_priv->current_page = 0;
 607         }
 608         OUT_RING(0);
 609         ADVANCE_LP_RING();
 610
 611         BEGIN_LP_RING(2);
 612         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 613         OUT_RING(0);
 614         ADVANCE_LP_RING();
 615
 616         master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
 617
 618         BEGIN_LP_RING(4);
 619         OUT_RING(MI_STORE_DWORD_INDEX);
 620         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 621         OUT_RING(dev_priv->counter);
 622         OUT_RING(0);
 623         ADVANCE_LP_RING();
 624
 625         master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 626         return 0;
 627 }
 628
 629 static int i915_quiescent(struct drm_device * dev)
 630 {
 631         drm_i915_private_t *dev_priv = dev->dev_private;
 632
 633         i915_kernel_lost_context(dev);
 634         return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
 635 }
 636
 637 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 638                             struct drm_file *file_priv)
 639 {
 640         int ret;
 641
 642         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 643
 644         mutex_lock(&dev->struct_mutex);
 645         ret = i915_quiescent(dev);
 646         mutex_unlock(&dev->struct_mutex);
 647
 648         return ret;
 649 }
 650
 651 static int i915_batchbuffer(struct drm_device *dev, void *data,
 652                             struct drm_file *file_priv)
 653 {
 654         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 655         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 656         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 657             master_priv->sarea_priv;
 658         drm_i915_batchbuffer_t *batch = data;
 659         int ret;
 660         struct drm_clip_rect *cliprects = NULL;
 661
 662         if (!dev_priv->allow_batchbuffer) {
 663                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 664                 return -EINVAL;
 665         }
 666
 667         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 668                         batch->start, batch->used, batch->num_cliprects);
 669
 670         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 671
 672         if (batch->num_cliprects < 0)
 673                 return -EINVAL;
 674
 675         if (batch->num_cliprects) {
 676                 cliprects = kcalloc(batch->num_cliprects,
 677                                     sizeof(struct drm_clip_rect),
 678                                     GFP_KERNEL);
 679                 if (cliprects == NULL)
 680                         return -ENOMEM;
 681
 682                 ret = copy_from_user(cliprects, batch->cliprects,
 683                                      batch->num_cliprects *
 684                                      sizeof(struct drm_clip_rect));
 685                 if (ret != 0)
 686                         goto fail_free;
 687         }
 688
 689         mutex_lock(&dev->struct_mutex);
 690         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 691         mutex_unlock(&dev->struct_mutex);
 692
 693         if (sarea_priv)
 694                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 695
 696 fail_free:
 697         kfree(cliprects);
 698
 699         return ret;
 700 }
 701
 702 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 703                           struct drm_file *file_priv)
 704 {
 705         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 706         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 707         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 708             master_priv->sarea_priv;
 709         drm_i915_cmdbuffer_t *cmdbuf = data;
 710         struct drm_clip_rect *cliprects = NULL;
 711         void *batch_data;
 712         int ret;
 713
 714         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 715                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 716
 717         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 718
 719         if (cmdbuf->num_cliprects < 0)
 720                 return -EINVAL;
 721
 722         batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
 723         if (batch_data == NULL)
 724                 return -ENOMEM;
 725
 726         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 727         if (ret != 0)
 728                 goto fail_batch_free;
 729
 730         if (cmdbuf->num_cliprects) {
 731                 cliprects = kcalloc(cmdbuf->num_cliprects,
 732                                     sizeof(struct drm_clip_rect), GFP_KERNEL);
 733                 if (cliprects == NULL)
 734                         goto fail_batch_free;
 735
 736                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 737                                      cmdbuf->num_cliprects *
 738                                      sizeof(struct drm_clip_rect));
 739                 if (ret != 0)
 740                         goto fail_clip_free;
 741         }
 742
 743         mutex_lock(&dev->struct_mutex);
 744         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 745         mutex_unlock(&dev->struct_mutex);
 746         if (ret) {
 747                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 748                 goto fail_clip_free;
 749         }
 750
 751         if (sarea_priv)
 752                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 753
 754 fail_clip_free:
 755         kfree(cliprects);
 756 fail_batch_free:
 757         kfree(batch_data);
 758
 759         return ret;
 760 }
 761
 762 static int i915_flip_bufs(struct drm_device *dev, void *data,
 763                           struct drm_file *file_priv)
 764 {
 765         int ret;
 766
 767         DRM_DEBUG_DRIVER("%s\n", __func__);
 768
 769         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 770
 771         mutex_lock(&dev->struct_mutex);
 772         ret = i915_dispatch_flip(dev);
 773         mutex_unlock(&dev->struct_mutex);
 774
 775         return ret;
 776 }
 777
 778 static int i915_getparam(struct drm_device *dev, void *data,
 779                          struct drm_file *file_priv)
 780 {
 781         drm_i915_private_t *dev_priv = dev->dev_private;
 782         drm_i915_getparam_t *param = data;
 783         int value;
 784
 785         if (!dev_priv) {
 786                 DRM_ERROR("called with no initialization\n");
 787                 return -EINVAL;
 788         }
 789
 790         switch (param->param) {
 791         case I915_PARAM_IRQ_ACTIVE:
 792                 value = dev->pdev->irq ? 1 : 0;
 793                 break;
 794         case I915_PARAM_ALLOW_BATCHBUFFER:
 795                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 796                 break;
 797         case I915_PARAM_LAST_DISPATCH:
 798                 value = READ_BREADCRUMB(dev_priv);
 799                 break;
 800         case I915_PARAM_CHIPSET_ID:
 801                 value = dev->pci_device;
 802                 break;
 803         case I915_PARAM_HAS_GEM:
 804                 value = dev_priv->has_gem;
 805                 break;
 806         case I915_PARAM_NUM_FENCES_AVAIL:
 807                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 808                 break;
 809         default:
 810                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 811                                         param->param);
 812                 return -EINVAL;
 813         }
 814
 815         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 816                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 817                 return -EFAULT;
 818         }
 819
 820         return 0;
 821 }
 822
 823 static int i915_setparam(struct drm_device *dev, void *data,
 824                          struct drm_file *file_priv)
 825 {
 826         drm_i915_private_t *dev_priv = dev->dev_private;
 827         drm_i915_setparam_t *param = data;
 828
 829         if (!dev_priv) {
 830                 DRM_ERROR("called with no initialization\n");
 831                 return -EINVAL;
 832         }
 833
 834         switch (param->param) {
 835         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 836                 break;
 837         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 838                 dev_priv->tex_lru_log_granularity = param->value;
 839                 break;
 840         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 841                 dev_priv->allow_batchbuffer = param->value;
 842                 break;
 843         case I915_SETPARAM_NUM_USED_FENCES:
 844                 if (param->value > dev_priv->num_fence_regs ||
 845                     param->value < 0)
 846                         return -EINVAL;
 847                 /* Userspace can use first N regs */
 848                 dev_priv->fence_reg_start = param->value;
 849                 break;
 850         default:
 851                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
 852                                         param->param);
 853                 return -EINVAL;
 854         }
 855
 856         return 0;
 857 }
 858
 859 static int i915_set_status_page(struct drm_device *dev, void *data,
 860                                 struct drm_file *file_priv)
 861 {
 862         drm_i915_private_t *dev_priv = dev->dev_private;
 863         drm_i915_hws_addr_t *hws = data;
 864
 865         if (!I915_NEED_GFX_HWS(dev))
 866                 return -EINVAL;
 867
 868         if (!dev_priv) {
 869                 DRM_ERROR("called with no initialization\n");
 870                 return -EINVAL;
 871         }
 872
 873         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 874                 WARN(1, "tried to set status page when mode setting active\n");
 875                 return 0;
 876         }
 877
 878         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
 879
 880         dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
 881
 882         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
 883         dev_priv->hws_map.size = 4*1024;
 884         dev_priv->hws_map.type = 0;
 885         dev_priv->hws_map.flags = 0;
 886         dev_priv->hws_map.mtrr = 0;
 887
 888         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
 889         if (dev_priv->hws_map.handle == NULL) {
 890                 i915_dma_cleanup(dev);
 891                 dev_priv->status_gfx_addr = 0;
 892                 DRM_ERROR("can not ioremap virtual address for"
 893                                 " G33 hw status page\n");
 894                 return -ENOMEM;
 895         }
 896         dev_priv->hw_status_page = dev_priv->hws_map.handle;
 897
 898         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 899         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
 900         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
 901                                 dev_priv->status_gfx_addr);
 902         DRM_DEBUG_DRIVER("load hws at %p\n",
 903                                 dev_priv->hw_status_page);
 904         return 0;
 905 }
 906
 907 static int i915_get_bridge_dev(struct drm_device *dev)
 908 {
 909         struct drm_i915_private *dev_priv = dev->dev_private;
 910
 911         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
 912         if (!dev_priv->bridge_dev) {
 913                 DRM_ERROR("bridge device not found\n");
 914                 return -1;
 915         }
 916         return 0;
 917 }
 918
 919 /**
 920  * i915_probe_agp - get AGP bootup configuration
 921  * @pdev: PCI device
 922  * @aperture_size: returns AGP aperture configured size
 923  * @preallocated_size: returns size of BIOS preallocated AGP space
 924  *
 925  * Since Intel integrated graphics are UMA, the BIOS has to set aside
 926  * some RAM for the framebuffer at early boot.  This code figures out
 927  * how much was set aside so we can use it for our own purposes.
 928  */
 929 static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
 930                           uint32_t *preallocated_size,
 931                           uint32_t *start)
 932 {
 933         struct drm_i915_private *dev_priv = dev->dev_private;
 934         u16 tmp = 0;
 935         unsigned long overhead;
 936         unsigned long stolen;
 937
 938         /* Get the fb aperture size and "stolen" memory amount. */
 939         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp);
 940
 941         *aperture_size = 1024 * 1024;
 942         *preallocated_size = 1024 * 1024;
 943
 944         switch (dev->pdev->device) {
 945         case PCI_DEVICE_ID_INTEL_82830_CGC:
 946         case PCI_DEVICE_ID_INTEL_82845G_IG:
 947         case PCI_DEVICE_ID_INTEL_82855GM_IG:
 948         case PCI_DEVICE_ID_INTEL_82865_IG:
 949                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
 950                         *aperture_size *= 64;
 951                 else
 952                         *aperture_size *= 128;
 953                 break;
 954         default:
 955                 /* 9xx supports large sizes, just look at the length */
 956                 *aperture_size = pci_resource_len(dev->pdev, 2);
 957                 break;
 958         }
 959
 960         /*
 961          * Some of the preallocated space is taken by the GTT
 962          * and popup.  GTT is 1K per MB of aperture size, and popup is 4K.
 963          */
 964         if (IS_G4X(dev) || IS_IGD(dev) || IS_IGDNG(dev))
 965                 overhead = 4096;
 966         else
 967                 overhead = (*aperture_size / 1024) + 4096;
 968
 969         switch (tmp & INTEL_GMCH_GMS_MASK) {
 970         case INTEL_855_GMCH_GMS_DISABLED:
 971                 DRM_ERROR("video memory is disabled\n");
 972                 return -1;
 973         case INTEL_855_GMCH_GMS_STOLEN_1M:
 974                 stolen = 1 * 1024 * 1024;
 975                 break;
 976         case INTEL_855_GMCH_GMS_STOLEN_4M:
 977                 stolen = 4 * 1024 * 1024;
 978                 break;
 979         case INTEL_855_GMCH_GMS_STOLEN_8M:
 980                 stolen = 8 * 1024 * 1024;
 981                 break;
 982         case INTEL_855_GMCH_GMS_STOLEN_16M:
 983                 stolen = 16 * 1024 * 1024;
 984                 break;
 985         case INTEL_855_GMCH_GMS_STOLEN_32M:
 986                 stolen = 32 * 1024 * 1024;
 987                 break;
 988         case INTEL_915G_GMCH_GMS_STOLEN_48M:
 989                 stolen = 48 * 1024 * 1024;
 990                 break;
 991         case INTEL_915G_GMCH_GMS_STOLEN_64M:
 992                 stolen = 64 * 1024 * 1024;
 993                 break;
 994         case INTEL_GMCH_GMS_STOLEN_128M:
 995                 stolen = 128 * 1024 * 1024;
 996                 break;
 997         case INTEL_GMCH_GMS_STOLEN_256M:
 998                 stolen = 256 * 1024 * 1024;
 999                 break;
1000         case INTEL_GMCH_GMS_STOLEN_96M:
1001                 stolen = 96 * 1024 * 1024;
1002                 break;
1003         case INTEL_GMCH_GMS_STOLEN_160M:
1004                 stolen = 160 * 1024 * 1024;
1005                 break;
1006         case INTEL_GMCH_GMS_STOLEN_224M:
1007                 stolen = 224 * 1024 * 1024;
1008                 break;
1009         case INTEL_GMCH_GMS_STOLEN_352M:
1010                 stolen = 352 * 1024 * 1024;
1011                 break;
1012         default:
1013                 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1014                         tmp & INTEL_GMCH_GMS_MASK);
1015                 return -1;
1016         }
1017         *preallocated_size = stolen - overhead;
1018         *start = overhead;
1019
1020         return 0;
1021 }
1022
1023 #define PTE_ADDRESS_MASK                0xfffff000
1024 #define PTE_ADDRESS_MASK_HIGH           0x000000f0 /* i915+ */
1025 #define PTE_MAPPING_TYPE_UNCACHED       (0 << 1)
1026 #define PTE_MAPPING_TYPE_DCACHE         (1 << 1) /* i830 only */
1027 #define PTE_MAPPING_TYPE_CACHED         (3 << 1)
1028 #define PTE_MAPPING_TYPE_MASK           (3 << 1)
1029 #define PTE_VALID                       (1 << 0)
1030
1031 /**
1032  * i915_gtt_to_phys - take a GTT address and turn it into a physical one
1033  * @dev: drm device
1034  * @gtt_addr: address to translate
1035  *
1036  * Some chip functions require allocations from stolen space but need the
1037  * physical address of the memory in question.  We use this routine
1038  * to get a physical address suitable for register programming from a given
1039  * GTT address.
1040  */
1041 static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1042                                       unsigned long gtt_addr)
1043 {
1044         unsigned long *gtt;
1045         unsigned long entry, phys;
1046         int gtt_bar = IS_I9XX(dev) ? 0 : 1;
1047         int gtt_offset, gtt_size;
1048
1049         if (IS_I965G(dev)) {
1050                 if (IS_G4X(dev) || IS_IGDNG(dev)) {
1051                         gtt_offset = 2*1024*1024;
1052                         gtt_size = 2*1024*1024;
1053                 } else {
1054                         gtt_offset = 512*1024;
1055                         gtt_size = 512*1024;
1056                 }
1057         } else {
1058                 gtt_bar = 3;
1059                 gtt_offset = 0;
1060                 gtt_size = pci_resource_len(dev->pdev, gtt_bar);
1061         }
1062
1063         gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
1064                          gtt_size);
1065         if (!gtt) {
1066                 DRM_ERROR("ioremap of GTT failed\n");
1067                 return 0;
1068         }
1069
1070         entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
1071
1072         DRM_DEBUG("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
1073
1074         /* Mask out these reserved bits on this hardware. */
1075         if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) ||
1076             IS_I945G(dev) || IS_I945GM(dev)) {
1077                 entry &= ~PTE_ADDRESS_MASK_HIGH;
1078         }
1079
1080         /* If it's not a mapping type we know, then bail. */
1081         if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
1082             (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) {
1083                 iounmap(gtt);
1084                 return 0;
1085         }
1086
1087         if (!(entry & PTE_VALID)) {
1088                 DRM_ERROR("bad GTT entry in stolen space\n");
1089                 iounmap(gtt);
1090                 return 0;
1091         }
1092
1093         iounmap(gtt);
1094
1095         phys =(entry & PTE_ADDRESS_MASK) |
1096                 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
1097
1098         DRM_DEBUG("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
1099
1100         return phys;
1101 }
1102
1103 static void i915_warn_stolen(struct drm_device *dev)
1104 {
1105         DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1106         DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1107 }
1108
1109 static void i915_setup_compression(struct drm_device *dev, int size)
1110 {
1111         struct drm_i915_private *dev_priv = dev->dev_private;
1112         struct drm_mm_node *compressed_fb, *compressed_llb;
1113         unsigned long cfb_base, ll_base;
1114
1115         /* Leave 1M for line length buffer & misc. */
1116         compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);
1117         if (!compressed_fb) {
1118                 i915_warn_stolen(dev);
1119                 return;
1120         }
1121
1122         compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1123         if (!compressed_fb) {
1124                 i915_warn_stolen(dev);
1125                 return;
1126         }
1127
1128         cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
1129         if (!cfb_base) {
1130                 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1131                 drm_mm_put_block(compressed_fb);
1132         }
1133
1134         if (!IS_GM45(dev)) {
1135                 compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096,
1136                                                     4096, 0);
1137                 if (!compressed_llb) {
1138                         i915_warn_stolen(dev);
1139                         return;
1140                 }
1141
1142                 compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
1143                 if (!compressed_llb) {
1144                         i915_warn_stolen(dev);
1145                         return;
1146                 }
1147
1148                 ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
1149                 if (!ll_base) {
1150                         DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1151                         drm_mm_put_block(compressed_fb);
1152                         drm_mm_put_block(compressed_llb);
1153                 }
1154         }
1155
1156         dev_priv->cfb_size = size;
1157
1158         if (IS_GM45(dev)) {
1159                 g4x_disable_fbc(dev);
1160                 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1161         } else {
1162                 i8xx_disable_fbc(dev);
1163                 I915_WRITE(FBC_CFB_BASE, cfb_base);
1164                 I915_WRITE(FBC_LL_BASE, ll_base);
1165         }
1166
1167         DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
1168                   ll_base, size >> 20);
1169 }
1170
1171 static int i915_load_modeset_init(struct drm_device *dev,
1172                                   unsigned long prealloc_start,
1173                                   unsigned long prealloc_size,
1174                                   unsigned long agp_size)
1175 {
1176         struct drm_i915_private *dev_priv = dev->dev_private;
1177         int fb_bar = IS_I9XX(dev) ? 2 : 0;
1178         int ret = 0;
1179
1180         dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) &
1181                 0xff000000;
1182
1183         if (IS_MOBILE(dev) || IS_I9XX(dev))
1184                 dev_priv->cursor_needs_physical = true;
1185         else
1186                 dev_priv->cursor_needs_physical = false;
1187
1188         if (IS_I965G(dev) || IS_G33(dev))
1189                 dev_priv->cursor_needs_physical = false;
1190
1191         /* Basic memrange allocator for stolen space (aka vram) */
1192         drm_mm_init(&dev_priv->vram, 0, prealloc_size);
1193         DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
1194
1195         /* We're off and running w/KMS */
1196         dev_priv->mm.suspended = 0;
1197
1198         /* Let GEM Manage from end of prealloc space to end of aperture.
1199          *
1200          * However, leave one page at the end still bound to the scratch page.
1201          * There are a number of places where the hardware apparently
1202          * prefetches past the end of the object, and we've seen multiple
1203          * hangs with the GPU head pointer stuck in a batchbuffer bound
1204          * at the last page of the aperture.  One page should be enough to
1205          * keep any prefetching inside of the aperture.
1206          */
1207         i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
1208
1209         mutex_lock(&dev->struct_mutex);
1210         ret = i915_gem_init_ringbuffer(dev);
1211         mutex_unlock(&dev->struct_mutex);
1212         if (ret)
1213                 goto out;
1214
1215         /* Try to set up FBC with a reasonable compressed buffer size */
1216         if (IS_MOBILE(dev) && (IS_I9XX(dev) || IS_I965G(dev) || IS_GM45(dev)) &&
1217             i915_powersave) {
1218                 int cfb_size;
1219
1220                 /* Try to get an 8M buffer... */
1221                 if (prealloc_size > (9*1024*1024))
1222                         cfb_size = 8*1024*1024;
1223                 else /* fall back to 7/8 of the stolen space */
1224                         cfb_size = prealloc_size * 7 / 8;
1225                 i915_setup_compression(dev, cfb_size);
1226         }
1227
1228         /* Allow hardware batchbuffers unless told otherwise.
1229          */
1230         dev_priv->allow_batchbuffer = 1;
1231
1232         ret = intel_init_bios(dev);
1233         if (ret)
1234                 DRM_INFO("failed to find VBIOS tables\n");
1235
1236         ret = drm_irq_install(dev);
1237         if (ret)
1238                 goto destroy_ringbuffer;
1239
1240         /* Always safe in the mode setting case. */
1241         /* FIXME: do pre/post-mode set stuff in core KMS code */
1242         dev->vblank_disable_allowed = 1;
1243
1244         /*
1245          * Initialize the hardware status page IRQ location.
1246          */
1247
1248         I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
1249
1250         intel_modeset_init(dev);
1251
1252         drm_helper_initial_config(dev);
1253
1254         return 0;
1255
1256 destroy_ringbuffer:
1257         i915_gem_cleanup_ringbuffer(dev);
1258 out:
1259         return ret;
1260 }
1261
1262 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1263 {
1264         struct drm_i915_master_private *master_priv;
1265
1266         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1267         if (!master_priv)
1268                 return -ENOMEM;
1269
1270         master->driver_priv = master_priv;
1271         return 0;
1272 }
1273
1274 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1275 {
1276         struct drm_i915_master_private *master_priv = master->driver_priv;
1277
1278         if (!master_priv)
1279                 return;
1280
1281         kfree(master_priv);
1282
1283         master->driver_priv = NULL;
1284 }
1285
1286 static void i915_get_mem_freq(struct drm_device *dev)
1287 {
1288         drm_i915_private_t *dev_priv = dev->dev_private;
1289         u32 tmp;
1290
1291         if (!IS_IGD(dev))
1292                 return;
1293
1294         tmp = I915_READ(CLKCFG);
1295
1296         switch (tmp & CLKCFG_FSB_MASK) {
1297         case CLKCFG_FSB_533:
1298                 dev_priv->fsb_freq = 533; /* 133*4 */
1299                 break;
1300         case CLKCFG_FSB_800:
1301                 dev_priv->fsb_freq = 800; /* 200*4 */
1302                 break;
1303         case CLKCFG_FSB_667:
1304                 dev_priv->fsb_freq =  667; /* 167*4 */
1305                 break;
1306         case CLKCFG_FSB_400:
1307                 dev_priv->fsb_freq = 400; /* 100*4 */
1308                 break;
1309         }
1310
1311         switch (tmp & CLKCFG_MEM_MASK) {
1312         case CLKCFG_MEM_533:
1313                 dev_priv->mem_freq = 533;
1314                 break;
1315         case CLKCFG_MEM_667:
1316                 dev_priv->mem_freq = 667;
1317                 break;
1318         case CLKCFG_MEM_800:
1319                 dev_priv->mem_freq = 800;
1320                 break;
1321         }
1322 }
1323
1324 /**
1325  * i915_driver_load - setup chip and create an initial config
1326  * @dev: DRM device
1327  * @flags: startup flags
1328  *
1329  * The driver load routine has to do several things:
1330  *   - drive output discovery via intel_modeset_init()
1331  *   - initialize the memory manager
1332  *   - allocate initial config memory
1333  *   - setup the DRM framebuffer with the allocated memory
1334  */
1335 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1336 {
1337         struct drm_i915_private *dev_priv = dev->dev_private;
1338         resource_size_t base, size;
1339         int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
1340         uint32_t agp_size, prealloc_size, prealloc_start;
1341
1342         /* i915 has 4 more counters */
1343         dev->counters += 4;
1344         dev->types[6] = _DRM_STAT_IRQ;
1345         dev->types[7] = _DRM_STAT_PRIMARY;
1346         dev->types[8] = _DRM_STAT_SECONDARY;
1347         dev->types[9] = _DRM_STAT_DMA;
1348
1349         dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1350         if (dev_priv == NULL)
1351                 return -ENOMEM;
1352
1353         dev->dev_private = (void *)dev_priv;
1354         dev_priv->dev = dev;
1355
1356         /* Add register map (needed for suspend/resume) */
1357         base = drm_get_resource_start(dev, mmio_bar);
1358         size = drm_get_resource_len(dev, mmio_bar);
1359
1360         if (i915_get_bridge_dev(dev)) {
1361                 ret = -EIO;
1362                 goto free_priv;
1363         }
1364
1365         dev_priv->regs = ioremap(base, size);
1366         if (!dev_priv->regs) {
1367                 DRM_ERROR("failed to map registers\n");
1368                 ret = -EIO;
1369                 goto put_bridge;
1370         }
1371
1372         dev_priv->mm.gtt_mapping =
1373                 io_mapping_create_wc(dev->agp->base,
1374                                      dev->agp->agp_info.aper_size * 1024*1024);
1375         if (dev_priv->mm.gtt_mapping == NULL) {
1376                 ret = -EIO;
1377                 goto out_rmmap;
1378         }
1379
1380         /* Set up a WC MTRR for non-PAT systems.  This is more common than
1381          * one would think, because the kernel disables PAT on first
1382          * generation Core chips because WC PAT gets overridden by a UC
1383          * MTRR if present.  Even if a UC MTRR isn't present.
1384          */
1385         dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
1386                                          dev->agp->agp_info.aper_size *
1387                                          1024 * 1024,
1388                                          MTRR_TYPE_WRCOMB, 1);
1389         if (dev_priv->mm.gtt_mtrr < 0) {
1390                 DRM_INFO("MTRR allocation failed.  Graphics "
1391                          "performance may suffer.\n");
1392         }
1393
1394         ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start);
1395         if (ret)
1396                 goto out_iomapfree;
1397
1398         dev_priv->wq = create_workqueue("i915");
1399         if (dev_priv->wq == NULL) {
1400                 DRM_ERROR("Failed to create our workqueue.\n");
1401                 ret = -ENOMEM;
1402                 goto out_iomapfree;
1403         }
1404
1405         /* enable GEM by default */
1406         dev_priv->has_gem = 1;
1407
1408         if (prealloc_size > agp_size * 3 / 4) {
1409                 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
1410                           "memory stolen.\n",
1411                           prealloc_size / 1024, agp_size / 1024);
1412                 DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
1413                           "updating the BIOS to fix).\n");
1414                 dev_priv->has_gem = 0;
1415         }
1416
1417         dev->driver->get_vblank_counter = i915_get_vblank_counter;
1418         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1419         if (IS_G4X(dev) || IS_IGDNG(dev)) {
1420                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
1421                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
1422         }
1423
1424         i915_gem_load(dev);
1425
1426         /* Init HWS */
1427         if (!I915_NEED_GFX_HWS(dev)) {
1428                 ret = i915_init_phys_hws(dev);
1429                 if (ret != 0)
1430                         goto out_workqueue_free;
1431         }
1432
1433         i915_get_mem_freq(dev);
1434
1435         /* On the 945G/GM, the chipset reports the MSI capability on the
1436          * integrated graphics even though the support isn't actually there
1437          * according to the published specs.  It doesn't appear to function
1438          * correctly in testing on 945G.
1439          * This may be a side effect of MSI having been made available for PEG
1440          * and the registers being closely associated.
1441          *
1442          * According to chipset errata, on the 965GM, MSI interrupts may
1443          * be lost or delayed, but we use them anyways to avoid
1444          * stuck interrupts on some machines.
1445          */
1446         if (!IS_I945G(dev) && !IS_I945GM(dev))
1447                 pci_enable_msi(dev->pdev);
1448
1449         spin_lock_init(&dev_priv->user_irq_lock);
1450         spin_lock_init(&dev_priv->error_lock);
1451         dev_priv->user_irq_refcount = 0;
1452
1453         ret = drm_vblank_init(dev, I915_NUM_PIPE);
1454
1455         if (ret) {
1456                 (void) i915_driver_unload(dev);
1457                 return ret;
1458         }
1459
1460         /* Start out suspended */
1461         dev_priv->mm.suspended = 1;
1462
1463         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1464                 ret = i915_load_modeset_init(dev, prealloc_start,
1465                                              prealloc_size, agp_size);
1466                 if (ret < 0) {
1467                         DRM_ERROR("failed to init modeset\n");
1468                         goto out_workqueue_free;
1469                 }
1470         }
1471
1472         /* Must be done after probing outputs */
1473         /* FIXME: verify on IGDNG */
1474         if (!IS_IGDNG(dev))
1475                 intel_opregion_init(dev, 0);
1476
1477         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
1478                     (unsigned long) dev);
1479         return 0;
1480
1481 out_workqueue_free:
1482         destroy_workqueue(dev_priv->wq);
1483 out_iomapfree:
1484         io_mapping_free(dev_priv->mm.gtt_mapping);
1485 out_rmmap:
1486         iounmap(dev_priv->regs);
1487 put_bridge:
1488         pci_dev_put(dev_priv->bridge_dev);
1489 free_priv:
1490         kfree(dev_priv);
1491         return ret;
1492 }
1493
1494 int i915_driver_unload(struct drm_device *dev)
1495 {
1496         struct drm_i915_private *dev_priv = dev->dev_private;
1497
1498         destroy_workqueue(dev_priv->wq);
1499         del_timer_sync(&dev_priv->hangcheck_timer);
1500
1501         io_mapping_free(dev_priv->mm.gtt_mapping);
1502         if (dev_priv->mm.gtt_mtrr >= 0) {
1503                 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
1504                          dev->agp->agp_info.aper_size * 1024 * 1024);
1505                 dev_priv->mm.gtt_mtrr = -1;
1506         }
1507
1508         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1509                 drm_irq_uninstall(dev);
1510         }
1511
1512         if (dev->pdev->msi_enabled)
1513                 pci_disable_msi(dev->pdev);
1514
1515         if (dev_priv->regs != NULL)
1516                 iounmap(dev_priv->regs);
1517
1518         if (!IS_IGDNG(dev))
1519                 intel_opregion_free(dev, 0);
1520
1521         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1522                 intel_modeset_cleanup(dev);
1523
1524                 i915_gem_free_all_phys_object(dev);
1525
1526                 mutex_lock(&dev->struct_mutex);
1527                 i915_gem_cleanup_ringbuffer(dev);
1528                 mutex_unlock(&dev->struct_mutex);
1529                 drm_mm_takedown(&dev_priv->vram);
1530                 i915_gem_lastclose(dev);
1531         }
1532
1533         pci_dev_put(dev_priv->bridge_dev);
1534         kfree(dev->dev_private);
1535
1536         return 0;
1537 }
1538
1539 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1540 {
1541         struct drm_i915_file_private *i915_file_priv;
1542
1543         DRM_DEBUG_DRIVER("\n");
1544         i915_file_priv = (struct drm_i915_file_private *)
1545             kmalloc(sizeof(*i915_file_priv), GFP_KERNEL);
1546
1547         if (!i915_file_priv)
1548                 return -ENOMEM;
1549
1550         file_priv->driver_priv = i915_file_priv;
1551
1552         INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
1553
1554         return 0;
1555 }
1556
1557 /**
1558  * i915_driver_lastclose - clean up after all DRM clients have exited
1559  * @dev: DRM device
1560  *
1561  * Take care of cleaning up after all DRM clients have exited.  In the
1562  * mode setting case, we want to restore the kernel's initial mode (just
1563  * in case the last client left us in a bad state).
1564  *
1565  * Additionally, in the non-mode setting case, we'll tear down the AGP
1566  * and DMA structures, since the kernel won't be using them, and clea
1567  * up any GEM state.
1568  */
1569 void i915_driver_lastclose(struct drm_device * dev)
1570 {
1571         drm_i915_private_t *dev_priv = dev->dev_private;
1572
1573         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1574                 drm_fb_helper_restore();
1575                 return;
1576         }
1577
1578         i915_gem_lastclose(dev);
1579
1580         if (dev_priv->agp_heap)
1581                 i915_mem_takedown(&(dev_priv->agp_heap));
1582
1583         i915_dma_cleanup(dev);
1584 }
1585
1586 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1587 {
1588         drm_i915_private_t *dev_priv = dev->dev_private;
1589         i915_gem_release(dev, file_priv);
1590         if (!drm_core_check_feature(dev, DRIVER_MODESET))
1591                 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
1592 }
1593
1594 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1595 {
1596         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1597
1598         kfree(i915_file_priv);
1599 }
1600
1601 struct drm_ioctl_desc i915_ioctls[] = {
1602         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1603         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1604         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1605         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1606         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1607         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1608         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1609         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1610         DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
1611         DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
1612         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1613         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1614         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1615         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1616         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
1617         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1618         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1619         DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1620         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
1621         DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1622         DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1623         DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH),
1624         DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
1625         DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1626         DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1627         DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
1628         DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0),
1629         DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0),
1630         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
1631         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, 0),
1632         DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0),
1633         DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0),
1634         DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
1635         DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
1636         DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0),
1637         DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
1638         DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, 0),
1639 };
1640
1641 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1642
1643 /**
1644  * Determine if the device really is AGP or not.
1645  *
1646  * All Intel graphics chipsets are treated as AGP, even if they are really
1647  * PCI-e.
1648  *
1649  * \param dev   The device to be tested.
1650  *
1651  * \returns
1652  * A value of 1 is always retured to indictate every i9x5 is AGP.
1653  */
1654 int i915_driver_device_is_agp(struct drm_device * dev)
1655 {
1656         return 1;
1657 }