SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "drm_crtc_helper.h"
  32 #include "drm_fb_helper.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include <linux/vgaarb.h>
  38 #include <linux/vga_switcheroo.h>
  39
  40 /* Really want an OS-independent resettable timer.  Would like to have
  41  * this loop run for (eg) 3 sec, but have the timer reset every time
  42  * the head pointer changes, so that EBUSY only happens if the ring
  43  * actually stalls for (eg) 3 seconds.
  44  */
  45 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
  46 {
  47         drm_i915_private_t *dev_priv = dev->dev_private;
  48         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  49         u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
  50         u32 last_acthd = I915_READ(acthd_reg);
  51         u32 acthd;
  52         u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  53         int i;
  54
  55         trace_i915_ring_wait_begin (dev);
  56
  57         for (i = 0; i < 100000; i++) {
  58                 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  59                 acthd = I915_READ(acthd_reg);
  60                 ring->space = ring->head - (ring->tail + 8);
  61                 if (ring->space < 0)
  62                         ring->space += ring->Size;
  63                 if (ring->space >= n) {
  64                         trace_i915_ring_wait_end (dev);
  65                         return 0;
  66                 }
  67
  68                 if (dev->primary->master) {
  69                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  70                         if (master_priv->sarea_priv)
  71                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
  72                 }
  73
  74
  75                 if (ring->head != last_head)
  76                         i = 0;
  77                 if (acthd != last_acthd)
  78                         i = 0;
  79
  80                 last_head = ring->head;
  81                 last_acthd = acthd;
  82                 msleep_interruptible(10);
  83
  84         }
  85
  86         trace_i915_ring_wait_end (dev);
  87         return -EBUSY;
  88 }
  89
  90 /* As a ringbuffer is only allowed to wrap between instructions, fill
  91  * the tail with NOOPs.
  92  */
  93 int i915_wrap_ring(struct drm_device *dev)
  94 {
  95         drm_i915_private_t *dev_priv = dev->dev_private;
  96         volatile unsigned int *virt;
  97         int rem;
  98
  99         rem = dev_priv->ring.Size - dev_priv->ring.tail;
 100         if (dev_priv->ring.space < rem) {
 101                 int ret = i915_wait_ring(dev, rem, __func__);
 102                 if (ret)
 103                         return ret;
 104         }
 105         dev_priv->ring.space -= rem;
 106
 107         virt = (unsigned int *)
 108                 (dev_priv->ring.virtual_start + dev_priv->ring.tail);
 109         rem /= 4;
 110         while (rem--)
 111                 *virt++ = MI_NOOP;
 112
 113         dev_priv->ring.tail = 0;
 114
 115         return 0;
 116 }
 117
 118 /**
 119  * Sets up the hardware status page for devices that need a physical address
 120  * in the register.
 121  */
 122 static int i915_init_phys_hws(struct drm_device *dev)
 123 {
 124         drm_i915_private_t *dev_priv = dev->dev_private;
 125         /* Program Hardware Status Page */
 126         dev_priv->status_page_dmah =
 127                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
 128
 129         if (!dev_priv->status_page_dmah) {
 130                 DRM_ERROR("Can not allocate hardware status page\n");
 131                 return -ENOMEM;
 132         }
 133         dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
 134         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
 135
 136         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 137
 138         if (IS_I965G(dev))
 139                 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
 140                                              0xf0;
 141
 142         I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
 143         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 144         return 0;
 145 }
 146
 147 /**
 148  * Frees the hardware status page, whether it's a physical address or a virtual
 149  * address set up by the X Server.
 150  */
 151 static void i915_free_hws(struct drm_device *dev)
 152 {
 153         drm_i915_private_t *dev_priv = dev->dev_private;
 154         if (dev_priv->status_page_dmah) {
 155                 drm_pci_free(dev, dev_priv->status_page_dmah);
 156                 dev_priv->status_page_dmah = NULL;
 157         }
 158
 159         if (dev_priv->status_gfx_addr) {
 160                 dev_priv->status_gfx_addr = 0;
 161                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 162         }
 163
 164         /* Need to rewrite hardware status page */
 165         I915_WRITE(HWS_PGA, 0x1ffff000);
 166 }
 167
 168 void i915_kernel_lost_context(struct drm_device * dev)
 169 {
 170         drm_i915_private_t *dev_priv = dev->dev_private;
 171         struct drm_i915_master_private *master_priv;
 172         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
 173
 174         /*
 175          * We should never lose context on the ring with modesetting
 176          * as we don't expose it to userspace
 177          */
 178         if (drm_core_check_feature(dev, DRIVER_MODESET))
 179                 return;
 180
 181         ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 182         ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
 183         ring->space = ring->head - (ring->tail + 8);
 184         if (ring->space < 0)
 185                 ring->space += ring->Size;
 186
 187         if (!dev->primary->master)
 188                 return;
 189
 190         master_priv = dev->primary->master->driver_priv;
 191         if (ring->head == ring->tail && master_priv->sarea_priv)
 192                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 193 }
 194
 195 static int i915_dma_cleanup(struct drm_device * dev)
 196 {
 197         drm_i915_private_t *dev_priv = dev->dev_private;
 198         /* Make sure interrupts are disabled here because the uninstall ioctl
 199          * may not have been called from userspace and after dev_private
 200          * is freed, it's too late.
 201          */
 202         if (dev->irq_enabled)
 203                 drm_irq_uninstall(dev);
 204
 205         if (dev_priv->ring.virtual_start) {
 206                 drm_core_ioremapfree(&dev_priv->ring.map, dev);
 207                 dev_priv->ring.virtual_start = NULL;
 208                 dev_priv->ring.map.handle = NULL;
 209                 dev_priv->ring.map.size = 0;
 210         }
 211
 212         /* Clear the HWS virtual address at teardown */
 213         if (I915_NEED_GFX_HWS(dev))
 214                 i915_free_hws(dev);
 215
 216         return 0;
 217 }
 218
 219 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 220 {
 221         drm_i915_private_t *dev_priv = dev->dev_private;
 222         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 223
 224         master_priv->sarea = drm_getsarea(dev);
 225         if (master_priv->sarea) {
 226                 master_priv->sarea_priv = (drm_i915_sarea_t *)
 227                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
 228         } else {
 229                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
 230         }
 231
 232         if (init->ring_size != 0) {
 233                 if (dev_priv->ring.ring_obj != NULL) {
 234                         i915_dma_cleanup(dev);
 235                         DRM_ERROR("Client tried to initialize ringbuffer in "
 236                                   "GEM mode\n");
 237                         return -EINVAL;
 238                 }
 239
 240                 dev_priv->ring.Size = init->ring_size;
 241
 242                 dev_priv->ring.map.offset = init->ring_start;
 243                 dev_priv->ring.map.size = init->ring_size;
 244                 dev_priv->ring.map.type = 0;
 245                 dev_priv->ring.map.flags = 0;
 246                 dev_priv->ring.map.mtrr = 0;
 247
 248                 drm_core_ioremap_wc(&dev_priv->ring.map, dev);
 249
 250                 if (dev_priv->ring.map.handle == NULL) {
 251                         i915_dma_cleanup(dev);
 252                         DRM_ERROR("can not ioremap virtual address for"
 253                                   " ring buffer\n");
 254                         return -ENOMEM;
 255                 }
 256         }
 257
 258         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 259
 260         dev_priv->cpp = init->cpp;
 261         dev_priv->back_offset = init->back_offset;
 262         dev_priv->front_offset = init->front_offset;
 263         dev_priv->current_page = 0;
 264         if (master_priv->sarea_priv)
 265                 master_priv->sarea_priv->pf_current_page = 0;
 266
 267         /* Allow hardware batchbuffers unless told otherwise.
 268          */
 269         dev_priv->allow_batchbuffer = 1;
 270
 271         return 0;
 272 }
 273
 274 static int i915_dma_resume(struct drm_device * dev)
 275 {
 276         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 277
 278         DRM_DEBUG_DRIVER("%s\n", __func__);
 279
 280         if (dev_priv->ring.map.handle == NULL) {
 281                 DRM_ERROR("can not ioremap virtual address for"
 282                           " ring buffer\n");
 283                 return -ENOMEM;
 284         }
 285
 286         /* Program Hardware Status Page */
 287         if (!dev_priv->hw_status_page) {
 288                 DRM_ERROR("Can not find hardware status page\n");
 289                 return -EINVAL;
 290         }
 291         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 292                                 dev_priv->hw_status_page);
 293
 294         if (dev_priv->status_gfx_addr != 0)
 295                 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
 296         else
 297                 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
 298         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 299
 300         return 0;
 301 }
 302
 303 static int i915_dma_init(struct drm_device *dev, void *data,
 304                          struct drm_file *file_priv)
 305 {
 306         drm_i915_init_t *init = data;
 307         int retcode = 0;
 308
 309         switch (init->func) {
 310         case I915_INIT_DMA:
 311                 retcode = i915_initialize(dev, init);
 312                 break;
 313         case I915_CLEANUP_DMA:
 314                 retcode = i915_dma_cleanup(dev);
 315                 break;
 316         case I915_RESUME_DMA:
 317                 retcode = i915_dma_resume(dev);
 318                 break;
 319         default:
 320                 retcode = -EINVAL;
 321                 break;
 322         }
 323
 324         return retcode;
 325 }
 326
 327 /* Implement basically the same security restrictions as hardware does
 328  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 329  *
 330  * Most of the calculations below involve calculating the size of a
 331  * particular instruction.  It's important to get the size right as
 332  * that tells us where the next instruction to check is.  Any illegal
 333  * instruction detected will be given a size of zero, which is a
 334  * signal to abort the rest of the buffer.
 335  */
 336 static int do_validate_cmd(int cmd)
 337 {
 338         switch (((cmd >> 29) & 0x7)) {
 339         case 0x0:
 340                 switch ((cmd >> 23) & 0x3f) {
 341                 case 0x0:
 342                         return 1;       /* MI_NOOP */
 343                 case 0x4:
 344                         return 1;       /* MI_FLUSH */
 345                 default:
 346                         return 0;       /* disallow everything else */
 347                 }
 348                 break;
 349         case 0x1:
 350                 return 0;       /* reserved */
 351         case 0x2:
 352                 return (cmd & 0xff) + 2;        /* 2d commands */
 353         case 0x3:
 354                 if (((cmd >> 24) & 0x1f) <= 0x18)
 355                         return 1;
 356
 357                 switch ((cmd >> 24) & 0x1f) {
 358                 case 0x1c:
 359                         return 1;
 360                 case 0x1d:
 361                         switch ((cmd >> 16) & 0xff) {
 362                         case 0x3:
 363                                 return (cmd & 0x1f) + 2;
 364                         case 0x4:
 365                                 return (cmd & 0xf) + 2;
 366                         default:
 367                                 return (cmd & 0xffff) + 2;
 368                         }
 369                 case 0x1e:
 370                         if (cmd & (1 << 23))
 371                                 return (cmd & 0xffff) + 1;
 372                         else
 373                                 return 1;
 374                 case 0x1f:
 375                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 376                                 return (cmd & 0x1ffff) + 2;
 377                         else if (cmd & (1 << 17))       /* indirect random */
 378                                 if ((cmd & 0xffff) == 0)
 379                                         return 0;       /* unknown length, too hard */
 380                                 else
 381                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 382                         else
 383                                 return 2;       /* indirect sequential */
 384                 default:
 385                         return 0;
 386                 }
 387         default:
 388                 return 0;
 389         }
 390
 391         return 0;
 392 }
 393
 394 static int validate_cmd(int cmd)
 395 {
 396         int ret = do_validate_cmd(cmd);
 397
 398 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 399
 400         return ret;
 401 }
 402
 403 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 404 {
 405         drm_i915_private_t *dev_priv = dev->dev_private;
 406         int i;
 407         RING_LOCALS;
 408
 409         if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
 410                 return -EINVAL;
 411
 412         BEGIN_LP_RING((dwords+1)&~1);
 413
 414         for (i = 0; i < dwords;) {
 415                 int cmd, sz;
 416
 417                 cmd = buffer[i];
 418
 419                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 420                         return -EINVAL;
 421
 422                 OUT_RING(cmd);
 423
 424                 while (++i, --sz) {
 425                         OUT_RING(buffer[i]);
 426                 }
 427         }
 428
 429         if (dwords & 1)
 430                 OUT_RING(0);
 431
 432         ADVANCE_LP_RING();
 433
 434         return 0;
 435 }
 436
 437 int
 438 i915_emit_box(struct drm_device *dev,
 439               struct drm_clip_rect *boxes,
 440               int i, int DR1, int DR4)
 441 {
 442         drm_i915_private_t *dev_priv = dev->dev_private;
 443         struct drm_clip_rect box = boxes[i];
 444         RING_LOCALS;
 445
 446         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 447                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 448                           box.x1, box.y1, box.x2, box.y2);
 449                 return -EINVAL;
 450         }
 451
 452         if (IS_I965G(dev)) {
 453                 BEGIN_LP_RING(4);
 454                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 455                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 456                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 457                 OUT_RING(DR4);
 458                 ADVANCE_LP_RING();
 459         } else {
 460                 BEGIN_LP_RING(6);
 461                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 462                 OUT_RING(DR1);
 463                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 464                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 465                 OUT_RING(DR4);
 466                 OUT_RING(0);
 467                 ADVANCE_LP_RING();
 468         }
 469
 470         return 0;
 471 }
 472
 473 /* XXX: Emitting the counter should really be moved to part of the IRQ
 474  * emit. For now, do it in both places:
 475  */
 476
 477 static void i915_emit_breadcrumb(struct drm_device *dev)
 478 {
 479         drm_i915_private_t *dev_priv = dev->dev_private;
 480         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 481         RING_LOCALS;
 482
 483         dev_priv->counter++;
 484         if (dev_priv->counter > 0x7FFFFFFFUL)
 485                 dev_priv->counter = 0;
 486         if (master_priv->sarea_priv)
 487                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 488
 489         BEGIN_LP_RING(4);
 490         OUT_RING(MI_STORE_DWORD_INDEX);
 491         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 492         OUT_RING(dev_priv->counter);
 493         OUT_RING(0);
 494         ADVANCE_LP_RING();
 495 }
 496
 497 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 498                                    drm_i915_cmdbuffer_t *cmd,
 499                                    struct drm_clip_rect *cliprects,
 500                                    void *cmdbuf)
 501 {
 502         int nbox = cmd->num_cliprects;
 503         int i = 0, count, ret;
 504
 505         if (cmd->sz & 0x3) {
 506                 DRM_ERROR("alignment");
 507                 return -EINVAL;
 508         }
 509
 510         i915_kernel_lost_context(dev);
 511
 512         count = nbox ? nbox : 1;
 513
 514         for (i = 0; i < count; i++) {
 515                 if (i < nbox) {
 516                         ret = i915_emit_box(dev, cliprects, i,
 517                                             cmd->DR1, cmd->DR4);
 518                         if (ret)
 519                                 return ret;
 520                 }
 521
 522                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 523                 if (ret)
 524                         return ret;
 525         }
 526
 527         i915_emit_breadcrumb(dev);
 528         return 0;
 529 }
 530
 531 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 532                                      drm_i915_batchbuffer_t * batch,
 533                                      struct drm_clip_rect *cliprects)
 534 {
 535         drm_i915_private_t *dev_priv = dev->dev_private;
 536         int nbox = batch->num_cliprects;
 537         int i = 0, count;
 538         RING_LOCALS;
 539
 540         if ((batch->start | batch->used) & 0x7) {
 541                 DRM_ERROR("alignment");
 542                 return -EINVAL;
 543         }
 544
 545         i915_kernel_lost_context(dev);
 546
 547         count = nbox ? nbox : 1;
 548
 549         for (i = 0; i < count; i++) {
 550                 if (i < nbox) {
 551                         int ret = i915_emit_box(dev, cliprects, i,
 552                                                 batch->DR1, batch->DR4);
 553                         if (ret)
 554                                 return ret;
 555                 }
 556
 557                 if (!IS_I830(dev) && !IS_845G(dev)) {
 558                         BEGIN_LP_RING(2);
 559                         if (IS_I965G(dev)) {
 560                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 561                                 OUT_RING(batch->start);
 562                         } else {
 563                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 564                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 565                         }
 566                         ADVANCE_LP_RING();
 567                 } else {
 568                         BEGIN_LP_RING(4);
 569                         OUT_RING(MI_BATCH_BUFFER);
 570                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 571                         OUT_RING(batch->start + batch->used - 4);
 572                         OUT_RING(0);
 573                         ADVANCE_LP_RING();
 574                 }
 575         }
 576
 577         i915_emit_breadcrumb(dev);
 578
 579         return 0;
 580 }
 581
 582 static int i915_dispatch_flip(struct drm_device * dev)
 583 {
 584         drm_i915_private_t *dev_priv = dev->dev_private;
 585         struct drm_i915_master_private *master_priv =
 586                 dev->primary->master->driver_priv;
 587         RING_LOCALS;
 588
 589         if (!master_priv->sarea_priv)
 590                 return -EINVAL;
 591
 592         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 593                           __func__,
 594                          dev_priv->current_page,
 595                          master_priv->sarea_priv->pf_current_page);
 596
 597         i915_kernel_lost_context(dev);
 598
 599         BEGIN_LP_RING(2);
 600         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 601         OUT_RING(0);
 602         ADVANCE_LP_RING();
 603
 604         BEGIN_LP_RING(6);
 605         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 606         OUT_RING(0);
 607         if (dev_priv->current_page == 0) {
 608                 OUT_RING(dev_priv->back_offset);
 609                 dev_priv->current_page = 1;
 610         } else {
 611                 OUT_RING(dev_priv->front_offset);
 612                 dev_priv->current_page = 0;
 613         }
 614         OUT_RING(0);
 615         ADVANCE_LP_RING();
 616
 617         BEGIN_LP_RING(2);
 618         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 619         OUT_RING(0);
 620         ADVANCE_LP_RING();
 621
 622         master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
 623
 624         BEGIN_LP_RING(4);
 625         OUT_RING(MI_STORE_DWORD_INDEX);
 626         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 627         OUT_RING(dev_priv->counter);
 628         OUT_RING(0);
 629         ADVANCE_LP_RING();
 630
 631         master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 632         return 0;
 633 }
 634
 635 static int i915_quiescent(struct drm_device * dev)
 636 {
 637         drm_i915_private_t *dev_priv = dev->dev_private;
 638
 639         i915_kernel_lost_context(dev);
 640         return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
 641 }
 642
 643 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 644                             struct drm_file *file_priv)
 645 {
 646         int ret;
 647
 648         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 649
 650         mutex_lock(&dev->struct_mutex);
 651         ret = i915_quiescent(dev);
 652         mutex_unlock(&dev->struct_mutex);
 653
 654         return ret;
 655 }
 656
 657 static int i915_batchbuffer(struct drm_device *dev, void *data,
 658                             struct drm_file *file_priv)
 659 {
 660         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 661         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 662         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 663             master_priv->sarea_priv;
 664         drm_i915_batchbuffer_t *batch = data;
 665         int ret;
 666         struct drm_clip_rect *cliprects = NULL;
 667
 668         if (!dev_priv->allow_batchbuffer) {
 669                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 670                 return -EINVAL;
 671         }
 672
 673         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 674                         batch->start, batch->used, batch->num_cliprects);
 675
 676         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 677
 678         if (batch->num_cliprects < 0)
 679                 return -EINVAL;
 680
 681         if (batch->num_cliprects) {
 682                 cliprects = kcalloc(batch->num_cliprects,
 683                                     sizeof(struct drm_clip_rect),
 684                                     GFP_KERNEL);
 685                 if (cliprects == NULL)
 686                         return -ENOMEM;
 687
 688                 ret = copy_from_user(cliprects, batch->cliprects,
 689                                      batch->num_cliprects *
 690                                      sizeof(struct drm_clip_rect));
 691                 if (ret != 0)
 692                         goto fail_free;
 693         }
 694
 695         mutex_lock(&dev->struct_mutex);
 696         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 697         mutex_unlock(&dev->struct_mutex);
 698
 699         if (sarea_priv)
 700                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 701
 702 fail_free:
 703         kfree(cliprects);
 704
 705         return ret;
 706 }
 707
 708 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 709                           struct drm_file *file_priv)
 710 {
 711         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 712         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 713         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 714             master_priv->sarea_priv;
 715         drm_i915_cmdbuffer_t *cmdbuf = data;
 716         struct drm_clip_rect *cliprects = NULL;
 717         void *batch_data;
 718         int ret;
 719
 720         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 721                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 722
 723         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 724
 725         if (cmdbuf->num_cliprects < 0)
 726                 return -EINVAL;
 727
 728         batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
 729         if (batch_data == NULL)
 730                 return -ENOMEM;
 731
 732         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 733         if (ret != 0)
 734                 goto fail_batch_free;
 735
 736         if (cmdbuf->num_cliprects) {
 737                 cliprects = kcalloc(cmdbuf->num_cliprects,
 738                                     sizeof(struct drm_clip_rect), GFP_KERNEL);
 739                 if (cliprects == NULL) {
 740                         ret = -ENOMEM;
 741                         goto fail_batch_free;
 742                 }
 743
 744                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 745                                      cmdbuf->num_cliprects *
 746                                      sizeof(struct drm_clip_rect));
 747                 if (ret != 0)
 748                         goto fail_clip_free;
 749         }
 750
 751         mutex_lock(&dev->struct_mutex);
 752         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 753         mutex_unlock(&dev->struct_mutex);
 754         if (ret) {
 755                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 756                 goto fail_clip_free;
 757         }
 758
 759         if (sarea_priv)
 760                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 761
 762 fail_clip_free:
 763         kfree(cliprects);
 764 fail_batch_free:
 765         kfree(batch_data);
 766
 767         return ret;
 768 }
 769
 770 static int i915_flip_bufs(struct drm_device *dev, void *data,
 771                           struct drm_file *file_priv)
 772 {
 773         int ret;
 774
 775         DRM_DEBUG_DRIVER("%s\n", __func__);
 776
 777         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 778
 779         mutex_lock(&dev->struct_mutex);
 780         ret = i915_dispatch_flip(dev);
 781         mutex_unlock(&dev->struct_mutex);
 782
 783         return ret;
 784 }
 785
 786 static int i915_getparam(struct drm_device *dev, void *data,
 787                          struct drm_file *file_priv)
 788 {
 789         drm_i915_private_t *dev_priv = dev->dev_private;
 790         drm_i915_getparam_t *param = data;
 791         int value;
 792
 793         if (!dev_priv) {
 794                 DRM_ERROR("called with no initialization\n");
 795                 return -EINVAL;
 796         }
 797
 798         switch (param->param) {
 799         case I915_PARAM_IRQ_ACTIVE:
 800                 value = dev->pdev->irq ? 1 : 0;
 801                 break;
 802         case I915_PARAM_ALLOW_BATCHBUFFER:
 803                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 804                 break;
 805         case I915_PARAM_LAST_DISPATCH:
 806                 value = READ_BREADCRUMB(dev_priv);
 807                 break;
 808         case I915_PARAM_CHIPSET_ID:
 809                 value = dev->pci_device;
 810                 break;
 811         case I915_PARAM_HAS_GEM:
 812                 value = dev_priv->has_gem;
 813                 break;
 814         case I915_PARAM_NUM_FENCES_AVAIL:
 815                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 816                 break;
 817         case I915_PARAM_HAS_OVERLAY:
 818                 value = dev_priv->overlay ? 1 : 0;
 819                 break;
 820         case I915_PARAM_HAS_PAGEFLIPPING:
 821                 value = 1;
 822                 break;
 823         case I915_PARAM_HAS_EXECBUF2:
 824                 /* depends on GEM */
 825                 value = dev_priv->has_gem;
 826                 break;
 827         default:
 828                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 829                                  param->param);
 830                 return -EINVAL;
 831         }
 832
 833         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 834                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 835                 return -EFAULT;
 836         }
 837
 838         return 0;
 839 }
 840
 841 static int i915_setparam(struct drm_device *dev, void *data,
 842                          struct drm_file *file_priv)
 843 {
 844         drm_i915_private_t *dev_priv = dev->dev_private;
 845         drm_i915_setparam_t *param = data;
 846
 847         if (!dev_priv) {
 848                 DRM_ERROR("called with no initialization\n");
 849                 return -EINVAL;
 850         }
 851
 852         switch (param->param) {
 853         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 854                 break;
 855         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 856                 dev_priv->tex_lru_log_granularity = param->value;
 857                 break;
 858         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 859                 dev_priv->allow_batchbuffer = param->value;
 860                 break;
 861         case I915_SETPARAM_NUM_USED_FENCES:
 862                 if (param->value > dev_priv->num_fence_regs ||
 863                     param->value < 0)
 864                         return -EINVAL;
 865                 /* Userspace can use first N regs */
 866                 dev_priv->fence_reg_start = param->value;
 867                 break;
 868         default:
 869                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
 870                                         param->param);
 871                 return -EINVAL;
 872         }
 873
 874         return 0;
 875 }
 876
 877 static int i915_set_status_page(struct drm_device *dev, void *data,
 878                                 struct drm_file *file_priv)
 879 {
 880         drm_i915_private_t *dev_priv = dev->dev_private;
 881         drm_i915_hws_addr_t *hws = data;
 882
 883         if (!I915_NEED_GFX_HWS(dev))
 884                 return -EINVAL;
 885
 886         if (!dev_priv) {
 887                 DRM_ERROR("called with no initialization\n");
 888                 return -EINVAL;
 889         }
 890
 891         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 892                 WARN(1, "tried to set status page when mode setting active\n");
 893                 return 0;
 894         }
 895
 896         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
 897
 898         dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
 899
 900         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
 901         dev_priv->hws_map.size = 4*1024;
 902         dev_priv->hws_map.type = 0;
 903         dev_priv->hws_map.flags = 0;
 904         dev_priv->hws_map.mtrr = 0;
 905
 906         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
 907         if (dev_priv->hws_map.handle == NULL) {
 908                 i915_dma_cleanup(dev);
 909                 dev_priv->status_gfx_addr = 0;
 910                 DRM_ERROR("can not ioremap virtual address for"
 911                                 " G33 hw status page\n");
 912                 return -ENOMEM;
 913         }
 914         dev_priv->hw_status_page = dev_priv->hws_map.handle;
 915
 916         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 917         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
 918         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
 919                                 dev_priv->status_gfx_addr);
 920         DRM_DEBUG_DRIVER("load hws at %p\n",
 921                                 dev_priv->hw_status_page);
 922         return 0;
 923 }
 924
 925 static int i915_get_bridge_dev(struct drm_device *dev)
 926 {
 927         struct drm_i915_private *dev_priv = dev->dev_private;
 928
 929         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
 930         if (!dev_priv->bridge_dev) {
 931                 DRM_ERROR("bridge device not found\n");
 932                 return -1;
 933         }
 934         return 0;
 935 }
 936
 937 /**
 938  * i915_probe_agp - get AGP bootup configuration
 939  * @pdev: PCI device
 940  * @aperture_size: returns AGP aperture configured size
 941  * @preallocated_size: returns size of BIOS preallocated AGP space
 942  *
 943  * Since Intel integrated graphics are UMA, the BIOS has to set aside
 944  * some RAM for the framebuffer at early boot.  This code figures out
 945  * how much was set aside so we can use it for our own purposes.
 946  */
 947 static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
 948                           uint32_t *preallocated_size,
 949                           uint32_t *start)
 950 {
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         u16 tmp = 0;
 953         unsigned long overhead;
 954         unsigned long stolen;
 955
 956         /* Get the fb aperture size and "stolen" memory amount. */
 957         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp);
 958
 959         *aperture_size = 1024 * 1024;
 960         *preallocated_size = 1024 * 1024;
 961
 962         switch (dev->pdev->device) {
 963         case PCI_DEVICE_ID_INTEL_82830_CGC:
 964         case PCI_DEVICE_ID_INTEL_82845G_IG:
 965         case PCI_DEVICE_ID_INTEL_82855GM_IG:
 966         case PCI_DEVICE_ID_INTEL_82865_IG:
 967                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
 968                         *aperture_size *= 64;
 969                 else
 970                         *aperture_size *= 128;
 971                 break;
 972         default:
 973                 /* 9xx supports large sizes, just look at the length */
 974                 *aperture_size = pci_resource_len(dev->pdev, 2);
 975                 break;
 976         }
 977
 978         /*
 979          * Some of the preallocated space is taken by the GTT
 980          * and popup.  GTT is 1K per MB of aperture size, and popup is 4K.
 981          */
 982         if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev))
 983                 overhead = 4096;
 984         else
 985                 overhead = (*aperture_size / 1024) + 4096;
 986
 987         switch (tmp & INTEL_GMCH_GMS_MASK) {
 988         case INTEL_855_GMCH_GMS_DISABLED:
 989                 DRM_ERROR("video memory is disabled\n");
 990                 return -1;
 991         case INTEL_855_GMCH_GMS_STOLEN_1M:
 992                 stolen = 1 * 1024 * 1024;
 993                 break;
 994         case INTEL_855_GMCH_GMS_STOLEN_4M:
 995                 stolen = 4 * 1024 * 1024;
 996                 break;
 997         case INTEL_855_GMCH_GMS_STOLEN_8M:
 998                 stolen = 8 * 1024 * 1024;
 999                 break;
1000         case INTEL_855_GMCH_GMS_STOLEN_16M:
1001                 stolen = 16 * 1024 * 1024;
1002                 break;
1003         case INTEL_855_GMCH_GMS_STOLEN_32M:
1004                 stolen = 32 * 1024 * 1024;
1005                 break;
1006         case INTEL_915G_GMCH_GMS_STOLEN_48M:
1007                 stolen = 48 * 1024 * 1024;
1008                 break;
1009         case INTEL_915G_GMCH_GMS_STOLEN_64M:
1010                 stolen = 64 * 1024 * 1024;
1011                 break;
1012         case INTEL_GMCH_GMS_STOLEN_128M:
1013                 stolen = 128 * 1024 * 1024;
1014                 break;
1015         case INTEL_GMCH_GMS_STOLEN_256M:
1016                 stolen = 256 * 1024 * 1024;
1017                 break;
1018         case INTEL_GMCH_GMS_STOLEN_96M:
1019                 stolen = 96 * 1024 * 1024;
1020                 break;
1021         case INTEL_GMCH_GMS_STOLEN_160M:
1022                 stolen = 160 * 1024 * 1024;
1023                 break;
1024         case INTEL_GMCH_GMS_STOLEN_224M:
1025                 stolen = 224 * 1024 * 1024;
1026                 break;
1027         case INTEL_GMCH_GMS_STOLEN_352M:
1028                 stolen = 352 * 1024 * 1024;
1029                 break;
1030         default:
1031                 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1032                         tmp & INTEL_GMCH_GMS_MASK);
1033                 return -1;
1034         }
1035         *preallocated_size = stolen - overhead;
1036         *start = overhead;
1037
1038         return 0;
1039 }
1040
1041 #define PTE_ADDRESS_MASK                0xfffff000
1042 #define PTE_ADDRESS_MASK_HIGH           0x000000f0 /* i915+ */
1043 #define PTE_MAPPING_TYPE_UNCACHED       (0 << 1)
1044 #define PTE_MAPPING_TYPE_DCACHE         (1 << 1) /* i830 only */
1045 #define PTE_MAPPING_TYPE_CACHED         (3 << 1)
1046 #define PTE_MAPPING_TYPE_MASK           (3 << 1)
1047 #define PTE_VALID                       (1 << 0)
1048
1049 /**
1050  * i915_gtt_to_phys - take a GTT address and turn it into a physical one
1051  * @dev: drm device
1052  * @gtt_addr: address to translate
1053  *
1054  * Some chip functions require allocations from stolen space but need the
1055  * physical address of the memory in question.  We use this routine
1056  * to get a physical address suitable for register programming from a given
1057  * GTT address.
1058  */
1059 static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1060                                       unsigned long gtt_addr)
1061 {
1062         unsigned long *gtt;
1063         unsigned long entry, phys;
1064         int gtt_bar = IS_I9XX(dev) ? 0 : 1;
1065         int gtt_offset, gtt_size;
1066
1067         if (IS_I965G(dev)) {
1068                 if (IS_G4X(dev) || IS_IRONLAKE(dev)) {
1069                         gtt_offset = 2*1024*1024;
1070                         gtt_size = 2*1024*1024;
1071                 } else {
1072                         gtt_offset = 512*1024;
1073                         gtt_size = 512*1024;
1074                 }
1075         } else {
1076                 gtt_bar = 3;
1077                 gtt_offset = 0;
1078                 gtt_size = pci_resource_len(dev->pdev, gtt_bar);
1079         }
1080
1081         gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
1082                          gtt_size);
1083         if (!gtt) {
1084                 DRM_ERROR("ioremap of GTT failed\n");
1085                 return 0;
1086         }
1087
1088         entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
1089
1090         DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
1091
1092         /* Mask out these reserved bits on this hardware. */
1093         if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) ||
1094             IS_I945G(dev) || IS_I945GM(dev)) {
1095                 entry &= ~PTE_ADDRESS_MASK_HIGH;
1096         }
1097
1098         /* If it's not a mapping type we know, then bail. */
1099         if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
1100             (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) {
1101                 iounmap(gtt);
1102                 return 0;
1103         }
1104
1105         if (!(entry & PTE_VALID)) {
1106                 DRM_ERROR("bad GTT entry in stolen space\n");
1107                 iounmap(gtt);
1108                 return 0;
1109         }
1110
1111         iounmap(gtt);
1112
1113         phys =(entry & PTE_ADDRESS_MASK) |
1114                 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
1115
1116         DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
1117
1118         return phys;
1119 }
1120
1121 static void i915_warn_stolen(struct drm_device *dev)
1122 {
1123         DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1124         DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1125 }
1126
1127 static void i915_setup_compression(struct drm_device *dev, int size)
1128 {
1129         struct drm_i915_private *dev_priv = dev->dev_private;
1130         struct drm_mm_node *compressed_fb, *compressed_llb;
1131         unsigned long cfb_base;
1132         unsigned long ll_base = 0;
1133
1134         /* Leave 1M for line length buffer & misc. */
1135         compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);
1136         if (!compressed_fb) {
1137                 i915_warn_stolen(dev);
1138                 return;
1139         }
1140
1141         compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1142         if (!compressed_fb) {
1143                 i915_warn_stolen(dev);
1144                 return;
1145         }
1146
1147         cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
1148         if (!cfb_base) {
1149                 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1150                 drm_mm_put_block(compressed_fb);
1151         }
1152
1153         if (!IS_GM45(dev)) {
1154                 compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096,
1155                                                     4096, 0);
1156                 if (!compressed_llb) {
1157                         i915_warn_stolen(dev);
1158                         return;
1159                 }
1160
1161                 compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
1162                 if (!compressed_llb) {
1163                         i915_warn_stolen(dev);
1164                         return;
1165                 }
1166
1167                 ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
1168                 if (!ll_base) {
1169                         DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1170                         drm_mm_put_block(compressed_fb);
1171                         drm_mm_put_block(compressed_llb);
1172                 }
1173         }
1174
1175         dev_priv->cfb_size = size;
1176
1177         if (IS_GM45(dev)) {
1178                 g4x_disable_fbc(dev);
1179                 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1180         } else {
1181                 i8xx_disable_fbc(dev);
1182                 I915_WRITE(FBC_CFB_BASE, cfb_base);
1183                 I915_WRITE(FBC_LL_BASE, ll_base);
1184         }
1185
1186         DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
1187                   ll_base, size >> 20);
1188 }
1189
1190 /* true = enable decode, false = disable decoder */
1191 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1192 {
1193         struct drm_device *dev = cookie;
1194
1195         intel_modeset_vga_set_state(dev, state);
1196         if (state)
1197                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1198                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1199         else
1200                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1201 }
1202
1203 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1204 {
1205         struct drm_device *dev = pci_get_drvdata(pdev);
1206         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1207         if (state == VGA_SWITCHEROO_ON) {
1208                 printk(KERN_INFO "i915: switched off\n");
1209                 /* i915 resume handler doesn't set to D0 */
1210                 pci_set_power_state(dev->pdev, PCI_D0);
1211                 i915_resume(dev);
1212         } else {
1213                 printk(KERN_ERR "i915: switched off\n");
1214                 i915_suspend(dev, pmm);
1215         }
1216 }
1217
1218 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1219 {
1220         struct drm_device *dev = pci_get_drvdata(pdev);
1221         bool can_switch;
1222
1223         spin_lock(&dev->count_lock);
1224         can_switch = (dev->open_count == 0);
1225         spin_unlock(&dev->count_lock);
1226         return can_switch;
1227 }
1228
1229 static int i915_load_modeset_init(struct drm_device *dev,
1230                                   unsigned long prealloc_start,
1231                                   unsigned long prealloc_size,
1232                                   unsigned long agp_size)
1233 {
1234         struct drm_i915_private *dev_priv = dev->dev_private;
1235         int fb_bar = IS_I9XX(dev) ? 2 : 0;
1236         int ret = 0;
1237
1238         dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) &
1239                 0xff000000;
1240
1241         /* Basic memrange allocator for stolen space (aka vram) */
1242         drm_mm_init(&dev_priv->vram, 0, prealloc_size);
1243         DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
1244
1245         /* We're off and running w/KMS */
1246         dev_priv->mm.suspended = 0;
1247
1248         /* Let GEM Manage from end of prealloc space to end of aperture.
1249          *
1250          * However, leave one page at the end still bound to the scratch page.
1251          * There are a number of places where the hardware apparently
1252          * prefetches past the end of the object, and we've seen multiple
1253          * hangs with the GPU head pointer stuck in a batchbuffer bound
1254          * at the last page of the aperture.  One page should be enough to
1255          * keep any prefetching inside of the aperture.
1256          */
1257         i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
1258
1259         mutex_lock(&dev->struct_mutex);
1260         ret = i915_gem_init_ringbuffer(dev);
1261         mutex_unlock(&dev->struct_mutex);
1262         if (ret)
1263                 goto out;
1264
1265         /* Try to set up FBC with a reasonable compressed buffer size */
1266         if (I915_HAS_FBC(dev) && i915_powersave) {
1267                 int cfb_size;
1268
1269                 /* Try to get an 8M buffer... */
1270                 if (prealloc_size > (9*1024*1024))
1271                         cfb_size = 8*1024*1024;
1272                 else /* fall back to 7/8 of the stolen space */
1273                         cfb_size = prealloc_size * 7 / 8;
1274                 i915_setup_compression(dev, cfb_size);
1275         }
1276
1277         /* Allow hardware batchbuffers unless told otherwise.
1278          */
1279         dev_priv->allow_batchbuffer = 1;
1280
1281         ret = intel_init_bios(dev);
1282         if (ret)
1283                 DRM_INFO("failed to find VBIOS tables\n");
1284
1285         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1286         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1287         if (ret)
1288                 goto destroy_ringbuffer;
1289
1290         ret = vga_switcheroo_register_client(dev->pdev,
1291                                              i915_switcheroo_set_state,
1292                                              i915_switcheroo_can_switch);
1293         if (ret)
1294                 goto destroy_ringbuffer;
1295
1296         intel_modeset_init(dev);
1297
1298         ret = drm_irq_install(dev);
1299         if (ret)
1300                 goto destroy_ringbuffer;
1301
1302         /* Always safe in the mode setting case. */
1303         /* FIXME: do pre/post-mode set stuff in core KMS code */
1304         dev->vblank_disable_allowed = 1;
1305
1306         /*
1307          * Initialize the hardware status page IRQ location.
1308          */
1309
1310         I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
1311
1312         drm_helper_initial_config(dev);
1313
1314         return 0;
1315
1316 destroy_ringbuffer:
1317         i915_gem_cleanup_ringbuffer(dev);
1318 out:
1319         return ret;
1320 }
1321
1322 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1323 {
1324         struct drm_i915_master_private *master_priv;
1325
1326         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1327         if (!master_priv)
1328                 return -ENOMEM;
1329
1330         master->driver_priv = master_priv;
1331         return 0;
1332 }
1333
1334 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1335 {
1336         struct drm_i915_master_private *master_priv = master->driver_priv;
1337
1338         if (!master_priv)
1339                 return;
1340
1341         kfree(master_priv);
1342
1343         master->driver_priv = NULL;
1344 }
1345
1346 static void i915_get_mem_freq(struct drm_device *dev)
1347 {
1348         drm_i915_private_t *dev_priv = dev->dev_private;
1349         u32 tmp;
1350
1351         if (!IS_PINEVIEW(dev))
1352                 return;
1353
1354         tmp = I915_READ(CLKCFG);
1355
1356         switch (tmp & CLKCFG_FSB_MASK) {
1357         case CLKCFG_FSB_533:
1358                 dev_priv->fsb_freq = 533; /* 133*4 */
1359                 break;
1360         case CLKCFG_FSB_800:
1361                 dev_priv->fsb_freq = 800; /* 200*4 */
1362                 break;
1363         case CLKCFG_FSB_667:
1364                 dev_priv->fsb_freq =  667; /* 167*4 */
1365                 break;
1366         case CLKCFG_FSB_400:
1367                 dev_priv->fsb_freq = 400; /* 100*4 */
1368                 break;
1369         }
1370
1371         switch (tmp & CLKCFG_MEM_MASK) {
1372         case CLKCFG_MEM_533:
1373                 dev_priv->mem_freq = 533;
1374                 break;
1375         case CLKCFG_MEM_667:
1376                 dev_priv->mem_freq = 667;
1377                 break;
1378         case CLKCFG_MEM_800:
1379                 dev_priv->mem_freq = 800;
1380                 break;
1381         }
1382 }
1383
1384 /**
1385  * i915_driver_load - setup chip and create an initial config
1386  * @dev: DRM device
1387  * @flags: startup flags
1388  *
1389  * The driver load routine has to do several things:
1390  *   - drive output discovery via intel_modeset_init()
1391  *   - initialize the memory manager
1392  *   - allocate initial config memory
1393  *   - setup the DRM framebuffer with the allocated memory
1394  */
1395 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1396 {
1397         struct drm_i915_private *dev_priv = dev->dev_private;
1398         resource_size_t base, size;
1399         int ret = 0, mmio_bar;
1400         uint32_t agp_size, prealloc_size, prealloc_start;
1401
1402         /* i915 has 4 more counters */
1403         dev->counters += 4;
1404         dev->types[6] = _DRM_STAT_IRQ;
1405         dev->types[7] = _DRM_STAT_PRIMARY;
1406         dev->types[8] = _DRM_STAT_SECONDARY;
1407         dev->types[9] = _DRM_STAT_DMA;
1408
1409         dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1410         if (dev_priv == NULL)
1411                 return -ENOMEM;
1412
1413         dev->dev_private = (void *)dev_priv;
1414         dev_priv->dev = dev;
1415         dev_priv->info = (struct intel_device_info *) flags;
1416
1417         /* Add register map (needed for suspend/resume) */
1418         mmio_bar = IS_I9XX(dev) ? 0 : 1;
1419         base = drm_get_resource_start(dev, mmio_bar);
1420         size = drm_get_resource_len(dev, mmio_bar);
1421
1422         if (i915_get_bridge_dev(dev)) {
1423                 ret = -EIO;
1424                 goto free_priv;
1425         }
1426
1427         dev_priv->regs = ioremap(base, size);
1428         if (!dev_priv->regs) {
1429                 DRM_ERROR("failed to map registers\n");
1430                 ret = -EIO;
1431                 goto put_bridge;
1432         }
1433
1434         dev_priv->mm.gtt_mapping =
1435                 io_mapping_create_wc(dev->agp->base,
1436                                      dev->agp->agp_info.aper_size * 1024*1024);
1437         if (dev_priv->mm.gtt_mapping == NULL) {
1438                 ret = -EIO;
1439                 goto out_rmmap;
1440         }
1441
1442         /* Set up a WC MTRR for non-PAT systems.  This is more common than
1443          * one would think, because the kernel disables PAT on first
1444          * generation Core chips because WC PAT gets overridden by a UC
1445          * MTRR if present.  Even if a UC MTRR isn't present.
1446          */
1447         dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
1448                                          dev->agp->agp_info.aper_size *
1449                                          1024 * 1024,
1450                                          MTRR_TYPE_WRCOMB, 1);
1451         if (dev_priv->mm.gtt_mtrr < 0) {
1452                 DRM_INFO("MTRR allocation failed.  Graphics "
1453                          "performance may suffer.\n");
1454         }
1455
1456         ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start);
1457         if (ret)
1458                 goto out_iomapfree;
1459
1460         dev_priv->wq = create_singlethread_workqueue("i915");
1461         if (dev_priv->wq == NULL) {
1462                 DRM_ERROR("Failed to create our workqueue.\n");
1463                 ret = -ENOMEM;
1464                 goto out_iomapfree;
1465         }
1466
1467         /* enable GEM by default */
1468         dev_priv->has_gem = 1;
1469
1470         if (prealloc_size > agp_size * 3 / 4) {
1471                 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
1472                           "memory stolen.\n",
1473                           prealloc_size / 1024, agp_size / 1024);
1474                 DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
1475                           "updating the BIOS to fix).\n");
1476                 dev_priv->has_gem = 0;
1477         }
1478
1479         dev->driver->get_vblank_counter = i915_get_vblank_counter;
1480         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1481         if (IS_G4X(dev) || IS_IRONLAKE(dev)) {
1482                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
1483                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
1484         }
1485
1486         i915_gem_load(dev);
1487
1488         /* Init HWS */
1489         if (!I915_NEED_GFX_HWS(dev)) {
1490                 ret = i915_init_phys_hws(dev);
1491                 if (ret != 0)
1492                         goto out_workqueue_free;
1493         }
1494
1495         i915_get_mem_freq(dev);
1496
1497         /* On the 945G/GM, the chipset reports the MSI capability on the
1498          * integrated graphics even though the support isn't actually there
1499          * according to the published specs.  It doesn't appear to function
1500          * correctly in testing on 945G.
1501          * This may be a side effect of MSI having been made available for PEG
1502          * and the registers being closely associated.
1503          *
1504          * According to chipset errata, on the 965GM, MSI interrupts may
1505          * be lost or delayed, but we use them anyways to avoid
1506          * stuck interrupts on some machines.
1507          */
1508         if (!IS_I945G(dev) && !IS_I945GM(dev))
1509                 pci_enable_msi(dev->pdev);
1510
1511         spin_lock_init(&dev_priv->user_irq_lock);
1512         spin_lock_init(&dev_priv->error_lock);
1513         dev_priv->user_irq_refcount = 0;
1514         dev_priv->trace_irq_seqno = 0;
1515
1516         ret = drm_vblank_init(dev, I915_NUM_PIPE);
1517
1518         if (ret) {
1519                 (void) i915_driver_unload(dev);
1520                 return ret;
1521         }
1522
1523         /* Start out suspended */
1524         dev_priv->mm.suspended = 1;
1525
1526         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1527                 ret = i915_load_modeset_init(dev, prealloc_start,
1528                                              prealloc_size, agp_size);
1529                 if (ret < 0) {
1530                         DRM_ERROR("failed to init modeset\n");
1531                         goto out_workqueue_free;
1532                 }
1533         }
1534
1535         /* Must be done after probing outputs */
1536         intel_opregion_init(dev, 0);
1537
1538         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
1539                     (unsigned long) dev);
1540         return 0;
1541
1542 out_workqueue_free:
1543         destroy_workqueue(dev_priv->wq);
1544 out_iomapfree:
1545         io_mapping_free(dev_priv->mm.gtt_mapping);
1546 out_rmmap:
1547         iounmap(dev_priv->regs);
1548 put_bridge:
1549         pci_dev_put(dev_priv->bridge_dev);
1550 free_priv:
1551         kfree(dev_priv);
1552         return ret;
1553 }
1554
1555 int i915_driver_unload(struct drm_device *dev)
1556 {
1557         struct drm_i915_private *dev_priv = dev->dev_private;
1558
1559         destroy_workqueue(dev_priv->wq);
1560         del_timer_sync(&dev_priv->hangcheck_timer);
1561
1562         io_mapping_free(dev_priv->mm.gtt_mapping);
1563         if (dev_priv->mm.gtt_mtrr >= 0) {
1564                 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
1565                          dev->agp->agp_info.aper_size * 1024 * 1024);
1566                 dev_priv->mm.gtt_mtrr = -1;
1567         }
1568
1569         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1570                 /*
1571                  * free the memory space allocated for the child device
1572                  * config parsed from VBT
1573                  */
1574                 if (dev_priv->child_dev && dev_priv->child_dev_num) {
1575                         kfree(dev_priv->child_dev);
1576                         dev_priv->child_dev = NULL;
1577                         dev_priv->child_dev_num = 0;
1578                 }
1579                 drm_irq_uninstall(dev);
1580                 vga_switcheroo_unregister_client(dev->pdev);
1581                 vga_client_register(dev->pdev, NULL, NULL, NULL);
1582         }
1583
1584         if (dev->pdev->msi_enabled)
1585                 pci_disable_msi(dev->pdev);
1586
1587         if (dev_priv->regs != NULL)
1588                 iounmap(dev_priv->regs);
1589
1590         intel_opregion_free(dev, 0);
1591
1592         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1593                 intel_modeset_cleanup(dev);
1594
1595                 i915_gem_free_all_phys_object(dev);
1596
1597                 mutex_lock(&dev->struct_mutex);
1598                 i915_gem_cleanup_ringbuffer(dev);
1599                 mutex_unlock(&dev->struct_mutex);
1600                 drm_mm_takedown(&dev_priv->vram);
1601                 i915_gem_lastclose(dev);
1602
1603                 intel_cleanup_overlay(dev);
1604         }
1605
1606         pci_dev_put(dev_priv->bridge_dev);
1607         kfree(dev->dev_private);
1608
1609         return 0;
1610 }
1611
1612 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1613 {
1614         struct drm_i915_file_private *i915_file_priv;
1615
1616         DRM_DEBUG_DRIVER("\n");
1617         i915_file_priv = (struct drm_i915_file_private *)
1618             kmalloc(sizeof(*i915_file_priv), GFP_KERNEL);
1619
1620         if (!i915_file_priv)
1621                 return -ENOMEM;
1622
1623         file_priv->driver_priv = i915_file_priv;
1624
1625         INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
1626
1627         return 0;
1628 }
1629
1630 /**
1631  * i915_driver_lastclose - clean up after all DRM clients have exited
1632  * @dev: DRM device
1633  *
1634  * Take care of cleaning up after all DRM clients have exited.  In the
1635  * mode setting case, we want to restore the kernel's initial mode (just
1636  * in case the last client left us in a bad state).
1637  *
1638  * Additionally, in the non-mode setting case, we'll tear down the AGP
1639  * and DMA structures, since the kernel won't be using them, and clea
1640  * up any GEM state.
1641  */
1642 void i915_driver_lastclose(struct drm_device * dev)
1643 {
1644         drm_i915_private_t *dev_priv = dev->dev_private;
1645
1646         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1647                 drm_fb_helper_restore();
1648                 vga_switcheroo_process_delayed_switch();
1649                 return;
1650         }
1651
1652         i915_gem_lastclose(dev);
1653
1654         if (dev_priv->agp_heap)
1655                 i915_mem_takedown(&(dev_priv->agp_heap));
1656
1657         i915_dma_cleanup(dev);
1658 }
1659
1660 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1661 {
1662         drm_i915_private_t *dev_priv = dev->dev_private;
1663         i915_gem_release(dev, file_priv);
1664         if (!drm_core_check_feature(dev, DRIVER_MODESET))
1665                 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
1666 }
1667
1668 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1669 {
1670         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1671
1672         kfree(i915_file_priv);
1673 }
1674
1675 struct drm_ioctl_desc i915_ioctls[] = {
1676         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1677         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1678         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1679         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1680         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1681         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1682         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1683         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1684         DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
1685         DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
1686         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1687         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1688         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1689         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1690         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
1691         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1692         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1693         DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1694         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
1695         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH),
1696         DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1697         DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1698         DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH),
1699         DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
1700         DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1701         DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1702         DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
1703         DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0),
1704         DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0),
1705         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
1706         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, 0),
1707         DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0),
1708         DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0),
1709         DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
1710         DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
1711         DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0),
1712         DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
1713         DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, 0),
1714         DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW),
1715         DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW),
1716 };
1717
1718 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1719
1720 /**
1721  * Determine if the device really is AGP or not.
1722  *
1723  * All Intel graphics chipsets are treated as AGP, even if they are really
1724  * PCI-e.
1725  *
1726  * \param dev   The device to be tested.
1727  *
1728  * \returns
1729  * A value of 1 is always retured to indictate every i9x5 is AGP.
1730  */
1731 int i915_driver_device_is_agp(struct drm_device * dev)
1732 {
1733         return 1;
1734 }