SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "drm_crtc_helper.h"
  32 #include "drm_fb_helper.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36
  37 /* Really want an OS-independent resettable timer.  Would like to have
  38  * this loop run for (eg) 3 sec, but have the timer reset every time
  39  * the head pointer changes, so that EBUSY only happens if the ring
  40  * actually stalls for (eg) 3 seconds.
  41  */
  42 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
  43 {
  44         drm_i915_private_t *dev_priv = dev->dev_private;
  45         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  46         u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
  47         u32 last_acthd = I915_READ(acthd_reg);
  48         u32 acthd;
  49         u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  50         int i;
  51
  52         for (i = 0; i < 100000; i++) {
  53                 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  54                 acthd = I915_READ(acthd_reg);
  55                 ring->space = ring->head - (ring->tail + 8);
  56                 if (ring->space < 0)
  57                         ring->space += ring->Size;
  58                 if (ring->space >= n)
  59                         return 0;
  60
  61                 if (dev->primary->master) {
  62                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  63                         if (master_priv->sarea_priv)
  64                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
  65                 }
  66
  67
  68                 if (ring->head != last_head)
  69                         i = 0;
  70                 if (acthd != last_acthd)
  71                         i = 0;
  72
  73                 last_head = ring->head;
  74                 last_acthd = acthd;
  75                 msleep_interruptible(10);
  76
  77         }
  78
  79         return -EBUSY;
  80 }
  81
  82 /* As a ringbuffer is only allowed to wrap between instructions, fill
  83  * the tail with NOOPs.
  84  */
  85 int i915_wrap_ring(struct drm_device *dev)
  86 {
  87         drm_i915_private_t *dev_priv = dev->dev_private;
  88         volatile unsigned int *virt;
  89         int rem;
  90
  91         rem = dev_priv->ring.Size - dev_priv->ring.tail;
  92         if (dev_priv->ring.space < rem) {
  93                 int ret = i915_wait_ring(dev, rem, __func__);
  94                 if (ret)
  95                         return ret;
  96         }
  97         dev_priv->ring.space -= rem;
  98
  99         virt = (unsigned int *)
 100                 (dev_priv->ring.virtual_start + dev_priv->ring.tail);
 101         rem /= 4;
 102         while (rem--)
 103                 *virt++ = MI_NOOP;
 104
 105         dev_priv->ring.tail = 0;
 106
 107         return 0;
 108 }
 109
 110 /**
 111  * Sets up the hardware status page for devices that need a physical address
 112  * in the register.
 113  */
 114 static int i915_init_phys_hws(struct drm_device *dev)
 115 {
 116         drm_i915_private_t *dev_priv = dev->dev_private;
 117         /* Program Hardware Status Page */
 118         dev_priv->status_page_dmah =
 119                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
 120
 121         if (!dev_priv->status_page_dmah) {
 122                 DRM_ERROR("Can not allocate hardware status page\n");
 123                 return -ENOMEM;
 124         }
 125         dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
 126         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
 127
 128         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 129
 130         I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
 131         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 132         return 0;
 133 }
 134
 135 /**
 136  * Frees the hardware status page, whether it's a physical address or a virtual
 137  * address set up by the X Server.
 138  */
 139 static void i915_free_hws(struct drm_device *dev)
 140 {
 141         drm_i915_private_t *dev_priv = dev->dev_private;
 142         if (dev_priv->status_page_dmah) {
 143                 drm_pci_free(dev, dev_priv->status_page_dmah);
 144                 dev_priv->status_page_dmah = NULL;
 145         }
 146
 147         if (dev_priv->status_gfx_addr) {
 148                 dev_priv->status_gfx_addr = 0;
 149                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 150         }
 151
 152         /* Need to rewrite hardware status page */
 153         I915_WRITE(HWS_PGA, 0x1ffff000);
 154 }
 155
 156 void i915_kernel_lost_context(struct drm_device * dev)
 157 {
 158         drm_i915_private_t *dev_priv = dev->dev_private;
 159         struct drm_i915_master_private *master_priv;
 160         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
 161
 162         /*
 163          * We should never lose context on the ring with modesetting
 164          * as we don't expose it to userspace
 165          */
 166         if (drm_core_check_feature(dev, DRIVER_MODESET))
 167                 return;
 168
 169         ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 170         ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
 171         ring->space = ring->head - (ring->tail + 8);
 172         if (ring->space < 0)
 173                 ring->space += ring->Size;
 174
 175         if (!dev->primary->master)
 176                 return;
 177
 178         master_priv = dev->primary->master->driver_priv;
 179         if (ring->head == ring->tail && master_priv->sarea_priv)
 180                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 181 }
 182
 183 static int i915_dma_cleanup(struct drm_device * dev)
 184 {
 185         drm_i915_private_t *dev_priv = dev->dev_private;
 186         /* Make sure interrupts are disabled here because the uninstall ioctl
 187          * may not have been called from userspace and after dev_private
 188          * is freed, it's too late.
 189          */
 190         if (dev->irq_enabled)
 191                 drm_irq_uninstall(dev);
 192
 193         if (dev_priv->ring.virtual_start) {
 194                 drm_core_ioremapfree(&dev_priv->ring.map, dev);
 195                 dev_priv->ring.virtual_start = NULL;
 196                 dev_priv->ring.map.handle = NULL;
 197                 dev_priv->ring.map.size = 0;
 198         }
 199
 200         /* Clear the HWS virtual address at teardown */
 201         if (I915_NEED_GFX_HWS(dev))
 202                 i915_free_hws(dev);
 203
 204         return 0;
 205 }
 206
 207 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 208 {
 209         drm_i915_private_t *dev_priv = dev->dev_private;
 210         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 211
 212         master_priv->sarea = drm_getsarea(dev);
 213         if (master_priv->sarea) {
 214                 master_priv->sarea_priv = (drm_i915_sarea_t *)
 215                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
 216         } else {
 217                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
 218         }
 219
 220         if (init->ring_size != 0) {
 221                 if (dev_priv->ring.ring_obj != NULL) {
 222                         i915_dma_cleanup(dev);
 223                         DRM_ERROR("Client tried to initialize ringbuffer in "
 224                                   "GEM mode\n");
 225                         return -EINVAL;
 226                 }
 227
 228                 dev_priv->ring.Size = init->ring_size;
 229
 230                 dev_priv->ring.map.offset = init->ring_start;
 231                 dev_priv->ring.map.size = init->ring_size;
 232                 dev_priv->ring.map.type = 0;
 233                 dev_priv->ring.map.flags = 0;
 234                 dev_priv->ring.map.mtrr = 0;
 235
 236                 drm_core_ioremap_wc(&dev_priv->ring.map, dev);
 237
 238                 if (dev_priv->ring.map.handle == NULL) {
 239                         i915_dma_cleanup(dev);
 240                         DRM_ERROR("can not ioremap virtual address for"
 241                                   " ring buffer\n");
 242                         return -ENOMEM;
 243                 }
 244         }
 245
 246         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 247
 248         dev_priv->cpp = init->cpp;
 249         dev_priv->back_offset = init->back_offset;
 250         dev_priv->front_offset = init->front_offset;
 251         dev_priv->current_page = 0;
 252         if (master_priv->sarea_priv)
 253                 master_priv->sarea_priv->pf_current_page = 0;
 254
 255         /* Allow hardware batchbuffers unless told otherwise.
 256          */
 257         dev_priv->allow_batchbuffer = 1;
 258
 259         return 0;
 260 }
 261
 262 static int i915_dma_resume(struct drm_device * dev)
 263 {
 264         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 265
 266         DRM_DEBUG_DRIVER("%s\n", __func__);
 267
 268         if (dev_priv->ring.map.handle == NULL) {
 269                 DRM_ERROR("can not ioremap virtual address for"
 270                           " ring buffer\n");
 271                 return -ENOMEM;
 272         }
 273
 274         /* Program Hardware Status Page */
 275         if (!dev_priv->hw_status_page) {
 276                 DRM_ERROR("Can not find hardware status page\n");
 277                 return -EINVAL;
 278         }
 279         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 280                                 dev_priv->hw_status_page);
 281
 282         if (dev_priv->status_gfx_addr != 0)
 283                 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
 284         else
 285                 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
 286         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 287
 288         return 0;
 289 }
 290
 291 static int i915_dma_init(struct drm_device *dev, void *data,
 292                          struct drm_file *file_priv)
 293 {
 294         drm_i915_init_t *init = data;
 295         int retcode = 0;
 296
 297         switch (init->func) {
 298         case I915_INIT_DMA:
 299                 retcode = i915_initialize(dev, init);
 300                 break;
 301         case I915_CLEANUP_DMA:
 302                 retcode = i915_dma_cleanup(dev);
 303                 break;
 304         case I915_RESUME_DMA:
 305                 retcode = i915_dma_resume(dev);
 306                 break;
 307         default:
 308                 retcode = -EINVAL;
 309                 break;
 310         }
 311
 312         return retcode;
 313 }
 314
 315 /* Implement basically the same security restrictions as hardware does
 316  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 317  *
 318  * Most of the calculations below involve calculating the size of a
 319  * particular instruction.  It's important to get the size right as
 320  * that tells us where the next instruction to check is.  Any illegal
 321  * instruction detected will be given a size of zero, which is a
 322  * signal to abort the rest of the buffer.
 323  */
 324 static int do_validate_cmd(int cmd)
 325 {
 326         switch (((cmd >> 29) & 0x7)) {
 327         case 0x0:
 328                 switch ((cmd >> 23) & 0x3f) {
 329                 case 0x0:
 330                         return 1;       /* MI_NOOP */
 331                 case 0x4:
 332                         return 1;       /* MI_FLUSH */
 333                 default:
 334                         return 0;       /* disallow everything else */
 335                 }
 336                 break;
 337         case 0x1:
 338                 return 0;       /* reserved */
 339         case 0x2:
 340                 return (cmd & 0xff) + 2;        /* 2d commands */
 341         case 0x3:
 342                 if (((cmd >> 24) & 0x1f) <= 0x18)
 343                         return 1;
 344
 345                 switch ((cmd >> 24) & 0x1f) {
 346                 case 0x1c:
 347                         return 1;
 348                 case 0x1d:
 349                         switch ((cmd >> 16) & 0xff) {
 350                         case 0x3:
 351                                 return (cmd & 0x1f) + 2;
 352                         case 0x4:
 353                                 return (cmd & 0xf) + 2;
 354                         default:
 355                                 return (cmd & 0xffff) + 2;
 356                         }
 357                 case 0x1e:
 358                         if (cmd & (1 << 23))
 359                                 return (cmd & 0xffff) + 1;
 360                         else
 361                                 return 1;
 362                 case 0x1f:
 363                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 364                                 return (cmd & 0x1ffff) + 2;
 365                         else if (cmd & (1 << 17))       /* indirect random */
 366                                 if ((cmd & 0xffff) == 0)
 367                                         return 0;       /* unknown length, too hard */
 368                                 else
 369                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 370                         else
 371                                 return 2;       /* indirect sequential */
 372                 default:
 373                         return 0;
 374                 }
 375         default:
 376                 return 0;
 377         }
 378
 379         return 0;
 380 }
 381
 382 static int validate_cmd(int cmd)
 383 {
 384         int ret = do_validate_cmd(cmd);
 385
 386 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 387
 388         return ret;
 389 }
 390
 391 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 392 {
 393         drm_i915_private_t *dev_priv = dev->dev_private;
 394         int i;
 395         RING_LOCALS;
 396
 397         if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
 398                 return -EINVAL;
 399
 400         BEGIN_LP_RING((dwords+1)&~1);
 401
 402         for (i = 0; i < dwords;) {
 403                 int cmd, sz;
 404
 405                 cmd = buffer[i];
 406
 407                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 408                         return -EINVAL;
 409
 410                 OUT_RING(cmd);
 411
 412                 while (++i, --sz) {
 413                         OUT_RING(buffer[i]);
 414                 }
 415         }
 416
 417         if (dwords & 1)
 418                 OUT_RING(0);
 419
 420         ADVANCE_LP_RING();
 421
 422         return 0;
 423 }
 424
 425 int
 426 i915_emit_box(struct drm_device *dev,
 427               struct drm_clip_rect *boxes,
 428               int i, int DR1, int DR4)
 429 {
 430         drm_i915_private_t *dev_priv = dev->dev_private;
 431         struct drm_clip_rect box = boxes[i];
 432         RING_LOCALS;
 433
 434         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 435                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 436                           box.x1, box.y1, box.x2, box.y2);
 437                 return -EINVAL;
 438         }
 439
 440         if (IS_I965G(dev)) {
 441                 BEGIN_LP_RING(4);
 442                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 443                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 444                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 445                 OUT_RING(DR4);
 446                 ADVANCE_LP_RING();
 447         } else {
 448                 BEGIN_LP_RING(6);
 449                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 450                 OUT_RING(DR1);
 451                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 452                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 453                 OUT_RING(DR4);
 454                 OUT_RING(0);
 455                 ADVANCE_LP_RING();
 456         }
 457
 458         return 0;
 459 }
 460
 461 /* XXX: Emitting the counter should really be moved to part of the IRQ
 462  * emit. For now, do it in both places:
 463  */
 464
 465 static void i915_emit_breadcrumb(struct drm_device *dev)
 466 {
 467         drm_i915_private_t *dev_priv = dev->dev_private;
 468         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 469         RING_LOCALS;
 470
 471         dev_priv->counter++;
 472         if (dev_priv->counter > 0x7FFFFFFFUL)
 473                 dev_priv->counter = 0;
 474         if (master_priv->sarea_priv)
 475                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 476
 477         BEGIN_LP_RING(4);
 478         OUT_RING(MI_STORE_DWORD_INDEX);
 479         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 480         OUT_RING(dev_priv->counter);
 481         OUT_RING(0);
 482         ADVANCE_LP_RING();
 483 }
 484
 485 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 486                                    drm_i915_cmdbuffer_t *cmd,
 487                                    struct drm_clip_rect *cliprects,
 488                                    void *cmdbuf)
 489 {
 490         int nbox = cmd->num_cliprects;
 491         int i = 0, count, ret;
 492
 493         if (cmd->sz & 0x3) {
 494                 DRM_ERROR("alignment");
 495                 return -EINVAL;
 496         }
 497
 498         i915_kernel_lost_context(dev);
 499
 500         count = nbox ? nbox : 1;
 501
 502         for (i = 0; i < count; i++) {
 503                 if (i < nbox) {
 504                         ret = i915_emit_box(dev, cliprects, i,
 505                                             cmd->DR1, cmd->DR4);
 506                         if (ret)
 507                                 return ret;
 508                 }
 509
 510                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 511                 if (ret)
 512                         return ret;
 513         }
 514
 515         i915_emit_breadcrumb(dev);
 516         return 0;
 517 }
 518
 519 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 520                                      drm_i915_batchbuffer_t * batch,
 521                                      struct drm_clip_rect *cliprects)
 522 {
 523         drm_i915_private_t *dev_priv = dev->dev_private;
 524         int nbox = batch->num_cliprects;
 525         int i = 0, count;
 526         RING_LOCALS;
 527
 528         if ((batch->start | batch->used) & 0x7) {
 529                 DRM_ERROR("alignment");
 530                 return -EINVAL;
 531         }
 532
 533         i915_kernel_lost_context(dev);
 534
 535         count = nbox ? nbox : 1;
 536
 537         for (i = 0; i < count; i++) {
 538                 if (i < nbox) {
 539                         int ret = i915_emit_box(dev, cliprects, i,
 540                                                 batch->DR1, batch->DR4);
 541                         if (ret)
 542                                 return ret;
 543                 }
 544
 545                 if (!IS_I830(dev) && !IS_845G(dev)) {
 546                         BEGIN_LP_RING(2);
 547                         if (IS_I965G(dev)) {
 548                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 549                                 OUT_RING(batch->start);
 550                         } else {
 551                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 552                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 553                         }
 554                         ADVANCE_LP_RING();
 555                 } else {
 556                         BEGIN_LP_RING(4);
 557                         OUT_RING(MI_BATCH_BUFFER);
 558                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 559                         OUT_RING(batch->start + batch->used - 4);
 560                         OUT_RING(0);
 561                         ADVANCE_LP_RING();
 562                 }
 563         }
 564
 565         i915_emit_breadcrumb(dev);
 566
 567         return 0;
 568 }
 569
 570 static int i915_dispatch_flip(struct drm_device * dev)
 571 {
 572         drm_i915_private_t *dev_priv = dev->dev_private;
 573         struct drm_i915_master_private *master_priv =
 574                 dev->primary->master->driver_priv;
 575         RING_LOCALS;
 576
 577         if (!master_priv->sarea_priv)
 578                 return -EINVAL;
 579
 580         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 581                           __func__,
 582                          dev_priv->current_page,
 583                          master_priv->sarea_priv->pf_current_page);
 584
 585         i915_kernel_lost_context(dev);
 586
 587         BEGIN_LP_RING(2);
 588         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 589         OUT_RING(0);
 590         ADVANCE_LP_RING();
 591
 592         BEGIN_LP_RING(6);
 593         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 594         OUT_RING(0);
 595         if (dev_priv->current_page == 0) {
 596                 OUT_RING(dev_priv->back_offset);
 597                 dev_priv->current_page = 1;
 598         } else {
 599                 OUT_RING(dev_priv->front_offset);
 600                 dev_priv->current_page = 0;
 601         }
 602         OUT_RING(0);
 603         ADVANCE_LP_RING();
 604
 605         BEGIN_LP_RING(2);
 606         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 607         OUT_RING(0);
 608         ADVANCE_LP_RING();
 609
 610         master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
 611
 612         BEGIN_LP_RING(4);
 613         OUT_RING(MI_STORE_DWORD_INDEX);
 614         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 615         OUT_RING(dev_priv->counter);
 616         OUT_RING(0);
 617         ADVANCE_LP_RING();
 618
 619         master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 620         return 0;
 621 }
 622
 623 static int i915_quiescent(struct drm_device * dev)
 624 {
 625         drm_i915_private_t *dev_priv = dev->dev_private;
 626
 627         i915_kernel_lost_context(dev);
 628         return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
 629 }
 630
 631 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 632                             struct drm_file *file_priv)
 633 {
 634         int ret;
 635
 636         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 637
 638         mutex_lock(&dev->struct_mutex);
 639         ret = i915_quiescent(dev);
 640         mutex_unlock(&dev->struct_mutex);
 641
 642         return ret;
 643 }
 644
 645 static int i915_batchbuffer(struct drm_device *dev, void *data,
 646                             struct drm_file *file_priv)
 647 {
 648         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 649         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 650         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 651             master_priv->sarea_priv;
 652         drm_i915_batchbuffer_t *batch = data;
 653         int ret;
 654         struct drm_clip_rect *cliprects = NULL;
 655
 656         if (!dev_priv->allow_batchbuffer) {
 657                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 658                 return -EINVAL;
 659         }
 660
 661         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 662                         batch->start, batch->used, batch->num_cliprects);
 663
 664         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 665
 666         if (batch->num_cliprects < 0)
 667                 return -EINVAL;
 668
 669         if (batch->num_cliprects) {
 670                 cliprects = kcalloc(batch->num_cliprects,
 671                                     sizeof(struct drm_clip_rect),
 672                                     GFP_KERNEL);
 673                 if (cliprects == NULL)
 674                         return -ENOMEM;
 675
 676                 ret = copy_from_user(cliprects, batch->cliprects,
 677                                      batch->num_cliprects *
 678                                      sizeof(struct drm_clip_rect));
 679                 if (ret != 0)
 680                         goto fail_free;
 681         }
 682
 683         mutex_lock(&dev->struct_mutex);
 684         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 685         mutex_unlock(&dev->struct_mutex);
 686
 687         if (sarea_priv)
 688                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 689
 690 fail_free:
 691         kfree(cliprects);
 692
 693         return ret;
 694 }
 695
 696 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 697                           struct drm_file *file_priv)
 698 {
 699         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 700         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 701         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 702             master_priv->sarea_priv;
 703         drm_i915_cmdbuffer_t *cmdbuf = data;
 704         struct drm_clip_rect *cliprects = NULL;
 705         void *batch_data;
 706         int ret;
 707
 708         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 709                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 710
 711         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 712
 713         if (cmdbuf->num_cliprects < 0)
 714                 return -EINVAL;
 715
 716         batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
 717         if (batch_data == NULL)
 718                 return -ENOMEM;
 719
 720         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 721         if (ret != 0)
 722                 goto fail_batch_free;
 723
 724         if (cmdbuf->num_cliprects) {
 725                 cliprects = kcalloc(cmdbuf->num_cliprects,
 726                                     sizeof(struct drm_clip_rect), GFP_KERNEL);
 727                 if (cliprects == NULL)
 728                         goto fail_batch_free;
 729
 730                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 731                                      cmdbuf->num_cliprects *
 732                                      sizeof(struct drm_clip_rect));
 733                 if (ret != 0)
 734                         goto fail_clip_free;
 735         }
 736
 737         mutex_lock(&dev->struct_mutex);
 738         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 739         mutex_unlock(&dev->struct_mutex);
 740         if (ret) {
 741                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 742                 goto fail_clip_free;
 743         }
 744
 745         if (sarea_priv)
 746                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 747
 748 fail_clip_free:
 749         kfree(cliprects);
 750 fail_batch_free:
 751         kfree(batch_data);
 752
 753         return ret;
 754 }
 755
 756 static int i915_flip_bufs(struct drm_device *dev, void *data,
 757                           struct drm_file *file_priv)
 758 {
 759         int ret;
 760
 761         DRM_DEBUG_DRIVER("%s\n", __func__);
 762
 763         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 764
 765         mutex_lock(&dev->struct_mutex);
 766         ret = i915_dispatch_flip(dev);
 767         mutex_unlock(&dev->struct_mutex);
 768
 769         return ret;
 770 }
 771
 772 static int i915_getparam(struct drm_device *dev, void *data,
 773                          struct drm_file *file_priv)
 774 {
 775         drm_i915_private_t *dev_priv = dev->dev_private;
 776         drm_i915_getparam_t *param = data;
 777         int value;
 778
 779         if (!dev_priv) {
 780                 DRM_ERROR("called with no initialization\n");
 781                 return -EINVAL;
 782         }
 783
 784         switch (param->param) {
 785         case I915_PARAM_IRQ_ACTIVE:
 786                 value = dev->pdev->irq ? 1 : 0;
 787                 break;
 788         case I915_PARAM_ALLOW_BATCHBUFFER:
 789                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 790                 break;
 791         case I915_PARAM_LAST_DISPATCH:
 792                 value = READ_BREADCRUMB(dev_priv);
 793                 break;
 794         case I915_PARAM_CHIPSET_ID:
 795                 value = dev->pci_device;
 796                 break;
 797         case I915_PARAM_HAS_GEM:
 798                 value = dev_priv->has_gem;
 799                 break;
 800         case I915_PARAM_NUM_FENCES_AVAIL:
 801                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 802                 break;
 803         default:
 804                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 805                                         param->param);
 806                 return -EINVAL;
 807         }
 808
 809         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 810                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 811                 return -EFAULT;
 812         }
 813
 814         return 0;
 815 }
 816
 817 static int i915_setparam(struct drm_device *dev, void *data,
 818                          struct drm_file *file_priv)
 819 {
 820         drm_i915_private_t *dev_priv = dev->dev_private;
 821         drm_i915_setparam_t *param = data;
 822
 823         if (!dev_priv) {
 824                 DRM_ERROR("called with no initialization\n");
 825                 return -EINVAL;
 826         }
 827
 828         switch (param->param) {
 829         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 830                 break;
 831         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 832                 dev_priv->tex_lru_log_granularity = param->value;
 833                 break;
 834         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 835                 dev_priv->allow_batchbuffer = param->value;
 836                 break;
 837         case I915_SETPARAM_NUM_USED_FENCES:
 838                 if (param->value > dev_priv->num_fence_regs ||
 839                     param->value < 0)
 840                         return -EINVAL;
 841                 /* Userspace can use first N regs */
 842                 dev_priv->fence_reg_start = param->value;
 843                 break;
 844         default:
 845                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
 846                                         param->param);
 847                 return -EINVAL;
 848         }
 849
 850         return 0;
 851 }
 852
 853 static int i915_set_status_page(struct drm_device *dev, void *data,
 854                                 struct drm_file *file_priv)
 855 {
 856         drm_i915_private_t *dev_priv = dev->dev_private;
 857         drm_i915_hws_addr_t *hws = data;
 858
 859         if (!I915_NEED_GFX_HWS(dev))
 860                 return -EINVAL;
 861
 862         if (!dev_priv) {
 863                 DRM_ERROR("called with no initialization\n");
 864                 return -EINVAL;
 865         }
 866
 867         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 868                 WARN(1, "tried to set status page when mode setting active\n");
 869                 return 0;
 870         }
 871
 872         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
 873
 874         dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
 875
 876         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
 877         dev_priv->hws_map.size = 4*1024;
 878         dev_priv->hws_map.type = 0;
 879         dev_priv->hws_map.flags = 0;
 880         dev_priv->hws_map.mtrr = 0;
 881
 882         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
 883         if (dev_priv->hws_map.handle == NULL) {
 884                 i915_dma_cleanup(dev);
 885                 dev_priv->status_gfx_addr = 0;
 886                 DRM_ERROR("can not ioremap virtual address for"
 887                                 " G33 hw status page\n");
 888                 return -ENOMEM;
 889         }
 890         dev_priv->hw_status_page = dev_priv->hws_map.handle;
 891
 892         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 893         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
 894         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
 895                                 dev_priv->status_gfx_addr);
 896         DRM_DEBUG_DRIVER("load hws at %p\n",
 897                                 dev_priv->hw_status_page);
 898         return 0;
 899 }
 900
 901 static int i915_get_bridge_dev(struct drm_device *dev)
 902 {
 903         struct drm_i915_private *dev_priv = dev->dev_private;
 904
 905         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
 906         if (!dev_priv->bridge_dev) {
 907                 DRM_ERROR("bridge device not found\n");
 908                 return -1;
 909         }
 910         return 0;
 911 }
 912
 913 /**
 914  * i915_probe_agp - get AGP bootup configuration
 915  * @pdev: PCI device
 916  * @aperture_size: returns AGP aperture configured size
 917  * @preallocated_size: returns size of BIOS preallocated AGP space
 918  *
 919  * Since Intel integrated graphics are UMA, the BIOS has to set aside
 920  * some RAM for the framebuffer at early boot.  This code figures out
 921  * how much was set aside so we can use it for our own purposes.
 922  */
 923 static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
 924                           uint32_t *preallocated_size,
 925                           uint32_t *start)
 926 {
 927         struct drm_i915_private *dev_priv = dev->dev_private;
 928         u16 tmp = 0;
 929         unsigned long overhead;
 930         unsigned long stolen;
 931
 932         /* Get the fb aperture size and "stolen" memory amount. */
 933         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp);
 934
 935         *aperture_size = 1024 * 1024;
 936         *preallocated_size = 1024 * 1024;
 937
 938         switch (dev->pdev->device) {
 939         case PCI_DEVICE_ID_INTEL_82830_CGC:
 940         case PCI_DEVICE_ID_INTEL_82845G_IG:
 941         case PCI_DEVICE_ID_INTEL_82855GM_IG:
 942         case PCI_DEVICE_ID_INTEL_82865_IG:
 943                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
 944                         *aperture_size *= 64;
 945                 else
 946                         *aperture_size *= 128;
 947                 break;
 948         default:
 949                 /* 9xx supports large sizes, just look at the length */
 950                 *aperture_size = pci_resource_len(dev->pdev, 2);
 951                 break;
 952         }
 953
 954         /*
 955          * Some of the preallocated space is taken by the GTT
 956          * and popup.  GTT is 1K per MB of aperture size, and popup is 4K.
 957          */
 958         if (IS_G4X(dev) || IS_IGD(dev) || IS_IGDNG(dev))
 959                 overhead = 4096;
 960         else
 961                 overhead = (*aperture_size / 1024) + 4096;
 962
 963         switch (tmp & INTEL_GMCH_GMS_MASK) {
 964         case INTEL_855_GMCH_GMS_DISABLED:
 965                 DRM_ERROR("video memory is disabled\n");
 966                 return -1;
 967         case INTEL_855_GMCH_GMS_STOLEN_1M:
 968                 stolen = 1 * 1024 * 1024;
 969                 break;
 970         case INTEL_855_GMCH_GMS_STOLEN_4M:
 971                 stolen = 4 * 1024 * 1024;
 972                 break;
 973         case INTEL_855_GMCH_GMS_STOLEN_8M:
 974                 stolen = 8 * 1024 * 1024;
 975                 break;
 976         case INTEL_855_GMCH_GMS_STOLEN_16M:
 977                 stolen = 16 * 1024 * 1024;
 978                 break;
 979         case INTEL_855_GMCH_GMS_STOLEN_32M:
 980                 stolen = 32 * 1024 * 1024;
 981                 break;
 982         case INTEL_915G_GMCH_GMS_STOLEN_48M:
 983                 stolen = 48 * 1024 * 1024;
 984                 break;
 985         case INTEL_915G_GMCH_GMS_STOLEN_64M:
 986                 stolen = 64 * 1024 * 1024;
 987                 break;
 988         case INTEL_GMCH_GMS_STOLEN_128M:
 989                 stolen = 128 * 1024 * 1024;
 990                 break;
 991         case INTEL_GMCH_GMS_STOLEN_256M:
 992                 stolen = 256 * 1024 * 1024;
 993                 break;
 994         case INTEL_GMCH_GMS_STOLEN_96M:
 995                 stolen = 96 * 1024 * 1024;
 996                 break;
 997         case INTEL_GMCH_GMS_STOLEN_160M:
 998                 stolen = 160 * 1024 * 1024;
 999                 break;
1000         case INTEL_GMCH_GMS_STOLEN_224M:
1001                 stolen = 224 * 1024 * 1024;
1002                 break;
1003         case INTEL_GMCH_GMS_STOLEN_352M:
1004                 stolen = 352 * 1024 * 1024;
1005                 break;
1006         default:
1007                 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1008                         tmp & INTEL_GMCH_GMS_MASK);
1009                 return -1;
1010         }
1011         *preallocated_size = stolen - overhead;
1012         *start = overhead;
1013
1014         return 0;
1015 }
1016
1017 #define PTE_ADDRESS_MASK                0xfffff000
1018 #define PTE_ADDRESS_MASK_HIGH           0x000000f0 /* i915+ */
1019 #define PTE_MAPPING_TYPE_UNCACHED       (0 << 1)
1020 #define PTE_MAPPING_TYPE_DCACHE         (1 << 1) /* i830 only */
1021 #define PTE_MAPPING_TYPE_CACHED         (3 << 1)
1022 #define PTE_MAPPING_TYPE_MASK           (3 << 1)
1023 #define PTE_VALID                       (1 << 0)
1024
1025 /**
1026  * i915_gtt_to_phys - take a GTT address and turn it into a physical one
1027  * @dev: drm device
1028  * @gtt_addr: address to translate
1029  *
1030  * Some chip functions require allocations from stolen space but need the
1031  * physical address of the memory in question.  We use this routine
1032  * to get a physical address suitable for register programming from a given
1033  * GTT address.
1034  */
1035 static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1036                                       unsigned long gtt_addr)
1037 {
1038         unsigned long *gtt;
1039         unsigned long entry, phys;
1040         int gtt_bar = IS_I9XX(dev) ? 0 : 1;
1041         int gtt_offset, gtt_size;
1042
1043         if (IS_I965G(dev)) {
1044                 if (IS_G4X(dev) || IS_IGDNG(dev)) {
1045                         gtt_offset = 2*1024*1024;
1046                         gtt_size = 2*1024*1024;
1047                 } else {
1048                         gtt_offset = 512*1024;
1049                         gtt_size = 512*1024;
1050                 }
1051         } else {
1052                 gtt_bar = 3;
1053                 gtt_offset = 0;
1054                 gtt_size = pci_resource_len(dev->pdev, gtt_bar);
1055         }
1056
1057         gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
1058                          gtt_size);
1059         if (!gtt) {
1060                 DRM_ERROR("ioremap of GTT failed\n");
1061                 return 0;
1062         }
1063
1064         entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
1065
1066         DRM_DEBUG("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
1067
1068         /* Mask out these reserved bits on this hardware. */
1069         if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) ||
1070             IS_I945G(dev) || IS_I945GM(dev)) {
1071                 entry &= ~PTE_ADDRESS_MASK_HIGH;
1072         }
1073
1074         /* If it's not a mapping type we know, then bail. */
1075         if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
1076             (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) {
1077                 iounmap(gtt);
1078                 return 0;
1079         }
1080
1081         if (!(entry & PTE_VALID)) {
1082                 DRM_ERROR("bad GTT entry in stolen space\n");
1083                 iounmap(gtt);
1084                 return 0;
1085         }
1086
1087         iounmap(gtt);
1088
1089         phys =(entry & PTE_ADDRESS_MASK) |
1090                 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
1091
1092         DRM_DEBUG("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
1093
1094         return phys;
1095 }
1096
1097 static void i915_warn_stolen(struct drm_device *dev)
1098 {
1099         DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1100         DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1101 }
1102
1103 static void i915_setup_compression(struct drm_device *dev, int size)
1104 {
1105         struct drm_i915_private *dev_priv = dev->dev_private;
1106         struct drm_mm_node *compressed_fb, *compressed_llb;
1107         unsigned long cfb_base, ll_base;
1108
1109         /* Leave 1M for line length buffer & misc. */
1110         compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);
1111         if (!compressed_fb) {
1112                 i915_warn_stolen(dev);
1113                 return;
1114         }
1115
1116         compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1117         if (!compressed_fb) {
1118                 i915_warn_stolen(dev);
1119                 return;
1120         }
1121
1122         compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096, 4096, 0);
1123         if (!compressed_llb) {
1124                 i915_warn_stolen(dev);
1125                 return;
1126         }
1127
1128         compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
1129         if (!compressed_llb) {
1130                 i915_warn_stolen(dev);
1131                 return;
1132         }
1133
1134         dev_priv->cfb_size = size;
1135
1136         cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
1137         ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
1138         if (!cfb_base || !ll_base) {
1139                 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1140                 drm_mm_put_block(compressed_fb);
1141                 drm_mm_put_block(compressed_llb);
1142         }
1143
1144         i8xx_disable_fbc(dev);
1145
1146         DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
1147                   ll_base, size >> 20);
1148         I915_WRITE(FBC_CFB_BASE, cfb_base);
1149         I915_WRITE(FBC_LL_BASE, ll_base);
1150 }
1151
1152 static int i915_load_modeset_init(struct drm_device *dev,
1153                                   unsigned long prealloc_start,
1154                                   unsigned long prealloc_size,
1155                                   unsigned long agp_size)
1156 {
1157         struct drm_i915_private *dev_priv = dev->dev_private;
1158         int fb_bar = IS_I9XX(dev) ? 2 : 0;
1159         int ret = 0;
1160
1161         dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) &
1162                 0xff000000;
1163
1164         if (IS_MOBILE(dev) || IS_I9XX(dev))
1165                 dev_priv->cursor_needs_physical = true;
1166         else
1167                 dev_priv->cursor_needs_physical = false;
1168
1169         if (IS_I965G(dev) || IS_G33(dev))
1170                 dev_priv->cursor_needs_physical = false;
1171
1172         /* Basic memrange allocator for stolen space (aka vram) */
1173         drm_mm_init(&dev_priv->vram, 0, prealloc_size);
1174         DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
1175
1176         /* We're off and running w/KMS */
1177         dev_priv->mm.suspended = 0;
1178
1179         /* Let GEM Manage from end of prealloc space to end of aperture.
1180          *
1181          * However, leave one page at the end still bound to the scratch page.
1182          * There are a number of places where the hardware apparently
1183          * prefetches past the end of the object, and we've seen multiple
1184          * hangs with the GPU head pointer stuck in a batchbuffer bound
1185          * at the last page of the aperture.  One page should be enough to
1186          * keep any prefetching inside of the aperture.
1187          */
1188         i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
1189
1190         mutex_lock(&dev->struct_mutex);
1191         ret = i915_gem_init_ringbuffer(dev);
1192         mutex_unlock(&dev->struct_mutex);
1193         if (ret)
1194                 goto out;
1195
1196         /* Try to set up FBC with a reasonable compressed buffer size */
1197         if (IS_MOBILE(dev) && (IS_I9XX(dev) || IS_I965G(dev)) &&
1198             i915_powersave) {
1199                 int cfb_size;
1200
1201                 /* Try to get an 8M buffer... */
1202                 if (prealloc_size > (9*1024*1024))
1203                         cfb_size = 8*1024*1024;
1204                 else /* fall back to 7/8 of the stolen space */
1205                         cfb_size = prealloc_size * 7 / 8;
1206                 i915_setup_compression(dev, cfb_size);
1207         }
1208
1209         /* Allow hardware batchbuffers unless told otherwise.
1210          */
1211         dev_priv->allow_batchbuffer = 1;
1212
1213         ret = intel_init_bios(dev);
1214         if (ret)
1215                 DRM_INFO("failed to find VBIOS tables\n");
1216
1217         ret = drm_irq_install(dev);
1218         if (ret)
1219                 goto destroy_ringbuffer;
1220
1221         /* Always safe in the mode setting case. */
1222         /* FIXME: do pre/post-mode set stuff in core KMS code */
1223         dev->vblank_disable_allowed = 1;
1224
1225         /*
1226          * Initialize the hardware status page IRQ location.
1227          */
1228
1229         I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
1230
1231         intel_modeset_init(dev);
1232
1233         drm_helper_initial_config(dev);
1234
1235         return 0;
1236
1237 destroy_ringbuffer:
1238         i915_gem_cleanup_ringbuffer(dev);
1239 out:
1240         return ret;
1241 }
1242
1243 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1244 {
1245         struct drm_i915_master_private *master_priv;
1246
1247         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1248         if (!master_priv)
1249                 return -ENOMEM;
1250
1251         master->driver_priv = master_priv;
1252         return 0;
1253 }
1254
1255 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1256 {
1257         struct drm_i915_master_private *master_priv = master->driver_priv;
1258
1259         if (!master_priv)
1260                 return;
1261
1262         kfree(master_priv);
1263
1264         master->driver_priv = NULL;
1265 }
1266
1267 static void i915_get_mem_freq(struct drm_device *dev)
1268 {
1269         drm_i915_private_t *dev_priv = dev->dev_private;
1270         u32 tmp;
1271
1272         if (!IS_IGD(dev))
1273                 return;
1274
1275         tmp = I915_READ(CLKCFG);
1276
1277         switch (tmp & CLKCFG_FSB_MASK) {
1278         case CLKCFG_FSB_533:
1279                 dev_priv->fsb_freq = 533; /* 133*4 */
1280                 break;
1281         case CLKCFG_FSB_800:
1282                 dev_priv->fsb_freq = 800; /* 200*4 */
1283                 break;
1284         case CLKCFG_FSB_667:
1285                 dev_priv->fsb_freq =  667; /* 167*4 */
1286                 break;
1287         case CLKCFG_FSB_400:
1288                 dev_priv->fsb_freq = 400; /* 100*4 */
1289                 break;
1290         }
1291
1292         switch (tmp & CLKCFG_MEM_MASK) {
1293         case CLKCFG_MEM_533:
1294                 dev_priv->mem_freq = 533;
1295                 break;
1296         case CLKCFG_MEM_667:
1297                 dev_priv->mem_freq = 667;
1298                 break;
1299         case CLKCFG_MEM_800:
1300                 dev_priv->mem_freq = 800;
1301                 break;
1302         }
1303 }
1304
1305 /**
1306  * i915_driver_load - setup chip and create an initial config
1307  * @dev: DRM device
1308  * @flags: startup flags
1309  *
1310  * The driver load routine has to do several things:
1311  *   - drive output discovery via intel_modeset_init()
1312  *   - initialize the memory manager
1313  *   - allocate initial config memory
1314  *   - setup the DRM framebuffer with the allocated memory
1315  */
1316 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1317 {
1318         struct drm_i915_private *dev_priv = dev->dev_private;
1319         resource_size_t base, size;
1320         int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
1321         uint32_t agp_size, prealloc_size, prealloc_start;
1322
1323         /* i915 has 4 more counters */
1324         dev->counters += 4;
1325         dev->types[6] = _DRM_STAT_IRQ;
1326         dev->types[7] = _DRM_STAT_PRIMARY;
1327         dev->types[8] = _DRM_STAT_SECONDARY;
1328         dev->types[9] = _DRM_STAT_DMA;
1329
1330         dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1331         if (dev_priv == NULL)
1332                 return -ENOMEM;
1333
1334         dev->dev_private = (void *)dev_priv;
1335         dev_priv->dev = dev;
1336
1337         /* Add register map (needed for suspend/resume) */
1338         base = drm_get_resource_start(dev, mmio_bar);
1339         size = drm_get_resource_len(dev, mmio_bar);
1340
1341         if (i915_get_bridge_dev(dev)) {
1342                 ret = -EIO;
1343                 goto free_priv;
1344         }
1345
1346         dev_priv->regs = ioremap(base, size);
1347         if (!dev_priv->regs) {
1348                 DRM_ERROR("failed to map registers\n");
1349                 ret = -EIO;
1350                 goto put_bridge;
1351         }
1352
1353         dev_priv->mm.gtt_mapping =
1354                 io_mapping_create_wc(dev->agp->base,
1355                                      dev->agp->agp_info.aper_size * 1024*1024);
1356         if (dev_priv->mm.gtt_mapping == NULL) {
1357                 ret = -EIO;
1358                 goto out_rmmap;
1359         }
1360
1361         /* Set up a WC MTRR for non-PAT systems.  This is more common than
1362          * one would think, because the kernel disables PAT on first
1363          * generation Core chips because WC PAT gets overridden by a UC
1364          * MTRR if present.  Even if a UC MTRR isn't present.
1365          */
1366         dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
1367                                          dev->agp->agp_info.aper_size *
1368                                          1024 * 1024,
1369                                          MTRR_TYPE_WRCOMB, 1);
1370         if (dev_priv->mm.gtt_mtrr < 0) {
1371                 DRM_INFO("MTRR allocation failed.  Graphics "
1372                          "performance may suffer.\n");
1373         }
1374
1375         ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start);
1376         if (ret)
1377                 goto out_iomapfree;
1378
1379         dev_priv->wq = create_workqueue("i915");
1380         if (dev_priv->wq == NULL) {
1381                 DRM_ERROR("Failed to create our workqueue.\n");
1382                 ret = -ENOMEM;
1383                 goto out_iomapfree;
1384         }
1385
1386         /* enable GEM by default */
1387         dev_priv->has_gem = 1;
1388
1389         if (prealloc_size > agp_size * 3 / 4) {
1390                 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
1391                           "memory stolen.\n",
1392                           prealloc_size / 1024, agp_size / 1024);
1393                 DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
1394                           "updating the BIOS to fix).\n");
1395                 dev_priv->has_gem = 0;
1396         }
1397
1398         dev->driver->get_vblank_counter = i915_get_vblank_counter;
1399         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1400         if (IS_G4X(dev) || IS_IGDNG(dev)) {
1401                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
1402                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
1403         }
1404
1405         i915_gem_load(dev);
1406
1407         /* Init HWS */
1408         if (!I915_NEED_GFX_HWS(dev)) {
1409                 ret = i915_init_phys_hws(dev);
1410                 if (ret != 0)
1411                         goto out_workqueue_free;
1412         }
1413
1414         i915_get_mem_freq(dev);
1415
1416         /* On the 945G/GM, the chipset reports the MSI capability on the
1417          * integrated graphics even though the support isn't actually there
1418          * according to the published specs.  It doesn't appear to function
1419          * correctly in testing on 945G.
1420          * This may be a side effect of MSI having been made available for PEG
1421          * and the registers being closely associated.
1422          *
1423          * According to chipset errata, on the 965GM, MSI interrupts may
1424          * be lost or delayed, but we use them anyways to avoid
1425          * stuck interrupts on some machines.
1426          */
1427         if (!IS_I945G(dev) && !IS_I945GM(dev))
1428                 pci_enable_msi(dev->pdev);
1429
1430         spin_lock_init(&dev_priv->user_irq_lock);
1431         spin_lock_init(&dev_priv->error_lock);
1432         dev_priv->user_irq_refcount = 0;
1433
1434         ret = drm_vblank_init(dev, I915_NUM_PIPE);
1435
1436         if (ret) {
1437                 (void) i915_driver_unload(dev);
1438                 return ret;
1439         }
1440
1441         /* Start out suspended */
1442         dev_priv->mm.suspended = 1;
1443
1444         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1445                 ret = i915_load_modeset_init(dev, prealloc_start,
1446                                              prealloc_size, agp_size);
1447                 if (ret < 0) {
1448                         DRM_ERROR("failed to init modeset\n");
1449                         goto out_workqueue_free;
1450                 }
1451         }
1452
1453         /* Must be done after probing outputs */
1454         /* FIXME: verify on IGDNG */
1455         if (!IS_IGDNG(dev))
1456                 intel_opregion_init(dev, 0);
1457
1458         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
1459                     (unsigned long) dev);
1460         return 0;
1461
1462 out_workqueue_free:
1463         destroy_workqueue(dev_priv->wq);
1464 out_iomapfree:
1465         io_mapping_free(dev_priv->mm.gtt_mapping);
1466 out_rmmap:
1467         iounmap(dev_priv->regs);
1468 put_bridge:
1469         pci_dev_put(dev_priv->bridge_dev);
1470 free_priv:
1471         kfree(dev_priv);
1472         return ret;
1473 }
1474
1475 int i915_driver_unload(struct drm_device *dev)
1476 {
1477         struct drm_i915_private *dev_priv = dev->dev_private;
1478
1479         destroy_workqueue(dev_priv->wq);
1480         del_timer_sync(&dev_priv->hangcheck_timer);
1481
1482         io_mapping_free(dev_priv->mm.gtt_mapping);
1483         if (dev_priv->mm.gtt_mtrr >= 0) {
1484                 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
1485                          dev->agp->agp_info.aper_size * 1024 * 1024);
1486                 dev_priv->mm.gtt_mtrr = -1;
1487         }
1488
1489         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1490                 drm_irq_uninstall(dev);
1491         }
1492
1493         if (dev->pdev->msi_enabled)
1494                 pci_disable_msi(dev->pdev);
1495
1496         if (dev_priv->regs != NULL)
1497                 iounmap(dev_priv->regs);
1498
1499         if (!IS_IGDNG(dev))
1500                 intel_opregion_free(dev, 0);
1501
1502         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1503                 intel_modeset_cleanup(dev);
1504
1505                 i915_gem_free_all_phys_object(dev);
1506
1507                 mutex_lock(&dev->struct_mutex);
1508                 i915_gem_cleanup_ringbuffer(dev);
1509                 mutex_unlock(&dev->struct_mutex);
1510                 drm_mm_takedown(&dev_priv->vram);
1511                 i915_gem_lastclose(dev);
1512         }
1513
1514         pci_dev_put(dev_priv->bridge_dev);
1515         kfree(dev->dev_private);
1516
1517         return 0;
1518 }
1519
1520 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1521 {
1522         struct drm_i915_file_private *i915_file_priv;
1523
1524         DRM_DEBUG_DRIVER("\n");
1525         i915_file_priv = (struct drm_i915_file_private *)
1526             kmalloc(sizeof(*i915_file_priv), GFP_KERNEL);
1527
1528         if (!i915_file_priv)
1529                 return -ENOMEM;
1530
1531         file_priv->driver_priv = i915_file_priv;
1532
1533         INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
1534
1535         return 0;
1536 }
1537
1538 /**
1539  * i915_driver_lastclose - clean up after all DRM clients have exited
1540  * @dev: DRM device
1541  *
1542  * Take care of cleaning up after all DRM clients have exited.  In the
1543  * mode setting case, we want to restore the kernel's initial mode (just
1544  * in case the last client left us in a bad state).
1545  *
1546  * Additionally, in the non-mode setting case, we'll tear down the AGP
1547  * and DMA structures, since the kernel won't be using them, and clea
1548  * up any GEM state.
1549  */
1550 void i915_driver_lastclose(struct drm_device * dev)
1551 {
1552         drm_i915_private_t *dev_priv = dev->dev_private;
1553
1554         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1555                 drm_fb_helper_restore();
1556                 return;
1557         }
1558
1559         i915_gem_lastclose(dev);
1560
1561         if (dev_priv->agp_heap)
1562                 i915_mem_takedown(&(dev_priv->agp_heap));
1563
1564         i915_dma_cleanup(dev);
1565 }
1566
1567 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1568 {
1569         drm_i915_private_t *dev_priv = dev->dev_private;
1570         i915_gem_release(dev, file_priv);
1571         if (!drm_core_check_feature(dev, DRIVER_MODESET))
1572                 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
1573 }
1574
1575 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1576 {
1577         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1578
1579         kfree(i915_file_priv);
1580 }
1581
1582 struct drm_ioctl_desc i915_ioctls[] = {
1583         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1584         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1585         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1586         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1587         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1588         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1589         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1590         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1591         DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
1592         DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
1593         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1594         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1595         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1596         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1597         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
1598         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1599         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1600         DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1601         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
1602         DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1603         DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1604         DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH),
1605         DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
1606         DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1607         DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1608         DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
1609         DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0),
1610         DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0),
1611         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
1612         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, 0),
1613         DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0),
1614         DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0),
1615         DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
1616         DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
1617         DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0),
1618         DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
1619         DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, 0),
1620 };
1621
1622 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1623
1624 /**
1625  * Determine if the device really is AGP or not.
1626  *
1627  * All Intel graphics chipsets are treated as AGP, even if they are really
1628  * PCI-e.
1629  *
1630  * \param dev   The device to be tested.
1631  *
1632  * \returns
1633  * A value of 1 is always retured to indictate every i9x5 is AGP.
1634  */
1635 int i915_driver_device_is_agp(struct drm_device * dev)
1636 {
1637         return 1;
1638 }