2 * Driver for OHCI 1394 controllers
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/firewire.h>
26 #include <linux/firewire-constants.h>
27 #include <linux/gfp.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <linux/kernel.h>
32 #include <linux/list.h>
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/pci.h>
37 #include <linux/pci_ids.h>
38 #include <linux/spinlock.h>
39 #include <linux/string.h>
41 #include <asm/byteorder.h>
43 #include <asm/system.h>
45 #ifdef CONFIG_PPC_PMAC
46 #include <asm/pmac_feature.h>
52 #define DESCRIPTOR_OUTPUT_MORE 0
53 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
54 #define DESCRIPTOR_INPUT_MORE (2 << 12)
55 #define DESCRIPTOR_INPUT_LAST (3 << 12)
56 #define DESCRIPTOR_STATUS (1 << 11)
57 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
58 #define DESCRIPTOR_PING (1 << 7)
59 #define DESCRIPTOR_YY (1 << 6)
60 #define DESCRIPTOR_NO_IRQ (0 << 4)
61 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
62 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
63 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
64 #define DESCRIPTOR_WAIT (3 << 0)
70 __le32 branch_address;
72 __le16 transfer_status;
73 } __attribute__((aligned(16)));
75 #define CONTROL_SET(regs) (regs)
76 #define CONTROL_CLEAR(regs) ((regs) + 4)
77 #define COMMAND_PTR(regs) ((regs) + 12)
78 #define CONTEXT_MATCH(regs) ((regs) + 16)
81 struct descriptor descriptor;
82 struct ar_buffer *next;
88 struct ar_buffer *current_buffer;
89 struct ar_buffer *last_buffer;
92 struct tasklet_struct tasklet;
97 typedef int (*descriptor_callback_t)(struct context *ctx,
99 struct descriptor *last);
102 * A buffer that contains a block of DMA-able coherent memory used for
103 * storing a portion of a DMA descriptor program.
105 struct descriptor_buffer {
106 struct list_head list;
107 dma_addr_t buffer_bus;
110 struct descriptor buffer[0];
114 struct fw_ohci *ohci;
116 int total_allocation;
119 * List of page-sized buffers for storing DMA descriptors.
120 * Head of list contains buffers in use and tail of list contains
123 struct list_head buffer_list;
126 * Pointer to a buffer inside buffer_list that contains the tail
127 * end of the current DMA program.
129 struct descriptor_buffer *buffer_tail;
132 * The descriptor containing the branch address of the first
133 * descriptor that has not yet been filled by the device.
135 struct descriptor *last;
138 * The last descriptor in the DMA program. It contains the branch
139 * address that must be updated upon appending a new descriptor.
141 struct descriptor *prev;
143 descriptor_callback_t callback;
145 struct tasklet_struct tasklet;
148 #define IT_HEADER_SY(v) ((v) << 0)
149 #define IT_HEADER_TCODE(v) ((v) << 4)
150 #define IT_HEADER_CHANNEL(v) ((v) << 8)
151 #define IT_HEADER_TAG(v) ((v) << 14)
152 #define IT_HEADER_SPEED(v) ((v) << 16)
153 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
156 struct fw_iso_context base;
157 struct context context;
160 size_t header_length;
163 #define CONFIG_ROM_SIZE 1024
168 __iomem char *registers;
171 int request_generation; /* for timestamping incoming requests */
175 * Spinlock for accessing fw_ohci data. Never call out of
176 * this driver with this lock held.
180 struct ar_context ar_request_ctx;
181 struct ar_context ar_response_ctx;
182 struct context at_request_ctx;
183 struct context at_response_ctx;
186 struct iso_context *it_context_list;
187 u64 ir_context_channels;
189 struct iso_context *ir_context_list;
192 dma_addr_t config_rom_bus;
193 __be32 *next_config_rom;
194 dma_addr_t next_config_rom_bus;
198 dma_addr_t self_id_bus;
199 struct tasklet_struct bus_reset_tasklet;
201 u32 self_id_buffer[512];
204 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
206 return container_of(card, struct fw_ohci, card);
209 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
210 #define IR_CONTEXT_BUFFER_FILL 0x80000000
211 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
212 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
213 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
214 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
216 #define CONTEXT_RUN 0x8000
217 #define CONTEXT_WAKE 0x1000
218 #define CONTEXT_DEAD 0x0800
219 #define CONTEXT_ACTIVE 0x0400
221 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
222 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
223 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
225 #define OHCI1394_REGISTER_SIZE 0x800
226 #define OHCI_LOOP_COUNT 500
227 #define OHCI1394_PCI_HCI_Control 0x40
228 #define SELF_ID_BUF_SIZE 0x800
229 #define OHCI_TCODE_PHY_PACKET 0x0e
230 #define OHCI_VERSION_1_1 0x010010
232 static char ohci_driver_name[] = KBUILD_MODNAME;
234 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
236 #define QUIRK_CYCLE_TIMER 1
237 #define QUIRK_RESET_PACKET 2
238 #define QUIRK_BE_HEADERS 4
240 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
241 static const struct {
242 unsigned short vendor, device, flags;
244 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, QUIRK_CYCLE_TIMER |
246 {PCI_VENDOR_ID_TI, PCI_ANY_ID, QUIRK_RESET_PACKET},
247 {PCI_VENDOR_ID_AL, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
248 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
249 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
250 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, QUIRK_BE_HEADERS},
253 /* This overrides anything that was found in ohci_quirks[]. */
254 static int param_quirks;
255 module_param_named(quirks, param_quirks, int, 0644);
256 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
257 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
258 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
259 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS)
262 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
264 #define OHCI_PARAM_DEBUG_AT_AR 1
265 #define OHCI_PARAM_DEBUG_SELFIDS 2
266 #define OHCI_PARAM_DEBUG_IRQS 4
267 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
269 static int param_debug;
270 module_param_named(debug, param_debug, int, 0644);
271 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
272 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
273 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
274 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
275 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
276 ", or a combination, or all = -1)");
278 static void log_irqs(u32 evt)
280 if (likely(!(param_debug &
281 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
284 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
285 !(evt & OHCI1394_busReset))
288 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
289 evt & OHCI1394_selfIDComplete ? " selfID" : "",
290 evt & OHCI1394_RQPkt ? " AR_req" : "",
291 evt & OHCI1394_RSPkt ? " AR_resp" : "",
292 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
293 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
294 evt & OHCI1394_isochRx ? " IR" : "",
295 evt & OHCI1394_isochTx ? " IT" : "",
296 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
297 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
298 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
299 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
300 evt & OHCI1394_busReset ? " busReset" : "",
301 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
302 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
303 OHCI1394_respTxComplete | OHCI1394_isochRx |
304 OHCI1394_isochTx | OHCI1394_postedWriteErr |
305 OHCI1394_cycleTooLong | OHCI1394_cycleInconsistent |
306 OHCI1394_regAccessFail | OHCI1394_busReset)
310 static const char *speed[] = {
311 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
313 static const char *power[] = {
314 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
315 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
317 static const char port[] = { '.', '-', 'p', 'c', };
319 static char _p(u32 *s, int shift)
321 return port[*s >> shift & 3];
324 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
326 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
329 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
330 self_id_count, generation, node_id);
332 for (; self_id_count--; ++s)
333 if ((*s & 1 << 23) == 0)
334 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
335 "%s gc=%d %s %s%s%s\n",
336 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
337 speed[*s >> 14 & 3], *s >> 16 & 63,
338 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
339 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
341 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
343 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
344 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
347 static const char *evts[] = {
348 [0x00] = "evt_no_status", [0x01] = "-reserved-",
349 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
350 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
351 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
352 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
353 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
354 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
355 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
356 [0x10] = "-reserved-", [0x11] = "ack_complete",
357 [0x12] = "ack_pending ", [0x13] = "-reserved-",
358 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
359 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
360 [0x18] = "-reserved-", [0x19] = "-reserved-",
361 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
362 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
363 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
364 [0x20] = "pending/cancelled",
366 static const char *tcodes[] = {
367 [0x0] = "QW req", [0x1] = "BW req",
368 [0x2] = "W resp", [0x3] = "-reserved-",
369 [0x4] = "QR req", [0x5] = "BR req",
370 [0x6] = "QR resp", [0x7] = "BR resp",
371 [0x8] = "cycle start", [0x9] = "Lk req",
372 [0xa] = "async stream packet", [0xb] = "Lk resp",
373 [0xc] = "-reserved-", [0xd] = "-reserved-",
374 [0xe] = "link internal", [0xf] = "-reserved-",
376 static const char *phys[] = {
377 [0x0] = "phy config packet", [0x1] = "link-on packet",
378 [0x2] = "self-id packet", [0x3] = "-reserved-",
381 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
383 int tcode = header[0] >> 4 & 0xf;
386 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
389 if (unlikely(evt >= ARRAY_SIZE(evts)))
392 if (evt == OHCI1394_evt_bus_reset) {
393 fw_notify("A%c evt_bus_reset, generation %d\n",
394 dir, (header[2] >> 16) & 0xff);
398 if (header[0] == ~header[1]) {
399 fw_notify("A%c %s, %s, %08x\n",
400 dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
405 case 0x0: case 0x6: case 0x8:
406 snprintf(specific, sizeof(specific), " = %08x",
407 be32_to_cpu((__force __be32)header[3]));
409 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
410 snprintf(specific, sizeof(specific), " %x,%x",
411 header[3] >> 16, header[3] & 0xffff);
419 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
421 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
422 fw_notify("A%c spd %x tl %02x, "
425 dir, speed, header[0] >> 10 & 0x3f,
426 header[1] >> 16, header[0] >> 16, evts[evt],
427 tcodes[tcode], header[1] & 0xffff, header[2], specific);
430 fw_notify("A%c spd %x tl %02x, "
433 dir, speed, header[0] >> 10 & 0x3f,
434 header[1] >> 16, header[0] >> 16, evts[evt],
435 tcodes[tcode], specific);
441 #define log_irqs(evt)
442 #define log_selfids(node_id, generation, self_id_count, sid)
443 #define log_ar_at_event(dir, speed, header, evt)
445 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
447 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
449 writel(data, ohci->registers + offset);
452 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
454 return readl(ohci->registers + offset);
457 static inline void flush_writes(const struct fw_ohci *ohci)
459 /* Do a dummy read to flush writes. */
460 reg_read(ohci, OHCI1394_Version);
463 static int read_phy_reg(struct fw_card *card, int addr, u32 *value)
465 struct fw_ohci *ohci = fw_ohci(card);
468 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
471 val = reg_read(ohci, OHCI1394_PhyControl);
472 if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
473 fw_error("failed to read phy reg bits\n");
477 *value = OHCI1394_PhyControl_ReadData(val);
482 static int ohci_update_phy_reg(struct fw_card *card, int addr,
483 int clear_bits, int set_bits)
485 struct fw_ohci *ohci = fw_ohci(card);
489 err = read_phy_reg(card, addr, &old);
494 * The interrupt status bits are cleared by writing a one bit.
495 * Avoid clearing them unless explicitly requested in set_bits.
498 clear_bits |= PHY_INT_STATUS_BITS;
500 old = (old & ~clear_bits) | set_bits;
501 reg_write(ohci, OHCI1394_PhyControl,
502 OHCI1394_PhyControl_Write(addr, old));
507 static int ar_context_add_page(struct ar_context *ctx)
509 struct device *dev = ctx->ohci->card.device;
510 struct ar_buffer *ab;
511 dma_addr_t uninitialized_var(ab_bus);
514 ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
519 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
520 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
522 DESCRIPTOR_BRANCH_ALWAYS);
523 offset = offsetof(struct ar_buffer, data);
524 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
525 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
526 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
527 ab->descriptor.branch_address = 0;
529 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
530 ctx->last_buffer->next = ab;
531 ctx->last_buffer = ab;
533 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
534 flush_writes(ctx->ohci);
539 static void ar_context_release(struct ar_context *ctx)
541 struct ar_buffer *ab, *ab_next;
545 for (ab = ctx->current_buffer; ab; ab = ab_next) {
547 offset = offsetof(struct ar_buffer, data);
548 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
549 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
554 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
555 #define cond_le32_to_cpu(v) \
556 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
558 #define cond_le32_to_cpu(v) le32_to_cpu(v)
561 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
563 struct fw_ohci *ohci = ctx->ohci;
565 u32 status, length, tcode;
568 p.header[0] = cond_le32_to_cpu(buffer[0]);
569 p.header[1] = cond_le32_to_cpu(buffer[1]);
570 p.header[2] = cond_le32_to_cpu(buffer[2]);
572 tcode = (p.header[0] >> 4) & 0x0f;
574 case TCODE_WRITE_QUADLET_REQUEST:
575 case TCODE_READ_QUADLET_RESPONSE:
576 p.header[3] = (__force __u32) buffer[3];
577 p.header_length = 16;
578 p.payload_length = 0;
581 case TCODE_READ_BLOCK_REQUEST :
582 p.header[3] = cond_le32_to_cpu(buffer[3]);
583 p.header_length = 16;
584 p.payload_length = 0;
587 case TCODE_WRITE_BLOCK_REQUEST:
588 case TCODE_READ_BLOCK_RESPONSE:
589 case TCODE_LOCK_REQUEST:
590 case TCODE_LOCK_RESPONSE:
591 p.header[3] = cond_le32_to_cpu(buffer[3]);
592 p.header_length = 16;
593 p.payload_length = p.header[3] >> 16;
596 case TCODE_WRITE_RESPONSE:
597 case TCODE_READ_QUADLET_REQUEST:
598 case OHCI_TCODE_PHY_PACKET:
599 p.header_length = 12;
600 p.payload_length = 0;
604 /* FIXME: Stop context, discard everything, and restart? */
606 p.payload_length = 0;
609 p.payload = (void *) buffer + p.header_length;
611 /* FIXME: What to do about evt_* errors? */
612 length = (p.header_length + p.payload_length + 3) / 4;
613 status = cond_le32_to_cpu(buffer[length]);
614 evt = (status >> 16) & 0x1f;
617 p.speed = (status >> 21) & 0x7;
618 p.timestamp = status & 0xffff;
619 p.generation = ohci->request_generation;
621 log_ar_at_event('R', p.speed, p.header, evt);
624 * The OHCI bus reset handler synthesizes a phy packet with
625 * the new generation number when a bus reset happens (see
626 * section 8.4.2.3). This helps us determine when a request
627 * was received and make sure we send the response in the same
628 * generation. We only need this for requests; for responses
629 * we use the unique tlabel for finding the matching
632 * Alas some chips sometimes emit bus reset packets with a
633 * wrong generation. We set the correct generation for these
634 * at a slightly incorrect time (in bus_reset_tasklet).
636 if (evt == OHCI1394_evt_bus_reset) {
637 if (!(ohci->quirks & QUIRK_RESET_PACKET))
638 ohci->request_generation = (p.header[2] >> 16) & 0xff;
639 } else if (ctx == &ohci->ar_request_ctx) {
640 fw_core_handle_request(&ohci->card, &p);
642 fw_core_handle_response(&ohci->card, &p);
645 return buffer + length + 1;
648 static void ar_context_tasklet(unsigned long data)
650 struct ar_context *ctx = (struct ar_context *)data;
651 struct fw_ohci *ohci = ctx->ohci;
652 struct ar_buffer *ab;
653 struct descriptor *d;
656 ab = ctx->current_buffer;
659 if (d->res_count == 0) {
660 size_t size, rest, offset;
661 dma_addr_t start_bus;
665 * This descriptor is finished and we may have a
666 * packet split across this and the next buffer. We
667 * reuse the page for reassembling the split packet.
670 offset = offsetof(struct ar_buffer, data);
672 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
676 size = buffer + PAGE_SIZE - ctx->pointer;
677 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
678 memmove(buffer, ctx->pointer, size);
679 memcpy(buffer + size, ab->data, rest);
680 ctx->current_buffer = ab;
681 ctx->pointer = (void *) ab->data + rest;
682 end = buffer + size + rest;
685 buffer = handle_ar_packet(ctx, buffer);
687 dma_free_coherent(ohci->card.device, PAGE_SIZE,
689 ar_context_add_page(ctx);
691 buffer = ctx->pointer;
693 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
696 buffer = handle_ar_packet(ctx, buffer);
700 static int ar_context_init(struct ar_context *ctx,
701 struct fw_ohci *ohci, u32 regs)
707 ctx->last_buffer = &ab;
708 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
710 ar_context_add_page(ctx);
711 ar_context_add_page(ctx);
712 ctx->current_buffer = ab.next;
713 ctx->pointer = ctx->current_buffer->data;
718 static void ar_context_run(struct ar_context *ctx)
720 struct ar_buffer *ab = ctx->current_buffer;
724 offset = offsetof(struct ar_buffer, data);
725 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
727 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
728 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
729 flush_writes(ctx->ohci);
732 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
736 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
737 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
739 /* figure out which descriptor the branch address goes in */
740 if (z == 2 && (b == 3 || key == 2))
746 static void context_tasklet(unsigned long data)
748 struct context *ctx = (struct context *) data;
749 struct descriptor *d, *last;
752 struct descriptor_buffer *desc;
754 desc = list_entry(ctx->buffer_list.next,
755 struct descriptor_buffer, list);
757 while (last->branch_address != 0) {
758 struct descriptor_buffer *old_desc = desc;
759 address = le32_to_cpu(last->branch_address);
763 /* If the branch address points to a buffer outside of the
764 * current buffer, advance to the next buffer. */
765 if (address < desc->buffer_bus ||
766 address >= desc->buffer_bus + desc->used)
767 desc = list_entry(desc->list.next,
768 struct descriptor_buffer, list);
769 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
770 last = find_branch_descriptor(d, z);
772 if (!ctx->callback(ctx, d, last))
775 if (old_desc != desc) {
776 /* If we've advanced to the next buffer, move the
777 * previous buffer to the free list. */
780 spin_lock_irqsave(&ctx->ohci->lock, flags);
781 list_move_tail(&old_desc->list, &ctx->buffer_list);
782 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
789 * Allocate a new buffer and add it to the list of free buffers for this
790 * context. Must be called with ohci->lock held.
792 static int context_add_buffer(struct context *ctx)
794 struct descriptor_buffer *desc;
795 dma_addr_t uninitialized_var(bus_addr);
799 * 16MB of descriptors should be far more than enough for any DMA
800 * program. This will catch run-away userspace or DoS attacks.
802 if (ctx->total_allocation >= 16*1024*1024)
805 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
806 &bus_addr, GFP_ATOMIC);
810 offset = (void *)&desc->buffer - (void *)desc;
811 desc->buffer_size = PAGE_SIZE - offset;
812 desc->buffer_bus = bus_addr + offset;
815 list_add_tail(&desc->list, &ctx->buffer_list);
816 ctx->total_allocation += PAGE_SIZE;
821 static int context_init(struct context *ctx, struct fw_ohci *ohci,
822 u32 regs, descriptor_callback_t callback)
826 ctx->total_allocation = 0;
828 INIT_LIST_HEAD(&ctx->buffer_list);
829 if (context_add_buffer(ctx) < 0)
832 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
833 struct descriptor_buffer, list);
835 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
836 ctx->callback = callback;
839 * We put a dummy descriptor in the buffer that has a NULL
840 * branch address and looks like it's been sent. That way we
841 * have a descriptor to append DMA programs to.
843 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
844 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
845 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
846 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
847 ctx->last = ctx->buffer_tail->buffer;
848 ctx->prev = ctx->buffer_tail->buffer;
853 static void context_release(struct context *ctx)
855 struct fw_card *card = &ctx->ohci->card;
856 struct descriptor_buffer *desc, *tmp;
858 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
859 dma_free_coherent(card->device, PAGE_SIZE, desc,
861 ((void *)&desc->buffer - (void *)desc));
864 /* Must be called with ohci->lock held */
865 static struct descriptor *context_get_descriptors(struct context *ctx,
866 int z, dma_addr_t *d_bus)
868 struct descriptor *d = NULL;
869 struct descriptor_buffer *desc = ctx->buffer_tail;
871 if (z * sizeof(*d) > desc->buffer_size)
874 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
875 /* No room for the descriptor in this buffer, so advance to the
878 if (desc->list.next == &ctx->buffer_list) {
879 /* If there is no free buffer next in the list,
881 if (context_add_buffer(ctx) < 0)
884 desc = list_entry(desc->list.next,
885 struct descriptor_buffer, list);
886 ctx->buffer_tail = desc;
889 d = desc->buffer + desc->used / sizeof(*d);
890 memset(d, 0, z * sizeof(*d));
891 *d_bus = desc->buffer_bus + desc->used;
896 static void context_run(struct context *ctx, u32 extra)
898 struct fw_ohci *ohci = ctx->ohci;
900 reg_write(ohci, COMMAND_PTR(ctx->regs),
901 le32_to_cpu(ctx->last->branch_address));
902 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
903 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
907 static void context_append(struct context *ctx,
908 struct descriptor *d, int z, int extra)
911 struct descriptor_buffer *desc = ctx->buffer_tail;
913 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
915 desc->used += (z + extra) * sizeof(*d);
916 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
917 ctx->prev = find_branch_descriptor(d, z);
919 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
920 flush_writes(ctx->ohci);
923 static void context_stop(struct context *ctx)
928 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
929 flush_writes(ctx->ohci);
931 for (i = 0; i < 10; i++) {
932 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
933 if ((reg & CONTEXT_ACTIVE) == 0)
938 fw_error("Error: DMA context still active (0x%08x)\n", reg);
942 struct fw_packet *packet;
946 * This function apppends a packet to the DMA queue for transmission.
947 * Must always be called with the ochi->lock held to ensure proper
948 * generation handling and locking around packet queue manipulation.
950 static int at_context_queue_packet(struct context *ctx,
951 struct fw_packet *packet)
953 struct fw_ohci *ohci = ctx->ohci;
954 dma_addr_t d_bus, uninitialized_var(payload_bus);
955 struct driver_data *driver_data;
956 struct descriptor *d, *last;
961 d = context_get_descriptors(ctx, 4, &d_bus);
963 packet->ack = RCODE_SEND_ERROR;
967 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
968 d[0].res_count = cpu_to_le16(packet->timestamp);
971 * The DMA format for asyncronous link packets is different
972 * from the IEEE1394 layout, so shift the fields around
973 * accordingly. If header_length is 8, it's a PHY packet, to
974 * which we need to prepend an extra quadlet.
977 header = (__le32 *) &d[1];
978 switch (packet->header_length) {
981 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
982 (packet->speed << 16));
983 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
984 (packet->header[0] & 0xffff0000));
985 header[2] = cpu_to_le32(packet->header[2]);
987 tcode = (packet->header[0] >> 4) & 0x0f;
988 if (TCODE_IS_BLOCK_PACKET(tcode))
989 header[3] = cpu_to_le32(packet->header[3]);
991 header[3] = (__force __le32) packet->header[3];
993 d[0].req_count = cpu_to_le16(packet->header_length);
997 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
998 (packet->speed << 16));
999 header[1] = cpu_to_le32(packet->header[0]);
1000 header[2] = cpu_to_le32(packet->header[1]);
1001 d[0].req_count = cpu_to_le16(12);
1005 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1006 (packet->speed << 16));
1007 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1008 d[0].req_count = cpu_to_le16(8);
1013 packet->ack = RCODE_SEND_ERROR;
1017 driver_data = (struct driver_data *) &d[3];
1018 driver_data->packet = packet;
1019 packet->driver_data = driver_data;
1021 if (packet->payload_length > 0) {
1023 dma_map_single(ohci->card.device, packet->payload,
1024 packet->payload_length, DMA_TO_DEVICE);
1025 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1026 packet->ack = RCODE_SEND_ERROR;
1029 packet->payload_bus = payload_bus;
1030 packet->payload_mapped = true;
1032 d[2].req_count = cpu_to_le16(packet->payload_length);
1033 d[2].data_address = cpu_to_le32(payload_bus);
1041 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1042 DESCRIPTOR_IRQ_ALWAYS |
1043 DESCRIPTOR_BRANCH_ALWAYS);
1046 * If the controller and packet generations don't match, we need to
1047 * bail out and try again. If IntEvent.busReset is set, the AT context
1048 * is halted, so appending to the context and trying to run it is
1049 * futile. Most controllers do the right thing and just flush the AT
1050 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1051 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1052 * up stalling out. So we just bail out in software and try again
1053 * later, and everyone is happy.
1054 * FIXME: Document how the locking works.
1056 if (ohci->generation != packet->generation ||
1057 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1058 if (packet->payload_mapped)
1059 dma_unmap_single(ohci->card.device, payload_bus,
1060 packet->payload_length, DMA_TO_DEVICE);
1061 packet->ack = RCODE_GENERATION;
1065 context_append(ctx, d, z, 4 - z);
1067 /* If the context isn't already running, start it up. */
1068 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1069 if ((reg & CONTEXT_RUN) == 0)
1070 context_run(ctx, 0);
1075 static int handle_at_packet(struct context *context,
1076 struct descriptor *d,
1077 struct descriptor *last)
1079 struct driver_data *driver_data;
1080 struct fw_packet *packet;
1081 struct fw_ohci *ohci = context->ohci;
1084 if (last->transfer_status == 0)
1085 /* This descriptor isn't done yet, stop iteration. */
1088 driver_data = (struct driver_data *) &d[3];
1089 packet = driver_data->packet;
1091 /* This packet was cancelled, just continue. */
1094 if (packet->payload_mapped)
1095 dma_unmap_single(ohci->card.device, packet->payload_bus,
1096 packet->payload_length, DMA_TO_DEVICE);
1098 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1099 packet->timestamp = le16_to_cpu(last->res_count);
1101 log_ar_at_event('T', packet->speed, packet->header, evt);
1104 case OHCI1394_evt_timeout:
1105 /* Async response transmit timed out. */
1106 packet->ack = RCODE_CANCELLED;
1109 case OHCI1394_evt_flushed:
1111 * The packet was flushed should give same error as
1112 * when we try to use a stale generation count.
1114 packet->ack = RCODE_GENERATION;
1117 case OHCI1394_evt_missing_ack:
1119 * Using a valid (current) generation count, but the
1120 * node is not on the bus or not sending acks.
1122 packet->ack = RCODE_NO_ACK;
1125 case ACK_COMPLETE + 0x10:
1126 case ACK_PENDING + 0x10:
1127 case ACK_BUSY_X + 0x10:
1128 case ACK_BUSY_A + 0x10:
1129 case ACK_BUSY_B + 0x10:
1130 case ACK_DATA_ERROR + 0x10:
1131 case ACK_TYPE_ERROR + 0x10:
1132 packet->ack = evt - 0x10;
1136 packet->ack = RCODE_SEND_ERROR;
1140 packet->callback(packet, &ohci->card, packet->ack);
1145 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1146 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1147 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1148 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1149 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1151 static void handle_local_rom(struct fw_ohci *ohci,
1152 struct fw_packet *packet, u32 csr)
1154 struct fw_packet response;
1155 int tcode, length, i;
1157 tcode = HEADER_GET_TCODE(packet->header[0]);
1158 if (TCODE_IS_BLOCK_PACKET(tcode))
1159 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1163 i = csr - CSR_CONFIG_ROM;
1164 if (i + length > CONFIG_ROM_SIZE) {
1165 fw_fill_response(&response, packet->header,
1166 RCODE_ADDRESS_ERROR, NULL, 0);
1167 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1168 fw_fill_response(&response, packet->header,
1169 RCODE_TYPE_ERROR, NULL, 0);
1171 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1172 (void *) ohci->config_rom + i, length);
1175 fw_core_handle_response(&ohci->card, &response);
1178 static void handle_local_lock(struct fw_ohci *ohci,
1179 struct fw_packet *packet, u32 csr)
1181 struct fw_packet response;
1182 int tcode, length, ext_tcode, sel;
1183 __be32 *payload, lock_old;
1184 u32 lock_arg, lock_data;
1186 tcode = HEADER_GET_TCODE(packet->header[0]);
1187 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1188 payload = packet->payload;
1189 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1191 if (tcode == TCODE_LOCK_REQUEST &&
1192 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1193 lock_arg = be32_to_cpu(payload[0]);
1194 lock_data = be32_to_cpu(payload[1]);
1195 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1199 fw_fill_response(&response, packet->header,
1200 RCODE_TYPE_ERROR, NULL, 0);
1204 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1205 reg_write(ohci, OHCI1394_CSRData, lock_data);
1206 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1207 reg_write(ohci, OHCI1394_CSRControl, sel);
1209 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
1210 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
1212 fw_notify("swap not done yet\n");
1214 fw_fill_response(&response, packet->header,
1215 RCODE_COMPLETE, &lock_old, sizeof(lock_old));
1217 fw_core_handle_response(&ohci->card, &response);
1220 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1225 if (ctx == &ctx->ohci->at_request_ctx) {
1226 packet->ack = ACK_PENDING;
1227 packet->callback(packet, &ctx->ohci->card, packet->ack);
1231 ((unsigned long long)
1232 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1234 csr = offset - CSR_REGISTER_BASE;
1236 /* Handle config rom reads. */
1237 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1238 handle_local_rom(ctx->ohci, packet, csr);
1240 case CSR_BUS_MANAGER_ID:
1241 case CSR_BANDWIDTH_AVAILABLE:
1242 case CSR_CHANNELS_AVAILABLE_HI:
1243 case CSR_CHANNELS_AVAILABLE_LO:
1244 handle_local_lock(ctx->ohci, packet, csr);
1247 if (ctx == &ctx->ohci->at_request_ctx)
1248 fw_core_handle_request(&ctx->ohci->card, packet);
1250 fw_core_handle_response(&ctx->ohci->card, packet);
1254 if (ctx == &ctx->ohci->at_response_ctx) {
1255 packet->ack = ACK_COMPLETE;
1256 packet->callback(packet, &ctx->ohci->card, packet->ack);
1260 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1262 unsigned long flags;
1265 spin_lock_irqsave(&ctx->ohci->lock, flags);
1267 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1268 ctx->ohci->generation == packet->generation) {
1269 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1270 handle_local_request(ctx, packet);
1274 ret = at_context_queue_packet(ctx, packet);
1275 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1278 packet->callback(packet, &ctx->ohci->card, packet->ack);
1282 static void bus_reset_tasklet(unsigned long data)
1284 struct fw_ohci *ohci = (struct fw_ohci *)data;
1285 int self_id_count, i, j, reg;
1286 int generation, new_generation;
1287 unsigned long flags;
1288 void *free_rom = NULL;
1289 dma_addr_t free_rom_bus = 0;
1291 reg = reg_read(ohci, OHCI1394_NodeID);
1292 if (!(reg & OHCI1394_NodeID_idValid)) {
1293 fw_notify("node ID not valid, new bus reset in progress\n");
1296 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1297 fw_notify("malconfigured bus\n");
1300 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1301 OHCI1394_NodeID_nodeNumber);
1303 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1304 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1305 fw_notify("inconsistent self IDs\n");
1309 * The count in the SelfIDCount register is the number of
1310 * bytes in the self ID receive buffer. Since we also receive
1311 * the inverted quadlets and a header quadlet, we shift one
1312 * bit extra to get the actual number of self IDs.
1314 self_id_count = (reg >> 3) & 0xff;
1315 if (self_id_count == 0 || self_id_count > 252) {
1316 fw_notify("inconsistent self IDs\n");
1319 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1322 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1323 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1324 fw_notify("inconsistent self IDs\n");
1327 ohci->self_id_buffer[j] =
1328 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1333 * Check the consistency of the self IDs we just read. The
1334 * problem we face is that a new bus reset can start while we
1335 * read out the self IDs from the DMA buffer. If this happens,
1336 * the DMA buffer will be overwritten with new self IDs and we
1337 * will read out inconsistent data. The OHCI specification
1338 * (section 11.2) recommends a technique similar to
1339 * linux/seqlock.h, where we remember the generation of the
1340 * self IDs in the buffer before reading them out and compare
1341 * it to the current generation after reading them out. If
1342 * the two generations match we know we have a consistent set
1346 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1347 if (new_generation != generation) {
1348 fw_notify("recursive bus reset detected, "
1349 "discarding self ids\n");
1353 /* FIXME: Document how the locking works. */
1354 spin_lock_irqsave(&ohci->lock, flags);
1356 ohci->generation = generation;
1357 context_stop(&ohci->at_request_ctx);
1358 context_stop(&ohci->at_response_ctx);
1359 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1361 if (ohci->quirks & QUIRK_RESET_PACKET)
1362 ohci->request_generation = generation;
1365 * This next bit is unrelated to the AT context stuff but we
1366 * have to do it under the spinlock also. If a new config rom
1367 * was set up before this reset, the old one is now no longer
1368 * in use and we can free it. Update the config rom pointers
1369 * to point to the current config rom and clear the
1370 * next_config_rom pointer so a new udpate can take place.
1373 if (ohci->next_config_rom != NULL) {
1374 if (ohci->next_config_rom != ohci->config_rom) {
1375 free_rom = ohci->config_rom;
1376 free_rom_bus = ohci->config_rom_bus;
1378 ohci->config_rom = ohci->next_config_rom;
1379 ohci->config_rom_bus = ohci->next_config_rom_bus;
1380 ohci->next_config_rom = NULL;
1383 * Restore config_rom image and manually update
1384 * config_rom registers. Writing the header quadlet
1385 * will indicate that the config rom is ready, so we
1388 reg_write(ohci, OHCI1394_BusOptions,
1389 be32_to_cpu(ohci->config_rom[2]));
1390 ohci->config_rom[0] = ohci->next_header;
1391 reg_write(ohci, OHCI1394_ConfigROMhdr,
1392 be32_to_cpu(ohci->next_header));
1395 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1396 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1397 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1400 spin_unlock_irqrestore(&ohci->lock, flags);
1403 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1404 free_rom, free_rom_bus);
1406 log_selfids(ohci->node_id, generation,
1407 self_id_count, ohci->self_id_buffer);
1409 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1410 self_id_count, ohci->self_id_buffer);
1413 static irqreturn_t irq_handler(int irq, void *data)
1415 struct fw_ohci *ohci = data;
1416 u32 event, iso_event;
1419 event = reg_read(ohci, OHCI1394_IntEventClear);
1421 if (!event || !~event)
1424 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1425 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1428 if (event & OHCI1394_selfIDComplete)
1429 tasklet_schedule(&ohci->bus_reset_tasklet);
1431 if (event & OHCI1394_RQPkt)
1432 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1434 if (event & OHCI1394_RSPkt)
1435 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1437 if (event & OHCI1394_reqTxComplete)
1438 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1440 if (event & OHCI1394_respTxComplete)
1441 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1443 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1444 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1447 i = ffs(iso_event) - 1;
1448 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1449 iso_event &= ~(1 << i);
1452 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1453 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1456 i = ffs(iso_event) - 1;
1457 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1458 iso_event &= ~(1 << i);
1461 if (unlikely(event & OHCI1394_regAccessFail))
1462 fw_error("Register access failure - "
1463 "please notify linux1394-devel@lists.sf.net\n");
1465 if (unlikely(event & OHCI1394_postedWriteErr))
1466 fw_error("PCI posted write error\n");
1468 if (unlikely(event & OHCI1394_cycleTooLong)) {
1469 if (printk_ratelimit())
1470 fw_notify("isochronous cycle too long\n");
1471 reg_write(ohci, OHCI1394_LinkControlSet,
1472 OHCI1394_LinkControl_cycleMaster);
1475 if (unlikely(event & OHCI1394_cycleInconsistent)) {
1477 * We need to clear this event bit in order to make
1478 * cycleMatch isochronous I/O work. In theory we should
1479 * stop active cycleMatch iso contexts now and restart
1480 * them at least two cycles later. (FIXME?)
1482 if (printk_ratelimit())
1483 fw_notify("isochronous cycle inconsistent\n");
1489 static int software_reset(struct fw_ohci *ohci)
1493 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1495 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1496 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1497 OHCI1394_HCControl_softReset) == 0)
1505 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1507 size_t size = length * 4;
1509 memcpy(dest, src, size);
1510 if (size < CONFIG_ROM_SIZE)
1511 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1514 static int ohci_enable(struct fw_card *card,
1515 const __be32 *config_rom, size_t length)
1517 struct fw_ohci *ohci = fw_ohci(card);
1518 struct pci_dev *dev = to_pci_dev(card->device);
1522 if (software_reset(ohci)) {
1523 fw_error("Failed to reset ohci card.\n");
1528 * Now enable LPS, which we need in order to start accessing
1529 * most of the registers. In fact, on some cards (ALI M5251),
1530 * accessing registers in the SClk domain without LPS enabled
1531 * will lock up the machine. Wait 50msec to make sure we have
1532 * full link enabled. However, with some cards (well, at least
1533 * a JMicron PCIe card), we have to try again sometimes.
1535 reg_write(ohci, OHCI1394_HCControlSet,
1536 OHCI1394_HCControl_LPS |
1537 OHCI1394_HCControl_postedWriteEnable);
1540 for (lps = 0, i = 0; !lps && i < 3; i++) {
1542 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1543 OHCI1394_HCControl_LPS;
1547 fw_error("Failed to set Link Power Status\n");
1551 reg_write(ohci, OHCI1394_HCControlClear,
1552 OHCI1394_HCControl_noByteSwapData);
1554 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1555 reg_write(ohci, OHCI1394_LinkControlClear,
1556 OHCI1394_LinkControl_rcvPhyPkt);
1557 reg_write(ohci, OHCI1394_LinkControlSet,
1558 OHCI1394_LinkControl_rcvSelfID |
1559 OHCI1394_LinkControl_cycleTimerEnable |
1560 OHCI1394_LinkControl_cycleMaster);
1562 reg_write(ohci, OHCI1394_ATRetries,
1563 OHCI1394_MAX_AT_REQ_RETRIES |
1564 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1565 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1567 ar_context_run(&ohci->ar_request_ctx);
1568 ar_context_run(&ohci->ar_response_ctx);
1570 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1571 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1572 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1573 reg_write(ohci, OHCI1394_IntMaskSet,
1574 OHCI1394_selfIDComplete |
1575 OHCI1394_RQPkt | OHCI1394_RSPkt |
1576 OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1577 OHCI1394_isochRx | OHCI1394_isochTx |
1578 OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
1579 OHCI1394_cycleInconsistent | OHCI1394_regAccessFail |
1580 OHCI1394_masterIntEnable);
1581 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1582 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
1584 /* Activate link_on bit and contender bit in our self ID packets.*/
1585 if (ohci_update_phy_reg(card, 4, 0,
1586 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1590 * When the link is not yet enabled, the atomic config rom
1591 * update mechanism described below in ohci_set_config_rom()
1592 * is not active. We have to update ConfigRomHeader and
1593 * BusOptions manually, and the write to ConfigROMmap takes
1594 * effect immediately. We tie this to the enabling of the
1595 * link, so we have a valid config rom before enabling - the
1596 * OHCI requires that ConfigROMhdr and BusOptions have valid
1597 * values before enabling.
1599 * However, when the ConfigROMmap is written, some controllers
1600 * always read back quadlets 0 and 2 from the config rom to
1601 * the ConfigRomHeader and BusOptions registers on bus reset.
1602 * They shouldn't do that in this initial case where the link
1603 * isn't enabled. This means we have to use the same
1604 * workaround here, setting the bus header to 0 and then write
1605 * the right values in the bus reset tasklet.
1609 ohci->next_config_rom =
1610 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1611 &ohci->next_config_rom_bus,
1613 if (ohci->next_config_rom == NULL)
1616 copy_config_rom(ohci->next_config_rom, config_rom, length);
1619 * In the suspend case, config_rom is NULL, which
1620 * means that we just reuse the old config rom.
1622 ohci->next_config_rom = ohci->config_rom;
1623 ohci->next_config_rom_bus = ohci->config_rom_bus;
1626 ohci->next_header = ohci->next_config_rom[0];
1627 ohci->next_config_rom[0] = 0;
1628 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1629 reg_write(ohci, OHCI1394_BusOptions,
1630 be32_to_cpu(ohci->next_config_rom[2]));
1631 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1633 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1635 if (request_irq(dev->irq, irq_handler,
1636 IRQF_SHARED, ohci_driver_name, ohci)) {
1637 fw_error("Failed to allocate shared interrupt %d.\n",
1639 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1640 ohci->config_rom, ohci->config_rom_bus);
1644 reg_write(ohci, OHCI1394_HCControlSet,
1645 OHCI1394_HCControl_linkEnable |
1646 OHCI1394_HCControl_BIBimageValid);
1650 * We are ready to go, initiate bus reset to finish the
1654 fw_core_initiate_bus_reset(&ohci->card, 1);
1659 static int ohci_set_config_rom(struct fw_card *card,
1660 const __be32 *config_rom, size_t length)
1662 struct fw_ohci *ohci;
1663 unsigned long flags;
1665 __be32 *next_config_rom;
1666 dma_addr_t uninitialized_var(next_config_rom_bus);
1668 ohci = fw_ohci(card);
1671 * When the OHCI controller is enabled, the config rom update
1672 * mechanism is a bit tricky, but easy enough to use. See
1673 * section 5.5.6 in the OHCI specification.
1675 * The OHCI controller caches the new config rom address in a
1676 * shadow register (ConfigROMmapNext) and needs a bus reset
1677 * for the changes to take place. When the bus reset is
1678 * detected, the controller loads the new values for the
1679 * ConfigRomHeader and BusOptions registers from the specified
1680 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1681 * shadow register. All automatically and atomically.
1683 * Now, there's a twist to this story. The automatic load of
1684 * ConfigRomHeader and BusOptions doesn't honor the
1685 * noByteSwapData bit, so with a be32 config rom, the
1686 * controller will load be32 values in to these registers
1687 * during the atomic update, even on litte endian
1688 * architectures. The workaround we use is to put a 0 in the
1689 * header quadlet; 0 is endian agnostic and means that the
1690 * config rom isn't ready yet. In the bus reset tasklet we
1691 * then set up the real values for the two registers.
1693 * We use ohci->lock to avoid racing with the code that sets
1694 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1698 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1699 &next_config_rom_bus, GFP_KERNEL);
1700 if (next_config_rom == NULL)
1703 spin_lock_irqsave(&ohci->lock, flags);
1705 if (ohci->next_config_rom == NULL) {
1706 ohci->next_config_rom = next_config_rom;
1707 ohci->next_config_rom_bus = next_config_rom_bus;
1709 copy_config_rom(ohci->next_config_rom, config_rom, length);
1711 ohci->next_header = config_rom[0];
1712 ohci->next_config_rom[0] = 0;
1714 reg_write(ohci, OHCI1394_ConfigROMmap,
1715 ohci->next_config_rom_bus);
1719 spin_unlock_irqrestore(&ohci->lock, flags);
1722 * Now initiate a bus reset to have the changes take
1723 * effect. We clean up the old config rom memory and DMA
1724 * mappings in the bus reset tasklet, since the OHCI
1725 * controller could need to access it before the bus reset
1729 fw_core_initiate_bus_reset(&ohci->card, 1);
1731 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1732 next_config_rom, next_config_rom_bus);
1737 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1739 struct fw_ohci *ohci = fw_ohci(card);
1741 at_context_transmit(&ohci->at_request_ctx, packet);
1744 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1746 struct fw_ohci *ohci = fw_ohci(card);
1748 at_context_transmit(&ohci->at_response_ctx, packet);
1751 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1753 struct fw_ohci *ohci = fw_ohci(card);
1754 struct context *ctx = &ohci->at_request_ctx;
1755 struct driver_data *driver_data = packet->driver_data;
1758 tasklet_disable(&ctx->tasklet);
1760 if (packet->ack != 0)
1763 if (packet->payload_mapped)
1764 dma_unmap_single(ohci->card.device, packet->payload_bus,
1765 packet->payload_length, DMA_TO_DEVICE);
1767 log_ar_at_event('T', packet->speed, packet->header, 0x20);
1768 driver_data->packet = NULL;
1769 packet->ack = RCODE_CANCELLED;
1770 packet->callback(packet, &ohci->card, packet->ack);
1773 tasklet_enable(&ctx->tasklet);
1778 static int ohci_enable_phys_dma(struct fw_card *card,
1779 int node_id, int generation)
1781 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1784 struct fw_ohci *ohci = fw_ohci(card);
1785 unsigned long flags;
1789 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1790 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1793 spin_lock_irqsave(&ohci->lock, flags);
1795 if (ohci->generation != generation) {
1801 * Note, if the node ID contains a non-local bus ID, physical DMA is
1802 * enabled for _all_ nodes on remote buses.
1805 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1807 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1809 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1813 spin_unlock_irqrestore(&ohci->lock, flags);
1816 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1819 static u32 cycle_timer_ticks(u32 cycle_timer)
1823 ticks = cycle_timer & 0xfff;
1824 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1825 ticks += (3072 * 8000) * (cycle_timer >> 25);
1831 * Some controllers exhibit one or more of the following bugs when updating the
1832 * iso cycle timer register:
1833 * - When the lowest six bits are wrapping around to zero, a read that happens
1834 * at the same time will return garbage in the lowest ten bits.
1835 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1836 * not incremented for about 60 ns.
1837 * - Occasionally, the entire register reads zero.
1839 * To catch these, we read the register three times and ensure that the
1840 * difference between each two consecutive reads is approximately the same, i.e.
1841 * less than twice the other. Furthermore, any negative difference indicates an
1842 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1843 * execute, so we have enough precision to compute the ratio of the differences.)
1845 static u32 ohci_get_cycle_time(struct fw_card *card)
1847 struct fw_ohci *ohci = fw_ohci(card);
1853 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1855 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1858 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1862 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1863 t0 = cycle_timer_ticks(c0);
1864 t1 = cycle_timer_ticks(c1);
1865 t2 = cycle_timer_ticks(c2);
1868 } while ((diff01 <= 0 || diff12 <= 0 ||
1869 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1876 static void copy_iso_headers(struct iso_context *ctx, void *p)
1878 int i = ctx->header_length;
1880 if (i + ctx->base.header_size > PAGE_SIZE)
1884 * The iso header is byteswapped to little endian by
1885 * the controller, but the remaining header quadlets
1886 * are big endian. We want to present all the headers
1887 * as big endian, so we have to swap the first quadlet.
1889 if (ctx->base.header_size > 0)
1890 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1891 if (ctx->base.header_size > 4)
1892 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
1893 if (ctx->base.header_size > 8)
1894 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
1895 ctx->header_length += ctx->base.header_size;
1898 static int handle_ir_packet_per_buffer(struct context *context,
1899 struct descriptor *d,
1900 struct descriptor *last)
1902 struct iso_context *ctx =
1903 container_of(context, struct iso_context, context);
1904 struct descriptor *pd;
1908 for (pd = d; pd <= last; pd++) {
1909 if (pd->transfer_status)
1913 /* Descriptor(s) not done yet, stop iteration */
1917 copy_iso_headers(ctx, p);
1919 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1920 ir_header = (__le32 *) p;
1921 ctx->base.callback(&ctx->base,
1922 le32_to_cpu(ir_header[0]) & 0xffff,
1923 ctx->header_length, ctx->header,
1924 ctx->base.callback_data);
1925 ctx->header_length = 0;
1931 static int handle_it_packet(struct context *context,
1932 struct descriptor *d,
1933 struct descriptor *last)
1935 struct iso_context *ctx =
1936 container_of(context, struct iso_context, context);
1938 struct descriptor *pd;
1940 for (pd = d; pd <= last; pd++)
1941 if (pd->transfer_status)
1944 /* Descriptor(s) not done yet, stop iteration */
1947 i = ctx->header_length;
1948 if (i + 4 < PAGE_SIZE) {
1949 /* Present this value as big-endian to match the receive code */
1950 *(__be32 *)(ctx->header + i) = cpu_to_be32(
1951 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
1952 le16_to_cpu(pd->res_count));
1953 ctx->header_length += 4;
1955 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1956 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1957 ctx->header_length, ctx->header,
1958 ctx->base.callback_data);
1959 ctx->header_length = 0;
1964 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
1965 int type, int channel, size_t header_size)
1967 struct fw_ohci *ohci = fw_ohci(card);
1968 struct iso_context *ctx, *list;
1969 descriptor_callback_t callback;
1970 u64 *channels, dont_care = ~0ULL;
1972 unsigned long flags;
1973 int index, ret = -ENOMEM;
1975 if (type == FW_ISO_CONTEXT_TRANSMIT) {
1976 channels = &dont_care;
1977 mask = &ohci->it_context_mask;
1978 list = ohci->it_context_list;
1979 callback = handle_it_packet;
1981 channels = &ohci->ir_context_channels;
1982 mask = &ohci->ir_context_mask;
1983 list = ohci->ir_context_list;
1984 callback = handle_ir_packet_per_buffer;
1987 spin_lock_irqsave(&ohci->lock, flags);
1988 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
1990 *channels &= ~(1ULL << channel);
1991 *mask &= ~(1 << index);
1993 spin_unlock_irqrestore(&ohci->lock, flags);
1996 return ERR_PTR(-EBUSY);
1998 if (type == FW_ISO_CONTEXT_TRANSMIT)
1999 regs = OHCI1394_IsoXmitContextBase(index);
2001 regs = OHCI1394_IsoRcvContextBase(index);
2004 memset(ctx, 0, sizeof(*ctx));
2005 ctx->header_length = 0;
2006 ctx->header = (void *) __get_free_page(GFP_KERNEL);
2007 if (ctx->header == NULL)
2010 ret = context_init(&ctx->context, ohci, regs, callback);
2012 goto out_with_header;
2017 free_page((unsigned long)ctx->header);
2019 spin_lock_irqsave(&ohci->lock, flags);
2020 *mask |= 1 << index;
2021 spin_unlock_irqrestore(&ohci->lock, flags);
2023 return ERR_PTR(ret);
2026 static int ohci_start_iso(struct fw_iso_context *base,
2027 s32 cycle, u32 sync, u32 tags)
2029 struct iso_context *ctx = container_of(base, struct iso_context, base);
2030 struct fw_ohci *ohci = ctx->context.ohci;
2034 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2035 index = ctx - ohci->it_context_list;
2038 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2039 (cycle & 0x7fff) << 16;
2041 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2042 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2043 context_run(&ctx->context, match);
2045 index = ctx - ohci->ir_context_list;
2046 control = IR_CONTEXT_ISOCH_HEADER;
2047 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2049 match |= (cycle & 0x07fff) << 12;
2050 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2053 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2054 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2055 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2056 context_run(&ctx->context, control);
2062 static int ohci_stop_iso(struct fw_iso_context *base)
2064 struct fw_ohci *ohci = fw_ohci(base->card);
2065 struct iso_context *ctx = container_of(base, struct iso_context, base);
2068 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2069 index = ctx - ohci->it_context_list;
2070 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2072 index = ctx - ohci->ir_context_list;
2073 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2076 context_stop(&ctx->context);
2081 static void ohci_free_iso_context(struct fw_iso_context *base)
2083 struct fw_ohci *ohci = fw_ohci(base->card);
2084 struct iso_context *ctx = container_of(base, struct iso_context, base);
2085 unsigned long flags;
2088 ohci_stop_iso(base);
2089 context_release(&ctx->context);
2090 free_page((unsigned long)ctx->header);
2092 spin_lock_irqsave(&ohci->lock, flags);
2094 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2095 index = ctx - ohci->it_context_list;
2096 ohci->it_context_mask |= 1 << index;
2098 index = ctx - ohci->ir_context_list;
2099 ohci->ir_context_mask |= 1 << index;
2100 ohci->ir_context_channels |= 1ULL << base->channel;
2103 spin_unlock_irqrestore(&ohci->lock, flags);
2106 static int ohci_queue_iso_transmit(struct fw_iso_context *base,
2107 struct fw_iso_packet *packet,
2108 struct fw_iso_buffer *buffer,
2109 unsigned long payload)
2111 struct iso_context *ctx = container_of(base, struct iso_context, base);
2112 struct descriptor *d, *last, *pd;
2113 struct fw_iso_packet *p;
2115 dma_addr_t d_bus, page_bus;
2116 u32 z, header_z, payload_z, irq;
2117 u32 payload_index, payload_end_index, next_page_index;
2118 int page, end_page, i, length, offset;
2121 payload_index = payload;
2127 if (p->header_length > 0)
2130 /* Determine the first page the payload isn't contained in. */
2131 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2132 if (p->payload_length > 0)
2133 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2139 /* Get header size in number of descriptors. */
2140 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2142 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2147 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2148 d[0].req_count = cpu_to_le16(8);
2150 * Link the skip address to this descriptor itself. This causes
2151 * a context to skip a cycle whenever lost cycles or FIFO
2152 * overruns occur, without dropping the data. The application
2153 * should then decide whether this is an error condition or not.
2154 * FIXME: Make the context's cycle-lost behaviour configurable?
2156 d[0].branch_address = cpu_to_le32(d_bus | z);
2158 header = (__le32 *) &d[1];
2159 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2160 IT_HEADER_TAG(p->tag) |
2161 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2162 IT_HEADER_CHANNEL(ctx->base.channel) |
2163 IT_HEADER_SPEED(ctx->base.speed));
2165 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2166 p->payload_length));
2169 if (p->header_length > 0) {
2170 d[2].req_count = cpu_to_le16(p->header_length);
2171 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2172 memcpy(&d[z], p->header, p->header_length);
2175 pd = d + z - payload_z;
2176 payload_end_index = payload_index + p->payload_length;
2177 for (i = 0; i < payload_z; i++) {
2178 page = payload_index >> PAGE_SHIFT;
2179 offset = payload_index & ~PAGE_MASK;
2180 next_page_index = (page + 1) << PAGE_SHIFT;
2182 min(next_page_index, payload_end_index) - payload_index;
2183 pd[i].req_count = cpu_to_le16(length);
2185 page_bus = page_private(buffer->pages[page]);
2186 pd[i].data_address = cpu_to_le32(page_bus + offset);
2188 payload_index += length;
2192 irq = DESCRIPTOR_IRQ_ALWAYS;
2194 irq = DESCRIPTOR_NO_IRQ;
2196 last = z == 2 ? d : d + z - 1;
2197 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2199 DESCRIPTOR_BRANCH_ALWAYS |
2202 context_append(&ctx->context, d, z, header_z);
2207 static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2208 struct fw_iso_packet *packet,
2209 struct fw_iso_buffer *buffer,
2210 unsigned long payload)
2212 struct iso_context *ctx = container_of(base, struct iso_context, base);
2213 struct descriptor *d, *pd;
2214 struct fw_iso_packet *p = packet;
2215 dma_addr_t d_bus, page_bus;
2216 u32 z, header_z, rest;
2218 int page, offset, packet_count, header_size, payload_per_buffer;
2221 * The OHCI controller puts the isochronous header and trailer in the
2222 * buffer, so we need at least 8 bytes.
2224 packet_count = p->header_length / ctx->base.header_size;
2225 header_size = max(ctx->base.header_size, (size_t)8);
2227 /* Get header size in number of descriptors. */
2228 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2229 page = payload >> PAGE_SHIFT;
2230 offset = payload & ~PAGE_MASK;
2231 payload_per_buffer = p->payload_length / packet_count;
2233 for (i = 0; i < packet_count; i++) {
2234 /* d points to the header descriptor */
2235 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2236 d = context_get_descriptors(&ctx->context,
2237 z + header_z, &d_bus);
2241 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
2242 DESCRIPTOR_INPUT_MORE);
2243 if (p->skip && i == 0)
2244 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2245 d->req_count = cpu_to_le16(header_size);
2246 d->res_count = d->req_count;
2247 d->transfer_status = 0;
2248 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2250 rest = payload_per_buffer;
2252 for (j = 1; j < z; j++) {
2254 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2255 DESCRIPTOR_INPUT_MORE);
2257 if (offset + rest < PAGE_SIZE)
2260 length = PAGE_SIZE - offset;
2261 pd->req_count = cpu_to_le16(length);
2262 pd->res_count = pd->req_count;
2263 pd->transfer_status = 0;
2265 page_bus = page_private(buffer->pages[page]);
2266 pd->data_address = cpu_to_le32(page_bus + offset);
2268 offset = (offset + length) & ~PAGE_MASK;
2273 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2274 DESCRIPTOR_INPUT_LAST |
2275 DESCRIPTOR_BRANCH_ALWAYS);
2276 if (p->interrupt && i == packet_count - 1)
2277 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2279 context_append(&ctx->context, d, z, header_z);
2285 static int ohci_queue_iso(struct fw_iso_context *base,
2286 struct fw_iso_packet *packet,
2287 struct fw_iso_buffer *buffer,
2288 unsigned long payload)
2290 struct iso_context *ctx = container_of(base, struct iso_context, base);
2291 unsigned long flags;
2294 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2295 if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2296 ret = ohci_queue_iso_transmit(base, packet, buffer, payload);
2298 ret = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2300 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2305 static const struct fw_card_driver ohci_driver = {
2306 .enable = ohci_enable,
2307 .update_phy_reg = ohci_update_phy_reg,
2308 .set_config_rom = ohci_set_config_rom,
2309 .send_request = ohci_send_request,
2310 .send_response = ohci_send_response,
2311 .cancel_packet = ohci_cancel_packet,
2312 .enable_phys_dma = ohci_enable_phys_dma,
2313 .get_cycle_time = ohci_get_cycle_time,
2315 .allocate_iso_context = ohci_allocate_iso_context,
2316 .free_iso_context = ohci_free_iso_context,
2317 .queue_iso = ohci_queue_iso,
2318 .start_iso = ohci_start_iso,
2319 .stop_iso = ohci_stop_iso,
2322 #ifdef CONFIG_PPC_PMAC
2323 static void ohci_pmac_on(struct pci_dev *dev)
2325 if (machine_is(powermac)) {
2326 struct device_node *ofn = pci_device_to_OF_node(dev);
2329 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2330 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2335 static void ohci_pmac_off(struct pci_dev *dev)
2337 if (machine_is(powermac)) {
2338 struct device_node *ofn = pci_device_to_OF_node(dev);
2341 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2342 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2347 #define ohci_pmac_on(dev)
2348 #define ohci_pmac_off(dev)
2349 #endif /* CONFIG_PPC_PMAC */
2351 static int __devinit pci_probe(struct pci_dev *dev,
2352 const struct pci_device_id *ent)
2354 struct fw_ohci *ohci;
2355 u32 bus_options, max_receive, link_speed, version;
2357 int i, err, n_ir, n_it;
2360 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2366 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2370 err = pci_enable_device(dev);
2372 fw_error("Failed to enable OHCI hardware\n");
2376 pci_set_master(dev);
2377 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2378 pci_set_drvdata(dev, ohci);
2380 spin_lock_init(&ohci->lock);
2382 tasklet_init(&ohci->bus_reset_tasklet,
2383 bus_reset_tasklet, (unsigned long)ohci);
2385 err = pci_request_region(dev, 0, ohci_driver_name);
2387 fw_error("MMIO resource unavailable\n");
2391 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2392 if (ohci->registers == NULL) {
2393 fw_error("Failed to remap registers\n");
2398 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
2399 if (ohci_quirks[i].vendor == dev->vendor &&
2400 (ohci_quirks[i].device == dev->device ||
2401 ohci_quirks[i].device == (unsigned short)PCI_ANY_ID)) {
2402 ohci->quirks = ohci_quirks[i].flags;
2406 ohci->quirks = param_quirks;
2408 ar_context_init(&ohci->ar_request_ctx, ohci,
2409 OHCI1394_AsReqRcvContextControlSet);
2411 ar_context_init(&ohci->ar_response_ctx, ohci,
2412 OHCI1394_AsRspRcvContextControlSet);
2414 context_init(&ohci->at_request_ctx, ohci,
2415 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2417 context_init(&ohci->at_response_ctx, ohci,
2418 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2420 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2421 ohci->ir_context_channels = ~0ULL;
2422 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2423 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2424 n_ir = hweight32(ohci->ir_context_mask);
2425 size = sizeof(struct iso_context) * n_ir;
2426 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2428 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2429 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2430 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2431 n_it = hweight32(ohci->it_context_mask);
2432 size = sizeof(struct iso_context) * n_it;
2433 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2435 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2440 /* self-id dma buffer allocation */
2441 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2445 if (ohci->self_id_cpu == NULL) {
2450 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2451 max_receive = (bus_options >> 12) & 0xf;
2452 link_speed = bus_options & 0x7;
2453 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2454 reg_read(ohci, OHCI1394_GUIDLo);
2456 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2460 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2461 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
2462 "%d IR + %d IT contexts, quirks 0x%x\n",
2463 dev_name(&dev->dev), version >> 16, version & 0xff,
2464 n_ir, n_it, ohci->quirks);
2469 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2470 ohci->self_id_cpu, ohci->self_id_bus);
2472 kfree(ohci->ir_context_list);
2473 kfree(ohci->it_context_list);
2474 context_release(&ohci->at_response_ctx);
2475 context_release(&ohci->at_request_ctx);
2476 ar_context_release(&ohci->ar_response_ctx);
2477 ar_context_release(&ohci->ar_request_ctx);
2478 pci_iounmap(dev, ohci->registers);
2480 pci_release_region(dev, 0);
2482 pci_disable_device(dev);
2488 fw_error("Out of memory\n");
2493 static void pci_remove(struct pci_dev *dev)
2495 struct fw_ohci *ohci;
2497 ohci = pci_get_drvdata(dev);
2498 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2500 fw_core_remove_card(&ohci->card);
2503 * FIXME: Fail all pending packets here, now that the upper
2504 * layers can't queue any more.
2507 software_reset(ohci);
2508 free_irq(dev->irq, ohci);
2510 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
2511 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2512 ohci->next_config_rom, ohci->next_config_rom_bus);
2513 if (ohci->config_rom)
2514 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2515 ohci->config_rom, ohci->config_rom_bus);
2516 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2517 ohci->self_id_cpu, ohci->self_id_bus);
2518 ar_context_release(&ohci->ar_request_ctx);
2519 ar_context_release(&ohci->ar_response_ctx);
2520 context_release(&ohci->at_request_ctx);
2521 context_release(&ohci->at_response_ctx);
2522 kfree(ohci->it_context_list);
2523 kfree(ohci->ir_context_list);
2524 pci_iounmap(dev, ohci->registers);
2525 pci_release_region(dev, 0);
2526 pci_disable_device(dev);
2530 fw_notify("Removed fw-ohci device.\n");
2534 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2536 struct fw_ohci *ohci = pci_get_drvdata(dev);
2539 software_reset(ohci);
2540 free_irq(dev->irq, ohci);
2541 err = pci_save_state(dev);
2543 fw_error("pci_save_state failed\n");
2546 err = pci_set_power_state(dev, pci_choose_state(dev, state));
2548 fw_error("pci_set_power_state failed with %d\n", err);
2554 static int pci_resume(struct pci_dev *dev)
2556 struct fw_ohci *ohci = pci_get_drvdata(dev);
2560 pci_set_power_state(dev, PCI_D0);
2561 pci_restore_state(dev);
2562 err = pci_enable_device(dev);
2564 fw_error("pci_enable_device failed\n");
2568 return ohci_enable(&ohci->card, NULL, 0);
2572 static const struct pci_device_id pci_table[] = {
2573 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2577 MODULE_DEVICE_TABLE(pci, pci_table);
2579 static struct pci_driver fw_ohci_pci_driver = {
2580 .name = ohci_driver_name,
2581 .id_table = pci_table,
2583 .remove = pci_remove,
2585 .resume = pci_resume,
2586 .suspend = pci_suspend,
2590 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2591 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2592 MODULE_LICENSE("GPL");
2594 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2595 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2596 MODULE_ALIAS("ohci1394");
2599 static int __init fw_ohci_init(void)
2601 return pci_register_driver(&fw_ohci_pci_driver);
2604 static void __exit fw_ohci_cleanup(void)
2606 pci_unregister_driver(&fw_ohci_pci_driver);
2609 module_init(fw_ohci_init);
2610 module_exit(fw_ohci_cleanup);