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   1 /*
   2  * Intel D82875P Memory Controller kernel module
   3  * (C) 2003 Linux Networx (http://lnxi.com)
   4  * This file may be distributed under the terms of the
   5  * GNU General Public License.
   6  *
   7  * Written by Thayne Harbaugh
   8  * Contributors:
   9  *      Wang Zhenyu at intel.com
  10  *
  11  * $Id: edac_i82875p.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
  12  *
  13  * Note: E7210 appears same as D82875P - zhenyu.z.wang at intel.com
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/init.h>
  18 #include <linux/pci.h>
  19 #include <linux/pci_ids.h>
  20 #include <linux/slab.h>
  21 #include <linux/edac.h>
  22 #include "edac_core.h"
  23
  24 #define I82875P_REVISION        " Ver: 2.0.2 " __DATE__
  25 #define EDAC_MOD_STR            "i82875p_edac"
  26
  27 #define i82875p_printk(level, fmt, arg...) \
  28         edac_printk(level, "i82875p", fmt, ##arg)
  29
  30 #define i82875p_mc_printk(mci, level, fmt, arg...) \
  31         edac_mc_chipset_printk(mci, level, "i82875p", fmt, ##arg)
  32
  33 #ifndef PCI_DEVICE_ID_INTEL_82875_0
  34 #define PCI_DEVICE_ID_INTEL_82875_0     0x2578
  35 #endif                          /* PCI_DEVICE_ID_INTEL_82875_0 */
  36
  37 #ifndef PCI_DEVICE_ID_INTEL_82875_6
  38 #define PCI_DEVICE_ID_INTEL_82875_6     0x257e
  39 #endif                          /* PCI_DEVICE_ID_INTEL_82875_6 */
  40
  41 /* four csrows in dual channel, eight in single channel */
  42 #define I82875P_NR_CSROWS(nr_chans) (8/(nr_chans))
  43
  44 /* Intel 82875p register addresses - device 0 function 0 - DRAM Controller */
  45 #define I82875P_EAP             0x58    /* Error Address Pointer (32b)
  46                                          *
  47                                          * 31:12 block address
  48                                          * 11:0  reserved
  49                                          */
  50
  51 #define I82875P_DERRSYN         0x5c    /* DRAM Error Syndrome (8b)
  52                                          *
  53                                          *  7:0  DRAM ECC Syndrome
  54                                          */
  55
  56 #define I82875P_DES             0x5d    /* DRAM Error Status (8b)
  57                                          *
  58                                          *  7:1  reserved
  59                                          *  0    Error channel 0/1
  60                                          */
  61
  62 #define I82875P_ERRSTS          0xc8    /* Error Status Register (16b)
  63                                          *
  64                                          * 15:10 reserved
  65                                          *  9    non-DRAM lock error (ndlock)
  66                                          *  8    Sftwr Generated SMI
  67                                          *  7    ECC UE
  68                                          *  6    reserved
  69                                          *  5    MCH detects unimplemented cycle
  70                                          *  4    AGP access outside GA
  71                                          *  3    Invalid AGP access
  72                                          *  2    Invalid GA translation table
  73                                          *  1    Unsupported AGP command
  74                                          *  0    ECC CE
  75                                          */
  76
  77 #define I82875P_ERRCMD          0xca    /* Error Command (16b)
  78                                          *
  79                                          * 15:10 reserved
  80                                          *  9    SERR on non-DRAM lock
  81                                          *  8    SERR on ECC UE
  82                                          *  7    SERR on ECC CE
  83                                          *  6    target abort on high exception
  84                                          *  5    detect unimplemented cyc
  85                                          *  4    AGP access outside of GA
  86                                          *  3    SERR on invalid AGP access
  87                                          *  2    invalid translation table
  88                                          *  1    SERR on unsupported AGP command
  89                                          *  0    reserved
  90                                          */
  91
  92 /* Intel 82875p register addresses - device 6 function 0 - DRAM Controller */
  93 #define I82875P_PCICMD6         0x04    /* PCI Command Register (16b)
  94                                          *
  95                                          * 15:10 reserved
  96                                          *  9    fast back-to-back - ro 0
  97                                          *  8    SERR enable - ro 0
  98                                          *  7    addr/data stepping - ro 0
  99                                          *  6    parity err enable - ro 0
 100                                          *  5    VGA palette snoop - ro 0
 101                                          *  4    mem wr & invalidate - ro 0
 102                                          *  3    special cycle - ro 0
 103                                          *  2    bus master - ro 0
 104                                          *  1    mem access dev6 - 0(dis),1(en)
 105                                          *  0    IO access dev3 - 0(dis),1(en)
 106                                          */
 107
 108 #define I82875P_BAR6            0x10    /* Mem Delays Base ADDR Reg (32b)
 109                                          *
 110                                          * 31:12 mem base addr [31:12]
 111                                          * 11:4  address mask - ro 0
 112                                          *  3    prefetchable - ro 0(non),1(pre)
 113                                          *  2:1  mem type - ro 0
 114                                          *  0    mem space - ro 0
 115                                          */
 116
 117 /* Intel 82875p MMIO register space - device 0 function 0 - MMR space */
 118
 119 #define I82875P_DRB_SHIFT 26    /* 64MiB grain */
 120 #define I82875P_DRB             0x00    /* DRAM Row Boundary (8b x 8)
 121                                          *
 122                                          *  7    reserved
 123                                          *  6:0  64MiB row boundary addr
 124                                          */
 125
 126 #define I82875P_DRA             0x10    /* DRAM Row Attribute (4b x 8)
 127                                          *
 128                                          *  7    reserved
 129                                          *  6:4  row attr row 1
 130                                          *  3    reserved
 131                                          *  2:0  row attr row 0
 132                                          *
 133                                          * 000 =  4KiB
 134                                          * 001 =  8KiB
 135                                          * 010 = 16KiB
 136                                          * 011 = 32KiB
 137                                          */
 138
 139 #define I82875P_DRC             0x68    /* DRAM Controller Mode (32b)
 140                                          *
 141                                          * 31:30 reserved
 142                                          * 29    init complete
 143                                          * 28:23 reserved
 144                                          * 22:21 nr chan 00=1,01=2
 145                                          * 20    reserved
 146                                          * 19:18 Data Integ Mode 00=none,01=ecc
 147                                          * 17:11 reserved
 148                                          * 10:8  refresh mode
 149                                          *  7    reserved
 150                                          *  6:4  mode select
 151                                          *  3:2  reserved
 152                                          *  1:0  DRAM type 01=DDR
 153                                          */
 154
 155 enum i82875p_chips {
 156         I82875P = 0,
 157 };
 158
 159 struct i82875p_pvt {
 160         struct pci_dev *ovrfl_pdev;
 161         void __iomem *ovrfl_window;
 162 };
 163
 164 struct i82875p_dev_info {
 165         const char *ctl_name;
 166 };
 167
 168 struct i82875p_error_info {
 169         u16 errsts;
 170         u32 eap;
 171         u8 des;
 172         u8 derrsyn;
 173         u16 errsts2;
 174 };
 175
 176 static const struct i82875p_dev_info i82875p_devs[] = {
 177         [I82875P] = {
 178                 .ctl_name = "i82875p"},
 179 };
 180
 181 static struct pci_dev *mci_pdev;        /* init dev: in case that AGP code has
 182                                          * already registered driver
 183                                          */
 184
 185 static int i82875p_registered = 1;
 186
 187 static struct edac_pci_ctl_info *i82875p_pci;
 188
 189 static void i82875p_get_error_info(struct mem_ctl_info *mci,
 190                                 struct i82875p_error_info *info)
 191 {
 192         struct pci_dev *pdev;
 193
 194         pdev = to_pci_dev(mci->dev);
 195
 196         /*
 197          * This is a mess because there is no atomic way to read all the
 198          * registers at once and the registers can transition from CE being
 199          * overwritten by UE.
 200          */
 201         pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts);
 202
 203         if (!(info->errsts & 0x0081))
 204                 return;
 205
 206         pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
 207         pci_read_config_byte(pdev, I82875P_DES, &info->des);
 208         pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn);
 209         pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts2);
 210
 211         /*
 212          * If the error is the same then we can for both reads then
 213          * the first set of reads is valid.  If there is a change then
 214          * there is a CE no info and the second set of reads is valid
 215          * and should be UE info.
 216          */
 217         if ((info->errsts ^ info->errsts2) & 0x0081) {
 218                 pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
 219                 pci_read_config_byte(pdev, I82875P_DES, &info->des);
 220                 pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn);
 221         }
 222
 223         pci_write_bits16(pdev, I82875P_ERRSTS, 0x0081, 0x0081);
 224 }
 225
 226 static int i82875p_process_error_info(struct mem_ctl_info *mci,
 227                                 struct i82875p_error_info *info,
 228                                 int handle_errors)
 229 {
 230         int row, multi_chan;
 231
 232         multi_chan = mci->csrows[0].nr_channels - 1;
 233
 234         if (!(info->errsts & 0x0081))
 235                 return 0;
 236
 237         if (!handle_errors)
 238                 return 1;
 239
 240         if ((info->errsts ^ info->errsts2) & 0x0081) {
 241                 edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
 242                 info->errsts = info->errsts2;
 243         }
 244
 245         info->eap >>= PAGE_SHIFT;
 246         row = edac_mc_find_csrow_by_page(mci, info->eap);
 247
 248         if (info->errsts & 0x0080)
 249                 edac_mc_handle_ue(mci, info->eap, 0, row, "i82875p UE");
 250         else
 251                 edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row,
 252                                 multi_chan ? (info->des & 0x1) : 0,
 253                                 "i82875p CE");
 254
 255         return 1;
 256 }
 257
 258 static void i82875p_check(struct mem_ctl_info *mci)
 259 {
 260         struct i82875p_error_info info;
 261
 262         debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
 263         i82875p_get_error_info(mci, &info);
 264         i82875p_process_error_info(mci, &info, 1);
 265 }
 266
 267 /* Return 0 on success or 1 on failure. */
 268 static int i82875p_setup_overfl_dev(struct pci_dev *pdev,
 269                                 struct pci_dev **ovrfl_pdev,
 270                                 void __iomem **ovrfl_window)
 271 {
 272         struct pci_dev *dev;
 273         void __iomem *window;
 274         int err;
 275
 276         *ovrfl_pdev = NULL;
 277         *ovrfl_window = NULL;
 278         dev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);
 279
 280         if (dev == NULL) {
 281                 /* Intel tells BIOS developers to hide device 6 which
 282                  * configures the overflow device access containing
 283                  * the DRBs - this is where we expose device 6.
 284                  * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
 285                  */
 286                 pci_write_bits8(pdev, 0xf4, 0x2, 0x2);
 287                 dev = pci_scan_single_device(pdev->bus, PCI_DEVFN(6, 0));
 288
 289                 if (dev == NULL)
 290                         return 1;
 291
 292                 err = pci_bus_add_device(dev);
 293                 if (err) {
 294                         i82875p_printk(KERN_ERR,
 295                                 "%s(): pci_bus_add_device() Failed\n",
 296                                 __func__);
 297                 }
 298         }
 299
 300         *ovrfl_pdev = dev;
 301
 302         if (pci_enable_device(dev)) {
 303                 i82875p_printk(KERN_ERR, "%s(): Failed to enable overflow "
 304                         "device\n", __func__);
 305                 return 1;
 306         }
 307
 308         if (pci_request_regions(dev, pci_name(dev))) {
 309 #ifdef CORRECT_BIOS
 310                 goto fail0;
 311 #endif
 312         }
 313
 314         /* cache is irrelevant for PCI bus reads/writes */
 315         window = ioremap_nocache(pci_resource_start(dev, 0),
 316                                  pci_resource_len(dev, 0));
 317
 318         if (window == NULL) {
 319                 i82875p_printk(KERN_ERR, "%s(): Failed to ioremap bar6\n",
 320                         __func__);
 321                 goto fail1;
 322         }
 323
 324         *ovrfl_window = window;
 325         return 0;
 326
 327 fail1:
 328         pci_release_regions(dev);
 329
 330 #ifdef CORRECT_BIOS
 331 fail0:
 332         pci_disable_device(dev);
 333 #endif
 334         /* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
 335         return 1;
 336 }
 337
 338 /* Return 1 if dual channel mode is active.  Else return 0. */
 339 static inline int dual_channel_active(u32 drc)
 340 {
 341         return (drc >> 21) & 0x1;
 342 }
 343
 344 static void i82875p_init_csrows(struct mem_ctl_info *mci,
 345                                 struct pci_dev *pdev,
 346                                 void __iomem * ovrfl_window, u32 drc)
 347 {
 348         struct csrow_info *csrow;
 349         unsigned long last_cumul_size;
 350         u8 value;
 351         u32 drc_ddim;           /* DRAM Data Integrity Mode 0=none,2=edac */
 352         u32 cumul_size;
 353         int index;
 354
 355         drc_ddim = (drc >> 18) & 0x1;
 356         last_cumul_size = 0;
 357
 358         /* The dram row boundary (DRB) reg values are boundary address
 359          * for each DRAM row with a granularity of 32 or 64MB (single/dual
 360          * channel operation).  DRB regs are cumulative; therefore DRB7 will
 361          * contain the total memory contained in all eight rows.
 362          */
 363
 364         for (index = 0; index < mci->nr_csrows; index++) {
 365                 csrow = &mci->csrows[index];
 366
 367                 value = readb(ovrfl_window + I82875P_DRB + index);
 368                 cumul_size = value << (I82875P_DRB_SHIFT - PAGE_SHIFT);
 369                 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
 370                         cumul_size);
 371                 if (cumul_size == last_cumul_size)
 372                         continue;       /* not populated */
 373
 374                 csrow->first_page = last_cumul_size;
 375                 csrow->last_page = cumul_size - 1;
 376                 csrow->nr_pages = cumul_size - last_cumul_size;
 377                 last_cumul_size = cumul_size;
 378                 csrow->grain = 1 << 12; /* I82875P_EAP has 4KiB reolution */
 379                 csrow->mtype = MEM_DDR;
 380                 csrow->dtype = DEV_UNKNOWN;
 381                 csrow->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE;
 382         }
 383 }
 384
 385 static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
 386 {
 387         int rc = -ENODEV;
 388         struct mem_ctl_info *mci;
 389         struct i82875p_pvt *pvt;
 390         struct pci_dev *ovrfl_pdev;
 391         void __iomem *ovrfl_window;
 392         u32 drc;
 393         u32 nr_chans;
 394         struct i82875p_error_info discard;
 395
 396         debugf0("%s()\n", __func__);
 397
 398         ovrfl_pdev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);
 399
 400         if (i82875p_setup_overfl_dev(pdev, &ovrfl_pdev, &ovrfl_window))
 401                 return -ENODEV;
 402         drc = readl(ovrfl_window + I82875P_DRC);
 403         nr_chans = dual_channel_active(drc) + 1;
 404         mci = edac_mc_alloc(sizeof(*pvt), I82875P_NR_CSROWS(nr_chans),
 405                         nr_chans, 0);
 406
 407         if (!mci) {
 408                 rc = -ENOMEM;
 409                 goto fail0;
 410         }
 411
 412         debugf3("%s(): init mci\n", __func__);
 413         mci->dev = &pdev->dev;
 414         mci->mtype_cap = MEM_FLAG_DDR;
 415         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
 416         mci->edac_cap = EDAC_FLAG_UNKNOWN;
 417         mci->mod_name = EDAC_MOD_STR;
 418         mci->mod_ver = I82875P_REVISION;
 419         mci->ctl_name = i82875p_devs[dev_idx].ctl_name;
 420         mci->dev_name = pci_name(pdev);
 421         mci->edac_check = i82875p_check;
 422         mci->ctl_page_to_phys = NULL;
 423         debugf3("%s(): init pvt\n", __func__);
 424         pvt = (struct i82875p_pvt *)mci->pvt_info;
 425         pvt->ovrfl_pdev = ovrfl_pdev;
 426         pvt->ovrfl_window = ovrfl_window;
 427         i82875p_init_csrows(mci, pdev, ovrfl_window, drc);
 428         i82875p_get_error_info(mci, &discard);  /* clear counters */
 429
 430         /* Here we assume that we will never see multiple instances of this
 431          * type of memory controller.  The ID is therefore hardcoded to 0.
 432          */
 433         if (edac_mc_add_mc(mci)) {
 434                 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
 435                 goto fail1;
 436         }
 437
 438         /* allocating generic PCI control info */
 439         i82875p_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
 440         if (!i82875p_pci) {
 441                 printk(KERN_WARNING
 442                         "%s(): Unable to create PCI control\n",
 443                         __func__);
 444                 printk(KERN_WARNING
 445                         "%s(): PCI error report via EDAC not setup\n",
 446                         __func__);
 447         }
 448
 449         /* get this far and it's successful */
 450         debugf3("%s(): success\n", __func__);
 451         return 0;
 452
 453 fail1:
 454         edac_mc_free(mci);
 455
 456 fail0:
 457         iounmap(ovrfl_window);
 458         pci_release_regions(ovrfl_pdev);
 459
 460         pci_disable_device(ovrfl_pdev);
 461         /* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
 462         return rc;
 463 }
 464
 465 /* returns count (>= 0), or negative on error */
 466 static int __devinit i82875p_init_one(struct pci_dev *pdev,
 467                                 const struct pci_device_id *ent)
 468 {
 469         int rc;
 470
 471         debugf0("%s()\n", __func__);
 472         i82875p_printk(KERN_INFO, "i82875p init one\n");
 473
 474         if (pci_enable_device(pdev) < 0)
 475                 return -EIO;
 476
 477         rc = i82875p_probe1(pdev, ent->driver_data);
 478
 479         if (mci_pdev == NULL)
 480                 mci_pdev = pci_dev_get(pdev);
 481
 482         return rc;
 483 }
 484
 485 static void __devexit i82875p_remove_one(struct pci_dev *pdev)
 486 {
 487         struct mem_ctl_info *mci;
 488         struct i82875p_pvt *pvt = NULL;
 489
 490         debugf0("%s()\n", __func__);
 491
 492         if (i82875p_pci)
 493                 edac_pci_release_generic_ctl(i82875p_pci);
 494
 495         if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
 496                 return;
 497
 498         pvt = (struct i82875p_pvt *)mci->pvt_info;
 499
 500         if (pvt->ovrfl_window)
 501                 iounmap(pvt->ovrfl_window);
 502
 503         if (pvt->ovrfl_pdev) {
 504 #ifdef CORRECT_BIOS
 505                 pci_release_regions(pvt->ovrfl_pdev);
 506 #endif                          /*CORRECT_BIOS */
 507                 pci_disable_device(pvt->ovrfl_pdev);
 508                 pci_dev_put(pvt->ovrfl_pdev);
 509         }
 510
 511         edac_mc_free(mci);
 512 }
 513
 514 static const struct pci_device_id i82875p_pci_tbl[] __devinitdata = {
 515         {
 516          PCI_VEND_DEV(INTEL, 82875_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 517          I82875P},
 518         {
 519          0,
 520          }                      /* 0 terminated list. */
 521 };
 522
 523 MODULE_DEVICE_TABLE(pci, i82875p_pci_tbl);
 524
 525 static struct pci_driver i82875p_driver = {
 526         .name = EDAC_MOD_STR,
 527         .probe = i82875p_init_one,
 528         .remove = __devexit_p(i82875p_remove_one),
 529         .id_table = i82875p_pci_tbl,
 530 };
 531
 532 static int __init i82875p_init(void)
 533 {
 534         int pci_rc;
 535
 536         debugf3("%s()\n", __func__);
 537
 538        /* Ensure that the OPSTATE is set correctly for POLL or NMI */
 539        opstate_init();
 540
 541         pci_rc = pci_register_driver(&i82875p_driver);
 542
 543         if (pci_rc < 0)
 544                 goto fail0;
 545
 546         if (mci_pdev == NULL) {
 547                 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
 548                                         PCI_DEVICE_ID_INTEL_82875_0, NULL);
 549
 550                 if (!mci_pdev) {
 551                         debugf0("875p pci_get_device fail\n");
 552                         pci_rc = -ENODEV;
 553                         goto fail1;
 554                 }
 555
 556                 pci_rc = i82875p_init_one(mci_pdev, i82875p_pci_tbl);
 557
 558                 if (pci_rc < 0) {
 559                         debugf0("875p init fail\n");
 560                         pci_rc = -ENODEV;
 561                         goto fail1;
 562                 }
 563         }
 564
 565         return 0;
 566
 567 fail1:
 568         pci_unregister_driver(&i82875p_driver);
 569
 570 fail0:
 571         if (mci_pdev != NULL)
 572                 pci_dev_put(mci_pdev);
 573
 574         return pci_rc;
 575 }
 576
 577 static void __exit i82875p_exit(void)
 578 {
 579         debugf3("%s()\n", __func__);
 580
 581         pci_unregister_driver(&i82875p_driver);
 582
 583         if (!i82875p_registered) {
 584                 i82875p_remove_one(mci_pdev);
 585                 pci_dev_put(mci_pdev);
 586         }
 587 }
 588
 589 module_init(i82875p_init);
 590 module_exit(i82875p_exit);
 591
 592 MODULE_LICENSE("GPL");
 593 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
 594 MODULE_DESCRIPTION("MC support for Intel 82875 memory hub controllers");
 595
 596 module_param(edac_op_state, int, 0444);
 597 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");