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   1 /*
   2  * Intel D82875P Memory Controller kernel module
   3  * (C) 2003 Linux Networx (http://lnxi.com)
   4  * This file may be distributed under the terms of the
   5  * GNU General Public License.
   6  *
   7  * Written by Thayne Harbaugh
   8  * Contributors:
   9  *      Wang Zhenyu at intel.com
  10  *
  11  * $Id: edac_i82875p.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
  12  *
  13  * Note: E7210 appears same as D82875P - zhenyu.z.wang at intel.com
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/init.h>
  18 #include <linux/pci.h>
  19 #include <linux/pci_ids.h>
  20 #include <linux/slab.h>
  21 #include "edac_core.h"
  22
  23 #define I82875P_REVISION        " Ver: 2.0.2 " __DATE__
  24 #define EDAC_MOD_STR            "i82875p_edac"
  25
  26 #define i82875p_printk(level, fmt, arg...) \
  27         edac_printk(level, "i82875p", fmt, ##arg)
  28
  29 #define i82875p_mc_printk(mci, level, fmt, arg...) \
  30         edac_mc_chipset_printk(mci, level, "i82875p", fmt, ##arg)
  31
  32 #ifndef PCI_DEVICE_ID_INTEL_82875_0
  33 #define PCI_DEVICE_ID_INTEL_82875_0     0x2578
  34 #endif                          /* PCI_DEVICE_ID_INTEL_82875_0 */
  35
  36 #ifndef PCI_DEVICE_ID_INTEL_82875_6
  37 #define PCI_DEVICE_ID_INTEL_82875_6     0x257e
  38 #endif                          /* PCI_DEVICE_ID_INTEL_82875_6 */
  39
  40 /* four csrows in dual channel, eight in single channel */
  41 #define I82875P_NR_CSROWS(nr_chans) (8/(nr_chans))
  42
  43 /* Intel 82875p register addresses - device 0 function 0 - DRAM Controller */
  44 #define I82875P_EAP             0x58    /* Error Address Pointer (32b)
  45                                          *
  46                                          * 31:12 block address
  47                                          * 11:0  reserved
  48                                          */
  49
  50 #define I82875P_DERRSYN         0x5c    /* DRAM Error Syndrome (8b)
  51                                          *
  52                                          *  7:0  DRAM ECC Syndrome
  53                                          */
  54
  55 #define I82875P_DES             0x5d    /* DRAM Error Status (8b)
  56                                          *
  57                                          *  7:1  reserved
  58                                          *  0    Error channel 0/1
  59                                          */
  60
  61 #define I82875P_ERRSTS          0xc8    /* Error Status Register (16b)
  62                                          *
  63                                          * 15:10 reserved
  64                                          *  9    non-DRAM lock error (ndlock)
  65                                          *  8    Sftwr Generated SMI
  66                                          *  7    ECC UE
  67                                          *  6    reserved
  68                                          *  5    MCH detects unimplemented cycle
  69                                          *  4    AGP access outside GA
  70                                          *  3    Invalid AGP access
  71                                          *  2    Invalid GA translation table
  72                                          *  1    Unsupported AGP command
  73                                          *  0    ECC CE
  74                                          */
  75
  76 #define I82875P_ERRCMD          0xca    /* Error Command (16b)
  77                                          *
  78                                          * 15:10 reserved
  79                                          *  9    SERR on non-DRAM lock
  80                                          *  8    SERR on ECC UE
  81                                          *  7    SERR on ECC CE
  82                                          *  6    target abort on high exception
  83                                          *  5    detect unimplemented cyc
  84                                          *  4    AGP access outside of GA
  85                                          *  3    SERR on invalid AGP access
  86                                          *  2    invalid translation table
  87                                          *  1    SERR on unsupported AGP command
  88                                          *  0    reserved
  89                                          */
  90
  91 /* Intel 82875p register addresses - device 6 function 0 - DRAM Controller */
  92 #define I82875P_PCICMD6         0x04    /* PCI Command Register (16b)
  93                                          *
  94                                          * 15:10 reserved
  95                                          *  9    fast back-to-back - ro 0
  96                                          *  8    SERR enable - ro 0
  97                                          *  7    addr/data stepping - ro 0
  98                                          *  6    parity err enable - ro 0
  99                                          *  5    VGA palette snoop - ro 0
 100                                          *  4    mem wr & invalidate - ro 0
 101                                          *  3    special cycle - ro 0
 102                                          *  2    bus master - ro 0
 103                                          *  1    mem access dev6 - 0(dis),1(en)
 104                                          *  0    IO access dev3 - 0(dis),1(en)
 105                                          */
 106
 107 #define I82875P_BAR6            0x10    /* Mem Delays Base ADDR Reg (32b)
 108                                          *
 109                                          * 31:12 mem base addr [31:12]
 110                                          * 11:4  address mask - ro 0
 111                                          *  3    prefetchable - ro 0(non),1(pre)
 112                                          *  2:1  mem type - ro 0
 113                                          *  0    mem space - ro 0
 114                                          */
 115
 116 /* Intel 82875p MMIO register space - device 0 function 0 - MMR space */
 117
 118 #define I82875P_DRB_SHIFT 26    /* 64MiB grain */
 119 #define I82875P_DRB             0x00    /* DRAM Row Boundary (8b x 8)
 120                                          *
 121                                          *  7    reserved
 122                                          *  6:0  64MiB row boundary addr
 123                                          */
 124
 125 #define I82875P_DRA             0x10    /* DRAM Row Attribute (4b x 8)
 126                                          *
 127                                          *  7    reserved
 128                                          *  6:4  row attr row 1
 129                                          *  3    reserved
 130                                          *  2:0  row attr row 0
 131                                          *
 132                                          * 000 =  4KiB
 133                                          * 001 =  8KiB
 134                                          * 010 = 16KiB
 135                                          * 011 = 32KiB
 136                                          */
 137
 138 #define I82875P_DRC             0x68    /* DRAM Controller Mode (32b)
 139                                          *
 140                                          * 31:30 reserved
 141                                          * 29    init complete
 142                                          * 28:23 reserved
 143                                          * 22:21 nr chan 00=1,01=2
 144                                          * 20    reserved
 145                                          * 19:18 Data Integ Mode 00=none,01=ecc
 146                                          * 17:11 reserved
 147                                          * 10:8  refresh mode
 148                                          *  7    reserved
 149                                          *  6:4  mode select
 150                                          *  3:2  reserved
 151                                          *  1:0  DRAM type 01=DDR
 152                                          */
 153
 154 enum i82875p_chips {
 155         I82875P = 0,
 156 };
 157
 158 struct i82875p_pvt {
 159         struct pci_dev *ovrfl_pdev;
 160         void __iomem *ovrfl_window;
 161 };
 162
 163 struct i82875p_dev_info {
 164         const char *ctl_name;
 165 };
 166
 167 struct i82875p_error_info {
 168         u16 errsts;
 169         u32 eap;
 170         u8 des;
 171         u8 derrsyn;
 172         u16 errsts2;
 173 };
 174
 175 static const struct i82875p_dev_info i82875p_devs[] = {
 176         [I82875P] = {
 177                 .ctl_name = "i82875p"},
 178 };
 179
 180 static struct pci_dev *mci_pdev = NULL; /* init dev: in case that AGP code has
 181                                          * already registered driver
 182                                          */
 183
 184 static int i82875p_registered = 1;
 185
 186 static struct edac_pci_ctl_info *i82875p_pci;
 187
 188 static void i82875p_get_error_info(struct mem_ctl_info *mci,
 189                                 struct i82875p_error_info *info)
 190 {
 191         struct pci_dev *pdev;
 192
 193         pdev = to_pci_dev(mci->dev);
 194
 195         /*
 196          * This is a mess because there is no atomic way to read all the
 197          * registers at once and the registers can transition from CE being
 198          * overwritten by UE.
 199          */
 200         pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts);
 201
 202         if (!(info->errsts & 0x0081))
 203                 return;
 204
 205         pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
 206         pci_read_config_byte(pdev, I82875P_DES, &info->des);
 207         pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn);
 208         pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts2);
 209
 210         /*
 211          * If the error is the same then we can for both reads then
 212          * the first set of reads is valid.  If there is a change then
 213          * there is a CE no info and the second set of reads is valid
 214          * and should be UE info.
 215          */
 216         if ((info->errsts ^ info->errsts2) & 0x0081) {
 217                 pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
 218                 pci_read_config_byte(pdev, I82875P_DES, &info->des);
 219                 pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn);
 220         }
 221
 222         pci_write_bits16(pdev, I82875P_ERRSTS, 0x0081, 0x0081);
 223 }
 224
 225 static int i82875p_process_error_info(struct mem_ctl_info *mci,
 226                                 struct i82875p_error_info *info,
 227                                 int handle_errors)
 228 {
 229         int row, multi_chan;
 230
 231         multi_chan = mci->csrows[0].nr_channels - 1;
 232
 233         if (!(info->errsts & 0x0081))
 234                 return 0;
 235
 236         if (!handle_errors)
 237                 return 1;
 238
 239         if ((info->errsts ^ info->errsts2) & 0x0081) {
 240                 edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
 241                 info->errsts = info->errsts2;
 242         }
 243
 244         info->eap >>= PAGE_SHIFT;
 245         row = edac_mc_find_csrow_by_page(mci, info->eap);
 246
 247         if (info->errsts & 0x0080)
 248                 edac_mc_handle_ue(mci, info->eap, 0, row, "i82875p UE");
 249         else
 250                 edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row,
 251                                 multi_chan ? (info->des & 0x1) : 0,
 252                                 "i82875p CE");
 253
 254         return 1;
 255 }
 256
 257 static void i82875p_check(struct mem_ctl_info *mci)
 258 {
 259         struct i82875p_error_info info;
 260
 261         debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
 262         i82875p_get_error_info(mci, &info);
 263         i82875p_process_error_info(mci, &info, 1);
 264 }
 265
 266 /* Return 0 on success or 1 on failure. */
 267 static int i82875p_setup_overfl_dev(struct pci_dev *pdev,
 268                                 struct pci_dev **ovrfl_pdev,
 269                                 void __iomem **ovrfl_window)
 270 {
 271         struct pci_dev *dev;
 272         void __iomem *window;
 273
 274         *ovrfl_pdev = NULL;
 275         *ovrfl_window = NULL;
 276         dev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);
 277
 278         if (dev == NULL) {
 279                 /* Intel tells BIOS developers to hide device 6 which
 280                  * configures the overflow device access containing
 281                  * the DRBs - this is where we expose device 6.
 282                  * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
 283                  */
 284                 pci_write_bits8(pdev, 0xf4, 0x2, 0x2);
 285                 dev = pci_scan_single_device(pdev->bus, PCI_DEVFN(6, 0));
 286
 287                 if (dev == NULL)
 288                         return 1;
 289
 290                 pci_bus_add_device(dev);
 291         }
 292
 293         *ovrfl_pdev = dev;
 294
 295         if (pci_enable_device(dev)) {
 296                 i82875p_printk(KERN_ERR, "%s(): Failed to enable overflow "
 297                         "device\n", __func__);
 298                 return 1;
 299         }
 300
 301         if (pci_request_regions(dev, pci_name(dev))) {
 302 #ifdef CORRECT_BIOS
 303                 goto fail0;
 304 #endif
 305         }
 306
 307         /* cache is irrelevant for PCI bus reads/writes */
 308         window = ioremap_nocache(pci_resource_start(dev, 0),
 309                                  pci_resource_len(dev, 0));
 310
 311         if (window == NULL) {
 312                 i82875p_printk(KERN_ERR, "%s(): Failed to ioremap bar6\n",
 313                         __func__);
 314                 goto fail1;
 315         }
 316
 317         *ovrfl_window = window;
 318         return 0;
 319
 320 fail1:
 321         pci_release_regions(dev);
 322
 323 #ifdef CORRECT_BIOS
 324 fail0:
 325         pci_disable_device(dev);
 326 #endif
 327         /* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
 328         return 1;
 329 }
 330
 331 /* Return 1 if dual channel mode is active.  Else return 0. */
 332 static inline int dual_channel_active(u32 drc)
 333 {
 334         return (drc >> 21) & 0x1;
 335 }
 336
 337 static void i82875p_init_csrows(struct mem_ctl_info *mci,
 338                                 struct pci_dev *pdev,
 339                                 void __iomem * ovrfl_window, u32 drc)
 340 {
 341         struct csrow_info *csrow;
 342         unsigned long last_cumul_size;
 343         u8 value;
 344         u32 drc_ddim;           /* DRAM Data Integrity Mode 0=none,2=edac */
 345         u32 cumul_size;
 346         int index;
 347
 348         drc_ddim = (drc >> 18) & 0x1;
 349         last_cumul_size = 0;
 350
 351         /* The dram row boundary (DRB) reg values are boundary address
 352          * for each DRAM row with a granularity of 32 or 64MB (single/dual
 353          * channel operation).  DRB regs are cumulative; therefore DRB7 will
 354          * contain the total memory contained in all eight rows.
 355          */
 356
 357         for (index = 0; index < mci->nr_csrows; index++) {
 358                 csrow = &mci->csrows[index];
 359
 360                 value = readb(ovrfl_window + I82875P_DRB + index);
 361                 cumul_size = value << (I82875P_DRB_SHIFT - PAGE_SHIFT);
 362                 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
 363                         cumul_size);
 364                 if (cumul_size == last_cumul_size)
 365                         continue;       /* not populated */
 366
 367                 csrow->first_page = last_cumul_size;
 368                 csrow->last_page = cumul_size - 1;
 369                 csrow->nr_pages = cumul_size - last_cumul_size;
 370                 last_cumul_size = cumul_size;
 371                 csrow->grain = 1 << 12; /* I82875P_EAP has 4KiB reolution */
 372                 csrow->mtype = MEM_DDR;
 373                 csrow->dtype = DEV_UNKNOWN;
 374                 csrow->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE;
 375         }
 376 }
 377
 378 static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
 379 {
 380         int rc = -ENODEV;
 381         struct mem_ctl_info *mci;
 382         struct i82875p_pvt *pvt;
 383         struct pci_dev *ovrfl_pdev;
 384         void __iomem *ovrfl_window;
 385         u32 drc;
 386         u32 nr_chans;
 387         struct i82875p_error_info discard;
 388
 389         debugf0("%s()\n", __func__);
 390         ovrfl_pdev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);
 391
 392         if (i82875p_setup_overfl_dev(pdev, &ovrfl_pdev, &ovrfl_window))
 393                 return -ENODEV;
 394         drc = readl(ovrfl_window + I82875P_DRC);
 395         nr_chans = dual_channel_active(drc) + 1;
 396         mci = edac_mc_alloc(sizeof(*pvt), I82875P_NR_CSROWS(nr_chans),
 397                         nr_chans);
 398
 399         if (!mci) {
 400                 rc = -ENOMEM;
 401                 goto fail0;
 402         }
 403
 404         debugf3("%s(): init mci\n", __func__);
 405         mci->dev = &pdev->dev;
 406         mci->mtype_cap = MEM_FLAG_DDR;
 407         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
 408         mci->edac_cap = EDAC_FLAG_UNKNOWN;
 409         mci->mod_name = EDAC_MOD_STR;
 410         mci->mod_ver = I82875P_REVISION;
 411         mci->ctl_name = i82875p_devs[dev_idx].ctl_name;
 412         mci->dev_name = pci_name(pdev);
 413         mci->edac_check = i82875p_check;
 414         mci->ctl_page_to_phys = NULL;
 415         debugf3("%s(): init pvt\n", __func__);
 416         pvt = (struct i82875p_pvt *)mci->pvt_info;
 417         pvt->ovrfl_pdev = ovrfl_pdev;
 418         pvt->ovrfl_window = ovrfl_window;
 419         i82875p_init_csrows(mci, pdev, ovrfl_window, drc);
 420         i82875p_get_error_info(mci, &discard);  /* clear counters */
 421
 422         /* Here we assume that we will never see multiple instances of this
 423          * type of memory controller.  The ID is therefore hardcoded to 0.
 424          */
 425         if (edac_mc_add_mc(mci, 0)) {
 426                 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
 427                 goto fail1;
 428         }
 429
 430         /* allocating generic PCI control info */
 431         i82875p_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
 432         if (!i82875p_pci) {
 433                 printk(KERN_WARNING
 434                         "%s(): Unable to create PCI control\n",
 435                         __func__);
 436                 printk(KERN_WARNING
 437                         "%s(): PCI error report via EDAC not setup\n",
 438                         __func__);
 439         }
 440
 441         /* get this far and it's successful */
 442         debugf3("%s(): success\n", __func__);
 443         return 0;
 444
 445 fail1:
 446         edac_mc_free(mci);
 447
 448 fail0:
 449         iounmap(ovrfl_window);
 450         pci_release_regions(ovrfl_pdev);
 451
 452         pci_disable_device(ovrfl_pdev);
 453         /* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
 454         return rc;
 455 }
 456
 457 /* returns count (>= 0), or negative on error */
 458 static int __devinit i82875p_init_one(struct pci_dev *pdev,
 459                                 const struct pci_device_id *ent)
 460 {
 461         int rc;
 462
 463         debugf0("%s()\n", __func__);
 464         i82875p_printk(KERN_INFO, "i82875p init one\n");
 465
 466         if (pci_enable_device(pdev) < 0)
 467                 return -EIO;
 468
 469         rc = i82875p_probe1(pdev, ent->driver_data);
 470
 471         if (mci_pdev == NULL)
 472                 mci_pdev = pci_dev_get(pdev);
 473
 474         return rc;
 475 }
 476
 477 static void __devexit i82875p_remove_one(struct pci_dev *pdev)
 478 {
 479         struct mem_ctl_info *mci;
 480         struct i82875p_pvt *pvt = NULL;
 481
 482         debugf0("%s()\n", __func__);
 483
 484         if (i82875p_pci)
 485                 edac_pci_release_generic_ctl(i82875p_pci);
 486
 487         if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
 488                 return;
 489
 490         pvt = (struct i82875p_pvt *)mci->pvt_info;
 491
 492         if (pvt->ovrfl_window)
 493                 iounmap(pvt->ovrfl_window);
 494
 495         if (pvt->ovrfl_pdev) {
 496 #ifdef CORRECT_BIOS
 497                 pci_release_regions(pvt->ovrfl_pdev);
 498 #endif                          /*CORRECT_BIOS */
 499                 pci_disable_device(pvt->ovrfl_pdev);
 500                 pci_dev_put(pvt->ovrfl_pdev);
 501         }
 502
 503         edac_mc_free(mci);
 504 }
 505
 506 static const struct pci_device_id i82875p_pci_tbl[] __devinitdata = {
 507         {
 508          PCI_VEND_DEV(INTEL, 82875_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 509          I82875P},
 510         {
 511          0,
 512          }                      /* 0 terminated list. */
 513 };
 514
 515 MODULE_DEVICE_TABLE(pci, i82875p_pci_tbl);
 516
 517 static struct pci_driver i82875p_driver = {
 518         .name = EDAC_MOD_STR,
 519         .probe = i82875p_init_one,
 520         .remove = __devexit_p(i82875p_remove_one),
 521         .id_table = i82875p_pci_tbl,
 522 };
 523
 524 static int __init i82875p_init(void)
 525 {
 526         int pci_rc;
 527
 528         debugf3("%s()\n", __func__);
 529         pci_rc = pci_register_driver(&i82875p_driver);
 530
 531         if (pci_rc < 0)
 532                 goto fail0;
 533
 534         if (mci_pdev == NULL) {
 535                 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
 536                                         PCI_DEVICE_ID_INTEL_82875_0, NULL);
 537
 538                 if (!mci_pdev) {
 539                         debugf0("875p pci_get_device fail\n");
 540                         pci_rc = -ENODEV;
 541                         goto fail1;
 542                 }
 543
 544                 pci_rc = i82875p_init_one(mci_pdev, i82875p_pci_tbl);
 545
 546                 if (pci_rc < 0) {
 547                         debugf0("875p init fail\n");
 548                         pci_rc = -ENODEV;
 549                         goto fail1;
 550                 }
 551         }
 552
 553         return 0;
 554
 555 fail1:
 556         pci_unregister_driver(&i82875p_driver);
 557
 558 fail0:
 559         if (mci_pdev != NULL)
 560                 pci_dev_put(mci_pdev);
 561
 562         return pci_rc;
 563 }
 564
 565 static void __exit i82875p_exit(void)
 566 {
 567         debugf3("%s()\n", __func__);
 568
 569         pci_unregister_driver(&i82875p_driver);
 570
 571         if (!i82875p_registered) {
 572                 i82875p_remove_one(mci_pdev);
 573                 pci_dev_put(mci_pdev);
 574         }
 575 }
 576
 577 module_init(i82875p_init);
 578 module_exit(i82875p_exit);
 579
 580 MODULE_LICENSE("GPL");
 581 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
 582 MODULE_DESCRIPTION("MC support for Intel 82875 memory hub controllers");