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   1 /*
   2  * Intel D82875P Memory Controller kernel module
   3  * (C) 2003 Linux Networx (http://lnxi.com)
   4  * This file may be distributed under the terms of the
   5  * GNU General Public License.
   6  *
   7  * Written by Thayne Harbaugh
   8  * Contributors:
   9  *      Wang Zhenyu at intel.com
  10  *
  11  * $Id: edac_i82875p.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
  12  *
  13  * Note: E7210 appears same as D82875P - zhenyu.z.wang at intel.com
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/init.h>
  18 #include <linux/pci.h>
  19 #include <linux/pci_ids.h>
  20 #include <linux/slab.h>
  21 #include "edac_mc.h"
  22
  23 #define I82875P_REVISION        " Ver: 2.0.0 " __DATE__
  24
  25 #define i82875p_printk(level, fmt, arg...) \
  26         edac_printk(level, "i82875p", fmt, ##arg)
  27
  28 #define i82875p_mc_printk(mci, level, fmt, arg...) \
  29         edac_mc_chipset_printk(mci, level, "i82875p", fmt, ##arg)
  30
  31 #ifndef PCI_DEVICE_ID_INTEL_82875_0
  32 #define PCI_DEVICE_ID_INTEL_82875_0     0x2578
  33 #endif                          /* PCI_DEVICE_ID_INTEL_82875_0 */
  34
  35 #ifndef PCI_DEVICE_ID_INTEL_82875_6
  36 #define PCI_DEVICE_ID_INTEL_82875_6     0x257e
  37 #endif                          /* PCI_DEVICE_ID_INTEL_82875_6 */
  38
  39 /* four csrows in dual channel, eight in single channel */
  40 #define I82875P_NR_CSROWS(nr_chans) (8/(nr_chans))
  41
  42 /* Intel 82875p register addresses - device 0 function 0 - DRAM Controller */
  43 #define I82875P_EAP             0x58    /* Error Address Pointer (32b)
  44                                          *
  45                                          * 31:12 block address
  46                                          * 11:0  reserved
  47                                          */
  48
  49 #define I82875P_DERRSYN         0x5c    /* DRAM Error Syndrome (8b)
  50                                          *
  51                                          *  7:0  DRAM ECC Syndrome
  52                                          */
  53
  54 #define I82875P_DES             0x5d    /* DRAM Error Status (8b)
  55                                          *
  56                                          *  7:1  reserved
  57                                          *  0    Error channel 0/1
  58                                          */
  59
  60 #define I82875P_ERRSTS          0xc8    /* Error Status Register (16b)
  61                                          *
  62                                          * 15:10 reserved
  63                                          *  9    non-DRAM lock error (ndlock)
  64                                          *  8    Sftwr Generated SMI
  65                                          *  7    ECC UE
  66                                          *  6    reserved
  67                                          *  5    MCH detects unimplemented cycle
  68                                          *  4    AGP access outside GA
  69                                          *  3    Invalid AGP access
  70                                          *  2    Invalid GA translation table
  71                                          *  1    Unsupported AGP command
  72                                          *  0    ECC CE
  73                                          */
  74
  75 #define I82875P_ERRCMD          0xca    /* Error Command (16b)
  76                                          *
  77                                          * 15:10 reserved
  78                                          *  9    SERR on non-DRAM lock
  79                                          *  8    SERR on ECC UE
  80                                          *  7    SERR on ECC CE
  81                                          *  6    target abort on high exception
  82                                          *  5    detect unimplemented cyc
  83                                          *  4    AGP access outside of GA
  84                                          *  3    SERR on invalid AGP access
  85                                          *  2    invalid translation table
  86                                          *  1    SERR on unsupported AGP command
  87                                          *  0    reserved
  88                                          */
  89
  90 /* Intel 82875p register addresses - device 6 function 0 - DRAM Controller */
  91 #define I82875P_PCICMD6         0x04    /* PCI Command Register (16b)
  92                                          *
  93                                          * 15:10 reserved
  94                                          *  9    fast back-to-back - ro 0
  95                                          *  8    SERR enable - ro 0
  96                                          *  7    addr/data stepping - ro 0
  97                                          *  6    parity err enable - ro 0
  98                                          *  5    VGA palette snoop - ro 0
  99                                          *  4    mem wr & invalidate - ro 0
 100                                          *  3    special cycle - ro 0
 101                                          *  2    bus master - ro 0
 102                                          *  1    mem access dev6 - 0(dis),1(en)
 103                                          *  0    IO access dev3 - 0(dis),1(en)
 104                                          */
 105
 106 #define I82875P_BAR6            0x10    /* Mem Delays Base ADDR Reg (32b)
 107                                          *
 108                                          * 31:12 mem base addr [31:12]
 109                                          * 11:4  address mask - ro 0
 110                                          *  3    prefetchable - ro 0(non),1(pre)
 111                                          *  2:1  mem type - ro 0
 112                                          *  0    mem space - ro 0
 113                                          */
 114
 115 /* Intel 82875p MMIO register space - device 0 function 0 - MMR space */
 116
 117 #define I82875P_DRB_SHIFT 26    /* 64MiB grain */
 118 #define I82875P_DRB             0x00    /* DRAM Row Boundary (8b x 8)
 119                                          *
 120                                          *  7    reserved
 121                                          *  6:0  64MiB row boundary addr
 122                                          */
 123
 124 #define I82875P_DRA             0x10    /* DRAM Row Attribute (4b x 8)
 125                                          *
 126                                          *  7    reserved
 127                                          *  6:4  row attr row 1
 128                                          *  3    reserved
 129                                          *  2:0  row attr row 0
 130                                          *
 131                                          * 000 =  4KiB
 132                                          * 001 =  8KiB
 133                                          * 010 = 16KiB
 134                                          * 011 = 32KiB
 135                                          */
 136
 137 #define I82875P_DRC             0x68    /* DRAM Controller Mode (32b)
 138                                          *
 139                                          * 31:30 reserved
 140                                          * 29    init complete
 141                                          * 28:23 reserved
 142                                          * 22:21 nr chan 00=1,01=2
 143                                          * 20    reserved
 144                                          * 19:18 Data Integ Mode 00=none,01=ecc
 145                                          * 17:11 reserved
 146                                          * 10:8  refresh mode
 147                                          *  7    reserved
 148                                          *  6:4  mode select
 149                                          *  3:2  reserved
 150                                          *  1:0  DRAM type 01=DDR
 151                                          */
 152
 153 enum i82875p_chips {
 154         I82875P = 0,
 155 };
 156
 157 struct i82875p_pvt {
 158         struct pci_dev *ovrfl_pdev;
 159         void __iomem *ovrfl_window;
 160 };
 161
 162 struct i82875p_dev_info {
 163         const char *ctl_name;
 164 };
 165
 166 struct i82875p_error_info {
 167         u16 errsts;
 168         u32 eap;
 169         u8 des;
 170         u8 derrsyn;
 171         u16 errsts2;
 172 };
 173
 174 static const struct i82875p_dev_info i82875p_devs[] = {
 175         [I82875P] = {
 176                 .ctl_name = "i82875p"
 177         },
 178 };
 179
 180 static struct pci_dev *mci_pdev = NULL; /* init dev: in case that AGP code has
 181                                          * already registered driver
 182                                          */
 183
 184 static int i82875p_registered = 1;
 185
 186 static void i82875p_get_error_info(struct mem_ctl_info *mci,
 187                 struct i82875p_error_info *info)
 188 {
 189         struct pci_dev *pdev;
 190
 191         pdev = to_pci_dev(mci->dev);
 192
 193         /*
 194          * This is a mess because there is no atomic way to read all the
 195          * registers at once and the registers can transition from CE being
 196          * overwritten by UE.
 197          */
 198         pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts);
 199         pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
 200         pci_read_config_byte(pdev, I82875P_DES, &info->des);
 201         pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn);
 202         pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts2);
 203
 204         pci_write_bits16(pdev, I82875P_ERRSTS, 0x0081, 0x0081);
 205
 206         /*
 207          * If the error is the same then we can for both reads then
 208          * the first set of reads is valid.  If there is a change then
 209          * there is a CE no info and the second set of reads is valid
 210          * and should be UE info.
 211          */
 212         if (!(info->errsts2 & 0x0081))
 213                 return;
 214
 215         if ((info->errsts ^ info->errsts2) & 0x0081) {
 216                 pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
 217                 pci_read_config_byte(pdev, I82875P_DES, &info->des);
 218                 pci_read_config_byte(pdev, I82875P_DERRSYN,
 219                                 &info->derrsyn);
 220         }
 221 }
 222
 223 static int i82875p_process_error_info(struct mem_ctl_info *mci,
 224                 struct i82875p_error_info *info, int handle_errors)
 225 {
 226         int row, multi_chan;
 227
 228         multi_chan = mci->csrows[0].nr_channels - 1;
 229
 230         if (!(info->errsts2 & 0x0081))
 231                 return 0;
 232
 233         if (!handle_errors)
 234                 return 1;
 235
 236         if ((info->errsts ^ info->errsts2) & 0x0081) {
 237                 edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
 238                 info->errsts = info->errsts2;
 239         }
 240
 241         info->eap >>= PAGE_SHIFT;
 242         row = edac_mc_find_csrow_by_page(mci, info->eap);
 243
 244         if (info->errsts & 0x0080)
 245                 edac_mc_handle_ue(mci, info->eap, 0, row, "i82875p UE");
 246         else
 247                 edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row,
 248                                 multi_chan ? (info->des & 0x1) : 0,
 249                                 "i82875p CE");
 250
 251         return 1;
 252 }
 253
 254 static void i82875p_check(struct mem_ctl_info *mci)
 255 {
 256         struct i82875p_error_info info;
 257
 258         debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
 259         i82875p_get_error_info(mci, &info);
 260         i82875p_process_error_info(mci, &info, 1);
 261 }
 262
 263 #ifdef CONFIG_PROC_FS
 264 extern int pci_proc_attach_device(struct pci_dev *);
 265 #endif
 266
 267 /* Return 0 on success or 1 on failure. */
 268 static int i82875p_setup_overfl_dev(struct pci_dev *pdev,
 269                 struct pci_dev **ovrfl_pdev, void __iomem **ovrfl_window)
 270 {
 271         struct pci_dev *dev;
 272         void __iomem *window;
 273
 274         *ovrfl_pdev = NULL;
 275         *ovrfl_window = NULL;
 276         dev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);
 277
 278         if (dev == NULL) {
 279                 /* Intel tells BIOS developers to hide device 6 which
 280                  * configures the overflow device access containing
 281                  * the DRBs - this is where we expose device 6.
 282                  * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
 283                  */
 284                 pci_write_bits8(pdev, 0xf4, 0x2, 0x2);
 285                 dev = pci_scan_single_device(pdev->bus, PCI_DEVFN(6, 0));
 286
 287                 if (dev == NULL)
 288                         return 1;
 289         }
 290
 291         *ovrfl_pdev = dev;
 292
 293 #ifdef CONFIG_PROC_FS
 294         if ((dev->procent == NULL) && pci_proc_attach_device(dev)) {
 295                 i82875p_printk(KERN_ERR, "%s(): Failed to attach overflow "
 296                                "device\n", __func__);
 297                 return 1;
 298         }
 299 #endif  /* CONFIG_PROC_FS */
 300         if (pci_enable_device(dev)) {
 301                 i82875p_printk(KERN_ERR, "%s(): Failed to enable overflow "
 302                                "device\n", __func__);
 303                 return 1;
 304         }
 305
 306         if (pci_request_regions(dev, pci_name(dev))) {
 307 #ifdef CORRECT_BIOS
 308                 goto fail0;
 309 #endif
 310         }
 311
 312         /* cache is irrelevant for PCI bus reads/writes */
 313         window = ioremap_nocache(pci_resource_start(dev, 0),
 314                                  pci_resource_len(dev, 0));
 315
 316         if (window == NULL) {
 317                 i82875p_printk(KERN_ERR, "%s(): Failed to ioremap bar6\n",
 318                                __func__);
 319                 goto fail1;
 320         }
 321
 322         *ovrfl_window = window;
 323         return 0;
 324
 325 fail1:
 326         pci_release_regions(dev);
 327
 328 #ifdef CORRECT_BIOS
 329 fail0:
 330         pci_disable_device(dev);
 331 #endif
 332         /* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
 333         return 1;
 334 }
 335
 336
 337 /* Return 1 if dual channel mode is active.  Else return 0. */
 338 static inline int dual_channel_active(u32 drc)
 339 {
 340         return (drc >> 21) & 0x1;
 341 }
 342
 343
 344 static void i82875p_init_csrows(struct mem_ctl_info *mci,
 345                 struct pci_dev *pdev, void __iomem *ovrfl_window, u32 drc)
 346 {
 347         struct csrow_info *csrow;
 348         unsigned long last_cumul_size;
 349         u8 value;
 350         u32 drc_ddim;  /* DRAM Data Integrity Mode 0=none,2=edac */
 351         u32 cumul_size;
 352         int index;
 353
 354         drc_ddim = (drc >> 18) & 0x1;
 355         last_cumul_size = 0;
 356
 357         /* The dram row boundary (DRB) reg values are boundary address
 358          * for each DRAM row with a granularity of 32 or 64MB (single/dual
 359          * channel operation).  DRB regs are cumulative; therefore DRB7 will
 360          * contain the total memory contained in all eight rows.
 361          */
 362
 363         for (index = 0; index < mci->nr_csrows; index++) {
 364                 csrow = &mci->csrows[index];
 365
 366                 value = readb(ovrfl_window + I82875P_DRB + index);
 367                 cumul_size = value << (I82875P_DRB_SHIFT - PAGE_SHIFT);
 368                 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
 369                         cumul_size);
 370                 if (cumul_size == last_cumul_size)
 371                         continue;       /* not populated */
 372
 373                 csrow->first_page = last_cumul_size;
 374                 csrow->last_page = cumul_size - 1;
 375                 csrow->nr_pages = cumul_size - last_cumul_size;
 376                 last_cumul_size = cumul_size;
 377                 csrow->grain = 1 << 12; /* I82875P_EAP has 4KiB reolution */
 378                 csrow->mtype = MEM_DDR;
 379                 csrow->dtype = DEV_UNKNOWN;
 380                 csrow->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE;
 381         }
 382 }
 383
 384 static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
 385 {
 386         int rc = -ENODEV;
 387         struct mem_ctl_info *mci;
 388         struct i82875p_pvt *pvt;
 389         struct pci_dev *ovrfl_pdev;
 390         void __iomem *ovrfl_window;
 391         u32 drc;
 392         u32 nr_chans;
 393         struct i82875p_error_info discard;
 394
 395         debugf0("%s()\n", __func__);
 396         ovrfl_pdev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);
 397
 398         if (i82875p_setup_overfl_dev(pdev, &ovrfl_pdev, &ovrfl_window))
 399                 return -ENODEV;
 400         drc = readl(ovrfl_window + I82875P_DRC);
 401         nr_chans = dual_channel_active(drc) + 1;
 402         mci = edac_mc_alloc(sizeof(*pvt), I82875P_NR_CSROWS(nr_chans),
 403                                 nr_chans);
 404
 405         if (!mci) {
 406                 rc = -ENOMEM;
 407                 goto fail0;
 408         }
 409
 410         debugf3("%s(): init mci\n", __func__);
 411         mci->dev = &pdev->dev;
 412         mci->mtype_cap = MEM_FLAG_DDR;
 413         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
 414         mci->edac_cap = EDAC_FLAG_UNKNOWN;
 415         mci->mod_name = EDAC_MOD_STR;
 416         mci->mod_ver = I82875P_REVISION;
 417         mci->ctl_name = i82875p_devs[dev_idx].ctl_name;
 418         mci->edac_check = i82875p_check;
 419         mci->ctl_page_to_phys = NULL;
 420         debugf3("%s(): init pvt\n", __func__);
 421         pvt = (struct i82875p_pvt *) mci->pvt_info;
 422         pvt->ovrfl_pdev = ovrfl_pdev;
 423         pvt->ovrfl_window = ovrfl_window;
 424         i82875p_init_csrows(mci, pdev, ovrfl_window, drc);
 425         i82875p_get_error_info(mci, &discard);  /* clear counters */
 426
 427         /* Here we assume that we will never see multiple instances of this
 428          * type of memory controller.  The ID is therefore hardcoded to 0.
 429          */
 430         if (edac_mc_add_mc(mci,0)) {
 431                 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
 432                 goto fail1;
 433         }
 434
 435         /* get this far and it's successful */
 436         debugf3("%s(): success\n", __func__);
 437         return 0;
 438
 439 fail1:
 440         edac_mc_free(mci);
 441
 442 fail0:
 443         iounmap(ovrfl_window);
 444         pci_release_regions(ovrfl_pdev);
 445
 446         pci_disable_device(ovrfl_pdev);
 447         /* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
 448         return rc;
 449 }
 450
 451 /* returns count (>= 0), or negative on error */
 452 static int __devinit i82875p_init_one(struct pci_dev *pdev,
 453                 const struct pci_device_id *ent)
 454 {
 455         int rc;
 456
 457         debugf0("%s()\n", __func__);
 458         i82875p_printk(KERN_INFO, "i82875p init one\n");
 459
 460         if (pci_enable_device(pdev) < 0)
 461                 return -EIO;
 462
 463         rc = i82875p_probe1(pdev, ent->driver_data);
 464
 465         if (mci_pdev == NULL)
 466                 mci_pdev = pci_dev_get(pdev);
 467
 468         return rc;
 469 }
 470
 471 static void __devexit i82875p_remove_one(struct pci_dev *pdev)
 472 {
 473         struct mem_ctl_info *mci;
 474         struct i82875p_pvt *pvt = NULL;
 475
 476         debugf0("%s()\n", __func__);
 477
 478         if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
 479                 return;
 480
 481         pvt = (struct i82875p_pvt *) mci->pvt_info;
 482
 483         if (pvt->ovrfl_window)
 484                 iounmap(pvt->ovrfl_window);
 485
 486         if (pvt->ovrfl_pdev) {
 487 #ifdef CORRECT_BIOS
 488                 pci_release_regions(pvt->ovrfl_pdev);
 489 #endif                          /*CORRECT_BIOS */
 490                 pci_disable_device(pvt->ovrfl_pdev);
 491                 pci_dev_put(pvt->ovrfl_pdev);
 492         }
 493
 494         edac_mc_free(mci);
 495 }
 496
 497 static const struct pci_device_id i82875p_pci_tbl[] __devinitdata = {
 498         {
 499                 PCI_VEND_DEV(INTEL, 82875_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 500                 I82875P
 501         },
 502         {
 503                 0,
 504         }       /* 0 terminated list. */
 505 };
 506
 507 MODULE_DEVICE_TABLE(pci, i82875p_pci_tbl);
 508
 509 static struct pci_driver i82875p_driver = {
 510         .name = EDAC_MOD_STR,
 511         .probe = i82875p_init_one,
 512         .remove = __devexit_p(i82875p_remove_one),
 513         .id_table = i82875p_pci_tbl,
 514 };
 515
 516 static int __init i82875p_init(void)
 517 {
 518         int pci_rc;
 519
 520         debugf3("%s()\n", __func__);
 521         pci_rc = pci_register_driver(&i82875p_driver);
 522
 523         if (pci_rc < 0)
 524                 goto fail0;
 525
 526         if (mci_pdev == NULL) {
 527                 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
 528                                 PCI_DEVICE_ID_INTEL_82875_0, NULL);
 529
 530                 if (!mci_pdev) {
 531                         debugf0("875p pci_get_device fail\n");
 532                         pci_rc = -ENODEV;
 533                         goto fail1;
 534                 }
 535
 536                 pci_rc = i82875p_init_one(mci_pdev, i82875p_pci_tbl);
 537
 538                 if (pci_rc < 0) {
 539                         debugf0("875p init fail\n");
 540                         pci_rc = -ENODEV;
 541                         goto fail1;
 542                 }
 543         }
 544
 545         return 0;
 546
 547 fail1:
 548         pci_unregister_driver(&i82875p_driver);
 549
 550 fail0:
 551         if (mci_pdev != NULL)
 552                 pci_dev_put(mci_pdev);
 553
 554         return pci_rc;
 555 }
 556
 557 static void __exit i82875p_exit(void)
 558 {
 559         debugf3("%s()\n", __func__);
 560
 561         pci_unregister_driver(&i82875p_driver);
 562
 563         if (!i82875p_registered) {
 564                 i82875p_remove_one(mci_pdev);
 565                 pci_dev_put(mci_pdev);
 566         }
 567 }
 568
 569 module_init(i82875p_init);
 570 module_exit(i82875p_exit);
 571
 572 MODULE_LICENSE("GPL");
 573 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
 574 MODULE_DESCRIPTION("MC support for Intel 82875 memory hub controllers");