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   1 /*
   2  * Intel e752x Memory Controller kernel module
   3  * (C) 2004 Linux Networx (http://lnxi.com)
   4  * This file may be distributed under the terms of the
   5  * GNU General Public License.
   6  *
   7  * See "enum e752x_chips" below for supported chipsets
   8  *
   9  * Written by Tom Zimmerman
  10  *
  11  * Contributors:
  12  *      Thayne Harbaugh at realmsys.com (?)
  13  *      Wang Zhenyu at intel.com
  14  *      Dave Jiang at mvista.com
  15  *
  16  * $Id: edac_e752x.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
  17  *
  18  */
  19
  20
  21 #include <linux/config.h>
  22 #include <linux/module.h>
  23 #include <linux/init.h>
  24
  25 #include <linux/pci.h>
  26 #include <linux/pci_ids.h>
  27
  28 #include <linux/slab.h>
  29
  30 #include "edac_mc.h"
  31
  32
  33 #define e752x_printk(level, fmt, arg...) \
  34     edac_printk(level, "e752x", fmt, ##arg)
  35
  36
  37 #define e752x_mc_printk(mci, level, fmt, arg...) \
  38     edac_mc_chipset_printk(mci, level, "e752x", fmt, ##arg)
  39
  40
  41 #ifndef PCI_DEVICE_ID_INTEL_7520_0
  42 #define PCI_DEVICE_ID_INTEL_7520_0      0x3590
  43 #endif                          /* PCI_DEVICE_ID_INTEL_7520_0      */
  44
  45 #ifndef PCI_DEVICE_ID_INTEL_7520_1_ERR
  46 #define PCI_DEVICE_ID_INTEL_7520_1_ERR  0x3591
  47 #endif                          /* PCI_DEVICE_ID_INTEL_7520_1_ERR  */
  48
  49 #ifndef PCI_DEVICE_ID_INTEL_7525_0
  50 #define PCI_DEVICE_ID_INTEL_7525_0      0x359E
  51 #endif                          /* PCI_DEVICE_ID_INTEL_7525_0      */
  52
  53 #ifndef PCI_DEVICE_ID_INTEL_7525_1_ERR
  54 #define PCI_DEVICE_ID_INTEL_7525_1_ERR  0x3593
  55 #endif                          /* PCI_DEVICE_ID_INTEL_7525_1_ERR  */
  56
  57 #ifndef PCI_DEVICE_ID_INTEL_7320_0
  58 #define PCI_DEVICE_ID_INTEL_7320_0      0x3592
  59 #endif                          /* PCI_DEVICE_ID_INTEL_7320_0 */
  60
  61 #ifndef PCI_DEVICE_ID_INTEL_7320_1_ERR
  62 #define PCI_DEVICE_ID_INTEL_7320_1_ERR  0x3593
  63 #endif                          /* PCI_DEVICE_ID_INTEL_7320_1_ERR */
  64
  65 #define E752X_NR_CSROWS         8       /* number of csrows */
  66
  67
  68 /* E752X register addresses - device 0 function 0 */
  69 #define E752X_DRB               0x60    /* DRAM row boundary register (8b) */
  70 #define E752X_DRA               0x70    /* DRAM row attribute register (8b) */
  71                                         /*
  72                                          * 31:30   Device width row 7
  73                                          *      01=x8 10=x4 11=x8 DDR2
  74                                          * 27:26   Device width row 6
  75                                          * 23:22   Device width row 5
  76                                          * 19:20   Device width row 4
  77                                          * 15:14   Device width row 3
  78                                          * 11:10   Device width row 2
  79                                          *  7:6    Device width row 1
  80                                          *  3:2    Device width row 0
  81                                          */
  82 #define E752X_DRC               0x7C    /* DRAM controller mode reg (32b) */
  83                                         /* FIXME:IS THIS RIGHT? */
  84                                         /*
  85                                          * 22    Number channels 0=1,1=2
  86                                          * 19:18 DRB Granularity 32/64MB
  87                                          */
  88 #define E752X_DRM               0x80    /* Dimm mapping register */
  89 #define E752X_DDRCSR            0x9A    /* DDR control and status reg (16b) */
  90                                         /*
  91                                          * 14:12 1 single A, 2 single B, 3 dual
  92                                          */
  93 #define E752X_TOLM              0xC4    /* DRAM top of low memory reg (16b) */
  94 #define E752X_REMAPBASE         0xC6    /* DRAM remap base address reg (16b) */
  95 #define E752X_REMAPLIMIT        0xC8    /* DRAM remap limit address reg (16b) */
  96 #define E752X_REMAPOFFSET       0xCA    /* DRAM remap limit offset reg (16b) */
  97
  98 /* E752X register addresses - device 0 function 1 */
  99 #define E752X_FERR_GLOBAL       0x40    /* Global first error register (32b) */
 100 #define E752X_NERR_GLOBAL       0x44    /* Global next error register (32b) */
 101 #define E752X_HI_FERR           0x50    /* Hub interface first error reg (8b) */
 102 #define E752X_HI_NERR           0x52    /* Hub interface next error reg (8b) */
 103 #define E752X_HI_ERRMASK        0x54    /* Hub interface error mask reg (8b) */
 104 #define E752X_HI_SMICMD         0x5A    /* Hub interface SMI command reg (8b) */
 105 #define E752X_SYSBUS_FERR       0x60    /* System buss first error reg (16b) */
 106 #define E752X_SYSBUS_NERR       0x62    /* System buss next error reg (16b) */
 107 #define E752X_SYSBUS_ERRMASK    0x64    /* System buss error mask reg (16b) */
 108 #define E752X_SYSBUS_SMICMD     0x6A    /* System buss SMI command reg (16b) */
 109 #define E752X_BUF_FERR          0x70    /* Memory buffer first error reg (8b) */
 110 #define E752X_BUF_NERR          0x72    /* Memory buffer next error reg (8b) */
 111 #define E752X_BUF_ERRMASK       0x74    /* Memory buffer error mask reg (8b) */
 112 #define E752X_BUF_SMICMD        0x7A    /* Memory buffer SMI command reg (8b) */
 113 #define E752X_DRAM_FERR         0x80    /* DRAM first error register (16b) */
 114 #define E752X_DRAM_NERR         0x82    /* DRAM next error register (16b) */
 115 #define E752X_DRAM_ERRMASK      0x84    /* DRAM error mask register (8b) */
 116 #define E752X_DRAM_SMICMD       0x8A    /* DRAM SMI command register (8b) */
 117 #define E752X_DRAM_RETR_ADD     0xAC    /* DRAM Retry address register (32b) */
 118 #define E752X_DRAM_SEC1_ADD     0xA0    /* DRAM first correctable memory */
 119                                         /*     error address register (32b) */
 120                                         /*
 121                                          * 31    Reserved
 122                                          * 30:2  CE address (64 byte block 34:6)
 123                                          * 1     Reserved
 124                                          * 0     HiLoCS
 125                                          */
 126 #define E752X_DRAM_SEC2_ADD     0xC8    /* DRAM first correctable memory */
 127                                         /*     error address register (32b) */
 128                                         /*
 129                                          * 31    Reserved
 130                                          * 30:2  CE address (64 byte block 34:6)
 131                                          * 1     Reserved
 132                                          * 0     HiLoCS
 133                                          */
 134 #define E752X_DRAM_DED_ADD      0xA4    /* DRAM first uncorrectable memory */
 135                                         /*     error address register (32b) */
 136                                         /*
 137                                          * 31    Reserved
 138                                          * 30:2  CE address (64 byte block 34:6)
 139                                          * 1     Reserved
 140                                          * 0     HiLoCS
 141                                          */
 142 #define E752X_DRAM_SCRB_ADD     0xA8    /* DRAM first uncorrectable scrub memory */
 143                                         /*     error address register (32b) */
 144                                         /*
 145                                          * 31    Reserved
 146                                          * 30:2  CE address (64 byte block 34:6)
 147                                          * 1     Reserved
 148                                          * 0     HiLoCS
 149                                          */
 150 #define E752X_DRAM_SEC1_SYNDROME 0xC4   /* DRAM first correctable memory */
 151                                         /*     error syndrome register (16b) */
 152 #define E752X_DRAM_SEC2_SYNDROME 0xC6   /* DRAM second correctable memory */
 153                                         /*     error syndrome register (16b) */
 154 #define E752X_DEVPRES1          0xF4    /* Device Present 1 register (8b) */
 155
 156 /* ICH5R register addresses - device 30 function 0 */
 157 #define ICH5R_PCI_STAT          0x06    /* PCI status register (16b) */
 158 #define ICH5R_PCI_2ND_STAT      0x1E    /* PCI status secondary reg (16b) */
 159 #define ICH5R_PCI_BRIDGE_CTL    0x3E    /* PCI bridge control register (16b) */
 160
 161 enum e752x_chips {
 162         E7520 = 0,
 163         E7525 = 1,
 164         E7320 = 2
 165 };
 166
 167
 168 struct e752x_pvt {
 169         struct pci_dev *bridge_ck;
 170         struct pci_dev *dev_d0f0;
 171         struct pci_dev *dev_d0f1;
 172         u32 tolm;
 173         u32 remapbase;
 174         u32 remaplimit;
 175         int mc_symmetric;
 176         u8 map[8];
 177         int map_type;
 178         const struct e752x_dev_info *dev_info;
 179 };
 180
 181
 182 struct e752x_dev_info {
 183         u16 err_dev;
 184         const char *ctl_name;
 185 };
 186
 187 struct e752x_error_info {
 188         u32 ferr_global;
 189         u32 nerr_global;
 190         u8 hi_ferr;
 191         u8 hi_nerr;
 192         u16 sysbus_ferr;
 193         u16 sysbus_nerr;
 194         u8 buf_ferr;
 195         u8 buf_nerr;
 196         u16 dram_ferr;
 197         u16 dram_nerr;
 198         u32 dram_sec1_add;
 199         u32 dram_sec2_add;
 200         u16 dram_sec1_syndrome;
 201         u16 dram_sec2_syndrome;
 202         u32 dram_ded_add;
 203         u32 dram_scrb_add;
 204         u32 dram_retr_add;
 205 };
 206
 207 static const struct e752x_dev_info e752x_devs[] = {
 208         [E7520] = {
 209                    .err_dev = PCI_DEVICE_ID_INTEL_7520_1_ERR,
 210                    .ctl_name = "E7520"},
 211         [E7525] = {
 212                    .err_dev = PCI_DEVICE_ID_INTEL_7525_1_ERR,
 213                    .ctl_name = "E7525"},
 214         [E7320] = {
 215                    .err_dev = PCI_DEVICE_ID_INTEL_7320_1_ERR,
 216                    .ctl_name = "E7320"},
 217 };
 218
 219
 220 static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
 221                                       unsigned long page)
 222 {
 223         u32 remap;
 224         struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
 225
 226         debugf3("%s()\n", __func__);
 227
 228         if (page < pvt->tolm)
 229                 return page;
 230         if ((page >= 0x100000) && (page < pvt->remapbase))
 231                 return page;
 232         remap = (page - pvt->tolm) + pvt->remapbase;
 233         if (remap < pvt->remaplimit)
 234                 return remap;
 235         e752x_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
 236         return pvt->tolm - 1;
 237 }
 238
 239 static void do_process_ce(struct mem_ctl_info *mci, u16 error_one,
 240                        u32 sec1_add, u16 sec1_syndrome)
 241 {
 242         u32 page;
 243         int row;
 244         int channel;
 245         int i;
 246         struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
 247
 248         debugf3("%s()\n", __func__);
 249
 250         /* convert the addr to 4k page */
 251         page = sec1_add >> (PAGE_SHIFT - 4);
 252
 253         /* FIXME - check for -1 */
 254         if (pvt->mc_symmetric) {
 255                 /* chip select are bits 14 & 13 */
 256                 row = ((page >> 1) & 3);
 257                 e752x_printk(KERN_WARNING,
 258                              "Test row %d Table %d %d %d %d %d %d %d %d\n",
 259                              row, pvt->map[0], pvt->map[1], pvt->map[2],
 260                              pvt->map[3], pvt->map[4], pvt->map[5],
 261                              pvt->map[6], pvt->map[7]);
 262
 263                 /* test for channel remapping */
 264                 for (i = 0; i < 8; i++) {
 265                         if (pvt->map[i] == row)
 266                                 break;
 267                 }
 268                 e752x_printk(KERN_WARNING, "Test computed row %d\n", i);
 269                 if (i < 8)
 270                         row = i;
 271                 else
 272                         e752x_mc_printk(mci, KERN_WARNING,
 273                             "row %d not found in remap table\n", row);
 274         } else
 275                 row = edac_mc_find_csrow_by_page(mci, page);
 276         /* 0 = channel A, 1 = channel B */
 277         channel = !(error_one & 1);
 278
 279         if (!pvt->map_type)
 280                 row = 7 - row;
 281         edac_mc_handle_ce(mci, page, 0, sec1_syndrome, row, channel,
 282             "e752x CE");
 283 }
 284
 285
 286 static inline void process_ce(struct mem_ctl_info *mci, u16 error_one,
 287                 u32 sec1_add, u16 sec1_syndrome, int *error_found,
 288                 int handle_error)
 289 {
 290         *error_found = 1;
 291
 292         if (handle_error)
 293                 do_process_ce(mci, error_one, sec1_add, sec1_syndrome);
 294 }
 295
 296 static void do_process_ue(struct mem_ctl_info *mci, u16 error_one, u32 ded_add,
 297                 u32 scrb_add)
 298 {
 299         u32 error_2b, block_page;
 300         int row;
 301         struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
 302
 303         debugf3("%s()\n", __func__);
 304
 305         if (error_one & 0x0202) {
 306                 error_2b = ded_add;
 307                 /* convert to 4k address */
 308                 block_page = error_2b >> (PAGE_SHIFT - 4);
 309                 row = pvt->mc_symmetric ?
 310                     /* chip select are bits 14 & 13 */
 311                     ((block_page >> 1) & 3) :
 312                     edac_mc_find_csrow_by_page(mci, block_page);
 313                 edac_mc_handle_ue(mci, block_page, 0, row,
 314                                        "e752x UE from Read");
 315         }
 316         if (error_one & 0x0404) {
 317                 error_2b = scrb_add;
 318                 /* convert to 4k address */
 319                 block_page = error_2b >> (PAGE_SHIFT - 4);
 320                 row = pvt->mc_symmetric ?
 321                     /* chip select are bits 14 & 13 */
 322                     ((block_page >> 1) & 3) :
 323                     edac_mc_find_csrow_by_page(mci, block_page);
 324                 edac_mc_handle_ue(mci, block_page, 0, row,
 325                                        "e752x UE from Scruber");
 326         }
 327 }
 328
 329 static inline void process_ue(struct mem_ctl_info *mci, u16 error_one,
 330                 u32 ded_add, u32 scrb_add, int *error_found, int handle_error)
 331 {
 332         *error_found = 1;
 333
 334         if (handle_error)
 335                 do_process_ue(mci, error_one, ded_add, scrb_add);
 336 }
 337
 338 static inline void process_ue_no_info_wr(struct mem_ctl_info *mci,
 339                 int *error_found, int handle_error)
 340 {
 341         *error_found = 1;
 342
 343         if (!handle_error)
 344                 return;
 345
 346         debugf3("%s()\n", __func__);
 347         edac_mc_handle_ue_no_info(mci, "e752x UE log memory write");
 348 }
 349
 350 static void do_process_ded_retry(struct mem_ctl_info *mci, u16 error,
 351                 u32 retry_add)
 352 {
 353         u32 error_1b, page;
 354         int row;
 355         struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
 356
 357         error_1b = retry_add;
 358         page = error_1b >> (PAGE_SHIFT - 4);    /* convert the addr to 4k page */
 359         row = pvt->mc_symmetric ?
 360             ((page >> 1) & 3) : /* chip select are bits 14 & 13 */
 361             edac_mc_find_csrow_by_page(mci, page);
 362         e752x_mc_printk(mci, KERN_WARNING,
 363             "CE page 0x%lx, row %d : Memory read retry\n",
 364             (long unsigned int) page, row);
 365 }
 366
 367 static inline void process_ded_retry(struct mem_ctl_info *mci, u16 error,
 368                 u32 retry_add, int *error_found, int handle_error)
 369 {
 370         *error_found = 1;
 371
 372         if (handle_error)
 373                 do_process_ded_retry(mci, error, retry_add);
 374 }
 375
 376 static inline void process_threshold_ce(struct mem_ctl_info *mci, u16 error,
 377                 int *error_found, int handle_error)
 378 {
 379         *error_found = 1;
 380
 381         if (handle_error)
 382                 e752x_mc_printk(mci, KERN_WARNING, "Memory threshold CE\n");
 383 }
 384
 385 static char *global_message[11] = {
 386         "PCI Express C1", "PCI Express C", "PCI Express B1",
 387         "PCI Express B", "PCI Express A1", "PCI Express A",
 388         "DMA Controler", "HUB Interface", "System Bus",
 389         "DRAM Controler", "Internal Buffer"
 390 };
 391
 392 static char *fatal_message[2] = { "Non-Fatal ", "Fatal " };
 393
 394 static void do_global_error(int fatal, u32 errors)
 395 {
 396         int i;
 397
 398         for (i = 0; i < 11; i++) {
 399                 if (errors & (1 << i))
 400                         e752x_printk(KERN_WARNING, "%sError %s\n",
 401                                fatal_message[fatal], global_message[i]);
 402         }
 403 }
 404
 405 static inline void global_error(int fatal, u32 errors, int *error_found,
 406                 int handle_error)
 407 {
 408         *error_found = 1;
 409
 410         if (handle_error)
 411                 do_global_error(fatal, errors);
 412 }
 413
 414 static char *hub_message[7] = {
 415         "HI Address or Command Parity", "HI Illegal Access",
 416         "HI Internal Parity", "Out of Range Access",
 417         "HI Data Parity", "Enhanced Config Access",
 418         "Hub Interface Target Abort"
 419 };
 420
 421 static void do_hub_error(int fatal, u8 errors)
 422 {
 423         int i;
 424
 425         for (i = 0; i < 7; i++) {
 426                 if (errors & (1 << i))
 427                         e752x_printk(KERN_WARNING, "%sError %s\n",
 428                                fatal_message[fatal], hub_message[i]);
 429         }
 430 }
 431
 432 static inline void hub_error(int fatal, u8 errors, int *error_found,
 433                 int handle_error)
 434 {
 435         *error_found = 1;
 436
 437         if (handle_error)
 438                 do_hub_error(fatal, errors);
 439 }
 440
 441 static char *membuf_message[4] = {
 442         "Internal PMWB to DRAM parity",
 443         "Internal PMWB to System Bus Parity",
 444         "Internal System Bus or IO to PMWB Parity",
 445         "Internal DRAM to PMWB Parity"
 446 };
 447
 448 static void do_membuf_error(u8 errors)
 449 {
 450         int i;
 451
 452         for (i = 0; i < 4; i++) {
 453                 if (errors & (1 << i))
 454                         e752x_printk(KERN_WARNING, "Non-Fatal Error %s\n",
 455                                membuf_message[i]);
 456         }
 457 }
 458
 459 static inline void membuf_error(u8 errors, int *error_found, int handle_error)
 460 {
 461         *error_found = 1;
 462
 463         if (handle_error)
 464                 do_membuf_error(errors);
 465 }
 466
 467 #if 0
 468 char *sysbus_message[10] = {
 469         "Addr or Request Parity",
 470         "Data Strobe Glitch",
 471         "Addr Strobe Glitch",
 472         "Data Parity",
 473         "Addr Above TOM",
 474         "Non DRAM Lock Error",
 475         "MCERR", "BINIT",
 476         "Memory Parity",
 477         "IO Subsystem Parity"
 478 };
 479 #endif  /*  0  */
 480
 481 static void do_sysbus_error(int fatal, u32 errors)
 482 {
 483         int i;
 484
 485         for (i = 0; i < 10; i++) {
 486                 if (errors & (1 << i))
 487                         e752x_printk(KERN_WARNING, "%sError System Bus %s\n",
 488                                fatal_message[fatal], global_message[i]);
 489         }
 490 }
 491
 492 static inline void sysbus_error(int fatal, u32 errors, int *error_found,
 493                 int handle_error)
 494 {
 495         *error_found = 1;
 496
 497         if (handle_error)
 498                 do_sysbus_error(fatal, errors);
 499 }
 500
 501 static void e752x_check_hub_interface (struct e752x_error_info *info,
 502                 int *error_found, int handle_error)
 503 {
 504         u8 stat8;
 505
 506         //pci_read_config_byte(dev,E752X_HI_FERR,&stat8);
 507         stat8 = info->hi_ferr;
 508         if(stat8 & 0x7f) { /* Error, so process */
 509                 stat8 &= 0x7f;
 510                 if(stat8 & 0x2b)
 511                         hub_error(1, stat8 & 0x2b, error_found, handle_error);
 512                 if(stat8 & 0x54)
 513                         hub_error(0, stat8 & 0x54, error_found, handle_error);
 514         }
 515         //pci_read_config_byte(dev,E752X_HI_NERR,&stat8);
 516         stat8 = info->hi_nerr;
 517         if(stat8 & 0x7f) { /* Error, so process */
 518                 stat8 &= 0x7f;
 519                 if (stat8 & 0x2b)
 520                         hub_error(1, stat8 & 0x2b, error_found, handle_error);
 521                 if(stat8 & 0x54)
 522                         hub_error(0, stat8 & 0x54, error_found, handle_error);
 523         }
 524 }
 525
 526 static void e752x_check_sysbus (struct e752x_error_info *info, int *error_found,
 527                 int handle_error)
 528 {
 529         u32 stat32, error32;
 530
 531         //pci_read_config_dword(dev,E752X_SYSBUS_FERR,&stat32);
 532         stat32 = info->sysbus_ferr + (info->sysbus_nerr << 16);
 533
 534         if (stat32 == 0)
 535                 return;  /* no errors */
 536
 537         error32 = (stat32 >> 16) & 0x3ff;
 538         stat32 = stat32 & 0x3ff;
 539         if(stat32 & 0x083)
 540                 sysbus_error(1, stat32 & 0x083, error_found, handle_error);
 541         if(stat32 & 0x37c)
 542                 sysbus_error(0, stat32 & 0x37c, error_found, handle_error);
 543         if(error32 & 0x083)
 544                 sysbus_error(1, error32 & 0x083, error_found, handle_error);
 545         if(error32 & 0x37c)
 546                 sysbus_error(0, error32 & 0x37c, error_found, handle_error);
 547 }
 548
 549 static void e752x_check_membuf (struct e752x_error_info *info, int *error_found,
 550                 int handle_error)
 551 {
 552         u8 stat8;
 553
 554         stat8 = info->buf_ferr;
 555         if (stat8 & 0x0f) { /* Error, so process */
 556                 stat8 &= 0x0f;
 557                 membuf_error(stat8, error_found, handle_error);
 558         }
 559         stat8 = info->buf_nerr;
 560         if (stat8 & 0x0f) { /* Error, so process */
 561                 stat8 &= 0x0f;
 562                 membuf_error(stat8, error_found, handle_error);
 563         }
 564 }
 565
 566 static void e752x_check_dram (struct mem_ctl_info *mci,
 567                 struct e752x_error_info *info, int *error_found, int handle_error)
 568 {
 569         u16 error_one, error_next;
 570
 571         error_one = info->dram_ferr;
 572         error_next = info->dram_nerr;
 573
 574         /* decode and report errors */
 575         if(error_one & 0x0101)  /* check first error correctable */
 576                 process_ce(mci, error_one, info->dram_sec1_add,
 577                            info->dram_sec1_syndrome, error_found,
 578                            handle_error);
 579
 580         if(error_next & 0x0101)  /* check next error correctable */
 581                 process_ce(mci, error_next, info->dram_sec2_add,
 582                            info->dram_sec2_syndrome, error_found,
 583                            handle_error);
 584
 585         if(error_one & 0x4040)
 586                 process_ue_no_info_wr(mci, error_found, handle_error);
 587
 588         if(error_next & 0x4040)
 589                 process_ue_no_info_wr(mci, error_found, handle_error);
 590
 591         if(error_one & 0x2020)
 592                 process_ded_retry(mci, error_one, info->dram_retr_add,
 593                                   error_found, handle_error);
 594
 595         if(error_next & 0x2020)
 596                 process_ded_retry(mci, error_next, info->dram_retr_add,
 597                                   error_found, handle_error);
 598
 599         if(error_one & 0x0808)
 600                 process_threshold_ce(mci, error_one, error_found,
 601                                      handle_error);
 602
 603         if(error_next & 0x0808)
 604                 process_threshold_ce(mci, error_next, error_found,
 605                                      handle_error);
 606
 607         if(error_one & 0x0606)
 608                 process_ue(mci, error_one, info->dram_ded_add,
 609                            info->dram_scrb_add, error_found, handle_error);
 610
 611         if(error_next & 0x0606)
 612                 process_ue(mci, error_next, info->dram_ded_add,
 613                            info->dram_scrb_add, error_found, handle_error);
 614 }
 615
 616 static void e752x_get_error_info (struct mem_ctl_info *mci,
 617                                   struct e752x_error_info *info)
 618 {
 619         struct pci_dev *dev;
 620         struct e752x_pvt *pvt;
 621
 622         memset(info, 0, sizeof(*info));
 623         pvt = (struct e752x_pvt *) mci->pvt_info;
 624         dev = pvt->dev_d0f1;
 625
 626         pci_read_config_dword(dev, E752X_FERR_GLOBAL, &info->ferr_global);
 627
 628         if (info->ferr_global) {
 629                 pci_read_config_byte(dev, E752X_HI_FERR, &info->hi_ferr);
 630                 pci_read_config_word(dev, E752X_SYSBUS_FERR,
 631                                 &info->sysbus_ferr);
 632                 pci_read_config_byte(dev, E752X_BUF_FERR, &info->buf_ferr);
 633                 pci_read_config_word(dev, E752X_DRAM_FERR,
 634                                 &info->dram_ferr);
 635                 pci_read_config_dword(dev, E752X_DRAM_SEC1_ADD,
 636                                 &info->dram_sec1_add);
 637                 pci_read_config_word(dev, E752X_DRAM_SEC1_SYNDROME,
 638                                 &info->dram_sec1_syndrome);
 639                 pci_read_config_dword(dev, E752X_DRAM_DED_ADD,
 640                                 &info->dram_ded_add);
 641                 pci_read_config_dword(dev, E752X_DRAM_SCRB_ADD,
 642                                 &info->dram_scrb_add);
 643                 pci_read_config_dword(dev, E752X_DRAM_RETR_ADD,
 644                                 &info->dram_retr_add);
 645
 646                 if (info->hi_ferr & 0x7f)
 647                         pci_write_config_byte(dev, E752X_HI_FERR,
 648                                         info->hi_ferr);
 649
 650                 if (info->sysbus_ferr)
 651                         pci_write_config_word(dev, E752X_SYSBUS_FERR,
 652                                         info->sysbus_ferr);
 653
 654                 if (info->buf_ferr & 0x0f)
 655                         pci_write_config_byte(dev, E752X_BUF_FERR,
 656                                         info->buf_ferr);
 657
 658                 if (info->dram_ferr)
 659                         pci_write_bits16(pvt->bridge_ck, E752X_DRAM_FERR,
 660                                         info->dram_ferr, info->dram_ferr);
 661
 662                 pci_write_config_dword(dev, E752X_FERR_GLOBAL,
 663                                 info->ferr_global);
 664         }
 665
 666         pci_read_config_dword(dev, E752X_NERR_GLOBAL, &info->nerr_global);
 667
 668         if (info->nerr_global) {
 669                 pci_read_config_byte(dev, E752X_HI_NERR, &info->hi_nerr);
 670                 pci_read_config_word(dev, E752X_SYSBUS_NERR,
 671                                 &info->sysbus_nerr);
 672                 pci_read_config_byte(dev, E752X_BUF_NERR, &info->buf_nerr);
 673                 pci_read_config_word(dev, E752X_DRAM_NERR,
 674                                 &info->dram_nerr);
 675                 pci_read_config_dword(dev, E752X_DRAM_SEC2_ADD,
 676                                 &info->dram_sec2_add);
 677                 pci_read_config_word(dev, E752X_DRAM_SEC2_SYNDROME,
 678                                 &info->dram_sec2_syndrome);
 679
 680                 if (info->hi_nerr & 0x7f)
 681                         pci_write_config_byte(dev, E752X_HI_NERR,
 682                                         info->hi_nerr);
 683
 684                 if (info->sysbus_nerr)
 685                         pci_write_config_word(dev, E752X_SYSBUS_NERR,
 686                                         info->sysbus_nerr);
 687
 688                 if (info->buf_nerr & 0x0f)
 689                         pci_write_config_byte(dev, E752X_BUF_NERR,
 690                                         info->buf_nerr);
 691
 692                 if (info->dram_nerr)
 693                         pci_write_bits16(pvt->bridge_ck, E752X_DRAM_NERR,
 694                                         info->dram_nerr, info->dram_nerr);
 695
 696                 pci_write_config_dword(dev, E752X_NERR_GLOBAL,
 697                                 info->nerr_global);
 698         }
 699 }
 700
 701 static int e752x_process_error_info (struct mem_ctl_info *mci,
 702                 struct e752x_error_info *info, int handle_errors)
 703 {
 704         u32 error32, stat32;
 705         int error_found;
 706
 707         error_found = 0;
 708         error32 = (info->ferr_global >> 18) & 0x3ff;
 709         stat32 = (info->ferr_global >> 4) & 0x7ff;
 710
 711         if (error32)
 712                 global_error(1, error32, &error_found, handle_errors);
 713
 714         if (stat32)
 715                 global_error(0, stat32, &error_found, handle_errors);
 716
 717         error32 = (info->nerr_global >> 18) & 0x3ff;
 718         stat32 = (info->nerr_global >> 4) & 0x7ff;
 719
 720         if (error32)
 721                 global_error(1, error32, &error_found, handle_errors);
 722
 723         if (stat32)
 724                 global_error(0, stat32, &error_found, handle_errors);
 725
 726         e752x_check_hub_interface(info, &error_found, handle_errors);
 727         e752x_check_sysbus(info, &error_found, handle_errors);
 728         e752x_check_membuf(info, &error_found, handle_errors);
 729         e752x_check_dram(mci, info, &error_found, handle_errors);
 730         return error_found;
 731 }
 732
 733 static void e752x_check(struct mem_ctl_info *mci)
 734 {
 735         struct e752x_error_info info;
 736         debugf3("%s()\n", __func__);
 737         e752x_get_error_info(mci, &info);
 738         e752x_process_error_info(mci, &info, 1);
 739 }
 740
 741 static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
 742 {
 743         int rc = -ENODEV;
 744         int index;
 745         u16 pci_data, stat;
 746         u32 stat32;
 747         u16 stat16;
 748         u8 stat8;
 749         struct mem_ctl_info *mci = NULL;
 750         struct e752x_pvt *pvt = NULL;
 751         u16 ddrcsr;
 752         u32 drc;
 753         int drc_chan;           /* Number of channels 0=1chan,1=2chan */
 754         int drc_drbg;           /* DRB granularity 0=64mb,1=128mb */
 755         int drc_ddim;           /* DRAM Data Integrity Mode 0=none,2=edac */
 756         u32 dra;
 757         unsigned long last_cumul_size;
 758         struct pci_dev *pres_dev;
 759         struct pci_dev *dev = NULL;
 760
 761         debugf0("%s(): mci\n", __func__);
 762         debugf0("Starting Probe1\n");
 763
 764         /* enable device 0 function 1 */
 765         pci_read_config_byte(pdev, E752X_DEVPRES1, &stat8);
 766         stat8 |= (1 << 5);
 767         pci_write_config_byte(pdev, E752X_DEVPRES1, stat8);
 768
 769         /* need to find out the number of channels */
 770         pci_read_config_dword(pdev, E752X_DRC, &drc);
 771         pci_read_config_word(pdev, E752X_DDRCSR, &ddrcsr);
 772         /* FIXME: should check >>12 or 0xf, true for all? */
 773         /* Dual channel = 1, Single channel = 0 */
 774         drc_chan = (((ddrcsr >> 12) & 3) == 3);
 775         drc_drbg = drc_chan + 1;        /* 128 in dual mode, 64 in single */
 776         drc_ddim = (drc >> 20) & 0x3;
 777
 778         mci = edac_mc_alloc(sizeof(*pvt), E752X_NR_CSROWS, drc_chan + 1);
 779
 780         if (mci == NULL) {
 781                 rc = -ENOMEM;
 782                 goto fail;
 783         }
 784
 785         debugf3("%s(): init mci\n", __func__);
 786
 787         mci->mtype_cap = MEM_FLAG_RDDR;
 788         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED |
 789             EDAC_FLAG_S4ECD4ED;
 790         /* FIXME - what if different memory types are in different csrows? */
 791         mci->mod_name = EDAC_MOD_STR;
 792         mci->mod_ver = "$Revision: 1.5.2.11 $";
 793         mci->pdev = pdev;
 794
 795         debugf3("%s(): init pvt\n", __func__);
 796         pvt = (struct e752x_pvt *) mci->pvt_info;
 797         pvt->dev_info = &e752x_devs[dev_idx];
 798         pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
 799                                          pvt->dev_info->err_dev,
 800                                          pvt->bridge_ck);
 801         if (pvt->bridge_ck == NULL)
 802                 pvt->bridge_ck = pci_scan_single_device(pdev->bus,
 803                                                         PCI_DEVFN(0, 1));
 804         if (pvt->bridge_ck == NULL) {
 805                 e752x_printk(KERN_ERR, "error reporting device not found:"
 806                        "vendor %x device 0x%x (broken BIOS?)\n",
 807                        PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].err_dev);
 808                 goto fail;
 809         }
 810         pvt->mc_symmetric = ((ddrcsr & 0x10) != 0);
 811
 812         debugf3("%s(): more mci init\n", __func__);
 813         mci->ctl_name = pvt->dev_info->ctl_name;
 814         mci->edac_check = e752x_check;
 815         mci->ctl_page_to_phys = ctl_page_to_phys;
 816
 817         /* find out the device types */
 818         pci_read_config_dword(pdev, E752X_DRA, &dra);
 819
 820         /*
 821          * The dram row boundary (DRB) reg values are boundary address for
 822          * each DRAM row with a granularity of 64 or 128MB (single/dual
 823          * channel operation).  DRB regs are cumulative; therefore DRB7 will
 824          * contain the total memory contained in all eight rows.
 825          */
 826         for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
 827                 u8 value;
 828                 u32 cumul_size;
 829                 /* mem_dev 0=x8, 1=x4 */
 830                 int mem_dev = (dra >> (index * 4 + 2)) & 0x3;
 831                 struct csrow_info *csrow = &mci->csrows[index];
 832
 833                 mem_dev = (mem_dev == 2);
 834                 pci_read_config_byte(mci->pdev, E752X_DRB + index, &value);
 835                 /* convert a 128 or 64 MiB DRB to a page size. */
 836                 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
 837                 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
 838                         cumul_size);
 839                 if (cumul_size == last_cumul_size)
 840                         continue;       /* not populated */
 841
 842                 csrow->first_page = last_cumul_size;
 843                 csrow->last_page = cumul_size - 1;
 844                 csrow->nr_pages = cumul_size - last_cumul_size;
 845                 last_cumul_size = cumul_size;
 846                 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */
 847                 csrow->mtype = MEM_RDDR;        /* only one type supported */
 848                 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
 849
 850                 /*
 851                  * if single channel or x8 devices then SECDED
 852                  * if dual channel and x4 then S4ECD4ED
 853                  */
 854                 if (drc_ddim) {
 855                         if (drc_chan && mem_dev) {
 856                                 csrow->edac_mode = EDAC_S4ECD4ED;
 857                                 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
 858                         } else {
 859                                 csrow->edac_mode = EDAC_SECDED;
 860                                 mci->edac_cap |= EDAC_FLAG_SECDED;
 861                         }
 862                 } else
 863                         csrow->edac_mode = EDAC_NONE;
 864         }
 865
 866         /* Fill in the memory map table */
 867         {
 868                 u8 value;
 869                 u8 last = 0;
 870                 u8 row = 0;
 871                 for (index = 0; index < 8; index += 2) {
 872
 873                         pci_read_config_byte(mci->pdev, E752X_DRB + index,
 874                                              &value);
 875                         /* test if there is a dimm in this slot */
 876                         if (value == last) {
 877                                 /* no dimm in the slot, so flag it as empty */
 878                                 pvt->map[index] = 0xff;
 879                                 pvt->map[index + 1] = 0xff;
 880                         } else {        /* there is a dimm in the slot */
 881                                 pvt->map[index] = row;
 882                                 row++;
 883                                 last = value;
 884                                 /* test the next value to see if the dimm is
 885                                    double sided */
 886                                 pci_read_config_byte(mci->pdev,
 887                                                      E752X_DRB + index + 1,
 888                                                      &value);
 889                                 pvt->map[index + 1] = (value == last) ?
 890                                     0xff :      /* the dimm is single sided,
 891                                                    so flag as empty */
 892                                     row;        /* this is a double sided dimm
 893                                                    to save the next row # */
 894                                 row++;
 895                                 last = value;
 896                         }
 897                 }
 898         }
 899
 900         /* set the map type.  1 = normal, 0 = reversed */
 901         pci_read_config_byte(mci->pdev, E752X_DRM, &stat8);
 902         pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f));
 903
 904         mci->edac_cap |= EDAC_FLAG_NONE;
 905
 906         debugf3("%s(): tolm, remapbase, remaplimit\n", __func__);
 907         /* load the top of low memory, remap base, and remap limit vars */
 908         pci_read_config_word(mci->pdev, E752X_TOLM, &pci_data);
 909         pvt->tolm = ((u32) pci_data) << 4;
 910         pci_read_config_word(mci->pdev, E752X_REMAPBASE, &pci_data);
 911         pvt->remapbase = ((u32) pci_data) << 14;
 912         pci_read_config_word(mci->pdev, E752X_REMAPLIMIT, &pci_data);
 913         pvt->remaplimit = ((u32) pci_data) << 14;
 914         e752x_printk(KERN_INFO,
 915                      "tolm = %x, remapbase = %x, remaplimit = %x\n",
 916                      pvt->tolm, pvt->remapbase, pvt->remaplimit);
 917
 918         if (edac_mc_add_mc(mci)) {
 919                 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
 920                 goto fail;
 921         }
 922
 923         /* Walk through the PCI table and clear errors */
 924         switch (dev_idx) {
 925         case E7520:
 926                 dev = pci_get_device(PCI_VENDOR_ID_INTEL,
 927                                       PCI_DEVICE_ID_INTEL_7520_0, NULL);
 928                 break;
 929         case E7525:
 930                 dev = pci_get_device(PCI_VENDOR_ID_INTEL,
 931                                       PCI_DEVICE_ID_INTEL_7525_0, NULL);
 932                 break;
 933         case E7320:
 934                 dev = pci_get_device(PCI_VENDOR_ID_INTEL,
 935                                       PCI_DEVICE_ID_INTEL_7320_0, NULL);
 936                 break;
 937         }
 938
 939
 940         pvt->dev_d0f0 = dev;
 941         for (pres_dev = dev;
 942              ((struct pci_dev *) pres_dev->global_list.next != dev);
 943              pres_dev = (struct pci_dev *) pres_dev->global_list.next) {
 944                 pci_read_config_dword(pres_dev, PCI_COMMAND, &stat32);
 945                 stat = (u16) (stat32 >> 16);
 946                 /* clear any error bits */
 947                 if (stat32 & ((1 << 6) + (1 << 8)))
 948                         pci_write_config_word(pres_dev, PCI_STATUS, stat);
 949         }
 950         /* find the error reporting device and clear errors */
 951         dev = pvt->dev_d0f1 = pci_dev_get(pvt->bridge_ck);
 952         /* Turn off error disable & SMI in case the BIOS turned it on */
 953         pci_write_config_byte(dev, E752X_HI_ERRMASK, 0x00);
 954         pci_write_config_byte(dev, E752X_HI_SMICMD, 0x00);
 955         pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x00);
 956         pci_write_config_word(dev, E752X_SYSBUS_SMICMD, 0x00);
 957         pci_write_config_byte(dev, E752X_BUF_ERRMASK, 0x00);
 958         pci_write_config_byte(dev, E752X_BUF_SMICMD, 0x00);
 959         pci_write_config_byte(dev, E752X_DRAM_ERRMASK, 0x00);
 960         pci_write_config_byte(dev, E752X_DRAM_SMICMD, 0x00);
 961         /* clear other MCH errors */
 962         pci_read_config_dword(dev, E752X_FERR_GLOBAL, &stat32);
 963         pci_write_config_dword(dev, E752X_FERR_GLOBAL, stat32);
 964         pci_read_config_dword(dev, E752X_NERR_GLOBAL, &stat32);
 965         pci_write_config_dword(dev, E752X_NERR_GLOBAL, stat32);
 966         pci_read_config_byte(dev, E752X_HI_FERR, &stat8);
 967         pci_write_config_byte(dev, E752X_HI_FERR, stat8);
 968         pci_read_config_byte(dev, E752X_HI_NERR, &stat8);
 969         pci_write_config_byte(dev, E752X_HI_NERR, stat8);
 970         pci_read_config_dword(dev, E752X_SYSBUS_FERR, &stat32);
 971         pci_write_config_dword(dev, E752X_SYSBUS_FERR, stat32);
 972         pci_read_config_byte(dev, E752X_BUF_FERR, &stat8);
 973         pci_write_config_byte(dev, E752X_BUF_FERR, stat8);
 974         pci_read_config_byte(dev, E752X_BUF_NERR, &stat8);
 975         pci_write_config_byte(dev, E752X_BUF_NERR, stat8);
 976         pci_read_config_word(dev, E752X_DRAM_FERR, &stat16);
 977         pci_write_config_word(dev, E752X_DRAM_FERR, stat16);
 978         pci_read_config_word(dev, E752X_DRAM_NERR, &stat16);
 979         pci_write_config_word(dev, E752X_DRAM_NERR, stat16);
 980
 981         /* get this far and it's successful */
 982         debugf3("%s(): success\n", __func__);
 983         return 0;
 984
 985 fail:
 986         if (mci) {
 987                 if (pvt->dev_d0f0)
 988                         pci_dev_put(pvt->dev_d0f0);
 989                 if (pvt->dev_d0f1)
 990                         pci_dev_put(pvt->dev_d0f1);
 991                 if (pvt->bridge_ck)
 992                         pci_dev_put(pvt->bridge_ck);
 993                 edac_mc_free(mci);
 994         }
 995         return rc;
 996 }
 997
 998 /* returns count (>= 0), or negative on error */
 999 static int __devinit e752x_init_one(struct pci_dev *pdev,
1000                                     const struct pci_device_id *ent)
1001 {
1002         debugf0("%s()\n", __func__);
1003
1004         /* wake up and enable device */
1005         if(pci_enable_device(pdev) < 0)
1006                 return -EIO;
1007         return e752x_probe1(pdev, ent->driver_data);
1008 }
1009
1010
1011 static void __devexit e752x_remove_one(struct pci_dev *pdev)
1012 {
1013         struct mem_ctl_info *mci;
1014         struct e752x_pvt *pvt;
1015
1016         debugf0("%s()\n", __func__);
1017
1018         if ((mci = edac_mc_find_mci_by_pdev(pdev)) == NULL)
1019                 return;
1020
1021         if (edac_mc_del_mc(mci))
1022                 return;
1023
1024         pvt = (struct e752x_pvt *) mci->pvt_info;
1025         pci_dev_put(pvt->dev_d0f0);
1026         pci_dev_put(pvt->dev_d0f1);
1027         pci_dev_put(pvt->bridge_ck);
1028         edac_mc_free(mci);
1029 }
1030
1031
1032 static const struct pci_device_id e752x_pci_tbl[] __devinitdata = {
1033         {PCI_VEND_DEV(INTEL, 7520_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1034          E7520},
1035         {PCI_VEND_DEV(INTEL, 7525_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1036          E7525},
1037         {PCI_VEND_DEV(INTEL, 7320_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1038          E7320},
1039         {0,}                    /* 0 terminated list. */
1040 };
1041
1042 MODULE_DEVICE_TABLE(pci, e752x_pci_tbl);
1043
1044
1045 static struct pci_driver e752x_driver = {
1046         .name = EDAC_MOD_STR,
1047         .probe = e752x_init_one,
1048         .remove = __devexit_p(e752x_remove_one),
1049         .id_table = e752x_pci_tbl,
1050 };
1051
1052
1053 static int __init e752x_init(void)
1054 {
1055         int pci_rc;
1056
1057         debugf3("%s()\n", __func__);
1058         pci_rc = pci_register_driver(&e752x_driver);
1059         return (pci_rc < 0) ? pci_rc : 0;
1060 }
1061
1062
1063 static void __exit e752x_exit(void)
1064 {
1065         debugf3("%s()\n", __func__);
1066         pci_unregister_driver(&e752x_driver);
1067 }
1068
1069
1070 module_init(e752x_init);
1071 module_exit(e752x_exit);
1072
1073 MODULE_LICENSE("GPL");
1074 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Tom Zimmerman\n");
1075 MODULE_DESCRIPTION("MC support for Intel e752x memory controllers");