SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/dma/mv_xor.c

   1 /*
   2  * offload engine driver for the Marvell XOR engine
   3  * Copyright (C) 2007, 2008, Marvell International Ltd.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/init.h>
  20 #include <linux/module.h>
  21 #include <linux/async_tx.h>
  22 #include <linux/delay.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/memory.h>
  28 #include <plat/mv_xor.h>
  29 #include "mv_xor.h"
  30
  31 static void mv_xor_issue_pending(struct dma_chan *chan);
  32
  33 #define to_mv_xor_chan(chan)            \
  34         container_of(chan, struct mv_xor_chan, common)
  35
  36 #define to_mv_xor_device(dev)           \
  37         container_of(dev, struct mv_xor_device, common)
  38
  39 #define to_mv_xor_slot(tx)              \
  40         container_of(tx, struct mv_xor_desc_slot, async_tx)
  41
  42 static void mv_desc_init(struct mv_xor_desc_slot *desc, unsigned long flags)
  43 {
  44         struct mv_xor_desc *hw_desc = desc->hw_desc;
  45
  46         hw_desc->status = (1 << 31);
  47         hw_desc->phy_next_desc = 0;
  48         hw_desc->desc_command = (1 << 31);
  49 }
  50
  51 static u32 mv_desc_get_dest_addr(struct mv_xor_desc_slot *desc)
  52 {
  53         struct mv_xor_desc *hw_desc = desc->hw_desc;
  54         return hw_desc->phy_dest_addr;
  55 }
  56
  57 static u32 mv_desc_get_src_addr(struct mv_xor_desc_slot *desc,
  58                                 int src_idx)
  59 {
  60         struct mv_xor_desc *hw_desc = desc->hw_desc;
  61         return hw_desc->phy_src_addr[src_idx];
  62 }
  63
  64
  65 static void mv_desc_set_byte_count(struct mv_xor_desc_slot *desc,
  66                                    u32 byte_count)
  67 {
  68         struct mv_xor_desc *hw_desc = desc->hw_desc;
  69         hw_desc->byte_count = byte_count;
  70 }
  71
  72 static void mv_desc_set_next_desc(struct mv_xor_desc_slot *desc,
  73                                   u32 next_desc_addr)
  74 {
  75         struct mv_xor_desc *hw_desc = desc->hw_desc;
  76         BUG_ON(hw_desc->phy_next_desc);
  77         hw_desc->phy_next_desc = next_desc_addr;
  78 }
  79
  80 static void mv_desc_clear_next_desc(struct mv_xor_desc_slot *desc)
  81 {
  82         struct mv_xor_desc *hw_desc = desc->hw_desc;
  83         hw_desc->phy_next_desc = 0;
  84 }
  85
  86 static void mv_desc_set_block_fill_val(struct mv_xor_desc_slot *desc, u32 val)
  87 {
  88         desc->value = val;
  89 }
  90
  91 static void mv_desc_set_dest_addr(struct mv_xor_desc_slot *desc,
  92                                   dma_addr_t addr)
  93 {
  94         struct mv_xor_desc *hw_desc = desc->hw_desc;
  95         hw_desc->phy_dest_addr = addr;
  96 }
  97
  98 static int mv_chan_memset_slot_count(size_t len)
  99 {
 100         return 1;
 101 }
 102
 103 #define mv_chan_memcpy_slot_count(c) mv_chan_memset_slot_count(c)
 104
 105 static void mv_desc_set_src_addr(struct mv_xor_desc_slot *desc,
 106                                  int index, dma_addr_t addr)
 107 {
 108         struct mv_xor_desc *hw_desc = desc->hw_desc;
 109         hw_desc->phy_src_addr[index] = addr;
 110         if (desc->type == DMA_XOR)
 111                 hw_desc->desc_command |= (1 << index);
 112 }
 113
 114 static u32 mv_chan_get_current_desc(struct mv_xor_chan *chan)
 115 {
 116         return __raw_readl(XOR_CURR_DESC(chan));
 117 }
 118
 119 static void mv_chan_set_next_descriptor(struct mv_xor_chan *chan,
 120                                         u32 next_desc_addr)
 121 {
 122         __raw_writel(next_desc_addr, XOR_NEXT_DESC(chan));
 123 }
 124
 125 static void mv_chan_set_dest_pointer(struct mv_xor_chan *chan, u32 desc_addr)
 126 {
 127         __raw_writel(desc_addr, XOR_DEST_POINTER(chan));
 128 }
 129
 130 static void mv_chan_set_block_size(struct mv_xor_chan *chan, u32 block_size)
 131 {
 132         __raw_writel(block_size, XOR_BLOCK_SIZE(chan));
 133 }
 134
 135 static void mv_chan_set_value(struct mv_xor_chan *chan, u32 value)
 136 {
 137         __raw_writel(value, XOR_INIT_VALUE_LOW(chan));
 138         __raw_writel(value, XOR_INIT_VALUE_HIGH(chan));
 139 }
 140
 141 static void mv_chan_unmask_interrupts(struct mv_xor_chan *chan)
 142 {
 143         u32 val = __raw_readl(XOR_INTR_MASK(chan));
 144         val |= XOR_INTR_MASK_VALUE << (chan->idx * 16);
 145         __raw_writel(val, XOR_INTR_MASK(chan));
 146 }
 147
 148 static u32 mv_chan_get_intr_cause(struct mv_xor_chan *chan)
 149 {
 150         u32 intr_cause = __raw_readl(XOR_INTR_CAUSE(chan));
 151         intr_cause = (intr_cause >> (chan->idx * 16)) & 0xFFFF;
 152         return intr_cause;
 153 }
 154
 155 static int mv_is_err_intr(u32 intr_cause)
 156 {
 157         if (intr_cause & ((1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<8)|(1<<9)))
 158                 return 1;
 159
 160         return 0;
 161 }
 162
 163 static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan *chan)
 164 {
 165         u32 val = (1 << (1 + (chan->idx * 16)));
 166         dev_dbg(chan->device->common.dev, "%s, val 0x%08x\n", __func__, val);
 167         __raw_writel(val, XOR_INTR_CAUSE(chan));
 168 }
 169
 170 static void mv_xor_device_clear_err_status(struct mv_xor_chan *chan)
 171 {
 172         u32 val = 0xFFFF0000 >> (chan->idx * 16);
 173         __raw_writel(val, XOR_INTR_CAUSE(chan));
 174 }
 175
 176 static int mv_can_chain(struct mv_xor_desc_slot *desc)
 177 {
 178         struct mv_xor_desc_slot *chain_old_tail = list_entry(
 179                 desc->chain_node.prev, struct mv_xor_desc_slot, chain_node);
 180
 181         if (chain_old_tail->type != desc->type)
 182                 return 0;
 183         if (desc->type == DMA_MEMSET)
 184                 return 0;
 185
 186         return 1;
 187 }
 188
 189 static void mv_set_mode(struct mv_xor_chan *chan,
 190                                enum dma_transaction_type type)
 191 {
 192         u32 op_mode;
 193         u32 config = __raw_readl(XOR_CONFIG(chan));
 194
 195         switch (type) {
 196         case DMA_XOR:
 197                 op_mode = XOR_OPERATION_MODE_XOR;
 198                 break;
 199         case DMA_MEMCPY:
 200                 op_mode = XOR_OPERATION_MODE_MEMCPY;
 201                 break;
 202         case DMA_MEMSET:
 203                 op_mode = XOR_OPERATION_MODE_MEMSET;
 204                 break;
 205         default:
 206                 dev_printk(KERN_ERR, chan->device->common.dev,
 207                            "error: unsupported operation %d.\n",
 208                            type);
 209                 BUG();
 210                 return;
 211         }
 212
 213         config &= ~0x7;
 214         config |= op_mode;
 215         __raw_writel(config, XOR_CONFIG(chan));
 216         chan->current_type = type;
 217 }
 218
 219 static void mv_chan_activate(struct mv_xor_chan *chan)
 220 {
 221         u32 activation;
 222
 223         dev_dbg(chan->device->common.dev, " activate chan.\n");
 224         activation = __raw_readl(XOR_ACTIVATION(chan));
 225         activation |= 0x1;
 226         __raw_writel(activation, XOR_ACTIVATION(chan));
 227 }
 228
 229 static char mv_chan_is_busy(struct mv_xor_chan *chan)
 230 {
 231         u32 state = __raw_readl(XOR_ACTIVATION(chan));
 232
 233         state = (state >> 4) & 0x3;
 234
 235         return (state == 1) ? 1 : 0;
 236 }
 237
 238 static int mv_chan_xor_slot_count(size_t len, int src_cnt)
 239 {
 240         return 1;
 241 }
 242
 243 /**
 244  * mv_xor_free_slots - flags descriptor slots for reuse
 245  * @slot: Slot to free
 246  * Caller must hold &mv_chan->lock while calling this function
 247  */
 248 static void mv_xor_free_slots(struct mv_xor_chan *mv_chan,
 249                               struct mv_xor_desc_slot *slot)
 250 {
 251         dev_dbg(mv_chan->device->common.dev, "%s %d slot %p\n",
 252                 __func__, __LINE__, slot);
 253
 254         slot->slots_per_op = 0;
 255
 256 }
 257
 258 /*
 259  * mv_xor_start_new_chain - program the engine to operate on new chain headed by
 260  * sw_desc
 261  * Caller must hold &mv_chan->lock while calling this function
 262  */
 263 static void mv_xor_start_new_chain(struct mv_xor_chan *mv_chan,
 264                                    struct mv_xor_desc_slot *sw_desc)
 265 {
 266         dev_dbg(mv_chan->device->common.dev, "%s %d: sw_desc %p\n",
 267                 __func__, __LINE__, sw_desc);
 268         if (sw_desc->type != mv_chan->current_type)
 269                 mv_set_mode(mv_chan, sw_desc->type);
 270
 271         if (sw_desc->type == DMA_MEMSET) {
 272                 /* for memset requests we need to program the engine, no
 273                  * descriptors used.
 274                  */
 275                 struct mv_xor_desc *hw_desc = sw_desc->hw_desc;
 276                 mv_chan_set_dest_pointer(mv_chan, hw_desc->phy_dest_addr);
 277                 mv_chan_set_block_size(mv_chan, sw_desc->unmap_len);
 278                 mv_chan_set_value(mv_chan, sw_desc->value);
 279         } else {
 280                 /* set the hardware chain */
 281                 mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys);
 282         }
 283         mv_chan->pending += sw_desc->slot_cnt;
 284         mv_xor_issue_pending(&mv_chan->common);
 285 }
 286
 287 static dma_cookie_t
 288 mv_xor_run_tx_complete_actions(struct mv_xor_desc_slot *desc,
 289         struct mv_xor_chan *mv_chan, dma_cookie_t cookie)
 290 {
 291         BUG_ON(desc->async_tx.cookie < 0);
 292
 293         if (desc->async_tx.cookie > 0) {
 294                 cookie = desc->async_tx.cookie;
 295
 296                 /* call the callback (must not sleep or submit new
 297                  * operations to this channel)
 298                  */
 299                 if (desc->async_tx.callback)
 300                         desc->async_tx.callback(
 301                                 desc->async_tx.callback_param);
 302
 303                 /* unmap dma addresses
 304                  * (unmap_single vs unmap_page?)
 305                  */
 306                 if (desc->group_head && desc->unmap_len) {
 307                         struct mv_xor_desc_slot *unmap = desc->group_head;
 308                         struct device *dev =
 309                                 &mv_chan->device->pdev->dev;
 310                         u32 len = unmap->unmap_len;
 311                         enum dma_ctrl_flags flags = desc->async_tx.flags;
 312                         u32 src_cnt;
 313                         dma_addr_t addr;
 314                         dma_addr_t dest;
 315
 316                         src_cnt = unmap->unmap_src_cnt;
 317                         dest = mv_desc_get_dest_addr(unmap);
 318                         if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
 319                                 enum dma_data_direction dir;
 320
 321                                 if (src_cnt > 1) /* is xor ? */
 322                                         dir = DMA_BIDIRECTIONAL;
 323                                 else
 324                                         dir = DMA_FROM_DEVICE;
 325                                 dma_unmap_page(dev, dest, len, dir);
 326                         }
 327
 328                         if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
 329                                 while (src_cnt--) {
 330                                         addr = mv_desc_get_src_addr(unmap,
 331                                                                     src_cnt);
 332                                         if (addr == dest)
 333                                                 continue;
 334                                         dma_unmap_page(dev, addr, len,
 335                                                        DMA_TO_DEVICE);
 336                                 }
 337                         }
 338                         desc->group_head = NULL;
 339                 }
 340         }
 341
 342         /* run dependent operations */
 343         async_tx_run_dependencies(&desc->async_tx);
 344
 345         return cookie;
 346 }
 347
 348 static int
 349 mv_xor_clean_completed_slots(struct mv_xor_chan *mv_chan)
 350 {
 351         struct mv_xor_desc_slot *iter, *_iter;
 352
 353         dev_dbg(mv_chan->device->common.dev, "%s %d\n", __func__, __LINE__);
 354         list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
 355                                  completed_node) {
 356
 357                 if (async_tx_test_ack(&iter->async_tx)) {
 358                         list_del(&iter->completed_node);
 359                         mv_xor_free_slots(mv_chan, iter);
 360                 }
 361         }
 362         return 0;
 363 }
 364
 365 static int
 366 mv_xor_clean_slot(struct mv_xor_desc_slot *desc,
 367         struct mv_xor_chan *mv_chan)
 368 {
 369         dev_dbg(mv_chan->device->common.dev, "%s %d: desc %p flags %d\n",
 370                 __func__, __LINE__, desc, desc->async_tx.flags);
 371         list_del(&desc->chain_node);
 372         /* the client is allowed to attach dependent operations
 373          * until 'ack' is set
 374          */
 375         if (!async_tx_test_ack(&desc->async_tx)) {
 376                 /* move this slot to the completed_slots */
 377                 list_add_tail(&desc->completed_node, &mv_chan->completed_slots);
 378                 return 0;
 379         }
 380
 381         mv_xor_free_slots(mv_chan, desc);
 382         return 0;
 383 }
 384
 385 static void __mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan)
 386 {
 387         struct mv_xor_desc_slot *iter, *_iter;
 388         dma_cookie_t cookie = 0;
 389         int busy = mv_chan_is_busy(mv_chan);
 390         u32 current_desc = mv_chan_get_current_desc(mv_chan);
 391         int seen_current = 0;
 392
 393         dev_dbg(mv_chan->device->common.dev, "%s %d\n", __func__, __LINE__);
 394         dev_dbg(mv_chan->device->common.dev, "current_desc %x\n", current_desc);
 395         mv_xor_clean_completed_slots(mv_chan);
 396
 397         /* free completed slots from the chain starting with
 398          * the oldest descriptor
 399          */
 400
 401         list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
 402                                         chain_node) {
 403                 prefetch(_iter);
 404                 prefetch(&_iter->async_tx);
 405
 406                 /* do not advance past the current descriptor loaded into the
 407                  * hardware channel, subsequent descriptors are either in
 408                  * process or have not been submitted
 409                  */
 410                 if (seen_current)
 411                         break;
 412
 413                 /* stop the search if we reach the current descriptor and the
 414                  * channel is busy
 415                  */
 416                 if (iter->async_tx.phys == current_desc) {
 417                         seen_current = 1;
 418                         if (busy)
 419                                 break;
 420                 }
 421
 422                 cookie = mv_xor_run_tx_complete_actions(iter, mv_chan, cookie);
 423
 424                 if (mv_xor_clean_slot(iter, mv_chan))
 425                         break;
 426         }
 427
 428         if ((busy == 0) && !list_empty(&mv_chan->chain)) {
 429                 struct mv_xor_desc_slot *chain_head;
 430                 chain_head = list_entry(mv_chan->chain.next,
 431                                         struct mv_xor_desc_slot,
 432                                         chain_node);
 433
 434                 mv_xor_start_new_chain(mv_chan, chain_head);
 435         }
 436
 437         if (cookie > 0)
 438                 mv_chan->completed_cookie = cookie;
 439 }
 440
 441 static void
 442 mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan)
 443 {
 444         spin_lock_bh(&mv_chan->lock);
 445         __mv_xor_slot_cleanup(mv_chan);
 446         spin_unlock_bh(&mv_chan->lock);
 447 }
 448
 449 static void mv_xor_tasklet(unsigned long data)
 450 {
 451         struct mv_xor_chan *chan = (struct mv_xor_chan *) data;
 452         __mv_xor_slot_cleanup(chan);
 453 }
 454
 455 static struct mv_xor_desc_slot *
 456 mv_xor_alloc_slots(struct mv_xor_chan *mv_chan, int num_slots,
 457                     int slots_per_op)
 458 {
 459         struct mv_xor_desc_slot *iter, *_iter, *alloc_start = NULL;
 460         LIST_HEAD(chain);
 461         int slots_found, retry = 0;
 462
 463         /* start search from the last allocated descrtiptor
 464          * if a contiguous allocation can not be found start searching
 465          * from the beginning of the list
 466          */
 467 retry:
 468         slots_found = 0;
 469         if (retry == 0)
 470                 iter = mv_chan->last_used;
 471         else
 472                 iter = list_entry(&mv_chan->all_slots,
 473                         struct mv_xor_desc_slot,
 474                         slot_node);
 475
 476         list_for_each_entry_safe_continue(
 477                 iter, _iter, &mv_chan->all_slots, slot_node) {
 478                 prefetch(_iter);
 479                 prefetch(&_iter->async_tx);
 480                 if (iter->slots_per_op) {
 481                         /* give up after finding the first busy slot
 482                          * on the second pass through the list
 483                          */
 484                         if (retry)
 485                                 break;
 486
 487                         slots_found = 0;
 488                         continue;
 489                 }
 490
 491                 /* start the allocation if the slot is correctly aligned */
 492                 if (!slots_found++)
 493                         alloc_start = iter;
 494
 495                 if (slots_found == num_slots) {
 496                         struct mv_xor_desc_slot *alloc_tail = NULL;
 497                         struct mv_xor_desc_slot *last_used = NULL;
 498                         iter = alloc_start;
 499                         while (num_slots) {
 500                                 int i;
 501
 502                                 /* pre-ack all but the last descriptor */
 503                                 async_tx_ack(&iter->async_tx);
 504
 505                                 list_add_tail(&iter->chain_node, &chain);
 506                                 alloc_tail = iter;
 507                                 iter->async_tx.cookie = 0;
 508                                 iter->slot_cnt = num_slots;
 509                                 iter->xor_check_result = NULL;
 510                                 for (i = 0; i < slots_per_op; i++) {
 511                                         iter->slots_per_op = slots_per_op - i;
 512                                         last_used = iter;
 513                                         iter = list_entry(iter->slot_node.next,
 514                                                 struct mv_xor_desc_slot,
 515                                                 slot_node);
 516                                 }
 517                                 num_slots -= slots_per_op;
 518                         }
 519                         alloc_tail->group_head = alloc_start;
 520                         alloc_tail->async_tx.cookie = -EBUSY;
 521                         list_splice(&chain, &alloc_tail->async_tx.tx_list);
 522                         mv_chan->last_used = last_used;
 523                         mv_desc_clear_next_desc(alloc_start);
 524                         mv_desc_clear_next_desc(alloc_tail);
 525                         return alloc_tail;
 526                 }
 527         }
 528         if (!retry++)
 529                 goto retry;
 530
 531         /* try to free some slots if the allocation fails */
 532         tasklet_schedule(&mv_chan->irq_tasklet);
 533
 534         return NULL;
 535 }
 536
 537 static dma_cookie_t
 538 mv_desc_assign_cookie(struct mv_xor_chan *mv_chan,
 539                       struct mv_xor_desc_slot *desc)
 540 {
 541         dma_cookie_t cookie = mv_chan->common.cookie;
 542
 543         if (++cookie < 0)
 544                 cookie = 1;
 545         mv_chan->common.cookie = desc->async_tx.cookie = cookie;
 546         return cookie;
 547 }
 548
 549 /************************ DMA engine API functions ****************************/
 550 static dma_cookie_t
 551 mv_xor_tx_submit(struct dma_async_tx_descriptor *tx)
 552 {
 553         struct mv_xor_desc_slot *sw_desc = to_mv_xor_slot(tx);
 554         struct mv_xor_chan *mv_chan = to_mv_xor_chan(tx->chan);
 555         struct mv_xor_desc_slot *grp_start, *old_chain_tail;
 556         dma_cookie_t cookie;
 557         int new_hw_chain = 1;
 558
 559         dev_dbg(mv_chan->device->common.dev,
 560                 "%s sw_desc %p: async_tx %p\n",
 561                 __func__, sw_desc, &sw_desc->async_tx);
 562
 563         grp_start = sw_desc->group_head;
 564
 565         spin_lock_bh(&mv_chan->lock);
 566         cookie = mv_desc_assign_cookie(mv_chan, sw_desc);
 567
 568         if (list_empty(&mv_chan->chain))
 569                 list_splice_init(&sw_desc->async_tx.tx_list, &mv_chan->chain);
 570         else {
 571                 new_hw_chain = 0;
 572
 573                 old_chain_tail = list_entry(mv_chan->chain.prev,
 574                                             struct mv_xor_desc_slot,
 575                                             chain_node);
 576                 list_splice_init(&grp_start->async_tx.tx_list,
 577                                  &old_chain_tail->chain_node);
 578
 579                 if (!mv_can_chain(grp_start))
 580                         goto submit_done;
 581
 582                 dev_dbg(mv_chan->device->common.dev, "Append to last desc %x\n",
 583                         old_chain_tail->async_tx.phys);
 584
 585                 /* fix up the hardware chain */
 586                 mv_desc_set_next_desc(old_chain_tail, grp_start->async_tx.phys);
 587
 588                 /* if the channel is not busy */
 589                 if (!mv_chan_is_busy(mv_chan)) {
 590                         u32 current_desc = mv_chan_get_current_desc(mv_chan);
 591                         /*
 592                          * and the curren desc is the end of the chain before
 593                          * the append, then we need to start the channel
 594                          */
 595                         if (current_desc == old_chain_tail->async_tx.phys)
 596                                 new_hw_chain = 1;
 597                 }
 598         }
 599
 600         if (new_hw_chain)
 601                 mv_xor_start_new_chain(mv_chan, grp_start);
 602
 603 submit_done:
 604         spin_unlock_bh(&mv_chan->lock);
 605
 606         return cookie;
 607 }
 608
 609 /* returns the number of allocated descriptors */
 610 static int mv_xor_alloc_chan_resources(struct dma_chan *chan,
 611                                        struct dma_client *client)
 612 {
 613         char *hw_desc;
 614         int idx;
 615         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
 616         struct mv_xor_desc_slot *slot = NULL;
 617         struct mv_xor_platform_data *plat_data =
 618                 mv_chan->device->pdev->dev.platform_data;
 619         int num_descs_in_pool = plat_data->pool_size/MV_XOR_SLOT_SIZE;
 620
 621         /* Allocate descriptor slots */
 622         idx = mv_chan->slots_allocated;
 623         while (idx < num_descs_in_pool) {
 624                 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
 625                 if (!slot) {
 626                         printk(KERN_INFO "MV XOR Channel only initialized"
 627                                 " %d descriptor slots", idx);
 628                         break;
 629                 }
 630                 hw_desc = (char *) mv_chan->device->dma_desc_pool_virt;
 631                 slot->hw_desc = (void *) &hw_desc[idx * MV_XOR_SLOT_SIZE];
 632
 633                 dma_async_tx_descriptor_init(&slot->async_tx, chan);
 634                 slot->async_tx.tx_submit = mv_xor_tx_submit;
 635                 INIT_LIST_HEAD(&slot->chain_node);
 636                 INIT_LIST_HEAD(&slot->slot_node);
 637                 INIT_LIST_HEAD(&slot->async_tx.tx_list);
 638                 hw_desc = (char *) mv_chan->device->dma_desc_pool;
 639                 slot->async_tx.phys =
 640                         (dma_addr_t) &hw_desc[idx * MV_XOR_SLOT_SIZE];
 641                 slot->idx = idx++;
 642
 643                 spin_lock_bh(&mv_chan->lock);
 644                 mv_chan->slots_allocated = idx;
 645                 list_add_tail(&slot->slot_node, &mv_chan->all_slots);
 646                 spin_unlock_bh(&mv_chan->lock);
 647         }
 648
 649         if (mv_chan->slots_allocated && !mv_chan->last_used)
 650                 mv_chan->last_used = list_entry(mv_chan->all_slots.next,
 651                                         struct mv_xor_desc_slot,
 652                                         slot_node);
 653
 654         dev_dbg(mv_chan->device->common.dev,
 655                 "allocated %d descriptor slots last_used: %p\n",
 656                 mv_chan->slots_allocated, mv_chan->last_used);
 657
 658         return mv_chan->slots_allocated ? : -ENOMEM;
 659 }
 660
 661 static struct dma_async_tx_descriptor *
 662 mv_xor_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 663                 size_t len, unsigned long flags)
 664 {
 665         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
 666         struct mv_xor_desc_slot *sw_desc, *grp_start;
 667         int slot_cnt;
 668
 669         dev_dbg(mv_chan->device->common.dev,
 670                 "%s dest: %x src %x len: %u flags: %ld\n",
 671                 __func__, dest, src, len, flags);
 672         if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
 673                 return NULL;
 674
 675         BUG_ON(unlikely(len > MV_XOR_MAX_BYTE_COUNT));
 676
 677         spin_lock_bh(&mv_chan->lock);
 678         slot_cnt = mv_chan_memcpy_slot_count(len);
 679         sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1);
 680         if (sw_desc) {
 681                 sw_desc->type = DMA_MEMCPY;
 682                 sw_desc->async_tx.flags = flags;
 683                 grp_start = sw_desc->group_head;
 684                 mv_desc_init(grp_start, flags);
 685                 mv_desc_set_byte_count(grp_start, len);
 686                 mv_desc_set_dest_addr(sw_desc->group_head, dest);
 687                 mv_desc_set_src_addr(grp_start, 0, src);
 688                 sw_desc->unmap_src_cnt = 1;
 689                 sw_desc->unmap_len = len;
 690         }
 691         spin_unlock_bh(&mv_chan->lock);
 692
 693         dev_dbg(mv_chan->device->common.dev,
 694                 "%s sw_desc %p async_tx %p\n",
 695                 __func__, sw_desc, sw_desc ? &sw_desc->async_tx : 0);
 696
 697         return sw_desc ? &sw_desc->async_tx : NULL;
 698 }
 699
 700 static struct dma_async_tx_descriptor *
 701 mv_xor_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value,
 702                        size_t len, unsigned long flags)
 703 {
 704         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
 705         struct mv_xor_desc_slot *sw_desc, *grp_start;
 706         int slot_cnt;
 707
 708         dev_dbg(mv_chan->device->common.dev,
 709                 "%s dest: %x len: %u flags: %ld\n",
 710                 __func__, dest, len, flags);
 711         if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
 712                 return NULL;
 713
 714         BUG_ON(unlikely(len > MV_XOR_MAX_BYTE_COUNT));
 715
 716         spin_lock_bh(&mv_chan->lock);
 717         slot_cnt = mv_chan_memset_slot_count(len);
 718         sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1);
 719         if (sw_desc) {
 720                 sw_desc->type = DMA_MEMSET;
 721                 sw_desc->async_tx.flags = flags;
 722                 grp_start = sw_desc->group_head;
 723                 mv_desc_init(grp_start, flags);
 724                 mv_desc_set_byte_count(grp_start, len);
 725                 mv_desc_set_dest_addr(sw_desc->group_head, dest);
 726                 mv_desc_set_block_fill_val(grp_start, value);
 727                 sw_desc->unmap_src_cnt = 1;
 728                 sw_desc->unmap_len = len;
 729         }
 730         spin_unlock_bh(&mv_chan->lock);
 731         dev_dbg(mv_chan->device->common.dev,
 732                 "%s sw_desc %p async_tx %p \n",
 733                 __func__, sw_desc, &sw_desc->async_tx);
 734         return sw_desc ? &sw_desc->async_tx : NULL;
 735 }
 736
 737 static struct dma_async_tx_descriptor *
 738 mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
 739                     unsigned int src_cnt, size_t len, unsigned long flags)
 740 {
 741         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
 742         struct mv_xor_desc_slot *sw_desc, *grp_start;
 743         int slot_cnt;
 744
 745         if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
 746                 return NULL;
 747
 748         BUG_ON(unlikely(len > MV_XOR_MAX_BYTE_COUNT));
 749
 750         dev_dbg(mv_chan->device->common.dev,
 751                 "%s src_cnt: %d len: dest %x %u flags: %ld\n",
 752                 __func__, src_cnt, len, dest, flags);
 753
 754         spin_lock_bh(&mv_chan->lock);
 755         slot_cnt = mv_chan_xor_slot_count(len, src_cnt);
 756         sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1);
 757         if (sw_desc) {
 758                 sw_desc->type = DMA_XOR;
 759                 sw_desc->async_tx.flags = flags;
 760                 grp_start = sw_desc->group_head;
 761                 mv_desc_init(grp_start, flags);
 762                 /* the byte count field is the same as in memcpy desc*/
 763                 mv_desc_set_byte_count(grp_start, len);
 764                 mv_desc_set_dest_addr(sw_desc->group_head, dest);
 765                 sw_desc->unmap_src_cnt = src_cnt;
 766                 sw_desc->unmap_len = len;
 767                 while (src_cnt--)
 768                         mv_desc_set_src_addr(grp_start, src_cnt, src[src_cnt]);
 769         }
 770         spin_unlock_bh(&mv_chan->lock);
 771         dev_dbg(mv_chan->device->common.dev,
 772                 "%s sw_desc %p async_tx %p \n",
 773                 __func__, sw_desc, &sw_desc->async_tx);
 774         return sw_desc ? &sw_desc->async_tx : NULL;
 775 }
 776
 777 static void mv_xor_free_chan_resources(struct dma_chan *chan)
 778 {
 779         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
 780         struct mv_xor_desc_slot *iter, *_iter;
 781         int in_use_descs = 0;
 782
 783         mv_xor_slot_cleanup(mv_chan);
 784
 785         spin_lock_bh(&mv_chan->lock);
 786         list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
 787                                         chain_node) {
 788                 in_use_descs++;
 789                 list_del(&iter->chain_node);
 790         }
 791         list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
 792                                  completed_node) {
 793                 in_use_descs++;
 794                 list_del(&iter->completed_node);
 795         }
 796         list_for_each_entry_safe_reverse(
 797                 iter, _iter, &mv_chan->all_slots, slot_node) {
 798                 list_del(&iter->slot_node);
 799                 kfree(iter);
 800                 mv_chan->slots_allocated--;
 801         }
 802         mv_chan->last_used = NULL;
 803
 804         dev_dbg(mv_chan->device->common.dev, "%s slots_allocated %d\n",
 805                 __func__, mv_chan->slots_allocated);
 806         spin_unlock_bh(&mv_chan->lock);
 807
 808         if (in_use_descs)
 809                 dev_err(mv_chan->device->common.dev,
 810                         "freeing %d in use descriptors!\n", in_use_descs);
 811 }
 812
 813 /**
 814  * mv_xor_is_complete - poll the status of an XOR transaction
 815  * @chan: XOR channel handle
 816  * @cookie: XOR transaction identifier
 817  */
 818 static enum dma_status mv_xor_is_complete(struct dma_chan *chan,
 819                                           dma_cookie_t cookie,
 820                                           dma_cookie_t *done,
 821                                           dma_cookie_t *used)
 822 {
 823         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
 824         dma_cookie_t last_used;
 825         dma_cookie_t last_complete;
 826         enum dma_status ret;
 827
 828         last_used = chan->cookie;
 829         last_complete = mv_chan->completed_cookie;
 830         mv_chan->is_complete_cookie = cookie;
 831         if (done)
 832                 *done = last_complete;
 833         if (used)
 834                 *used = last_used;
 835
 836         ret = dma_async_is_complete(cookie, last_complete, last_used);
 837         if (ret == DMA_SUCCESS) {
 838                 mv_xor_clean_completed_slots(mv_chan);
 839                 return ret;
 840         }
 841         mv_xor_slot_cleanup(mv_chan);
 842
 843         last_used = chan->cookie;
 844         last_complete = mv_chan->completed_cookie;
 845
 846         if (done)
 847                 *done = last_complete;
 848         if (used)
 849                 *used = last_used;
 850
 851         return dma_async_is_complete(cookie, last_complete, last_used);
 852 }
 853
 854 static void mv_dump_xor_regs(struct mv_xor_chan *chan)
 855 {
 856         u32 val;
 857
 858         val = __raw_readl(XOR_CONFIG(chan));
 859         dev_printk(KERN_ERR, chan->device->common.dev,
 860                    "config       0x%08x.\n", val);
 861
 862         val = __raw_readl(XOR_ACTIVATION(chan));
 863         dev_printk(KERN_ERR, chan->device->common.dev,
 864                    "activation   0x%08x.\n", val);
 865
 866         val = __raw_readl(XOR_INTR_CAUSE(chan));
 867         dev_printk(KERN_ERR, chan->device->common.dev,
 868                    "intr cause   0x%08x.\n", val);
 869
 870         val = __raw_readl(XOR_INTR_MASK(chan));
 871         dev_printk(KERN_ERR, chan->device->common.dev,
 872                    "intr mask    0x%08x.\n", val);
 873
 874         val = __raw_readl(XOR_ERROR_CAUSE(chan));
 875         dev_printk(KERN_ERR, chan->device->common.dev,
 876                    "error cause  0x%08x.\n", val);
 877
 878         val = __raw_readl(XOR_ERROR_ADDR(chan));
 879         dev_printk(KERN_ERR, chan->device->common.dev,
 880                    "error addr   0x%08x.\n", val);
 881 }
 882
 883 static void mv_xor_err_interrupt_handler(struct mv_xor_chan *chan,
 884                                          u32 intr_cause)
 885 {
 886         if (intr_cause & (1 << 4)) {
 887              dev_dbg(chan->device->common.dev,
 888                      "ignore this error\n");
 889              return;
 890         }
 891
 892         dev_printk(KERN_ERR, chan->device->common.dev,
 893                    "error on chan %d. intr cause 0x%08x.\n",
 894                    chan->idx, intr_cause);
 895
 896         mv_dump_xor_regs(chan);
 897         BUG();
 898 }
 899
 900 static irqreturn_t mv_xor_interrupt_handler(int irq, void *data)
 901 {
 902         struct mv_xor_chan *chan = data;
 903         u32 intr_cause = mv_chan_get_intr_cause(chan);
 904
 905         dev_dbg(chan->device->common.dev, "intr cause %x\n", intr_cause);
 906
 907         if (mv_is_err_intr(intr_cause))
 908                 mv_xor_err_interrupt_handler(chan, intr_cause);
 909
 910         tasklet_schedule(&chan->irq_tasklet);
 911
 912         mv_xor_device_clear_eoc_cause(chan);
 913
 914         return IRQ_HANDLED;
 915 }
 916
 917 static void mv_xor_issue_pending(struct dma_chan *chan)
 918 {
 919         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
 920
 921         if (mv_chan->pending >= MV_XOR_THRESHOLD) {
 922                 mv_chan->pending = 0;
 923                 mv_chan_activate(mv_chan);
 924         }
 925 }
 926
 927 /*
 928  * Perform a transaction to verify the HW works.
 929  */
 930 #define MV_XOR_TEST_SIZE 2000
 931
 932 static int __devinit mv_xor_memcpy_self_test(struct mv_xor_device *device)
 933 {
 934         int i;
 935         void *src, *dest;
 936         dma_addr_t src_dma, dest_dma;
 937         struct dma_chan *dma_chan;
 938         dma_cookie_t cookie;
 939         struct dma_async_tx_descriptor *tx;
 940         int err = 0;
 941         struct mv_xor_chan *mv_chan;
 942
 943         src = kmalloc(sizeof(u8) * MV_XOR_TEST_SIZE, GFP_KERNEL);
 944         if (!src)
 945                 return -ENOMEM;
 946
 947         dest = kzalloc(sizeof(u8) * MV_XOR_TEST_SIZE, GFP_KERNEL);
 948         if (!dest) {
 949                 kfree(src);
 950                 return -ENOMEM;
 951         }
 952
 953         /* Fill in src buffer */
 954         for (i = 0; i < MV_XOR_TEST_SIZE; i++)
 955                 ((u8 *) src)[i] = (u8)i;
 956
 957         /* Start copy, using first DMA channel */
 958         dma_chan = container_of(device->common.channels.next,
 959                                 struct dma_chan,
 960                                 device_node);
 961         if (mv_xor_alloc_chan_resources(dma_chan, NULL) < 1) {
 962                 err = -ENODEV;
 963                 goto out;
 964         }
 965
 966         dest_dma = dma_map_single(dma_chan->device->dev, dest,
 967                                   MV_XOR_TEST_SIZE, DMA_FROM_DEVICE);
 968
 969         src_dma = dma_map_single(dma_chan->device->dev, src,
 970                                  MV_XOR_TEST_SIZE, DMA_TO_DEVICE);
 971
 972         tx = mv_xor_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
 973                                     MV_XOR_TEST_SIZE, 0);
 974         cookie = mv_xor_tx_submit(tx);
 975         mv_xor_issue_pending(dma_chan);
 976         async_tx_ack(tx);
 977         msleep(1);
 978
 979         if (mv_xor_is_complete(dma_chan, cookie, NULL, NULL) !=
 980             DMA_SUCCESS) {
 981                 dev_printk(KERN_ERR, dma_chan->device->dev,
 982                            "Self-test copy timed out, disabling\n");
 983                 err = -ENODEV;
 984                 goto free_resources;
 985         }
 986
 987         mv_chan = to_mv_xor_chan(dma_chan);
 988         dma_sync_single_for_cpu(&mv_chan->device->pdev->dev, dest_dma,
 989                                 MV_XOR_TEST_SIZE, DMA_FROM_DEVICE);
 990         if (memcmp(src, dest, MV_XOR_TEST_SIZE)) {
 991                 dev_printk(KERN_ERR, dma_chan->device->dev,
 992                            "Self-test copy failed compare, disabling\n");
 993                 err = -ENODEV;
 994                 goto free_resources;
 995         }
 996
 997 free_resources:
 998         mv_xor_free_chan_resources(dma_chan);
 999 out:
1000         kfree(src);
1001         kfree(dest);
1002         return err;
1003 }
1004
1005 #define MV_XOR_NUM_SRC_TEST 4 /* must be <= 15 */
1006 static int __devinit
1007 mv_xor_xor_self_test(struct mv_xor_device *device)
1008 {
1009         int i, src_idx;
1010         struct page *dest;
1011         struct page *xor_srcs[MV_XOR_NUM_SRC_TEST];
1012         dma_addr_t dma_srcs[MV_XOR_NUM_SRC_TEST];
1013         dma_addr_t dest_dma;
1014         struct dma_async_tx_descriptor *tx;
1015         struct dma_chan *dma_chan;
1016         dma_cookie_t cookie;
1017         u8 cmp_byte = 0;
1018         u32 cmp_word;
1019         int err = 0;
1020         struct mv_xor_chan *mv_chan;
1021
1022         for (src_idx = 0; src_idx < MV_XOR_NUM_SRC_TEST; src_idx++) {
1023                 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
1024                 if (!xor_srcs[src_idx])
1025                         while (src_idx--) {
1026                                 __free_page(xor_srcs[src_idx]);
1027                                 return -ENOMEM;
1028                         }
1029         }
1030
1031         dest = alloc_page(GFP_KERNEL);
1032         if (!dest)
1033                 while (src_idx--) {
1034                         __free_page(xor_srcs[src_idx]);
1035                         return -ENOMEM;
1036                 }
1037
1038         /* Fill in src buffers */
1039         for (src_idx = 0; src_idx < MV_XOR_NUM_SRC_TEST; src_idx++) {
1040                 u8 *ptr = page_address(xor_srcs[src_idx]);
1041                 for (i = 0; i < PAGE_SIZE; i++)
1042                         ptr[i] = (1 << src_idx);
1043         }
1044
1045         for (src_idx = 0; src_idx < MV_XOR_NUM_SRC_TEST; src_idx++)
1046                 cmp_byte ^= (u8) (1 << src_idx);
1047
1048         cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
1049                 (cmp_byte << 8) | cmp_byte;
1050
1051         memset(page_address(dest), 0, PAGE_SIZE);
1052
1053         dma_chan = container_of(device->common.channels.next,
1054                                 struct dma_chan,
1055                                 device_node);
1056         if (mv_xor_alloc_chan_resources(dma_chan, NULL) < 1) {
1057                 err = -ENODEV;
1058                 goto out;
1059         }
1060
1061         /* test xor */
1062         dest_dma = dma_map_page(dma_chan->device->dev, dest, 0, PAGE_SIZE,
1063                                 DMA_FROM_DEVICE);
1064
1065         for (i = 0; i < MV_XOR_NUM_SRC_TEST; i++)
1066                 dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
1067                                            0, PAGE_SIZE, DMA_TO_DEVICE);
1068
1069         tx = mv_xor_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
1070                                  MV_XOR_NUM_SRC_TEST, PAGE_SIZE, 0);
1071
1072         cookie = mv_xor_tx_submit(tx);
1073         mv_xor_issue_pending(dma_chan);
1074         async_tx_ack(tx);
1075         msleep(8);
1076
1077         if (mv_xor_is_complete(dma_chan, cookie, NULL, NULL) !=
1078             DMA_SUCCESS) {
1079                 dev_printk(KERN_ERR, dma_chan->device->dev,
1080                            "Self-test xor timed out, disabling\n");
1081                 err = -ENODEV;
1082                 goto free_resources;
1083         }
1084
1085         mv_chan = to_mv_xor_chan(dma_chan);
1086         dma_sync_single_for_cpu(&mv_chan->device->pdev->dev, dest_dma,
1087                                 PAGE_SIZE, DMA_FROM_DEVICE);
1088         for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
1089                 u32 *ptr = page_address(dest);
1090                 if (ptr[i] != cmp_word) {
1091                         dev_printk(KERN_ERR, dma_chan->device->dev,
1092                                    "Self-test xor failed compare, disabling."
1093                                    " index %d, data %x, expected %x\n", i,
1094                                    ptr[i], cmp_word);
1095                         err = -ENODEV;
1096                         goto free_resources;
1097                 }
1098         }
1099
1100 free_resources:
1101         mv_xor_free_chan_resources(dma_chan);
1102 out:
1103         src_idx = MV_XOR_NUM_SRC_TEST;
1104         while (src_idx--)
1105                 __free_page(xor_srcs[src_idx]);
1106         __free_page(dest);
1107         return err;
1108 }
1109
1110 static int __devexit mv_xor_remove(struct platform_device *dev)
1111 {
1112         struct mv_xor_device *device = platform_get_drvdata(dev);
1113         struct dma_chan *chan, *_chan;
1114         struct mv_xor_chan *mv_chan;
1115         struct mv_xor_platform_data *plat_data = dev->dev.platform_data;
1116
1117         dma_async_device_unregister(&device->common);
1118
1119         dma_free_coherent(&dev->dev, plat_data->pool_size,
1120                         device->dma_desc_pool_virt, device->dma_desc_pool);
1121
1122         list_for_each_entry_safe(chan, _chan, &device->common.channels,
1123                                 device_node) {
1124                 mv_chan = to_mv_xor_chan(chan);
1125                 list_del(&chan->device_node);
1126         }
1127
1128         return 0;
1129 }
1130
1131 static int __devinit mv_xor_probe(struct platform_device *pdev)
1132 {
1133         int ret = 0;
1134         int irq;
1135         struct mv_xor_device *adev;
1136         struct mv_xor_chan *mv_chan;
1137         struct dma_device *dma_dev;
1138         struct mv_xor_platform_data *plat_data = pdev->dev.platform_data;
1139
1140
1141         adev = devm_kzalloc(&pdev->dev, sizeof(*adev), GFP_KERNEL);
1142         if (!adev)
1143                 return -ENOMEM;
1144
1145         dma_dev = &adev->common;
1146
1147         /* allocate coherent memory for hardware descriptors
1148          * note: writecombine gives slightly better performance, but
1149          * requires that we explicitly flush the writes
1150          */
1151         adev->dma_desc_pool_virt = dma_alloc_writecombine(&pdev->dev,
1152                                                           plat_data->pool_size,
1153                                                           &adev->dma_desc_pool,
1154                                                           GFP_KERNEL);
1155         if (!adev->dma_desc_pool_virt)
1156                 return -ENOMEM;
1157
1158         adev->id = plat_data->hw_id;
1159
1160         /* discover transaction capabilites from the platform data */
1161         dma_dev->cap_mask = plat_data->cap_mask;
1162         adev->pdev = pdev;
1163         platform_set_drvdata(pdev, adev);
1164
1165         adev->shared = platform_get_drvdata(plat_data->shared);
1166
1167         INIT_LIST_HEAD(&dma_dev->channels);
1168
1169         /* set base routines */
1170         dma_dev->device_alloc_chan_resources = mv_xor_alloc_chan_resources;
1171         dma_dev->device_free_chan_resources = mv_xor_free_chan_resources;
1172         dma_dev->device_is_tx_complete = mv_xor_is_complete;
1173         dma_dev->device_issue_pending = mv_xor_issue_pending;
1174         dma_dev->dev = &pdev->dev;
1175
1176         /* set prep routines based on capability */
1177         if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
1178                 dma_dev->device_prep_dma_memcpy = mv_xor_prep_dma_memcpy;
1179         if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask))
1180                 dma_dev->device_prep_dma_memset = mv_xor_prep_dma_memset;
1181         if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1182                 dma_dev->max_xor = 8;                  ;
1183                 dma_dev->device_prep_dma_xor = mv_xor_prep_dma_xor;
1184         }
1185
1186         mv_chan = devm_kzalloc(&pdev->dev, sizeof(*mv_chan), GFP_KERNEL);
1187         if (!mv_chan) {
1188                 ret = -ENOMEM;
1189                 goto err_free_dma;
1190         }
1191         mv_chan->device = adev;
1192         mv_chan->idx = plat_data->hw_id;
1193         mv_chan->mmr_base = adev->shared->xor_base;
1194
1195         if (!mv_chan->mmr_base) {
1196                 ret = -ENOMEM;
1197                 goto err_free_dma;
1198         }
1199         tasklet_init(&mv_chan->irq_tasklet, mv_xor_tasklet, (unsigned long)
1200                      mv_chan);
1201
1202         /* clear errors before enabling interrupts */
1203         mv_xor_device_clear_err_status(mv_chan);
1204
1205         irq = platform_get_irq(pdev, 0);
1206         if (irq < 0) {
1207                 ret = irq;
1208                 goto err_free_dma;
1209         }
1210         ret = devm_request_irq(&pdev->dev, irq,
1211                                mv_xor_interrupt_handler,
1212                                0, dev_name(&pdev->dev), mv_chan);
1213         if (ret)
1214                 goto err_free_dma;
1215
1216         mv_chan_unmask_interrupts(mv_chan);
1217
1218         mv_set_mode(mv_chan, DMA_MEMCPY);
1219
1220         spin_lock_init(&mv_chan->lock);
1221         INIT_LIST_HEAD(&mv_chan->chain);
1222         INIT_LIST_HEAD(&mv_chan->completed_slots);
1223         INIT_LIST_HEAD(&mv_chan->all_slots);
1224         INIT_RCU_HEAD(&mv_chan->common.rcu);
1225         mv_chan->common.device = dma_dev;
1226
1227         list_add_tail(&mv_chan->common.device_node, &dma_dev->channels);
1228
1229         if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1230                 ret = mv_xor_memcpy_self_test(adev);
1231                 dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
1232                 if (ret)
1233                         goto err_free_dma;
1234         }
1235
1236         if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1237                 ret = mv_xor_xor_self_test(adev);
1238                 dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
1239                 if (ret)
1240                         goto err_free_dma;
1241         }
1242
1243         dev_printk(KERN_INFO, &pdev->dev, "Marvell XOR: "
1244           "( %s%s%s%s)\n",
1245           dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
1246           dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)  ? "fill " : "",
1247           dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
1248           dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
1249
1250         dma_async_device_register(dma_dev);
1251         goto out;
1252
1253  err_free_dma:
1254         dma_free_coherent(&adev->pdev->dev, plat_data->pool_size,
1255                         adev->dma_desc_pool_virt, adev->dma_desc_pool);
1256  out:
1257         return ret;
1258 }
1259
1260 static void
1261 mv_xor_conf_mbus_windows(struct mv_xor_shared_private *msp,
1262                          struct mbus_dram_target_info *dram)
1263 {
1264         void __iomem *base = msp->xor_base;
1265         u32 win_enable = 0;
1266         int i;
1267
1268         for (i = 0; i < 8; i++) {
1269                 writel(0, base + WINDOW_BASE(i));
1270                 writel(0, base + WINDOW_SIZE(i));
1271                 if (i < 4)
1272                         writel(0, base + WINDOW_REMAP_HIGH(i));
1273         }
1274
1275         for (i = 0; i < dram->num_cs; i++) {
1276                 struct mbus_dram_window *cs = dram->cs + i;
1277
1278                 writel((cs->base & 0xffff0000) |
1279                        (cs->mbus_attr << 8) |
1280                        dram->mbus_dram_target_id, base + WINDOW_BASE(i));
1281                 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
1282
1283                 win_enable |= (1 << i);
1284                 win_enable |= 3 << (16 + (2 * i));
1285         }
1286
1287         writel(win_enable, base + WINDOW_BAR_ENABLE(0));
1288         writel(win_enable, base + WINDOW_BAR_ENABLE(1));
1289 }
1290
1291 static struct platform_driver mv_xor_driver = {
1292         .probe          = mv_xor_probe,
1293         .remove         = mv_xor_remove,
1294         .driver         = {
1295                 .owner  = THIS_MODULE,
1296                 .name   = MV_XOR_NAME,
1297         },
1298 };
1299
1300 static int mv_xor_shared_probe(struct platform_device *pdev)
1301 {
1302         struct mv_xor_platform_shared_data *msd = pdev->dev.platform_data;
1303         struct mv_xor_shared_private *msp;
1304         struct resource *res;
1305
1306         dev_printk(KERN_NOTICE, &pdev->dev, "Marvell shared XOR driver\n");
1307
1308         msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL);
1309         if (!msp)
1310                 return -ENOMEM;
1311
1312         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1313         if (!res)
1314                 return -ENODEV;
1315
1316         msp->xor_base = devm_ioremap(&pdev->dev, res->start,
1317                                      res->end - res->start + 1);
1318         if (!msp->xor_base)
1319                 return -EBUSY;
1320
1321         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1322         if (!res)
1323                 return -ENODEV;
1324
1325         msp->xor_high_base = devm_ioremap(&pdev->dev, res->start,
1326                                           res->end - res->start + 1);
1327         if (!msp->xor_high_base)
1328                 return -EBUSY;
1329
1330         platform_set_drvdata(pdev, msp);
1331
1332         /*
1333          * (Re-)program MBUS remapping windows if we are asked to.
1334          */
1335         if (msd != NULL && msd->dram != NULL)
1336                 mv_xor_conf_mbus_windows(msp, msd->dram);
1337
1338         return 0;
1339 }
1340
1341 static int mv_xor_shared_remove(struct platform_device *pdev)
1342 {
1343         return 0;
1344 }
1345
1346 static struct platform_driver mv_xor_shared_driver = {
1347         .probe          = mv_xor_shared_probe,
1348         .remove         = mv_xor_shared_remove,
1349         .driver         = {
1350                 .owner  = THIS_MODULE,
1351                 .name   = MV_XOR_SHARED_NAME,
1352         },
1353 };
1354
1355
1356 static int __init mv_xor_init(void)
1357 {
1358         int rc;
1359
1360         rc = platform_driver_register(&mv_xor_shared_driver);
1361         if (!rc) {
1362                 rc = platform_driver_register(&mv_xor_driver);
1363                 if (rc)
1364                         platform_driver_unregister(&mv_xor_shared_driver);
1365         }
1366         return rc;
1367 }
1368 module_init(mv_xor_init);
1369
1370 /* it's currently unsafe to unload this module */
1371 #if 0
1372 static void __exit mv_xor_exit(void)
1373 {
1374         platform_driver_unregister(&mv_xor_driver);
1375         platform_driver_unregister(&mv_xor_shared_driver);
1376         return;
1377 }
1378
1379 module_exit(mv_xor_exit);
1380 #endif
1381
1382 MODULE_AUTHOR("Saeed Bishara <saeed@marvell.com>");
1383 MODULE_DESCRIPTION("DMA engine driver for Marvell's XOR engine");
1384 MODULE_LICENSE("GPL");