SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/dma/dw_dmac.c

   1 /*
   2  * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on
   3  * AVR32 systems.)
   4  *
   5  * Copyright (C) 2007-2008 Atmel Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 #include <linux/clk.h>
  12 #include <linux/delay.h>
  13 #include <linux/dmaengine.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/mm.h>
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/slab.h>
  22
  23 #include "dw_dmac_regs.h"
  24
  25 /*
  26  * This supports the Synopsys "DesignWare AHB Central DMA Controller",
  27  * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
  28  * of which use ARM any more).  See the "Databook" from Synopsys for
  29  * information beyond what licensees probably provide.
  30  *
  31  * The driver has currently been tested only with the Atmel AT32AP7000,
  32  * which does not support descriptor writeback.
  33  */
  34
  35 /* NOTE:  DMS+SMS is system-specific. We should get this information
  36  * from the platform code somehow.
  37  */
  38 #define DWC_DEFAULT_CTLLO       (DWC_CTLL_DST_MSIZE(0)          \
  39                                 | DWC_CTLL_SRC_MSIZE(0)         \
  40                                 | DWC_CTLL_DMS(0)               \
  41                                 | DWC_CTLL_SMS(1)               \
  42                                 | DWC_CTLL_LLP_D_EN             \
  43                                 | DWC_CTLL_LLP_S_EN)
  44
  45 /*
  46  * This is configuration-dependent and usually a funny size like 4095.
  47  * Let's round it down to the nearest power of two.
  48  *
  49  * Note that this is a transfer count, i.e. if we transfer 32-bit
  50  * words, we can do 8192 bytes per descriptor.
  51  *
  52  * This parameter is also system-specific.
  53  */
  54 #define DWC_MAX_COUNT   2048U
  55
  56 /*
  57  * Number of descriptors to allocate for each channel. This should be
  58  * made configurable somehow; preferably, the clients (at least the
  59  * ones using slave transfers) should be able to give us a hint.
  60  */
  61 #define NR_DESCS_PER_CHANNEL    64
  62
  63 /*----------------------------------------------------------------------*/
  64
  65 /*
  66  * Because we're not relying on writeback from the controller (it may not
  67  * even be configured into the core!) we don't need to use dma_pool.  These
  68  * descriptors -- and associated data -- are cacheable.  We do need to make
  69  * sure their dcache entries are written back before handing them off to
  70  * the controller, though.
  71  */
  72
  73 static struct device *chan2dev(struct dma_chan *chan)
  74 {
  75         return &chan->dev->device;
  76 }
  77 static struct device *chan2parent(struct dma_chan *chan)
  78 {
  79         return chan->dev->device.parent;
  80 }
  81
  82 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
  83 {
  84         return list_entry(dwc->active_list.next, struct dw_desc, desc_node);
  85 }
  86
  87 static struct dw_desc *dwc_first_queued(struct dw_dma_chan *dwc)
  88 {
  89         return list_entry(dwc->queue.next, struct dw_desc, desc_node);
  90 }
  91
  92 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
  93 {
  94         struct dw_desc *desc, *_desc;
  95         struct dw_desc *ret = NULL;
  96         unsigned int i = 0;
  97
  98         spin_lock_bh(&dwc->lock);
  99         list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
 100                 if (async_tx_test_ack(&desc->txd)) {
 101                         list_del(&desc->desc_node);
 102                         ret = desc;
 103                         break;
 104                 }
 105                 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
 106                 i++;
 107         }
 108         spin_unlock_bh(&dwc->lock);
 109
 110         dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
 111
 112         return ret;
 113 }
 114
 115 static void dwc_sync_desc_for_cpu(struct dw_dma_chan *dwc, struct dw_desc *desc)
 116 {
 117         struct dw_desc  *child;
 118
 119         list_for_each_entry(child, &desc->tx_list, desc_node)
 120                 dma_sync_single_for_cpu(chan2parent(&dwc->chan),
 121                                 child->txd.phys, sizeof(child->lli),
 122                                 DMA_TO_DEVICE);
 123         dma_sync_single_for_cpu(chan2parent(&dwc->chan),
 124                         desc->txd.phys, sizeof(desc->lli),
 125                         DMA_TO_DEVICE);
 126 }
 127
 128 /*
 129  * Move a descriptor, including any children, to the free list.
 130  * `desc' must not be on any lists.
 131  */
 132 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
 133 {
 134         if (desc) {
 135                 struct dw_desc *child;
 136
 137                 dwc_sync_desc_for_cpu(dwc, desc);
 138
 139                 spin_lock_bh(&dwc->lock);
 140                 list_for_each_entry(child, &desc->tx_list, desc_node)
 141                         dev_vdbg(chan2dev(&dwc->chan),
 142                                         "moving child desc %p to freelist\n",
 143                                         child);
 144                 list_splice_init(&desc->tx_list, &dwc->free_list);
 145                 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
 146                 list_add(&desc->desc_node, &dwc->free_list);
 147                 spin_unlock_bh(&dwc->lock);
 148         }
 149 }
 150
 151 /* Called with dwc->lock held and bh disabled */
 152 static dma_cookie_t
 153 dwc_assign_cookie(struct dw_dma_chan *dwc, struct dw_desc *desc)
 154 {
 155         dma_cookie_t cookie = dwc->chan.cookie;
 156
 157         if (++cookie < 0)
 158                 cookie = 1;
 159
 160         dwc->chan.cookie = cookie;
 161         desc->txd.cookie = cookie;
 162
 163         return cookie;
 164 }
 165
 166 /*----------------------------------------------------------------------*/
 167
 168 /* Called with dwc->lock held and bh disabled */
 169 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
 170 {
 171         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 172
 173         /* ASSERT:  channel is idle */
 174         if (dma_readl(dw, CH_EN) & dwc->mask) {
 175                 dev_err(chan2dev(&dwc->chan),
 176                         "BUG: Attempted to start non-idle channel\n");
 177                 dev_err(chan2dev(&dwc->chan),
 178                         "  SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
 179                         channel_readl(dwc, SAR),
 180                         channel_readl(dwc, DAR),
 181                         channel_readl(dwc, LLP),
 182                         channel_readl(dwc, CTL_HI),
 183                         channel_readl(dwc, CTL_LO));
 184
 185                 /* The tasklet will hopefully advance the queue... */
 186                 return;
 187         }
 188
 189         channel_writel(dwc, LLP, first->txd.phys);
 190         channel_writel(dwc, CTL_LO,
 191                         DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
 192         channel_writel(dwc, CTL_HI, 0);
 193         channel_set_bit(dw, CH_EN, dwc->mask);
 194 }
 195
 196 /*----------------------------------------------------------------------*/
 197
 198 static void
 199 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc)
 200 {
 201         dma_async_tx_callback           callback;
 202         void                            *param;
 203         struct dma_async_tx_descriptor  *txd = &desc->txd;
 204
 205         dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
 206
 207         dwc->completed = txd->cookie;
 208         callback = txd->callback;
 209         param = txd->callback_param;
 210
 211         dwc_sync_desc_for_cpu(dwc, desc);
 212         list_splice_init(&desc->tx_list, &dwc->free_list);
 213         list_move(&desc->desc_node, &dwc->free_list);
 214
 215         if (!dwc->chan.private) {
 216                 struct device *parent = chan2parent(&dwc->chan);
 217                 if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
 218                         if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE)
 219                                 dma_unmap_single(parent, desc->lli.dar,
 220                                                 desc->len, DMA_FROM_DEVICE);
 221                         else
 222                                 dma_unmap_page(parent, desc->lli.dar,
 223                                                 desc->len, DMA_FROM_DEVICE);
 224                 }
 225                 if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
 226                         if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE)
 227                                 dma_unmap_single(parent, desc->lli.sar,
 228                                                 desc->len, DMA_TO_DEVICE);
 229                         else
 230                                 dma_unmap_page(parent, desc->lli.sar,
 231                                                 desc->len, DMA_TO_DEVICE);
 232                 }
 233         }
 234
 235         /*
 236          * The API requires that no submissions are done from a
 237          * callback, so we don't need to drop the lock here
 238          */
 239         if (callback)
 240                 callback(param);
 241 }
 242
 243 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
 244 {
 245         struct dw_desc *desc, *_desc;
 246         LIST_HEAD(list);
 247
 248         if (dma_readl(dw, CH_EN) & dwc->mask) {
 249                 dev_err(chan2dev(&dwc->chan),
 250                         "BUG: XFER bit set, but channel not idle!\n");
 251
 252                 /* Try to continue after resetting the channel... */
 253                 channel_clear_bit(dw, CH_EN, dwc->mask);
 254                 while (dma_readl(dw, CH_EN) & dwc->mask)
 255                         cpu_relax();
 256         }
 257
 258         /*
 259          * Submit queued descriptors ASAP, i.e. before we go through
 260          * the completed ones.
 261          */
 262         if (!list_empty(&dwc->queue))
 263                 dwc_dostart(dwc, dwc_first_queued(dwc));
 264         list_splice_init(&dwc->active_list, &list);
 265         list_splice_init(&dwc->queue, &dwc->active_list);
 266
 267         list_for_each_entry_safe(desc, _desc, &list, desc_node)
 268                 dwc_descriptor_complete(dwc, desc);
 269 }
 270
 271 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
 272 {
 273         dma_addr_t llp;
 274         struct dw_desc *desc, *_desc;
 275         struct dw_desc *child;
 276         u32 status_xfer;
 277
 278         /*
 279          * Clear block interrupt flag before scanning so that we don't
 280          * miss any, and read LLP before RAW_XFER to ensure it is
 281          * valid if we decide to scan the list.
 282          */
 283         dma_writel(dw, CLEAR.BLOCK, dwc->mask);
 284         llp = channel_readl(dwc, LLP);
 285         status_xfer = dma_readl(dw, RAW.XFER);
 286
 287         if (status_xfer & dwc->mask) {
 288                 /* Everything we've submitted is done */
 289                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 290                 dwc_complete_all(dw, dwc);
 291                 return;
 292         }
 293
 294         dev_vdbg(chan2dev(&dwc->chan), "scan_descriptors: llp=0x%x\n", llp);
 295
 296         list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
 297                 if (desc->lli.llp == llp)
 298                         /* This one is currently in progress */
 299                         return;
 300
 301                 list_for_each_entry(child, &desc->tx_list, desc_node)
 302                         if (child->lli.llp == llp)
 303                                 /* Currently in progress */
 304                                 return;
 305
 306                 /*
 307                  * No descriptors so far seem to be in progress, i.e.
 308                  * this one must be done.
 309                  */
 310                 dwc_descriptor_complete(dwc, desc);
 311         }
 312
 313         dev_err(chan2dev(&dwc->chan),
 314                 "BUG: All descriptors done, but channel not idle!\n");
 315
 316         /* Try to continue after resetting the channel... */
 317         channel_clear_bit(dw, CH_EN, dwc->mask);
 318         while (dma_readl(dw, CH_EN) & dwc->mask)
 319                 cpu_relax();
 320
 321         if (!list_empty(&dwc->queue)) {
 322                 dwc_dostart(dwc, dwc_first_queued(dwc));
 323                 list_splice_init(&dwc->queue, &dwc->active_list);
 324         }
 325 }
 326
 327 static void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
 328 {
 329         dev_printk(KERN_CRIT, chan2dev(&dwc->chan),
 330                         "  desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
 331                         lli->sar, lli->dar, lli->llp,
 332                         lli->ctlhi, lli->ctllo);
 333 }
 334
 335 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
 336 {
 337         struct dw_desc *bad_desc;
 338         struct dw_desc *child;
 339
 340         dwc_scan_descriptors(dw, dwc);
 341
 342         /*
 343          * The descriptor currently at the head of the active list is
 344          * borked. Since we don't have any way to report errors, we'll
 345          * just have to scream loudly and try to carry on.
 346          */
 347         bad_desc = dwc_first_active(dwc);
 348         list_del_init(&bad_desc->desc_node);
 349         list_splice_init(&dwc->queue, dwc->active_list.prev);
 350
 351         /* Clear the error flag and try to restart the controller */
 352         dma_writel(dw, CLEAR.ERROR, dwc->mask);
 353         if (!list_empty(&dwc->active_list))
 354                 dwc_dostart(dwc, dwc_first_active(dwc));
 355
 356         /*
 357          * KERN_CRITICAL may seem harsh, but since this only happens
 358          * when someone submits a bad physical address in a
 359          * descriptor, we should consider ourselves lucky that the
 360          * controller flagged an error instead of scribbling over
 361          * random memory locations.
 362          */
 363         dev_printk(KERN_CRIT, chan2dev(&dwc->chan),
 364                         "Bad descriptor submitted for DMA!\n");
 365         dev_printk(KERN_CRIT, chan2dev(&dwc->chan),
 366                         "  cookie: %d\n", bad_desc->txd.cookie);
 367         dwc_dump_lli(dwc, &bad_desc->lli);
 368         list_for_each_entry(child, &bad_desc->tx_list, desc_node)
 369                 dwc_dump_lli(dwc, &child->lli);
 370
 371         /* Pretend the descriptor completed successfully */
 372         dwc_descriptor_complete(dwc, bad_desc);
 373 }
 374
 375 /* --------------------- Cyclic DMA API extensions -------------------- */
 376
 377 inline dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
 378 {
 379         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 380         return channel_readl(dwc, SAR);
 381 }
 382 EXPORT_SYMBOL(dw_dma_get_src_addr);
 383
 384 inline dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
 385 {
 386         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 387         return channel_readl(dwc, DAR);
 388 }
 389 EXPORT_SYMBOL(dw_dma_get_dst_addr);
 390
 391 /* called with dwc->lock held and all DMAC interrupts disabled */
 392 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
 393                 u32 status_block, u32 status_err, u32 status_xfer)
 394 {
 395         if (status_block & dwc->mask) {
 396                 void (*callback)(void *param);
 397                 void *callback_param;
 398
 399                 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
 400                                 channel_readl(dwc, LLP));
 401                 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
 402
 403                 callback = dwc->cdesc->period_callback;
 404                 callback_param = dwc->cdesc->period_callback_param;
 405                 if (callback) {
 406                         spin_unlock(&dwc->lock);
 407                         callback(callback_param);
 408                         spin_lock(&dwc->lock);
 409                 }
 410         }
 411
 412         /*
 413          * Error and transfer complete are highly unlikely, and will most
 414          * likely be due to a configuration error by the user.
 415          */
 416         if (unlikely(status_err & dwc->mask) ||
 417                         unlikely(status_xfer & dwc->mask)) {
 418                 int i;
 419
 420                 dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s "
 421                                 "interrupt, stopping DMA transfer\n",
 422                                 status_xfer ? "xfer" : "error");
 423                 dev_err(chan2dev(&dwc->chan),
 424                         "  SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
 425                         channel_readl(dwc, SAR),
 426                         channel_readl(dwc, DAR),
 427                         channel_readl(dwc, LLP),
 428                         channel_readl(dwc, CTL_HI),
 429                         channel_readl(dwc, CTL_LO));
 430
 431                 channel_clear_bit(dw, CH_EN, dwc->mask);
 432                 while (dma_readl(dw, CH_EN) & dwc->mask)
 433                         cpu_relax();
 434
 435                 /* make sure DMA does not restart by loading a new list */
 436                 channel_writel(dwc, LLP, 0);
 437                 channel_writel(dwc, CTL_LO, 0);
 438                 channel_writel(dwc, CTL_HI, 0);
 439
 440                 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
 441                 dma_writel(dw, CLEAR.ERROR, dwc->mask);
 442                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 443
 444                 for (i = 0; i < dwc->cdesc->periods; i++)
 445                         dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
 446         }
 447 }
 448
 449 /* ------------------------------------------------------------------------- */
 450
 451 static void dw_dma_tasklet(unsigned long data)
 452 {
 453         struct dw_dma *dw = (struct dw_dma *)data;
 454         struct dw_dma_chan *dwc;
 455         u32 status_block;
 456         u32 status_xfer;
 457         u32 status_err;
 458         int i;
 459
 460         status_block = dma_readl(dw, RAW.BLOCK);
 461         status_xfer = dma_readl(dw, RAW.XFER);
 462         status_err = dma_readl(dw, RAW.ERROR);
 463
 464         dev_vdbg(dw->dma.dev, "tasklet: status_block=%x status_err=%x\n",
 465                         status_block, status_err);
 466
 467         for (i = 0; i < dw->dma.chancnt; i++) {
 468                 dwc = &dw->chan[i];
 469                 spin_lock(&dwc->lock);
 470                 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
 471                         dwc_handle_cyclic(dw, dwc, status_block, status_err,
 472                                         status_xfer);
 473                 else if (status_err & (1 << i))
 474                         dwc_handle_error(dw, dwc);
 475                 else if ((status_block | status_xfer) & (1 << i))
 476                         dwc_scan_descriptors(dw, dwc);
 477                 spin_unlock(&dwc->lock);
 478         }
 479
 480         /*
 481          * Re-enable interrupts. Block Complete interrupts are only
 482          * enabled if the INT_EN bit in the descriptor is set. This
 483          * will trigger a scan before the whole list is done.
 484          */
 485         channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
 486         channel_set_bit(dw, MASK.BLOCK, dw->all_chan_mask);
 487         channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
 488 }
 489
 490 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
 491 {
 492         struct dw_dma *dw = dev_id;
 493         u32 status;
 494
 495         dev_vdbg(dw->dma.dev, "interrupt: status=0x%x\n",
 496                         dma_readl(dw, STATUS_INT));
 497
 498         /*
 499          * Just disable the interrupts. We'll turn them back on in the
 500          * softirq handler.
 501          */
 502         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
 503         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
 504         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
 505
 506         status = dma_readl(dw, STATUS_INT);
 507         if (status) {
 508                 dev_err(dw->dma.dev,
 509                         "BUG: Unexpected interrupts pending: 0x%x\n",
 510                         status);
 511
 512                 /* Try to recover */
 513                 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
 514                 channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1);
 515                 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
 516                 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
 517                 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
 518         }
 519
 520         tasklet_schedule(&dw->tasklet);
 521
 522         return IRQ_HANDLED;
 523 }
 524
 525 /*----------------------------------------------------------------------*/
 526
 527 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
 528 {
 529         struct dw_desc          *desc = txd_to_dw_desc(tx);
 530         struct dw_dma_chan      *dwc = to_dw_dma_chan(tx->chan);
 531         dma_cookie_t            cookie;
 532
 533         spin_lock_bh(&dwc->lock);
 534         cookie = dwc_assign_cookie(dwc, desc);
 535
 536         /*
 537          * REVISIT: We should attempt to chain as many descriptors as
 538          * possible, perhaps even appending to those already submitted
 539          * for DMA. But this is hard to do in a race-free manner.
 540          */
 541         if (list_empty(&dwc->active_list)) {
 542                 dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n",
 543                                 desc->txd.cookie);
 544                 dwc_dostart(dwc, desc);
 545                 list_add_tail(&desc->desc_node, &dwc->active_list);
 546         } else {
 547                 dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n",
 548                                 desc->txd.cookie);
 549
 550                 list_add_tail(&desc->desc_node, &dwc->queue);
 551         }
 552
 553         spin_unlock_bh(&dwc->lock);
 554
 555         return cookie;
 556 }
 557
 558 static struct dma_async_tx_descriptor *
 559 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 560                 size_t len, unsigned long flags)
 561 {
 562         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 563         struct dw_desc          *desc;
 564         struct dw_desc          *first;
 565         struct dw_desc          *prev;
 566         size_t                  xfer_count;
 567         size_t                  offset;
 568         unsigned int            src_width;
 569         unsigned int            dst_width;
 570         u32                     ctllo;
 571
 572         dev_vdbg(chan2dev(chan), "prep_dma_memcpy d0x%x s0x%x l0x%zx f0x%lx\n",
 573                         dest, src, len, flags);
 574
 575         if (unlikely(!len)) {
 576                 dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
 577                 return NULL;
 578         }
 579
 580         /*
 581          * We can be a lot more clever here, but this should take care
 582          * of the most common optimization.
 583          */
 584         if (!((src | dest  | len) & 3))
 585                 src_width = dst_width = 2;
 586         else if (!((src | dest | len) & 1))
 587                 src_width = dst_width = 1;
 588         else
 589                 src_width = dst_width = 0;
 590
 591         ctllo = DWC_DEFAULT_CTLLO
 592                         | DWC_CTLL_DST_WIDTH(dst_width)
 593                         | DWC_CTLL_SRC_WIDTH(src_width)
 594                         | DWC_CTLL_DST_INC
 595                         | DWC_CTLL_SRC_INC
 596                         | DWC_CTLL_FC_M2M;
 597         prev = first = NULL;
 598
 599         for (offset = 0; offset < len; offset += xfer_count << src_width) {
 600                 xfer_count = min_t(size_t, (len - offset) >> src_width,
 601                                 DWC_MAX_COUNT);
 602
 603                 desc = dwc_desc_get(dwc);
 604                 if (!desc)
 605                         goto err_desc_get;
 606
 607                 desc->lli.sar = src + offset;
 608                 desc->lli.dar = dest + offset;
 609                 desc->lli.ctllo = ctllo;
 610                 desc->lli.ctlhi = xfer_count;
 611
 612                 if (!first) {
 613                         first = desc;
 614                 } else {
 615                         prev->lli.llp = desc->txd.phys;
 616                         dma_sync_single_for_device(chan2parent(chan),
 617                                         prev->txd.phys, sizeof(prev->lli),
 618                                         DMA_TO_DEVICE);
 619                         list_add_tail(&desc->desc_node,
 620                                         &first->tx_list);
 621                 }
 622                 prev = desc;
 623         }
 624
 625
 626         if (flags & DMA_PREP_INTERRUPT)
 627                 /* Trigger interrupt after last block */
 628                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 629
 630         prev->lli.llp = 0;
 631         dma_sync_single_for_device(chan2parent(chan),
 632                         prev->txd.phys, sizeof(prev->lli),
 633                         DMA_TO_DEVICE);
 634
 635         first->txd.flags = flags;
 636         first->len = len;
 637
 638         return &first->txd;
 639
 640 err_desc_get:
 641         dwc_desc_put(dwc, first);
 642         return NULL;
 643 }
 644
 645 static struct dma_async_tx_descriptor *
 646 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 647                 unsigned int sg_len, enum dma_data_direction direction,
 648                 unsigned long flags)
 649 {
 650         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 651         struct dw_dma_slave     *dws = chan->private;
 652         struct dw_desc          *prev;
 653         struct dw_desc          *first;
 654         u32                     ctllo;
 655         dma_addr_t              reg;
 656         unsigned int            reg_width;
 657         unsigned int            mem_width;
 658         unsigned int            i;
 659         struct scatterlist      *sg;
 660         size_t                  total_len = 0;
 661
 662         dev_vdbg(chan2dev(chan), "prep_dma_slave\n");
 663
 664         if (unlikely(!dws || !sg_len))
 665                 return NULL;
 666
 667         reg_width = dws->reg_width;
 668         prev = first = NULL;
 669
 670         switch (direction) {
 671         case DMA_TO_DEVICE:
 672                 ctllo = (DWC_DEFAULT_CTLLO
 673                                 | DWC_CTLL_DST_WIDTH(reg_width)
 674                                 | DWC_CTLL_DST_FIX
 675                                 | DWC_CTLL_SRC_INC
 676                                 | DWC_CTLL_FC_M2P);
 677                 reg = dws->tx_reg;
 678                 for_each_sg(sgl, sg, sg_len, i) {
 679                         struct dw_desc  *desc;
 680                         u32             len;
 681                         u32             mem;
 682
 683                         desc = dwc_desc_get(dwc);
 684                         if (!desc) {
 685                                 dev_err(chan2dev(chan),
 686                                         "not enough descriptors available\n");
 687                                 goto err_desc_get;
 688                         }
 689
 690                         mem = sg_phys(sg);
 691                         len = sg_dma_len(sg);
 692                         mem_width = 2;
 693                         if (unlikely(mem & 3 || len & 3))
 694                                 mem_width = 0;
 695
 696                         desc->lli.sar = mem;
 697                         desc->lli.dar = reg;
 698                         desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
 699                         desc->lli.ctlhi = len >> mem_width;
 700
 701                         if (!first) {
 702                                 first = desc;
 703                         } else {
 704                                 prev->lli.llp = desc->txd.phys;
 705                                 dma_sync_single_for_device(chan2parent(chan),
 706                                                 prev->txd.phys,
 707                                                 sizeof(prev->lli),
 708                                                 DMA_TO_DEVICE);
 709                                 list_add_tail(&desc->desc_node,
 710                                                 &first->tx_list);
 711                         }
 712                         prev = desc;
 713                         total_len += len;
 714                 }
 715                 break;
 716         case DMA_FROM_DEVICE:
 717                 ctllo = (DWC_DEFAULT_CTLLO
 718                                 | DWC_CTLL_SRC_WIDTH(reg_width)
 719                                 | DWC_CTLL_DST_INC
 720                                 | DWC_CTLL_SRC_FIX
 721                                 | DWC_CTLL_FC_P2M);
 722
 723                 reg = dws->rx_reg;
 724                 for_each_sg(sgl, sg, sg_len, i) {
 725                         struct dw_desc  *desc;
 726                         u32             len;
 727                         u32             mem;
 728
 729                         desc = dwc_desc_get(dwc);
 730                         if (!desc) {
 731                                 dev_err(chan2dev(chan),
 732                                         "not enough descriptors available\n");
 733                                 goto err_desc_get;
 734                         }
 735
 736                         mem = sg_phys(sg);
 737                         len = sg_dma_len(sg);
 738                         mem_width = 2;
 739                         if (unlikely(mem & 3 || len & 3))
 740                                 mem_width = 0;
 741
 742                         desc->lli.sar = reg;
 743                         desc->lli.dar = mem;
 744                         desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
 745                         desc->lli.ctlhi = len >> reg_width;
 746
 747                         if (!first) {
 748                                 first = desc;
 749                         } else {
 750                                 prev->lli.llp = desc->txd.phys;
 751                                 dma_sync_single_for_device(chan2parent(chan),
 752                                                 prev->txd.phys,
 753                                                 sizeof(prev->lli),
 754                                                 DMA_TO_DEVICE);
 755                                 list_add_tail(&desc->desc_node,
 756                                                 &first->tx_list);
 757                         }
 758                         prev = desc;
 759                         total_len += len;
 760                 }
 761                 break;
 762         default:
 763                 return NULL;
 764         }
 765
 766         if (flags & DMA_PREP_INTERRUPT)
 767                 /* Trigger interrupt after last block */
 768                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 769
 770         prev->lli.llp = 0;
 771         dma_sync_single_for_device(chan2parent(chan),
 772                         prev->txd.phys, sizeof(prev->lli),
 773                         DMA_TO_DEVICE);
 774
 775         first->len = total_len;
 776
 777         return &first->txd;
 778
 779 err_desc_get:
 780         dwc_desc_put(dwc, first);
 781         return NULL;
 782 }
 783
 784 static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd)
 785 {
 786         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 787         struct dw_dma           *dw = to_dw_dma(chan->device);
 788         struct dw_desc          *desc, *_desc;
 789         LIST_HEAD(list);
 790
 791         /* Only supports DMA_TERMINATE_ALL */
 792         if (cmd != DMA_TERMINATE_ALL)
 793                 return -ENXIO;
 794
 795         /*
 796          * This is only called when something went wrong elsewhere, so
 797          * we don't really care about the data. Just disable the
 798          * channel. We still have to poll the channel enable bit due
 799          * to AHB/HSB limitations.
 800          */
 801         spin_lock_bh(&dwc->lock);
 802
 803         channel_clear_bit(dw, CH_EN, dwc->mask);
 804
 805         while (dma_readl(dw, CH_EN) & dwc->mask)
 806                 cpu_relax();
 807
 808         /* active_list entries will end up before queued entries */
 809         list_splice_init(&dwc->queue, &list);
 810         list_splice_init(&dwc->active_list, &list);
 811
 812         spin_unlock_bh(&dwc->lock);
 813
 814         /* Flush all pending and queued descriptors */
 815         list_for_each_entry_safe(desc, _desc, &list, desc_node)
 816                 dwc_descriptor_complete(dwc, desc);
 817
 818         return 0;
 819 }
 820
 821 static enum dma_status
 822 dwc_tx_status(struct dma_chan *chan,
 823               dma_cookie_t cookie,
 824               struct dma_tx_state *txstate)
 825 {
 826         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 827         dma_cookie_t            last_used;
 828         dma_cookie_t            last_complete;
 829         int                     ret;
 830
 831         last_complete = dwc->completed;
 832         last_used = chan->cookie;
 833
 834         ret = dma_async_is_complete(cookie, last_complete, last_used);
 835         if (ret != DMA_SUCCESS) {
 836                 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
 837
 838                 last_complete = dwc->completed;
 839                 last_used = chan->cookie;
 840
 841                 ret = dma_async_is_complete(cookie, last_complete, last_used);
 842         }
 843
 844         dma_set_tx_state(txstate, last_complete, last_used, 0);
 845
 846         return ret;
 847 }
 848
 849 static void dwc_issue_pending(struct dma_chan *chan)
 850 {
 851         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 852
 853         spin_lock_bh(&dwc->lock);
 854         if (!list_empty(&dwc->queue))
 855                 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
 856         spin_unlock_bh(&dwc->lock);
 857 }
 858
 859 static int dwc_alloc_chan_resources(struct dma_chan *chan)
 860 {
 861         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 862         struct dw_dma           *dw = to_dw_dma(chan->device);
 863         struct dw_desc          *desc;
 864         struct dw_dma_slave     *dws;
 865         int                     i;
 866         u32                     cfghi;
 867         u32                     cfglo;
 868
 869         dev_vdbg(chan2dev(chan), "alloc_chan_resources\n");
 870
 871         /* ASSERT:  channel is idle */
 872         if (dma_readl(dw, CH_EN) & dwc->mask) {
 873                 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
 874                 return -EIO;
 875         }
 876
 877         dwc->completed = chan->cookie = 1;
 878
 879         cfghi = DWC_CFGH_FIFO_MODE;
 880         cfglo = 0;
 881
 882         dws = chan->private;
 883         if (dws) {
 884                 /*
 885                  * We need controller-specific data to set up slave
 886                  * transfers.
 887                  */
 888                 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
 889
 890                 cfghi = dws->cfg_hi;
 891                 cfglo = dws->cfg_lo;
 892         }
 893         channel_writel(dwc, CFG_LO, cfglo);
 894         channel_writel(dwc, CFG_HI, cfghi);
 895
 896         /*
 897          * NOTE: some controllers may have additional features that we
 898          * need to initialize here, like "scatter-gather" (which
 899          * doesn't mean what you think it means), and status writeback.
 900          */
 901
 902         spin_lock_bh(&dwc->lock);
 903         i = dwc->descs_allocated;
 904         while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
 905                 spin_unlock_bh(&dwc->lock);
 906
 907                 desc = kzalloc(sizeof(struct dw_desc), GFP_KERNEL);
 908                 if (!desc) {
 909                         dev_info(chan2dev(chan),
 910                                 "only allocated %d descriptors\n", i);
 911                         spin_lock_bh(&dwc->lock);
 912                         break;
 913                 }
 914
 915                 INIT_LIST_HEAD(&desc->tx_list);
 916                 dma_async_tx_descriptor_init(&desc->txd, chan);
 917                 desc->txd.tx_submit = dwc_tx_submit;
 918                 desc->txd.flags = DMA_CTRL_ACK;
 919                 desc->txd.phys = dma_map_single(chan2parent(chan), &desc->lli,
 920                                 sizeof(desc->lli), DMA_TO_DEVICE);
 921                 dwc_desc_put(dwc, desc);
 922
 923                 spin_lock_bh(&dwc->lock);
 924                 i = ++dwc->descs_allocated;
 925         }
 926
 927         /* Enable interrupts */
 928         channel_set_bit(dw, MASK.XFER, dwc->mask);
 929         channel_set_bit(dw, MASK.BLOCK, dwc->mask);
 930         channel_set_bit(dw, MASK.ERROR, dwc->mask);
 931
 932         spin_unlock_bh(&dwc->lock);
 933
 934         dev_dbg(chan2dev(chan),
 935                 "alloc_chan_resources allocated %d descriptors\n", i);
 936
 937         return i;
 938 }
 939
 940 static void dwc_free_chan_resources(struct dma_chan *chan)
 941 {
 942         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 943         struct dw_dma           *dw = to_dw_dma(chan->device);
 944         struct dw_desc          *desc, *_desc;
 945         LIST_HEAD(list);
 946
 947         dev_dbg(chan2dev(chan), "free_chan_resources (descs allocated=%u)\n",
 948                         dwc->descs_allocated);
 949
 950         /* ASSERT:  channel is idle */
 951         BUG_ON(!list_empty(&dwc->active_list));
 952         BUG_ON(!list_empty(&dwc->queue));
 953         BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
 954
 955         spin_lock_bh(&dwc->lock);
 956         list_splice_init(&dwc->free_list, &list);
 957         dwc->descs_allocated = 0;
 958
 959         /* Disable interrupts */
 960         channel_clear_bit(dw, MASK.XFER, dwc->mask);
 961         channel_clear_bit(dw, MASK.BLOCK, dwc->mask);
 962         channel_clear_bit(dw, MASK.ERROR, dwc->mask);
 963
 964         spin_unlock_bh(&dwc->lock);
 965
 966         list_for_each_entry_safe(desc, _desc, &list, desc_node) {
 967                 dev_vdbg(chan2dev(chan), "  freeing descriptor %p\n", desc);
 968                 dma_unmap_single(chan2parent(chan), desc->txd.phys,
 969                                 sizeof(desc->lli), DMA_TO_DEVICE);
 970                 kfree(desc);
 971         }
 972
 973         dev_vdbg(chan2dev(chan), "free_chan_resources done\n");
 974 }
 975
 976 /* --------------------- Cyclic DMA API extensions -------------------- */
 977
 978 /**
 979  * dw_dma_cyclic_start - start the cyclic DMA transfer
 980  * @chan: the DMA channel to start
 981  *
 982  * Must be called with soft interrupts disabled. Returns zero on success or
 983  * -errno on failure.
 984  */
 985 int dw_dma_cyclic_start(struct dma_chan *chan)
 986 {
 987         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 988         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
 989
 990         if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
 991                 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
 992                 return -ENODEV;
 993         }
 994
 995         spin_lock(&dwc->lock);
 996
 997         /* assert channel is idle */
 998         if (dma_readl(dw, CH_EN) & dwc->mask) {
 999                 dev_err(chan2dev(&dwc->chan),
1000                         "BUG: Attempted to start non-idle channel\n");
1001                 dev_err(chan2dev(&dwc->chan),
1002                         "  SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
1003                         channel_readl(dwc, SAR),
1004                         channel_readl(dwc, DAR),
1005                         channel_readl(dwc, LLP),
1006                         channel_readl(dwc, CTL_HI),
1007                         channel_readl(dwc, CTL_LO));
1008                 spin_unlock(&dwc->lock);
1009                 return -EBUSY;
1010         }
1011
1012         dma_writel(dw, CLEAR.BLOCK, dwc->mask);
1013         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1014         dma_writel(dw, CLEAR.XFER, dwc->mask);
1015
1016         /* setup DMAC channel registers */
1017         channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
1018         channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
1019         channel_writel(dwc, CTL_HI, 0);
1020
1021         channel_set_bit(dw, CH_EN, dwc->mask);
1022
1023         spin_unlock(&dwc->lock);
1024
1025         return 0;
1026 }
1027 EXPORT_SYMBOL(dw_dma_cyclic_start);
1028
1029 /**
1030  * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1031  * @chan: the DMA channel to stop
1032  *
1033  * Must be called with soft interrupts disabled.
1034  */
1035 void dw_dma_cyclic_stop(struct dma_chan *chan)
1036 {
1037         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1038         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1039
1040         spin_lock(&dwc->lock);
1041
1042         channel_clear_bit(dw, CH_EN, dwc->mask);
1043         while (dma_readl(dw, CH_EN) & dwc->mask)
1044                 cpu_relax();
1045
1046         spin_unlock(&dwc->lock);
1047 }
1048 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1049
1050 /**
1051  * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1052  * @chan: the DMA channel to prepare
1053  * @buf_addr: physical DMA address where the buffer starts
1054  * @buf_len: total number of bytes for the entire buffer
1055  * @period_len: number of bytes for each period
1056  * @direction: transfer direction, to or from device
1057  *
1058  * Must be called before trying to start the transfer. Returns a valid struct
1059  * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1060  */
1061 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1062                 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1063                 enum dma_data_direction direction)
1064 {
1065         struct dw_dma_chan              *dwc = to_dw_dma_chan(chan);
1066         struct dw_cyclic_desc           *cdesc;
1067         struct dw_cyclic_desc           *retval = NULL;
1068         struct dw_desc                  *desc;
1069         struct dw_desc                  *last = NULL;
1070         struct dw_dma_slave             *dws = chan->private;
1071         unsigned long                   was_cyclic;
1072         unsigned int                    reg_width;
1073         unsigned int                    periods;
1074         unsigned int                    i;
1075
1076         spin_lock_bh(&dwc->lock);
1077         if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1078                 spin_unlock_bh(&dwc->lock);
1079                 dev_dbg(chan2dev(&dwc->chan),
1080                                 "queue and/or active list are not empty\n");
1081                 return ERR_PTR(-EBUSY);
1082         }
1083
1084         was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1085         spin_unlock_bh(&dwc->lock);
1086         if (was_cyclic) {
1087                 dev_dbg(chan2dev(&dwc->chan),
1088                                 "channel already prepared for cyclic DMA\n");
1089                 return ERR_PTR(-EBUSY);
1090         }
1091
1092         retval = ERR_PTR(-EINVAL);
1093         reg_width = dws->reg_width;
1094         periods = buf_len / period_len;
1095
1096         /* Check for too big/unaligned periods and unaligned DMA buffer. */
1097         if (period_len > (DWC_MAX_COUNT << reg_width))
1098                 goto out_err;
1099         if (unlikely(period_len & ((1 << reg_width) - 1)))
1100                 goto out_err;
1101         if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1102                 goto out_err;
1103         if (unlikely(!(direction & (DMA_TO_DEVICE | DMA_FROM_DEVICE))))
1104                 goto out_err;
1105
1106         retval = ERR_PTR(-ENOMEM);
1107
1108         if (periods > NR_DESCS_PER_CHANNEL)
1109                 goto out_err;
1110
1111         cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1112         if (!cdesc)
1113                 goto out_err;
1114
1115         cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1116         if (!cdesc->desc)
1117                 goto out_err_alloc;
1118
1119         for (i = 0; i < periods; i++) {
1120                 desc = dwc_desc_get(dwc);
1121                 if (!desc)
1122                         goto out_err_desc_get;
1123
1124                 switch (direction) {
1125                 case DMA_TO_DEVICE:
1126                         desc->lli.dar = dws->tx_reg;
1127                         desc->lli.sar = buf_addr + (period_len * i);
1128                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO
1129                                         | DWC_CTLL_DST_WIDTH(reg_width)
1130                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1131                                         | DWC_CTLL_DST_FIX
1132                                         | DWC_CTLL_SRC_INC
1133                                         | DWC_CTLL_FC_M2P
1134                                         | DWC_CTLL_INT_EN);
1135                         break;
1136                 case DMA_FROM_DEVICE:
1137                         desc->lli.dar = buf_addr + (period_len * i);
1138                         desc->lli.sar = dws->rx_reg;
1139                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO
1140                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1141                                         | DWC_CTLL_DST_WIDTH(reg_width)
1142                                         | DWC_CTLL_DST_INC
1143                                         | DWC_CTLL_SRC_FIX
1144                                         | DWC_CTLL_FC_P2M
1145                                         | DWC_CTLL_INT_EN);
1146                         break;
1147                 default:
1148                         break;
1149                 }
1150
1151                 desc->lli.ctlhi = (period_len >> reg_width);
1152                 cdesc->desc[i] = desc;
1153
1154                 if (last) {
1155                         last->lli.llp = desc->txd.phys;
1156                         dma_sync_single_for_device(chan2parent(chan),
1157                                         last->txd.phys, sizeof(last->lli),
1158                                         DMA_TO_DEVICE);
1159                 }
1160
1161                 last = desc;
1162         }
1163
1164         /* lets make a cyclic list */
1165         last->lli.llp = cdesc->desc[0]->txd.phys;
1166         dma_sync_single_for_device(chan2parent(chan), last->txd.phys,
1167                         sizeof(last->lli), DMA_TO_DEVICE);
1168
1169         dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%08x len %zu "
1170                         "period %zu periods %d\n", buf_addr, buf_len,
1171                         period_len, periods);
1172
1173         cdesc->periods = periods;
1174         dwc->cdesc = cdesc;
1175
1176         return cdesc;
1177
1178 out_err_desc_get:
1179         while (i--)
1180                 dwc_desc_put(dwc, cdesc->desc[i]);
1181 out_err_alloc:
1182         kfree(cdesc);
1183 out_err:
1184         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1185         return (struct dw_cyclic_desc *)retval;
1186 }
1187 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1188
1189 /**
1190  * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1191  * @chan: the DMA channel to free
1192  */
1193 void dw_dma_cyclic_free(struct dma_chan *chan)
1194 {
1195         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1196         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1197         struct dw_cyclic_desc   *cdesc = dwc->cdesc;
1198         int                     i;
1199
1200         dev_dbg(chan2dev(&dwc->chan), "cyclic free\n");
1201
1202         if (!cdesc)
1203                 return;
1204
1205         spin_lock_bh(&dwc->lock);
1206
1207         channel_clear_bit(dw, CH_EN, dwc->mask);
1208         while (dma_readl(dw, CH_EN) & dwc->mask)
1209                 cpu_relax();
1210
1211         dma_writel(dw, CLEAR.BLOCK, dwc->mask);
1212         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1213         dma_writel(dw, CLEAR.XFER, dwc->mask);
1214
1215         spin_unlock_bh(&dwc->lock);
1216
1217         for (i = 0; i < cdesc->periods; i++)
1218                 dwc_desc_put(dwc, cdesc->desc[i]);
1219
1220         kfree(cdesc->desc);
1221         kfree(cdesc);
1222
1223         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1224 }
1225 EXPORT_SYMBOL(dw_dma_cyclic_free);
1226
1227 /*----------------------------------------------------------------------*/
1228
1229 static void dw_dma_off(struct dw_dma *dw)
1230 {
1231         dma_writel(dw, CFG, 0);
1232
1233         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1234         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1235         channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1236         channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1237         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1238
1239         while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1240                 cpu_relax();
1241 }
1242
1243 static int __init dw_probe(struct platform_device *pdev)
1244 {
1245         struct dw_dma_platform_data *pdata;
1246         struct resource         *io;
1247         struct dw_dma           *dw;
1248         size_t                  size;
1249         int                     irq;
1250         int                     err;
1251         int                     i;
1252
1253         pdata = pdev->dev.platform_data;
1254         if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS)
1255                 return -EINVAL;
1256
1257         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1258         if (!io)
1259                 return -EINVAL;
1260
1261         irq = platform_get_irq(pdev, 0);
1262         if (irq < 0)
1263                 return irq;
1264
1265         size = sizeof(struct dw_dma);
1266         size += pdata->nr_channels * sizeof(struct dw_dma_chan);
1267         dw = kzalloc(size, GFP_KERNEL);
1268         if (!dw)
1269                 return -ENOMEM;
1270
1271         if (!request_mem_region(io->start, DW_REGLEN, pdev->dev.driver->name)) {
1272                 err = -EBUSY;
1273                 goto err_kfree;
1274         }
1275
1276         dw->regs = ioremap(io->start, DW_REGLEN);
1277         if (!dw->regs) {
1278                 err = -ENOMEM;
1279                 goto err_release_r;
1280         }
1281
1282         dw->clk = clk_get(&pdev->dev, "hclk");
1283         if (IS_ERR(dw->clk)) {
1284                 err = PTR_ERR(dw->clk);
1285                 goto err_clk;
1286         }
1287         clk_enable(dw->clk);
1288
1289         /* force dma off, just in case */
1290         dw_dma_off(dw);
1291
1292         err = request_irq(irq, dw_dma_interrupt, 0, "dw_dmac", dw);
1293         if (err)
1294                 goto err_irq;
1295
1296         platform_set_drvdata(pdev, dw);
1297
1298         tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1299
1300         dw->all_chan_mask = (1 << pdata->nr_channels) - 1;
1301
1302         INIT_LIST_HEAD(&dw->dma.channels);
1303         for (i = 0; i < pdata->nr_channels; i++, dw->dma.chancnt++) {
1304                 struct dw_dma_chan      *dwc = &dw->chan[i];
1305
1306                 dwc->chan.device = &dw->dma;
1307                 dwc->chan.cookie = dwc->completed = 1;
1308                 dwc->chan.chan_id = i;
1309                 list_add_tail(&dwc->chan.device_node, &dw->dma.channels);
1310
1311                 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1312                 spin_lock_init(&dwc->lock);
1313                 dwc->mask = 1 << i;
1314
1315                 INIT_LIST_HEAD(&dwc->active_list);
1316                 INIT_LIST_HEAD(&dwc->queue);
1317                 INIT_LIST_HEAD(&dwc->free_list);
1318
1319                 channel_clear_bit(dw, CH_EN, dwc->mask);
1320         }
1321
1322         /* Clear/disable all interrupts on all channels. */
1323         dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1324         dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1325         dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1326         dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1327         dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1328
1329         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1330         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1331         channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1332         channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1333         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1334
1335         dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1336         dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1337         dw->dma.dev = &pdev->dev;
1338         dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1339         dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1340
1341         dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1342
1343         dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1344         dw->dma.device_control = dwc_control;
1345
1346         dw->dma.device_tx_status = dwc_tx_status;
1347         dw->dma.device_issue_pending = dwc_issue_pending;
1348
1349         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1350
1351         printk(KERN_INFO "%s: DesignWare DMA Controller, %d channels\n",
1352                         dev_name(&pdev->dev), dw->dma.chancnt);
1353
1354         dma_async_device_register(&dw->dma);
1355
1356         return 0;
1357
1358 err_irq:
1359         clk_disable(dw->clk);
1360         clk_put(dw->clk);
1361 err_clk:
1362         iounmap(dw->regs);
1363         dw->regs = NULL;
1364 err_release_r:
1365         release_resource(io);
1366 err_kfree:
1367         kfree(dw);
1368         return err;
1369 }
1370
1371 static int __exit dw_remove(struct platform_device *pdev)
1372 {
1373         struct dw_dma           *dw = platform_get_drvdata(pdev);
1374         struct dw_dma_chan      *dwc, *_dwc;
1375         struct resource         *io;
1376
1377         dw_dma_off(dw);
1378         dma_async_device_unregister(&dw->dma);
1379
1380         free_irq(platform_get_irq(pdev, 0), dw);
1381         tasklet_kill(&dw->tasklet);
1382
1383         list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1384                         chan.device_node) {
1385                 list_del(&dwc->chan.device_node);
1386                 channel_clear_bit(dw, CH_EN, dwc->mask);
1387         }
1388
1389         clk_disable(dw->clk);
1390         clk_put(dw->clk);
1391
1392         iounmap(dw->regs);
1393         dw->regs = NULL;
1394
1395         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1396         release_mem_region(io->start, DW_REGLEN);
1397
1398         kfree(dw);
1399
1400         return 0;
1401 }
1402
1403 static void dw_shutdown(struct platform_device *pdev)
1404 {
1405         struct dw_dma   *dw = platform_get_drvdata(pdev);
1406
1407         dw_dma_off(platform_get_drvdata(pdev));
1408         clk_disable(dw->clk);
1409 }
1410
1411 static int dw_suspend_noirq(struct device *dev)
1412 {
1413         struct platform_device *pdev = to_platform_device(dev);
1414         struct dw_dma   *dw = platform_get_drvdata(pdev);
1415
1416         dw_dma_off(platform_get_drvdata(pdev));
1417         clk_disable(dw->clk);
1418         return 0;
1419 }
1420
1421 static int dw_resume_noirq(struct device *dev)
1422 {
1423         struct platform_device *pdev = to_platform_device(dev);
1424         struct dw_dma   *dw = platform_get_drvdata(pdev);
1425
1426         clk_enable(dw->clk);
1427         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1428         return 0;
1429 }
1430
1431 static const struct dev_pm_ops dw_dev_pm_ops = {
1432         .suspend_noirq = dw_suspend_noirq,
1433         .resume_noirq = dw_resume_noirq,
1434 };
1435
1436 static struct platform_driver dw_driver = {
1437         .remove         = __exit_p(dw_remove),
1438         .shutdown       = dw_shutdown,
1439         .driver = {
1440                 .name   = "dw_dmac",
1441                 .pm     = &dw_dev_pm_ops,
1442         },
1443 };
1444
1445 static int __init dw_init(void)
1446 {
1447         return platform_driver_probe(&dw_driver, dw_probe);
1448 }
1449 module_init(dw_init);
1450
1451 static void __exit dw_exit(void)
1452 {
1453         platform_driver_unregister(&dw_driver);
1454 }
1455 module_exit(dw_exit);
1456
1457 MODULE_LICENSE("GPL v2");
1458 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver");
1459 MODULE_AUTHOR("Haavard Skinnemoen <haavard.skinnemoen@atmel.com>");