2 * Driver for the Atmel AHB DMA Controller (aka HDMA or DMAC on AT91 systems)
4 * Copyright (C) 2008 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 * This supports the Atmel AHB DMA Controller,
14 * The driver has currently been tested with the Atmel AT91SAM9RL
15 * and AT91SAM9G45 series.
18 #include <linux/clk.h>
19 #include <linux/dmaengine.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/dmapool.h>
22 #include <linux/interrupt.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
26 #include "at_hdmac_regs.h"
32 * at_hdmac : Name of the ATmel AHB DMA Controller
33 * at_dma_ / atdma : ATmel DMA controller entity related
34 * atc_ / atchan : ATmel DMA Channel entity related
37 #define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO)
38 #define ATC_DEFAULT_CTRLA (0)
39 #define ATC_DEFAULT_CTRLB (ATC_SIF(0) \
43 * Initial number of descriptors to allocate for each channel. This could
44 * be increased during dma usage.
46 static unsigned int init_nr_desc_per_channel = 64;
47 module_param(init_nr_desc_per_channel, uint, 0644);
48 MODULE_PARM_DESC(init_nr_desc_per_channel,
49 "initial descriptors per channel (default: 64)");
53 static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx);
56 /*----------------------------------------------------------------------*/
58 static struct at_desc *atc_first_active(struct at_dma_chan *atchan)
60 return list_first_entry(&atchan->active_list,
61 struct at_desc, desc_node);
64 static struct at_desc *atc_first_queued(struct at_dma_chan *atchan)
66 return list_first_entry(&atchan->queue,
67 struct at_desc, desc_node);
71 * atc_alloc_descriptor - allocate and return an initilized descriptor
72 * @chan: the channel to allocate descriptors for
73 * @gfp_flags: GFP allocation flags
75 * Note: The ack-bit is positioned in the descriptor flag at creation time
76 * to make initial allocation more convenient. This bit will be cleared
77 * and control will be given to client at usage time (during
78 * preparation functions).
80 static struct at_desc *atc_alloc_descriptor(struct dma_chan *chan,
83 struct at_desc *desc = NULL;
84 struct at_dma *atdma = to_at_dma(chan->device);
87 desc = dma_pool_alloc(atdma->dma_desc_pool, gfp_flags, &phys);
89 memset(desc, 0, sizeof(struct at_desc));
90 INIT_LIST_HEAD(&desc->tx_list);
91 dma_async_tx_descriptor_init(&desc->txd, chan);
92 /* txd.flags will be overwritten in prep functions */
93 desc->txd.flags = DMA_CTRL_ACK;
94 desc->txd.tx_submit = atc_tx_submit;
95 desc->txd.phys = phys;
102 * atc_desc_get - get a unsused descriptor from free_list
103 * @atchan: channel we want a new descriptor for
105 static struct at_desc *atc_desc_get(struct at_dma_chan *atchan)
107 struct at_desc *desc, *_desc;
108 struct at_desc *ret = NULL;
112 spin_lock_bh(&atchan->lock);
113 list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) {
115 if (async_tx_test_ack(&desc->txd)) {
116 list_del(&desc->desc_node);
120 dev_dbg(chan2dev(&atchan->chan_common),
121 "desc %p not ACKed\n", desc);
123 spin_unlock_bh(&atchan->lock);
124 dev_vdbg(chan2dev(&atchan->chan_common),
125 "scanned %u descriptors on freelist\n", i);
127 /* no more descriptor available in initial pool: create one more */
129 ret = atc_alloc_descriptor(&atchan->chan_common, GFP_ATOMIC);
131 spin_lock_bh(&atchan->lock);
132 atchan->descs_allocated++;
133 spin_unlock_bh(&atchan->lock);
135 dev_err(chan2dev(&atchan->chan_common),
136 "not enough descriptors available\n");
144 * atc_desc_put - move a descriptor, including any children, to the free list
145 * @atchan: channel we work on
146 * @desc: descriptor, at the head of a chain, to move to free list
148 static void atc_desc_put(struct at_dma_chan *atchan, struct at_desc *desc)
151 struct at_desc *child;
153 spin_lock_bh(&atchan->lock);
154 list_for_each_entry(child, &desc->tx_list, desc_node)
155 dev_vdbg(chan2dev(&atchan->chan_common),
156 "moving child desc %p to freelist\n",
158 list_splice_init(&desc->tx_list, &atchan->free_list);
159 dev_vdbg(chan2dev(&atchan->chan_common),
160 "moving desc %p to freelist\n", desc);
161 list_add(&desc->desc_node, &atchan->free_list);
162 spin_unlock_bh(&atchan->lock);
167 * atc_assign_cookie - compute and assign new cookie
168 * @atchan: channel we work on
169 * @desc: descriptor to asign cookie for
171 * Called with atchan->lock held and bh disabled
174 atc_assign_cookie(struct at_dma_chan *atchan, struct at_desc *desc)
176 dma_cookie_t cookie = atchan->chan_common.cookie;
181 atchan->chan_common.cookie = cookie;
182 desc->txd.cookie = cookie;
188 * atc_dostart - starts the DMA engine for real
189 * @atchan: the channel we want to start
190 * @first: first descriptor in the list we want to begin with
192 * Called with atchan->lock held and bh disabled
194 static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first)
196 struct at_dma *atdma = to_at_dma(atchan->chan_common.device);
198 /* ASSERT: channel is idle */
199 if (atc_chan_is_enabled(atchan)) {
200 dev_err(chan2dev(&atchan->chan_common),
201 "BUG: Attempted to start non-idle channel\n");
202 dev_err(chan2dev(&atchan->chan_common),
203 " channel: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n",
204 channel_readl(atchan, SADDR),
205 channel_readl(atchan, DADDR),
206 channel_readl(atchan, CTRLA),
207 channel_readl(atchan, CTRLB),
208 channel_readl(atchan, DSCR));
210 /* The tasklet will hopefully advance the queue... */
214 vdbg_dump_regs(atchan);
216 /* clear any pending interrupt */
217 while (dma_readl(atdma, EBCISR))
220 channel_writel(atchan, SADDR, 0);
221 channel_writel(atchan, DADDR, 0);
222 channel_writel(atchan, CTRLA, 0);
223 channel_writel(atchan, CTRLB, 0);
224 channel_writel(atchan, DSCR, first->txd.phys);
225 dma_writel(atdma, CHER, atchan->mask);
227 vdbg_dump_regs(atchan);
231 * atc_chain_complete - finish work for one transaction chain
232 * @atchan: channel we work on
233 * @desc: descriptor at the head of the chain we want do complete
235 * Called with atchan->lock held and bh disabled */
237 atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc)
239 dma_async_tx_callback callback;
241 struct dma_async_tx_descriptor *txd = &desc->txd;
243 dev_vdbg(chan2dev(&atchan->chan_common),
244 "descriptor %u complete\n", txd->cookie);
246 atchan->completed_cookie = txd->cookie;
247 callback = txd->callback;
248 param = txd->callback_param;
250 /* move children to free_list */
251 list_splice_init(&desc->tx_list, &atchan->free_list);
252 /* move myself to free_list */
253 list_move(&desc->desc_node, &atchan->free_list);
255 /* unmap dma addresses */
256 if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
257 if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE)
258 dma_unmap_single(chan2parent(&atchan->chan_common),
260 desc->len, DMA_FROM_DEVICE);
262 dma_unmap_page(chan2parent(&atchan->chan_common),
264 desc->len, DMA_FROM_DEVICE);
266 if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
267 if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE)
268 dma_unmap_single(chan2parent(&atchan->chan_common),
270 desc->len, DMA_TO_DEVICE);
272 dma_unmap_page(chan2parent(&atchan->chan_common),
274 desc->len, DMA_TO_DEVICE);
278 * The API requires that no submissions are done from a
279 * callback, so we don't need to drop the lock here
284 dma_run_dependencies(txd);
288 * atc_complete_all - finish work for all transactions
289 * @atchan: channel to complete transactions for
291 * Eventually submit queued descriptors if any
293 * Assume channel is idle while calling this function
294 * Called with atchan->lock held and bh disabled
296 static void atc_complete_all(struct at_dma_chan *atchan)
298 struct at_desc *desc, *_desc;
301 dev_vdbg(chan2dev(&atchan->chan_common), "complete all\n");
303 BUG_ON(atc_chan_is_enabled(atchan));
306 * Submit queued descriptors ASAP, i.e. before we go through
307 * the completed ones.
309 if (!list_empty(&atchan->queue))
310 atc_dostart(atchan, atc_first_queued(atchan));
311 /* empty active_list now it is completed */
312 list_splice_init(&atchan->active_list, &list);
313 /* empty queue list by moving descriptors (if any) to active_list */
314 list_splice_init(&atchan->queue, &atchan->active_list);
316 list_for_each_entry_safe(desc, _desc, &list, desc_node)
317 atc_chain_complete(atchan, desc);
321 * atc_cleanup_descriptors - cleanup up finished descriptors in active_list
322 * @atchan: channel to be cleaned up
324 * Called with atchan->lock held and bh disabled
326 static void atc_cleanup_descriptors(struct at_dma_chan *atchan)
328 struct at_desc *desc, *_desc;
329 struct at_desc *child;
331 dev_vdbg(chan2dev(&atchan->chan_common), "cleanup descriptors\n");
333 list_for_each_entry_safe(desc, _desc, &atchan->active_list, desc_node) {
334 if (!(desc->lli.ctrla & ATC_DONE))
335 /* This one is currently in progress */
338 list_for_each_entry(child, &desc->tx_list, desc_node)
339 if (!(child->lli.ctrla & ATC_DONE))
340 /* Currently in progress */
344 * No descriptors so far seem to be in progress, i.e.
345 * this chain must be done.
347 atc_chain_complete(atchan, desc);
352 * atc_advance_work - at the end of a transaction, move forward
353 * @atchan: channel where the transaction ended
355 * Called with atchan->lock held and bh disabled
357 static void atc_advance_work(struct at_dma_chan *atchan)
359 dev_vdbg(chan2dev(&atchan->chan_common), "advance_work\n");
361 if (list_empty(&atchan->active_list) ||
362 list_is_singular(&atchan->active_list)) {
363 atc_complete_all(atchan);
365 atc_chain_complete(atchan, atc_first_active(atchan));
367 atc_dostart(atchan, atc_first_active(atchan));
373 * atc_handle_error - handle errors reported by DMA controller
374 * @atchan: channel where error occurs
376 * Called with atchan->lock held and bh disabled
378 static void atc_handle_error(struct at_dma_chan *atchan)
380 struct at_desc *bad_desc;
381 struct at_desc *child;
384 * The descriptor currently at the head of the active list is
385 * broked. Since we don't have any way to report errors, we'll
386 * just have to scream loudly and try to carry on.
388 bad_desc = atc_first_active(atchan);
389 list_del_init(&bad_desc->desc_node);
391 /* As we are stopped, take advantage to push queued descriptors
393 list_splice_init(&atchan->queue, atchan->active_list.prev);
395 /* Try to restart the controller */
396 if (!list_empty(&atchan->active_list))
397 atc_dostart(atchan, atc_first_active(atchan));
400 * KERN_CRITICAL may seem harsh, but since this only happens
401 * when someone submits a bad physical address in a
402 * descriptor, we should consider ourselves lucky that the
403 * controller flagged an error instead of scribbling over
404 * random memory locations.
406 dev_crit(chan2dev(&atchan->chan_common),
407 "Bad descriptor submitted for DMA!\n");
408 dev_crit(chan2dev(&atchan->chan_common),
409 " cookie: %d\n", bad_desc->txd.cookie);
410 atc_dump_lli(atchan, &bad_desc->lli);
411 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
412 atc_dump_lli(atchan, &child->lli);
414 /* Pretend the descriptor completed successfully */
415 atc_chain_complete(atchan, bad_desc);
419 /*-- IRQ & Tasklet ---------------------------------------------------*/
421 static void atc_tasklet(unsigned long data)
423 struct at_dma_chan *atchan = (struct at_dma_chan *)data;
425 /* Channel cannot be enabled here */
426 if (atc_chan_is_enabled(atchan)) {
427 dev_err(chan2dev(&atchan->chan_common),
428 "BUG: channel enabled in tasklet\n");
432 spin_lock(&atchan->lock);
433 if (test_and_clear_bit(0, &atchan->error_status))
434 atc_handle_error(atchan);
436 atc_advance_work(atchan);
438 spin_unlock(&atchan->lock);
441 static irqreturn_t at_dma_interrupt(int irq, void *dev_id)
443 struct at_dma *atdma = (struct at_dma *)dev_id;
444 struct at_dma_chan *atchan;
446 u32 status, pending, imr;
450 imr = dma_readl(atdma, EBCIMR);
451 status = dma_readl(atdma, EBCISR);
452 pending = status & imr;
457 dev_vdbg(atdma->dma_common.dev,
458 "interrupt: status = 0x%08x, 0x%08x, 0x%08x\n",
459 status, imr, pending);
461 for (i = 0; i < atdma->dma_common.chancnt; i++) {
462 atchan = &atdma->chan[i];
463 if (pending & (AT_DMA_CBTC(i) | AT_DMA_ERR(i))) {
464 if (pending & AT_DMA_ERR(i)) {
465 /* Disable channel on AHB error */
466 dma_writel(atdma, CHDR, atchan->mask);
467 /* Give information to tasklet */
468 set_bit(0, &atchan->error_status);
470 tasklet_schedule(&atchan->tasklet);
481 /*-- DMA Engine API --------------------------------------------------*/
484 * atc_tx_submit - set the prepared descriptor(s) to be executed by the engine
485 * @desc: descriptor at the head of the transaction chain
487 * Queue chain if DMA engine is working already
489 * Cookie increment and adding to active_list or queue must be atomic
491 static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx)
493 struct at_desc *desc = txd_to_at_desc(tx);
494 struct at_dma_chan *atchan = to_at_dma_chan(tx->chan);
497 spin_lock_bh(&atchan->lock);
498 cookie = atc_assign_cookie(atchan, desc);
500 if (list_empty(&atchan->active_list)) {
501 dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n",
503 atc_dostart(atchan, desc);
504 list_add_tail(&desc->desc_node, &atchan->active_list);
506 dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n",
508 list_add_tail(&desc->desc_node, &atchan->queue);
511 spin_unlock_bh(&atchan->lock);
517 * atc_prep_dma_memcpy - prepare a memcpy operation
518 * @chan: the channel to prepare operation on
519 * @dest: operation virtual destination address
520 * @src: operation virtual source address
521 * @len: operation length
522 * @flags: tx descriptor status flags
524 static struct dma_async_tx_descriptor *
525 atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
526 size_t len, unsigned long flags)
528 struct at_dma_chan *atchan = to_at_dma_chan(chan);
529 struct at_desc *desc = NULL;
530 struct at_desc *first = NULL;
531 struct at_desc *prev = NULL;
534 unsigned int src_width;
535 unsigned int dst_width;
539 dev_vdbg(chan2dev(chan), "prep_dma_memcpy: d0x%x s0x%x l0x%zx f0x%lx\n",
540 dest, src, len, flags);
542 if (unlikely(!len)) {
543 dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
547 ctrla = ATC_DEFAULT_CTRLA;
548 ctrlb = ATC_DEFAULT_CTRLB
549 | ATC_SRC_ADDR_MODE_INCR
550 | ATC_DST_ADDR_MODE_INCR
554 * We can be a lot more clever here, but this should take care
555 * of the most common optimization.
557 if (!((src | dest | len) & 3)) {
558 ctrla |= ATC_SRC_WIDTH_WORD | ATC_DST_WIDTH_WORD;
559 src_width = dst_width = 2;
560 } else if (!((src | dest | len) & 1)) {
561 ctrla |= ATC_SRC_WIDTH_HALFWORD | ATC_DST_WIDTH_HALFWORD;
562 src_width = dst_width = 1;
564 ctrla |= ATC_SRC_WIDTH_BYTE | ATC_DST_WIDTH_BYTE;
565 src_width = dst_width = 0;
568 for (offset = 0; offset < len; offset += xfer_count << src_width) {
569 xfer_count = min_t(size_t, (len - offset) >> src_width,
572 desc = atc_desc_get(atchan);
576 desc->lli.saddr = src + offset;
577 desc->lli.daddr = dest + offset;
578 desc->lli.ctrla = ctrla | xfer_count;
579 desc->lli.ctrlb = ctrlb;
581 desc->txd.cookie = 0;
582 async_tx_ack(&desc->txd);
587 /* inform the HW lli about chaining */
588 prev->lli.dscr = desc->txd.phys;
589 /* insert the link descriptor to the LD ring */
590 list_add_tail(&desc->desc_node,
596 /* First descriptor of the chain embedds additional information */
597 first->txd.cookie = -EBUSY;
600 /* set end-of-link to the last link descriptor of list*/
603 desc->txd.flags = flags; /* client is in control of this ack */
608 atc_desc_put(atchan, first);
614 * atc_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
616 * @sgl: scatterlist to transfer to/from
617 * @sg_len: number of entries in @scatterlist
618 * @direction: DMA direction
619 * @flags: tx descriptor status flags
621 static struct dma_async_tx_descriptor *
622 atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
623 unsigned int sg_len, enum dma_data_direction direction,
626 struct at_dma_chan *atchan = to_at_dma_chan(chan);
627 struct at_dma_slave *atslave = chan->private;
628 struct at_desc *first = NULL;
629 struct at_desc *prev = NULL;
633 unsigned int reg_width;
634 unsigned int mem_width;
636 struct scatterlist *sg;
637 size_t total_len = 0;
639 dev_vdbg(chan2dev(chan), "prep_slave_sg: %s f0x%lx\n",
640 direction == DMA_TO_DEVICE ? "TO DEVICE" : "FROM DEVICE",
643 if (unlikely(!atslave || !sg_len)) {
644 dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
648 reg_width = atslave->reg_width;
650 sg_len = dma_map_sg(chan2parent(chan), sgl, sg_len, direction);
652 ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla;
653 ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN;
657 ctrla |= ATC_DST_WIDTH(reg_width);
658 ctrlb |= ATC_DST_ADDR_MODE_FIXED
659 | ATC_SRC_ADDR_MODE_INCR
661 reg = atslave->tx_reg;
662 for_each_sg(sgl, sg, sg_len, i) {
663 struct at_desc *desc;
667 desc = atc_desc_get(atchan);
672 len = sg_dma_len(sg);
674 if (unlikely(mem & 3 || len & 3))
677 desc->lli.saddr = mem;
678 desc->lli.daddr = reg;
679 desc->lli.ctrla = ctrla
680 | ATC_SRC_WIDTH(mem_width)
682 desc->lli.ctrlb = ctrlb;
687 /* inform the HW lli about chaining */
688 prev->lli.dscr = desc->txd.phys;
689 /* insert the link descriptor to the LD ring */
690 list_add_tail(&desc->desc_node,
697 case DMA_FROM_DEVICE:
698 ctrla |= ATC_SRC_WIDTH(reg_width);
699 ctrlb |= ATC_DST_ADDR_MODE_INCR
700 | ATC_SRC_ADDR_MODE_FIXED
703 reg = atslave->rx_reg;
704 for_each_sg(sgl, sg, sg_len, i) {
705 struct at_desc *desc;
709 desc = atc_desc_get(atchan);
714 len = sg_dma_len(sg);
716 if (unlikely(mem & 3 || len & 3))
719 desc->lli.saddr = reg;
720 desc->lli.daddr = mem;
721 desc->lli.ctrla = ctrla
722 | ATC_DST_WIDTH(mem_width)
724 desc->lli.ctrlb = ctrlb;
729 /* inform the HW lli about chaining */
730 prev->lli.dscr = desc->txd.phys;
731 /* insert the link descriptor to the LD ring */
732 list_add_tail(&desc->desc_node,
743 /* set end-of-link to the last link descriptor of list*/
746 /* First descriptor of the chain embedds additional information */
747 first->txd.cookie = -EBUSY;
748 first->len = total_len;
750 /* last link descriptor of list is responsible of flags */
751 prev->txd.flags = flags; /* client is in control of this ack */
756 dev_err(chan2dev(chan), "not enough descriptors available\n");
757 atc_desc_put(atchan, first);
761 static void atc_terminate_all(struct dma_chan *chan)
763 struct at_dma_chan *atchan = to_at_dma_chan(chan);
764 struct at_dma *atdma = to_at_dma(chan->device);
765 struct at_desc *desc, *_desc;
769 * This is only called when something went wrong elsewhere, so
770 * we don't really care about the data. Just disable the
771 * channel. We still have to poll the channel enable bit due
772 * to AHB/HSB limitations.
774 spin_lock_bh(&atchan->lock);
776 dma_writel(atdma, CHDR, atchan->mask);
778 /* confirm that this channel is disabled */
779 while (dma_readl(atdma, CHSR) & atchan->mask)
782 /* active_list entries will end up before queued entries */
783 list_splice_init(&atchan->queue, &list);
784 list_splice_init(&atchan->active_list, &list);
786 spin_unlock_bh(&atchan->lock);
788 /* Flush all pending and queued descriptors */
789 list_for_each_entry_safe(desc, _desc, &list, desc_node)
790 atc_chain_complete(atchan, desc);
794 * atc_is_tx_complete - poll for transaction completion
796 * @cookie: transaction identifier to check status of
797 * @done: if not %NULL, updated with last completed transaction
798 * @used: if not %NULL, updated with last used transaction
800 * If @done and @used are passed in, upon return they reflect the driver
801 * internal state and can be used with dma_async_is_complete() to check
802 * the status of multiple cookies without re-checking hardware state.
804 static enum dma_status
805 atc_is_tx_complete(struct dma_chan *chan,
807 dma_cookie_t *done, dma_cookie_t *used)
809 struct at_dma_chan *atchan = to_at_dma_chan(chan);
810 dma_cookie_t last_used;
811 dma_cookie_t last_complete;
814 dev_vdbg(chan2dev(chan), "is_tx_complete: %d (d%d, u%d)\n",
815 cookie, done ? *done : 0, used ? *used : 0);
817 spin_lock_bh(atchan->lock);
819 last_complete = atchan->completed_cookie;
820 last_used = chan->cookie;
822 ret = dma_async_is_complete(cookie, last_complete, last_used);
823 if (ret != DMA_SUCCESS) {
824 atc_cleanup_descriptors(atchan);
826 last_complete = atchan->completed_cookie;
827 last_used = chan->cookie;
829 ret = dma_async_is_complete(cookie, last_complete, last_used);
832 spin_unlock_bh(atchan->lock);
835 *done = last_complete;
843 * atc_issue_pending - try to finish work
844 * @chan: target DMA channel
846 static void atc_issue_pending(struct dma_chan *chan)
848 struct at_dma_chan *atchan = to_at_dma_chan(chan);
850 dev_vdbg(chan2dev(chan), "issue_pending\n");
852 if (!atc_chan_is_enabled(atchan)) {
853 spin_lock_bh(&atchan->lock);
854 atc_advance_work(atchan);
855 spin_unlock_bh(&atchan->lock);
860 * atc_alloc_chan_resources - allocate resources for DMA channel
861 * @chan: allocate descriptor resources for this channel
862 * @client: current client requesting the channel be ready for requests
864 * return - the number of allocated descriptors
866 static int atc_alloc_chan_resources(struct dma_chan *chan)
868 struct at_dma_chan *atchan = to_at_dma_chan(chan);
869 struct at_dma *atdma = to_at_dma(chan->device);
870 struct at_desc *desc;
871 struct at_dma_slave *atslave;
876 dev_vdbg(chan2dev(chan), "alloc_chan_resources\n");
878 /* ASSERT: channel is idle */
879 if (atc_chan_is_enabled(atchan)) {
880 dev_dbg(chan2dev(chan), "DMA channel not idle ?\n");
884 cfg = ATC_DEFAULT_CFG;
886 atslave = chan->private;
889 * We need controller-specific data to set up slave
892 BUG_ON(!atslave->dma_dev || atslave->dma_dev != atdma->dma_common.dev);
894 /* if cfg configuration specified take it instad of default */
899 /* have we already been set up?
900 * reconfigure channel but no need to reallocate descriptors */
901 if (!list_empty(&atchan->free_list))
902 return atchan->descs_allocated;
904 /* Allocate initial pool of descriptors */
905 for (i = 0; i < init_nr_desc_per_channel; i++) {
906 desc = atc_alloc_descriptor(chan, GFP_KERNEL);
908 dev_err(atdma->dma_common.dev,
909 "Only %d initial descriptors\n", i);
912 list_add_tail(&desc->desc_node, &tmp_list);
915 spin_lock_bh(&atchan->lock);
916 atchan->descs_allocated = i;
917 list_splice(&tmp_list, &atchan->free_list);
918 atchan->completed_cookie = chan->cookie = 1;
919 spin_unlock_bh(&atchan->lock);
921 /* channel parameters */
922 channel_writel(atchan, CFG, cfg);
924 dev_dbg(chan2dev(chan),
925 "alloc_chan_resources: allocated %d descriptors\n",
926 atchan->descs_allocated);
928 return atchan->descs_allocated;
932 * atc_free_chan_resources - free all channel resources
935 static void atc_free_chan_resources(struct dma_chan *chan)
937 struct at_dma_chan *atchan = to_at_dma_chan(chan);
938 struct at_dma *atdma = to_at_dma(chan->device);
939 struct at_desc *desc, *_desc;
942 dev_dbg(chan2dev(chan), "free_chan_resources: (descs allocated=%u)\n",
943 atchan->descs_allocated);
945 /* ASSERT: channel is idle */
946 BUG_ON(!list_empty(&atchan->active_list));
947 BUG_ON(!list_empty(&atchan->queue));
948 BUG_ON(atc_chan_is_enabled(atchan));
950 list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) {
951 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
952 list_del(&desc->desc_node);
953 /* free link descriptor */
954 dma_pool_free(atdma->dma_desc_pool, desc, desc->txd.phys);
956 list_splice_init(&atchan->free_list, &list);
957 atchan->descs_allocated = 0;
959 dev_vdbg(chan2dev(chan), "free_chan_resources: done\n");
963 /*-- Module Management -----------------------------------------------*/
966 * at_dma_off - disable DMA controller
967 * @atdma: the Atmel HDAMC device
969 static void at_dma_off(struct at_dma *atdma)
971 dma_writel(atdma, EN, 0);
973 /* disable all interrupts */
974 dma_writel(atdma, EBCIDR, -1L);
976 /* confirm that all channels are disabled */
977 while (dma_readl(atdma, CHSR) & atdma->all_chan_mask)
981 static int __init at_dma_probe(struct platform_device *pdev)
983 struct at_dma_platform_data *pdata;
985 struct at_dma *atdma;
991 /* get DMA Controller parameters from platform */
992 pdata = pdev->dev.platform_data;
993 if (!pdata || pdata->nr_channels > AT_DMA_MAX_NR_CHANNELS)
996 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1000 irq = platform_get_irq(pdev, 0);
1004 size = sizeof(struct at_dma);
1005 size += pdata->nr_channels * sizeof(struct at_dma_chan);
1006 atdma = kzalloc(size, GFP_KERNEL);
1010 /* discover transaction capabilites from the platform data */
1011 atdma->dma_common.cap_mask = pdata->cap_mask;
1012 atdma->all_chan_mask = (1 << pdata->nr_channels) - 1;
1014 size = io->end - io->start + 1;
1015 if (!request_mem_region(io->start, size, pdev->dev.driver->name)) {
1020 atdma->regs = ioremap(io->start, size);
1026 atdma->clk = clk_get(&pdev->dev, "dma_clk");
1027 if (IS_ERR(atdma->clk)) {
1028 err = PTR_ERR(atdma->clk);
1031 clk_enable(atdma->clk);
1033 /* force dma off, just in case */
1036 err = request_irq(irq, at_dma_interrupt, 0, "at_hdmac", atdma);
1040 platform_set_drvdata(pdev, atdma);
1042 /* create a pool of consistent memory blocks for hardware descriptors */
1043 atdma->dma_desc_pool = dma_pool_create("at_hdmac_desc_pool",
1044 &pdev->dev, sizeof(struct at_desc),
1045 4 /* word alignment */, 0);
1046 if (!atdma->dma_desc_pool) {
1047 dev_err(&pdev->dev, "No memory for descriptors dma pool\n");
1049 goto err_pool_create;
1052 /* clear any pending interrupt */
1053 while (dma_readl(atdma, EBCISR))
1056 /* initialize channels related values */
1057 INIT_LIST_HEAD(&atdma->dma_common.channels);
1058 for (i = 0; i < pdata->nr_channels; i++, atdma->dma_common.chancnt++) {
1059 struct at_dma_chan *atchan = &atdma->chan[i];
1061 atchan->chan_common.device = &atdma->dma_common;
1062 atchan->chan_common.cookie = atchan->completed_cookie = 1;
1063 atchan->chan_common.chan_id = i;
1064 list_add_tail(&atchan->chan_common.device_node,
1065 &atdma->dma_common.channels);
1067 atchan->ch_regs = atdma->regs + ch_regs(i);
1068 spin_lock_init(&atchan->lock);
1069 atchan->mask = 1 << i;
1071 INIT_LIST_HEAD(&atchan->active_list);
1072 INIT_LIST_HEAD(&atchan->queue);
1073 INIT_LIST_HEAD(&atchan->free_list);
1075 tasklet_init(&atchan->tasklet, atc_tasklet,
1076 (unsigned long)atchan);
1077 atc_enable_irq(atchan);
1080 /* set base routines */
1081 atdma->dma_common.device_alloc_chan_resources = atc_alloc_chan_resources;
1082 atdma->dma_common.device_free_chan_resources = atc_free_chan_resources;
1083 atdma->dma_common.device_is_tx_complete = atc_is_tx_complete;
1084 atdma->dma_common.device_issue_pending = atc_issue_pending;
1085 atdma->dma_common.dev = &pdev->dev;
1087 /* set prep routines based on capability */
1088 if (dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask))
1089 atdma->dma_common.device_prep_dma_memcpy = atc_prep_dma_memcpy;
1091 if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask)) {
1092 atdma->dma_common.device_prep_slave_sg = atc_prep_slave_sg;
1093 atdma->dma_common.device_terminate_all = atc_terminate_all;
1096 dma_writel(atdma, EN, AT_DMA_ENABLE);
1098 dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s), %d channels\n",
1099 dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask) ? "cpy " : "",
1100 dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ? "slave " : "",
1101 atdma->dma_common.chancnt);
1103 dma_async_device_register(&atdma->dma_common);
1108 platform_set_drvdata(pdev, NULL);
1109 free_irq(platform_get_irq(pdev, 0), atdma);
1111 clk_disable(atdma->clk);
1112 clk_put(atdma->clk);
1114 iounmap(atdma->regs);
1117 release_mem_region(io->start, size);
1123 static int __exit at_dma_remove(struct platform_device *pdev)
1125 struct at_dma *atdma = platform_get_drvdata(pdev);
1126 struct dma_chan *chan, *_chan;
1127 struct resource *io;
1130 dma_async_device_unregister(&atdma->dma_common);
1132 dma_pool_destroy(atdma->dma_desc_pool);
1133 platform_set_drvdata(pdev, NULL);
1134 free_irq(platform_get_irq(pdev, 0), atdma);
1136 list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
1138 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1140 /* Disable interrupts */
1141 atc_disable_irq(atchan);
1142 tasklet_disable(&atchan->tasklet);
1144 tasklet_kill(&atchan->tasklet);
1145 list_del(&chan->device_node);
1148 clk_disable(atdma->clk);
1149 clk_put(atdma->clk);
1151 iounmap(atdma->regs);
1154 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1155 release_mem_region(io->start, io->end - io->start + 1);
1162 static void at_dma_shutdown(struct platform_device *pdev)
1164 struct at_dma *atdma = platform_get_drvdata(pdev);
1166 at_dma_off(platform_get_drvdata(pdev));
1167 clk_disable(atdma->clk);
1170 static int at_dma_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1172 struct at_dma *atdma = platform_get_drvdata(pdev);
1174 at_dma_off(platform_get_drvdata(pdev));
1175 clk_disable(atdma->clk);
1179 static int at_dma_resume_early(struct platform_device *pdev)
1181 struct at_dma *atdma = platform_get_drvdata(pdev);
1183 clk_enable(atdma->clk);
1184 dma_writel(atdma, EN, AT_DMA_ENABLE);
1189 static struct platform_driver at_dma_driver = {
1190 .remove = __exit_p(at_dma_remove),
1191 .shutdown = at_dma_shutdown,
1192 .suspend_late = at_dma_suspend_late,
1193 .resume_early = at_dma_resume_early,
1199 static int __init at_dma_init(void)
1201 return platform_driver_probe(&at_dma_driver, at_dma_probe);
1203 module_init(at_dma_init);
1205 static void __exit at_dma_exit(void)
1207 platform_driver_unregister(&at_dma_driver);
1209 module_exit(at_dma_exit);
1211 MODULE_DESCRIPTION("Atmel AHB DMA Controller driver");
1212 MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>");
1213 MODULE_LICENSE("GPL");
1214 MODULE_ALIAS("platform:at_hdmac");