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   1 /*
   2  * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink Multiport
   5  * high speed multiprotocol serial adapter.
   6  *
   7  * written by Paul Fulghum for Microgate Corporation
   8  * paulkf@microgate.com
   9  *
  10  * Microgate and SyncLink are trademarks of Microgate Corporation
  11  *
  12  * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
  13  * This code is released under the GNU General Public License (GPL)
  14  *
  15  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  25  * OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29 #if defined(__i386__)
  30 #  define BREAKPOINT() asm("   int $3");
  31 #else
  32 #  define BREAKPOINT() { }
  33 #endif
  34
  35 #define MAX_DEVICES 12
  36
  37 #include <linux/module.h>
  38 #include <linux/errno.h>
  39 #include <linux/signal.h>
  40 #include <linux/sched.h>
  41 #include <linux/timer.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/pci.h>
  44 #include <linux/tty.h>
  45 #include <linux/tty_flip.h>
  46 #include <linux/serial.h>
  47 #include <linux/major.h>
  48 #include <linux/string.h>
  49 #include <linux/fcntl.h>
  50 #include <linux/ptrace.h>
  51 #include <linux/ioport.h>
  52 #include <linux/mm.h>
  53 #include <linux/slab.h>
  54 #include <linux/netdevice.h>
  55 #include <linux/vmalloc.h>
  56 #include <linux/init.h>
  57 #include <linux/delay.h>
  58 #include <linux/ioctl.h>
  59
  60 #include <asm/system.h>
  61 #include <asm/io.h>
  62 #include <asm/irq.h>
  63 #include <asm/dma.h>
  64 #include <linux/bitops.h>
  65 #include <asm/types.h>
  66 #include <linux/termios.h>
  67 #include <linux/workqueue.h>
  68 #include <linux/hdlc.h>
  69 #include <linux/synclink.h>
  70
  71 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
  72 #define SYNCLINK_GENERIC_HDLC 1
  73 #else
  74 #define SYNCLINK_GENERIC_HDLC 0
  75 #endif
  76
  77 #define GET_USER(error,value,addr) error = get_user(value,addr)
  78 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  79 #define PUT_USER(error,value,addr) error = put_user(value,addr)
  80 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  81
  82 #include <asm/uaccess.h>
  83
  84 static MGSL_PARAMS default_params = {
  85         MGSL_MODE_HDLC,                 /* unsigned long mode */
  86         0,                              /* unsigned char loopback; */
  87         HDLC_FLAG_UNDERRUN_ABORT15,     /* unsigned short flags; */
  88         HDLC_ENCODING_NRZI_SPACE,       /* unsigned char encoding; */
  89         0,                              /* unsigned long clock_speed; */
  90         0xff,                           /* unsigned char addr_filter; */
  91         HDLC_CRC_16_CCITT,              /* unsigned short crc_type; */
  92         HDLC_PREAMBLE_LENGTH_8BITS,     /* unsigned char preamble_length; */
  93         HDLC_PREAMBLE_PATTERN_NONE,     /* unsigned char preamble; */
  94         9600,                           /* unsigned long data_rate; */
  95         8,                              /* unsigned char data_bits; */
  96         1,                              /* unsigned char stop_bits; */
  97         ASYNC_PARITY_NONE               /* unsigned char parity; */
  98 };
  99
 100 /* size in bytes of DMA data buffers */
 101 #define SCABUFSIZE      1024
 102 #define SCA_MEM_SIZE    0x40000
 103 #define SCA_BASE_SIZE   512
 104 #define SCA_REG_SIZE    16
 105 #define SCA_MAX_PORTS   4
 106 #define SCAMAXDESC      128
 107
 108 #define BUFFERLISTSIZE  4096
 109
 110 /* SCA-I style DMA buffer descriptor */
 111 typedef struct _SCADESC
 112 {
 113         u16     next;           /* lower l6 bits of next descriptor addr */
 114         u16     buf_ptr;        /* lower 16 bits of buffer addr */
 115         u8      buf_base;       /* upper 8 bits of buffer addr */
 116         u8      pad1;
 117         u16     length;         /* length of buffer */
 118         u8      status;         /* status of buffer */
 119         u8      pad2;
 120 } SCADESC, *PSCADESC;
 121
 122 typedef struct _SCADESC_EX
 123 {
 124         /* device driver bookkeeping section */
 125         char    *virt_addr;     /* virtual address of data buffer */
 126         u16     phys_entry;     /* lower 16-bits of physical address of this descriptor */
 127 } SCADESC_EX, *PSCADESC_EX;
 128
 129 /* The queue of BH actions to be performed */
 130
 131 #define BH_RECEIVE  1
 132 #define BH_TRANSMIT 2
 133 #define BH_STATUS   4
 134
 135 #define IO_PIN_SHUTDOWN_LIMIT 100
 136
 137 struct  _input_signal_events {
 138         int     ri_up;
 139         int     ri_down;
 140         int     dsr_up;
 141         int     dsr_down;
 142         int     dcd_up;
 143         int     dcd_down;
 144         int     cts_up;
 145         int     cts_down;
 146 };
 147
 148 /*
 149  * Device instance data structure
 150  */
 151 typedef struct _synclinkmp_info {
 152         void *if_ptr;                           /* General purpose pointer (used by SPPP) */
 153         int                     magic;
 154         struct tty_port         port;
 155         int                     line;
 156         unsigned short          close_delay;
 157         unsigned short          closing_wait;   /* time to wait before closing */
 158
 159         struct mgsl_icount      icount;
 160
 161         int                     timeout;
 162         int                     x_char;         /* xon/xoff character */
 163         u16                     read_status_mask1;  /* break detection (SR1 indications) */
 164         u16                     read_status_mask2;  /* parity/framing/overun (SR2 indications) */
 165         unsigned char           ignore_status_mask1;  /* break detection (SR1 indications) */
 166         unsigned char           ignore_status_mask2;  /* parity/framing/overun (SR2 indications) */
 167         unsigned char           *tx_buf;
 168         int                     tx_put;
 169         int                     tx_get;
 170         int                     tx_count;
 171
 172         wait_queue_head_t       status_event_wait_q;
 173         wait_queue_head_t       event_wait_q;
 174         struct timer_list       tx_timer;       /* HDLC transmit timeout timer */
 175         struct _synclinkmp_info *next_device;   /* device list link */
 176         struct timer_list       status_timer;   /* input signal status check timer */
 177
 178         spinlock_t lock;                /* spinlock for synchronizing with ISR */
 179         struct work_struct task;                        /* task structure for scheduling bh */
 180
 181         u32 max_frame_size;                     /* as set by device config */
 182
 183         u32 pending_bh;
 184
 185         bool bh_running;                                /* Protection from multiple */
 186         int isr_overflow;
 187         bool bh_requested;
 188
 189         int dcd_chkcount;                       /* check counts to prevent */
 190         int cts_chkcount;                       /* too many IRQs if a signal */
 191         int dsr_chkcount;                       /* is floating */
 192         int ri_chkcount;
 193
 194         char *buffer_list;                      /* virtual address of Rx & Tx buffer lists */
 195         unsigned long buffer_list_phys;
 196
 197         unsigned int rx_buf_count;              /* count of total allocated Rx buffers */
 198         SCADESC *rx_buf_list;                   /* list of receive buffer entries */
 199         SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
 200         unsigned int current_rx_buf;
 201
 202         unsigned int tx_buf_count;              /* count of total allocated Tx buffers */
 203         SCADESC *tx_buf_list;           /* list of transmit buffer entries */
 204         SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
 205         unsigned int last_tx_buf;
 206
 207         unsigned char *tmp_rx_buf;
 208         unsigned int tmp_rx_buf_count;
 209
 210         bool rx_enabled;
 211         bool rx_overflow;
 212
 213         bool tx_enabled;
 214         bool tx_active;
 215         u32 idle_mode;
 216
 217         unsigned char ie0_value;
 218         unsigned char ie1_value;
 219         unsigned char ie2_value;
 220         unsigned char ctrlreg_value;
 221         unsigned char old_signals;
 222
 223         char device_name[25];                   /* device instance name */
 224
 225         int port_count;
 226         int adapter_num;
 227         int port_num;
 228
 229         struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
 230
 231         unsigned int bus_type;                  /* expansion bus type (ISA,EISA,PCI) */
 232
 233         unsigned int irq_level;                 /* interrupt level */
 234         unsigned long irq_flags;
 235         bool irq_requested;                     /* true if IRQ requested */
 236
 237         MGSL_PARAMS params;                     /* communications parameters */
 238
 239         unsigned char serial_signals;           /* current serial signal states */
 240
 241         bool irq_occurred;                      /* for diagnostics use */
 242         unsigned int init_error;                /* Initialization startup error */
 243
 244         u32 last_mem_alloc;
 245         unsigned char* memory_base;             /* shared memory address (PCI only) */
 246         u32 phys_memory_base;
 247         int shared_mem_requested;
 248
 249         unsigned char* sca_base;                /* HD64570 SCA Memory address */
 250         u32 phys_sca_base;
 251         u32 sca_offset;
 252         bool sca_base_requested;
 253
 254         unsigned char* lcr_base;                /* local config registers (PCI only) */
 255         u32 phys_lcr_base;
 256         u32 lcr_offset;
 257         int lcr_mem_requested;
 258
 259         unsigned char* statctrl_base;           /* status/control register memory */
 260         u32 phys_statctrl_base;
 261         u32 statctrl_offset;
 262         bool sca_statctrl_requested;
 263
 264         u32 misc_ctrl_value;
 265         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 266         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 267         bool drop_rts_on_tx_done;
 268
 269         struct  _input_signal_events    input_signal_events;
 270
 271         /* SPPP/Cisco HDLC device parts */
 272         int netcount;
 273         spinlock_t netlock;
 274
 275 #if SYNCLINK_GENERIC_HDLC
 276         struct net_device *netdev;
 277 #endif
 278
 279 } SLMP_INFO;
 280
 281 #define MGSL_MAGIC 0x5401
 282
 283 /*
 284  * define serial signal status change macros
 285  */
 286 #define MISCSTATUS_DCD_LATCHED  (SerialSignal_DCD<<8)   /* indicates change in DCD */
 287 #define MISCSTATUS_RI_LATCHED   (SerialSignal_RI<<8)    /* indicates change in RI */
 288 #define MISCSTATUS_CTS_LATCHED  (SerialSignal_CTS<<8)   /* indicates change in CTS */
 289 #define MISCSTATUS_DSR_LATCHED  (SerialSignal_DSR<<8)   /* change in DSR */
 290
 291 /* Common Register macros */
 292 #define LPR     0x00
 293 #define PABR0   0x02
 294 #define PABR1   0x03
 295 #define WCRL    0x04
 296 #define WCRM    0x05
 297 #define WCRH    0x06
 298 #define DPCR    0x08
 299 #define DMER    0x09
 300 #define ISR0    0x10
 301 #define ISR1    0x11
 302 #define ISR2    0x12
 303 #define IER0    0x14
 304 #define IER1    0x15
 305 #define IER2    0x16
 306 #define ITCR    0x18
 307 #define INTVR   0x1a
 308 #define IMVR    0x1c
 309
 310 /* MSCI Register macros */
 311 #define TRB     0x20
 312 #define TRBL    0x20
 313 #define TRBH    0x21
 314 #define SR0     0x22
 315 #define SR1     0x23
 316 #define SR2     0x24
 317 #define SR3     0x25
 318 #define FST     0x26
 319 #define IE0     0x28
 320 #define IE1     0x29
 321 #define IE2     0x2a
 322 #define FIE     0x2b
 323 #define CMD     0x2c
 324 #define MD0     0x2e
 325 #define MD1     0x2f
 326 #define MD2     0x30
 327 #define CTL     0x31
 328 #define SA0     0x32
 329 #define SA1     0x33
 330 #define IDL     0x34
 331 #define TMC     0x35
 332 #define RXS     0x36
 333 #define TXS     0x37
 334 #define TRC0    0x38
 335 #define TRC1    0x39
 336 #define RRC     0x3a
 337 #define CST0    0x3c
 338 #define CST1    0x3d
 339
 340 /* Timer Register Macros */
 341 #define TCNT    0x60
 342 #define TCNTL   0x60
 343 #define TCNTH   0x61
 344 #define TCONR   0x62
 345 #define TCONRL  0x62
 346 #define TCONRH  0x63
 347 #define TMCS    0x64
 348 #define TEPR    0x65
 349
 350 /* DMA Controller Register macros */
 351 #define DARL    0x80
 352 #define DARH    0x81
 353 #define DARB    0x82
 354 #define BAR     0x80
 355 #define BARL    0x80
 356 #define BARH    0x81
 357 #define BARB    0x82
 358 #define SAR     0x84
 359 #define SARL    0x84
 360 #define SARH    0x85
 361 #define SARB    0x86
 362 #define CPB     0x86
 363 #define CDA     0x88
 364 #define CDAL    0x88
 365 #define CDAH    0x89
 366 #define EDA     0x8a
 367 #define EDAL    0x8a
 368 #define EDAH    0x8b
 369 #define BFL     0x8c
 370 #define BFLL    0x8c
 371 #define BFLH    0x8d
 372 #define BCR     0x8e
 373 #define BCRL    0x8e
 374 #define BCRH    0x8f
 375 #define DSR     0x90
 376 #define DMR     0x91
 377 #define FCT     0x93
 378 #define DIR     0x94
 379 #define DCMD    0x95
 380
 381 /* combine with timer or DMA register address */
 382 #define TIMER0  0x00
 383 #define TIMER1  0x08
 384 #define TIMER2  0x10
 385 #define TIMER3  0x18
 386 #define RXDMA   0x00
 387 #define TXDMA   0x20
 388
 389 /* SCA Command Codes */
 390 #define NOOP            0x00
 391 #define TXRESET         0x01
 392 #define TXENABLE        0x02
 393 #define TXDISABLE       0x03
 394 #define TXCRCINIT       0x04
 395 #define TXCRCEXCL       0x05
 396 #define TXEOM           0x06
 397 #define TXABORT         0x07
 398 #define MPON            0x08
 399 #define TXBUFCLR        0x09
 400 #define RXRESET         0x11
 401 #define RXENABLE        0x12
 402 #define RXDISABLE       0x13
 403 #define RXCRCINIT       0x14
 404 #define RXREJECT        0x15
 405 #define SEARCHMP        0x16
 406 #define RXCRCEXCL       0x17
 407 #define RXCRCCALC       0x18
 408 #define CHRESET         0x21
 409 #define HUNT            0x31
 410
 411 /* DMA command codes */
 412 #define SWABORT         0x01
 413 #define FEICLEAR        0x02
 414
 415 /* IE0 */
 416 #define TXINTE          BIT7
 417 #define RXINTE          BIT6
 418 #define TXRDYE          BIT1
 419 #define RXRDYE          BIT0
 420
 421 /* IE1 & SR1 */
 422 #define UDRN    BIT7
 423 #define IDLE    BIT6
 424 #define SYNCD   BIT4
 425 #define FLGD    BIT4
 426 #define CCTS    BIT3
 427 #define CDCD    BIT2
 428 #define BRKD    BIT1
 429 #define ABTD    BIT1
 430 #define GAPD    BIT1
 431 #define BRKE    BIT0
 432 #define IDLD    BIT0
 433
 434 /* IE2 & SR2 */
 435 #define EOM     BIT7
 436 #define PMP     BIT6
 437 #define SHRT    BIT6
 438 #define PE      BIT5
 439 #define ABT     BIT5
 440 #define FRME    BIT4
 441 #define RBIT    BIT4
 442 #define OVRN    BIT3
 443 #define CRCE    BIT2
 444
 445
 446 /*
 447  * Global linked list of SyncLink devices
 448  */
 449 static SLMP_INFO *synclinkmp_device_list = NULL;
 450 static int synclinkmp_adapter_count = -1;
 451 static int synclinkmp_device_count = 0;
 452
 453 /*
 454  * Set this param to non-zero to load eax with the
 455  * .text section address and breakpoint on module load.
 456  * This is useful for use with gdb and add-symbol-file command.
 457  */
 458 static int break_on_load = 0;
 459
 460 /*
 461  * Driver major number, defaults to zero to get auto
 462  * assigned major number. May be forced as module parameter.
 463  */
 464 static int ttymajor = 0;
 465
 466 /*
 467  * Array of user specified options for ISA adapters.
 468  */
 469 static int debug_level = 0;
 470 static int maxframe[MAX_DEVICES] = {0,};
 471
 472 module_param(break_on_load, bool, 0);
 473 module_param(ttymajor, int, 0);
 474 module_param(debug_level, int, 0);
 475 module_param_array(maxframe, int, NULL, 0);
 476
 477 static char *driver_name = "SyncLink MultiPort driver";
 478 static char *driver_version = "$Revision: 4.38 $";
 479
 480 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 481 static void synclinkmp_remove_one(struct pci_dev *dev);
 482
 483 static struct pci_device_id synclinkmp_pci_tbl[] = {
 484         { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
 485         { 0, }, /* terminate list */
 486 };
 487 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
 488
 489 MODULE_LICENSE("GPL");
 490
 491 static struct pci_driver synclinkmp_pci_driver = {
 492         .name           = "synclinkmp",
 493         .id_table       = synclinkmp_pci_tbl,
 494         .probe          = synclinkmp_init_one,
 495         .remove         = __devexit_p(synclinkmp_remove_one),
 496 };
 497
 498
 499 static struct tty_driver *serial_driver;
 500
 501 /* number of characters left in xmit buffer before we ask for more */
 502 #define WAKEUP_CHARS 256
 503
 504
 505 /* tty callbacks */
 506
 507 static int  open(struct tty_struct *tty, struct file * filp);
 508 static void close(struct tty_struct *tty, struct file * filp);
 509 static void hangup(struct tty_struct *tty);
 510 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 511
 512 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 513 static int put_char(struct tty_struct *tty, unsigned char ch);
 514 static void send_xchar(struct tty_struct *tty, char ch);
 515 static void wait_until_sent(struct tty_struct *tty, int timeout);
 516 static int  write_room(struct tty_struct *tty);
 517 static void flush_chars(struct tty_struct *tty);
 518 static void flush_buffer(struct tty_struct *tty);
 519 static void tx_hold(struct tty_struct *tty);
 520 static void tx_release(struct tty_struct *tty);
 521
 522 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 523 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 524 static int  chars_in_buffer(struct tty_struct *tty);
 525 static void throttle(struct tty_struct * tty);
 526 static void unthrottle(struct tty_struct * tty);
 527 static int set_break(struct tty_struct *tty, int break_state);
 528
 529 #if SYNCLINK_GENERIC_HDLC
 530 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 531 static void hdlcdev_tx_done(SLMP_INFO *info);
 532 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
 533 static int  hdlcdev_init(SLMP_INFO *info);
 534 static void hdlcdev_exit(SLMP_INFO *info);
 535 #endif
 536
 537 /* ioctl handlers */
 538
 539 static int  get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
 540 static int  get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 541 static int  set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 542 static int  get_txidle(SLMP_INFO *info, int __user *idle_mode);
 543 static int  set_txidle(SLMP_INFO *info, int idle_mode);
 544 static int  tx_enable(SLMP_INFO *info, int enable);
 545 static int  tx_abort(SLMP_INFO *info);
 546 static int  rx_enable(SLMP_INFO *info, int enable);
 547 static int  modem_input_wait(SLMP_INFO *info,int arg);
 548 static int  wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
 549 static int  tiocmget(struct tty_struct *tty, struct file *file);
 550 static int  tiocmset(struct tty_struct *tty, struct file *file,
 551                      unsigned int set, unsigned int clear);
 552 static int  set_break(struct tty_struct *tty, int break_state);
 553
 554 static void add_device(SLMP_INFO *info);
 555 static void device_init(int adapter_num, struct pci_dev *pdev);
 556 static int  claim_resources(SLMP_INFO *info);
 557 static void release_resources(SLMP_INFO *info);
 558
 559 static int  startup(SLMP_INFO *info);
 560 static int  block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
 561 static int carrier_raised(struct tty_port *port);
 562 static void shutdown(SLMP_INFO *info);
 563 static void program_hw(SLMP_INFO *info);
 564 static void change_params(SLMP_INFO *info);
 565
 566 static bool init_adapter(SLMP_INFO *info);
 567 static bool register_test(SLMP_INFO *info);
 568 static bool irq_test(SLMP_INFO *info);
 569 static bool loopback_test(SLMP_INFO *info);
 570 static int  adapter_test(SLMP_INFO *info);
 571 static bool memory_test(SLMP_INFO *info);
 572
 573 static void reset_adapter(SLMP_INFO *info);
 574 static void reset_port(SLMP_INFO *info);
 575 static void async_mode(SLMP_INFO *info);
 576 static void hdlc_mode(SLMP_INFO *info);
 577
 578 static void rx_stop(SLMP_INFO *info);
 579 static void rx_start(SLMP_INFO *info);
 580 static void rx_reset_buffers(SLMP_INFO *info);
 581 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
 582 static bool rx_get_frame(SLMP_INFO *info);
 583
 584 static void tx_start(SLMP_INFO *info);
 585 static void tx_stop(SLMP_INFO *info);
 586 static void tx_load_fifo(SLMP_INFO *info);
 587 static void tx_set_idle(SLMP_INFO *info);
 588 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
 589
 590 static void get_signals(SLMP_INFO *info);
 591 static void set_signals(SLMP_INFO *info);
 592 static void enable_loopback(SLMP_INFO *info, int enable);
 593 static void set_rate(SLMP_INFO *info, u32 data_rate);
 594
 595 static int  bh_action(SLMP_INFO *info);
 596 static void bh_handler(struct work_struct *work);
 597 static void bh_receive(SLMP_INFO *info);
 598 static void bh_transmit(SLMP_INFO *info);
 599 static void bh_status(SLMP_INFO *info);
 600 static void isr_timer(SLMP_INFO *info);
 601 static void isr_rxint(SLMP_INFO *info);
 602 static void isr_rxrdy(SLMP_INFO *info);
 603 static void isr_txint(SLMP_INFO *info);
 604 static void isr_txrdy(SLMP_INFO *info);
 605 static void isr_rxdmaok(SLMP_INFO *info);
 606 static void isr_rxdmaerror(SLMP_INFO *info);
 607 static void isr_txdmaok(SLMP_INFO *info);
 608 static void isr_txdmaerror(SLMP_INFO *info);
 609 static void isr_io_pin(SLMP_INFO *info, u16 status);
 610
 611 static int  alloc_dma_bufs(SLMP_INFO *info);
 612 static void free_dma_bufs(SLMP_INFO *info);
 613 static int  alloc_buf_list(SLMP_INFO *info);
 614 static int  alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
 615 static int  alloc_tmp_rx_buf(SLMP_INFO *info);
 616 static void free_tmp_rx_buf(SLMP_INFO *info);
 617
 618 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
 619 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
 620 static void tx_timeout(unsigned long context);
 621 static void status_timeout(unsigned long context);
 622
 623 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
 624 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
 625 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
 626 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
 627 static unsigned char read_status_reg(SLMP_INFO * info);
 628 static void write_control_reg(SLMP_INFO * info);
 629
 630
 631 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
 632 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
 633 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
 634
 635 static u32 misc_ctrl_value = 0x007e4040;
 636 static u32 lcr1_brdr_value = 0x00800028;
 637
 638 static u32 read_ahead_count = 8;
 639
 640 /* DPCR, DMA Priority Control
 641  *
 642  * 07..05  Not used, must be 0
 643  * 04      BRC, bus release condition: 0=all transfers complete
 644  *              1=release after 1 xfer on all channels
 645  * 03      CCC, channel change condition: 0=every cycle
 646  *              1=after each channel completes all xfers
 647  * 02..00  PR<2..0>, priority 100=round robin
 648  *
 649  * 00000100 = 0x00
 650  */
 651 static unsigned char dma_priority = 0x04;
 652
 653 // Number of bytes that can be written to shared RAM
 654 // in a single write operation
 655 static u32 sca_pci_load_interval = 64;
 656
 657 /*
 658  * 1st function defined in .text section. Calling this function in
 659  * init_module() followed by a breakpoint allows a remote debugger
 660  * (gdb) to get the .text address for the add-symbol-file command.
 661  * This allows remote debugging of dynamically loadable modules.
 662  */
 663 static void* synclinkmp_get_text_ptr(void);
 664 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
 665
 666 static inline int sanity_check(SLMP_INFO *info,
 667                                char *name, const char *routine)
 668 {
 669 #ifdef SANITY_CHECK
 670         static const char *badmagic =
 671                 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
 672         static const char *badinfo =
 673                 "Warning: null synclinkmp_struct for (%s) in %s\n";
 674
 675         if (!info) {
 676                 printk(badinfo, name, routine);
 677                 return 1;
 678         }
 679         if (info->magic != MGSL_MAGIC) {
 680                 printk(badmagic, name, routine);
 681                 return 1;
 682         }
 683 #else
 684         if (!info)
 685                 return 1;
 686 #endif
 687         return 0;
 688 }
 689
 690 /**
 691  * line discipline callback wrappers
 692  *
 693  * The wrappers maintain line discipline references
 694  * while calling into the line discipline.
 695  *
 696  * ldisc_receive_buf  - pass receive data to line discipline
 697  */
 698
 699 static void ldisc_receive_buf(struct tty_struct *tty,
 700                               const __u8 *data, char *flags, int count)
 701 {
 702         struct tty_ldisc *ld;
 703         if (!tty)
 704                 return;
 705         ld = tty_ldisc_ref(tty);
 706         if (ld) {
 707                 if (ld->ops->receive_buf)
 708                         ld->ops->receive_buf(tty, data, flags, count);
 709                 tty_ldisc_deref(ld);
 710         }
 711 }
 712
 713 /* tty callbacks */
 714
 715 /* Called when a port is opened.  Init and enable port.
 716  */
 717 static int open(struct tty_struct *tty, struct file *filp)
 718 {
 719         SLMP_INFO *info;
 720         int retval, line;
 721         unsigned long flags;
 722
 723         line = tty->index;
 724         if ((line < 0) || (line >= synclinkmp_device_count)) {
 725                 printk("%s(%d): open with invalid line #%d.\n",
 726                         __FILE__,__LINE__,line);
 727                 return -ENODEV;
 728         }
 729
 730         info = synclinkmp_device_list;
 731         while(info && info->line != line)
 732                 info = info->next_device;
 733         if (sanity_check(info, tty->name, "open"))
 734                 return -ENODEV;
 735         if ( info->init_error ) {
 736                 printk("%s(%d):%s device is not allocated, init error=%d\n",
 737                         __FILE__,__LINE__,info->device_name,info->init_error);
 738                 return -ENODEV;
 739         }
 740
 741         tty->driver_data = info;
 742         info->port.tty = tty;
 743
 744         if (debug_level >= DEBUG_LEVEL_INFO)
 745                 printk("%s(%d):%s open(), old ref count = %d\n",
 746                          __FILE__,__LINE__,tty->driver->name, info->port.count);
 747
 748         /* If port is closing, signal caller to try again */
 749         if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
 750                 if (info->port.flags & ASYNC_CLOSING)
 751                         interruptible_sleep_on(&info->port.close_wait);
 752                 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
 753                         -EAGAIN : -ERESTARTSYS);
 754                 goto cleanup;
 755         }
 756
 757         info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 758
 759         spin_lock_irqsave(&info->netlock, flags);
 760         if (info->netcount) {
 761                 retval = -EBUSY;
 762                 spin_unlock_irqrestore(&info->netlock, flags);
 763                 goto cleanup;
 764         }
 765         info->port.count++;
 766         spin_unlock_irqrestore(&info->netlock, flags);
 767
 768         if (info->port.count == 1) {
 769                 /* 1st open on this device, init hardware */
 770                 retval = startup(info);
 771                 if (retval < 0)
 772                         goto cleanup;
 773         }
 774
 775         retval = block_til_ready(tty, filp, info);
 776         if (retval) {
 777                 if (debug_level >= DEBUG_LEVEL_INFO)
 778                         printk("%s(%d):%s block_til_ready() returned %d\n",
 779                                  __FILE__,__LINE__, info->device_name, retval);
 780                 goto cleanup;
 781         }
 782
 783         if (debug_level >= DEBUG_LEVEL_INFO)
 784                 printk("%s(%d):%s open() success\n",
 785                          __FILE__,__LINE__, info->device_name);
 786         retval = 0;
 787
 788 cleanup:
 789         if (retval) {
 790                 if (tty->count == 1)
 791                         info->port.tty = NULL; /* tty layer will release tty struct */
 792                 if(info->port.count)
 793                         info->port.count--;
 794         }
 795
 796         return retval;
 797 }
 798
 799 /* Called when port is closed. Wait for remaining data to be
 800  * sent. Disable port and free resources.
 801  */
 802 static void close(struct tty_struct *tty, struct file *filp)
 803 {
 804         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
 805
 806         if (sanity_check(info, tty->name, "close"))
 807                 return;
 808
 809         if (debug_level >= DEBUG_LEVEL_INFO)
 810                 printk("%s(%d):%s close() entry, count=%d\n",
 811                          __FILE__,__LINE__, info->device_name, info->port.count);
 812
 813         if (!info->port.count)
 814                 return;
 815
 816         if (tty_hung_up_p(filp))
 817                 goto cleanup;
 818
 819         if ((tty->count == 1) && (info->port.count != 1)) {
 820                 /*
 821                  * tty->count is 1 and the tty structure will be freed.
 822                  * info->port.count should be one in this case.
 823                  * if it's not, correct it so that the port is shutdown.
 824                  */
 825                 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
 826                        "info->port.count is %d\n",
 827                          __FILE__,__LINE__, info->device_name, info->port.count);
 828                 info->port.count = 1;
 829         }
 830
 831         info->port.count--;
 832
 833         /* if at least one open remaining, leave hardware active */
 834         if (info->port.count)
 835                 goto cleanup;
 836
 837         info->port.flags |= ASYNC_CLOSING;
 838
 839         /* set tty->closing to notify line discipline to
 840          * only process XON/XOFF characters. Only the N_TTY
 841          * discipline appears to use this (ppp does not).
 842          */
 843         tty->closing = 1;
 844
 845         /* wait for transmit data to clear all layers */
 846
 847         if (info->port.closing_wait != ASYNC_CLOSING_WAIT_NONE) {
 848                 if (debug_level >= DEBUG_LEVEL_INFO)
 849                         printk("%s(%d):%s close() calling tty_wait_until_sent\n",
 850                                  __FILE__,__LINE__, info->device_name );
 851                 tty_wait_until_sent(tty, info->port.closing_wait);
 852         }
 853
 854         if (info->port.flags & ASYNC_INITIALIZED)
 855                 wait_until_sent(tty, info->timeout);
 856
 857         flush_buffer(tty);
 858
 859         tty_ldisc_flush(tty);
 860
 861         shutdown(info);
 862
 863         tty->closing = 0;
 864         info->port.tty = NULL;
 865
 866         if (info->port.blocked_open) {
 867                 if (info->port.close_delay) {
 868                         msleep_interruptible(jiffies_to_msecs(info->port.close_delay));
 869                 }
 870                 wake_up_interruptible(&info->port.open_wait);
 871         }
 872
 873         info->port.flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
 874
 875         wake_up_interruptible(&info->port.close_wait);
 876
 877 cleanup:
 878         if (debug_level >= DEBUG_LEVEL_INFO)
 879                 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
 880                         tty->driver->name, info->port.count);
 881 }
 882
 883 /* Called by tty_hangup() when a hangup is signaled.
 884  * This is the same as closing all open descriptors for the port.
 885  */
 886 static void hangup(struct tty_struct *tty)
 887 {
 888         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 889
 890         if (debug_level >= DEBUG_LEVEL_INFO)
 891                 printk("%s(%d):%s hangup()\n",
 892                          __FILE__,__LINE__, info->device_name );
 893
 894         if (sanity_check(info, tty->name, "hangup"))
 895                 return;
 896
 897         flush_buffer(tty);
 898         shutdown(info);
 899
 900         info->port.count = 0;
 901         info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
 902         info->port.tty = NULL;
 903
 904         wake_up_interruptible(&info->port.open_wait);
 905 }
 906
 907 /* Set new termios settings
 908  */
 909 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 910 {
 911         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 912         unsigned long flags;
 913
 914         if (debug_level >= DEBUG_LEVEL_INFO)
 915                 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
 916                         tty->driver->name );
 917
 918         change_params(info);
 919
 920         /* Handle transition to B0 status */
 921         if (old_termios->c_cflag & CBAUD &&
 922             !(tty->termios->c_cflag & CBAUD)) {
 923                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 924                 spin_lock_irqsave(&info->lock,flags);
 925                 set_signals(info);
 926                 spin_unlock_irqrestore(&info->lock,flags);
 927         }
 928
 929         /* Handle transition away from B0 status */
 930         if (!(old_termios->c_cflag & CBAUD) &&
 931             tty->termios->c_cflag & CBAUD) {
 932                 info->serial_signals |= SerialSignal_DTR;
 933                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 934                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 935                         info->serial_signals |= SerialSignal_RTS;
 936                 }
 937                 spin_lock_irqsave(&info->lock,flags);
 938                 set_signals(info);
 939                 spin_unlock_irqrestore(&info->lock,flags);
 940         }
 941
 942         /* Handle turning off CRTSCTS */
 943         if (old_termios->c_cflag & CRTSCTS &&
 944             !(tty->termios->c_cflag & CRTSCTS)) {
 945                 tty->hw_stopped = 0;
 946                 tx_release(tty);
 947         }
 948 }
 949
 950 /* Send a block of data
 951  *
 952  * Arguments:
 953  *
 954  *      tty             pointer to tty information structure
 955  *      buf             pointer to buffer containing send data
 956  *      count           size of send data in bytes
 957  *
 958  * Return Value:        number of characters written
 959  */
 960 static int write(struct tty_struct *tty,
 961                  const unsigned char *buf, int count)
 962 {
 963         int     c, ret = 0;
 964         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 965         unsigned long flags;
 966
 967         if (debug_level >= DEBUG_LEVEL_INFO)
 968                 printk("%s(%d):%s write() count=%d\n",
 969                        __FILE__,__LINE__,info->device_name,count);
 970
 971         if (sanity_check(info, tty->name, "write"))
 972                 goto cleanup;
 973
 974         if (!info->tx_buf)
 975                 goto cleanup;
 976
 977         if (info->params.mode == MGSL_MODE_HDLC) {
 978                 if (count > info->max_frame_size) {
 979                         ret = -EIO;
 980                         goto cleanup;
 981                 }
 982                 if (info->tx_active)
 983                         goto cleanup;
 984                 if (info->tx_count) {
 985                         /* send accumulated data from send_char() calls */
 986                         /* as frame and wait before accepting more data. */
 987                         tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
 988                         goto start;
 989                 }
 990                 ret = info->tx_count = count;
 991                 tx_load_dma_buffer(info, buf, count);
 992                 goto start;
 993         }
 994
 995         for (;;) {
 996                 c = min_t(int, count,
 997                         min(info->max_frame_size - info->tx_count - 1,
 998                             info->max_frame_size - info->tx_put));
 999                 if (c <= 0)
1000                         break;
1001
1002                 memcpy(info->tx_buf + info->tx_put, buf, c);
1003
1004                 spin_lock_irqsave(&info->lock,flags);
1005                 info->tx_put += c;
1006                 if (info->tx_put >= info->max_frame_size)
1007                         info->tx_put -= info->max_frame_size;
1008                 info->tx_count += c;
1009                 spin_unlock_irqrestore(&info->lock,flags);
1010
1011                 buf += c;
1012                 count -= c;
1013                 ret += c;
1014         }
1015
1016         if (info->params.mode == MGSL_MODE_HDLC) {
1017                 if (count) {
1018                         ret = info->tx_count = 0;
1019                         goto cleanup;
1020                 }
1021                 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1022         }
1023 start:
1024         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1025                 spin_lock_irqsave(&info->lock,flags);
1026                 if (!info->tx_active)
1027                         tx_start(info);
1028                 spin_unlock_irqrestore(&info->lock,flags);
1029         }
1030
1031 cleanup:
1032         if (debug_level >= DEBUG_LEVEL_INFO)
1033                 printk( "%s(%d):%s write() returning=%d\n",
1034                         __FILE__,__LINE__,info->device_name,ret);
1035         return ret;
1036 }
1037
1038 /* Add a character to the transmit buffer.
1039  */
1040 static int put_char(struct tty_struct *tty, unsigned char ch)
1041 {
1042         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1043         unsigned long flags;
1044         int ret = 0;
1045
1046         if ( debug_level >= DEBUG_LEVEL_INFO ) {
1047                 printk( "%s(%d):%s put_char(%d)\n",
1048                         __FILE__,__LINE__,info->device_name,ch);
1049         }
1050
1051         if (sanity_check(info, tty->name, "put_char"))
1052                 return 0;
1053
1054         if (!info->tx_buf)
1055                 return 0;
1056
1057         spin_lock_irqsave(&info->lock,flags);
1058
1059         if ( (info->params.mode != MGSL_MODE_HDLC) ||
1060              !info->tx_active ) {
1061
1062                 if (info->tx_count < info->max_frame_size - 1) {
1063                         info->tx_buf[info->tx_put++] = ch;
1064                         if (info->tx_put >= info->max_frame_size)
1065                                 info->tx_put -= info->max_frame_size;
1066                         info->tx_count++;
1067                         ret = 1;
1068                 }
1069         }
1070
1071         spin_unlock_irqrestore(&info->lock,flags);
1072         return ret;
1073 }
1074
1075 /* Send a high-priority XON/XOFF character
1076  */
1077 static void send_xchar(struct tty_struct *tty, char ch)
1078 {
1079         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1080         unsigned long flags;
1081
1082         if (debug_level >= DEBUG_LEVEL_INFO)
1083                 printk("%s(%d):%s send_xchar(%d)\n",
1084                          __FILE__,__LINE__, info->device_name, ch );
1085
1086         if (sanity_check(info, tty->name, "send_xchar"))
1087                 return;
1088
1089         info->x_char = ch;
1090         if (ch) {
1091                 /* Make sure transmit interrupts are on */
1092                 spin_lock_irqsave(&info->lock,flags);
1093                 if (!info->tx_enabled)
1094                         tx_start(info);
1095                 spin_unlock_irqrestore(&info->lock,flags);
1096         }
1097 }
1098
1099 /* Wait until the transmitter is empty.
1100  */
1101 static void wait_until_sent(struct tty_struct *tty, int timeout)
1102 {
1103         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1104         unsigned long orig_jiffies, char_time;
1105
1106         if (!info )
1107                 return;
1108
1109         if (debug_level >= DEBUG_LEVEL_INFO)
1110                 printk("%s(%d):%s wait_until_sent() entry\n",
1111                          __FILE__,__LINE__, info->device_name );
1112
1113         if (sanity_check(info, tty->name, "wait_until_sent"))
1114                 return;
1115
1116         lock_kernel();
1117
1118         if (!(info->port.flags & ASYNC_INITIALIZED))
1119                 goto exit;
1120
1121         orig_jiffies = jiffies;
1122
1123         /* Set check interval to 1/5 of estimated time to
1124          * send a character, and make it at least 1. The check
1125          * interval should also be less than the timeout.
1126          * Note: use tight timings here to satisfy the NIST-PCTS.
1127          */
1128
1129         if ( info->params.data_rate ) {
1130                 char_time = info->timeout/(32 * 5);
1131                 if (!char_time)
1132                         char_time++;
1133         } else
1134                 char_time = 1;
1135
1136         if (timeout)
1137                 char_time = min_t(unsigned long, char_time, timeout);
1138
1139         if ( info->params.mode == MGSL_MODE_HDLC ) {
1140                 while (info->tx_active) {
1141                         msleep_interruptible(jiffies_to_msecs(char_time));
1142                         if (signal_pending(current))
1143                                 break;
1144                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1145                                 break;
1146                 }
1147         } else {
1148                 //TODO: determine if there is something similar to USC16C32
1149                 //      TXSTATUS_ALL_SENT status
1150                 while ( info->tx_active && info->tx_enabled) {
1151                         msleep_interruptible(jiffies_to_msecs(char_time));
1152                         if (signal_pending(current))
1153                                 break;
1154                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1155                                 break;
1156                 }
1157         }
1158
1159 exit:
1160         unlock_kernel();
1161         if (debug_level >= DEBUG_LEVEL_INFO)
1162                 printk("%s(%d):%s wait_until_sent() exit\n",
1163                          __FILE__,__LINE__, info->device_name );
1164 }
1165
1166 /* Return the count of free bytes in transmit buffer
1167  */
1168 static int write_room(struct tty_struct *tty)
1169 {
1170         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1171         int ret;
1172
1173         if (sanity_check(info, tty->name, "write_room"))
1174                 return 0;
1175
1176         lock_kernel();
1177         if (info->params.mode == MGSL_MODE_HDLC) {
1178                 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1179         } else {
1180                 ret = info->max_frame_size - info->tx_count - 1;
1181                 if (ret < 0)
1182                         ret = 0;
1183         }
1184         unlock_kernel();
1185
1186         if (debug_level >= DEBUG_LEVEL_INFO)
1187                 printk("%s(%d):%s write_room()=%d\n",
1188                        __FILE__, __LINE__, info->device_name, ret);
1189
1190         return ret;
1191 }
1192
1193 /* enable transmitter and send remaining buffered characters
1194  */
1195 static void flush_chars(struct tty_struct *tty)
1196 {
1197         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1198         unsigned long flags;
1199
1200         if ( debug_level >= DEBUG_LEVEL_INFO )
1201                 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1202                         __FILE__,__LINE__,info->device_name,info->tx_count);
1203
1204         if (sanity_check(info, tty->name, "flush_chars"))
1205                 return;
1206
1207         if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1208             !info->tx_buf)
1209                 return;
1210
1211         if ( debug_level >= DEBUG_LEVEL_INFO )
1212                 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1213                         __FILE__,__LINE__,info->device_name );
1214
1215         spin_lock_irqsave(&info->lock,flags);
1216
1217         if (!info->tx_active) {
1218                 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1219                         info->tx_count ) {
1220                         /* operating in synchronous (frame oriented) mode */
1221                         /* copy data from circular tx_buf to */
1222                         /* transmit DMA buffer. */
1223                         tx_load_dma_buffer(info,
1224                                  info->tx_buf,info->tx_count);
1225                 }
1226                 tx_start(info);
1227         }
1228
1229         spin_unlock_irqrestore(&info->lock,flags);
1230 }
1231
1232 /* Discard all data in the send buffer
1233  */
1234 static void flush_buffer(struct tty_struct *tty)
1235 {
1236         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1237         unsigned long flags;
1238
1239         if (debug_level >= DEBUG_LEVEL_INFO)
1240                 printk("%s(%d):%s flush_buffer() entry\n",
1241                          __FILE__,__LINE__, info->device_name );
1242
1243         if (sanity_check(info, tty->name, "flush_buffer"))
1244                 return;
1245
1246         spin_lock_irqsave(&info->lock,flags);
1247         info->tx_count = info->tx_put = info->tx_get = 0;
1248         del_timer(&info->tx_timer);
1249         spin_unlock_irqrestore(&info->lock,flags);
1250
1251         tty_wakeup(tty);
1252 }
1253
1254 /* throttle (stop) transmitter
1255  */
1256 static void tx_hold(struct tty_struct *tty)
1257 {
1258         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1259         unsigned long flags;
1260
1261         if (sanity_check(info, tty->name, "tx_hold"))
1262                 return;
1263
1264         if ( debug_level >= DEBUG_LEVEL_INFO )
1265                 printk("%s(%d):%s tx_hold()\n",
1266                         __FILE__,__LINE__,info->device_name);
1267
1268         spin_lock_irqsave(&info->lock,flags);
1269         if (info->tx_enabled)
1270                 tx_stop(info);
1271         spin_unlock_irqrestore(&info->lock,flags);
1272 }
1273
1274 /* release (start) transmitter
1275  */
1276 static void tx_release(struct tty_struct *tty)
1277 {
1278         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1279         unsigned long flags;
1280
1281         if (sanity_check(info, tty->name, "tx_release"))
1282                 return;
1283
1284         if ( debug_level >= DEBUG_LEVEL_INFO )
1285                 printk("%s(%d):%s tx_release()\n",
1286                         __FILE__,__LINE__,info->device_name);
1287
1288         spin_lock_irqsave(&info->lock,flags);
1289         if (!info->tx_enabled)
1290                 tx_start(info);
1291         spin_unlock_irqrestore(&info->lock,flags);
1292 }
1293
1294 /* Service an IOCTL request
1295  *
1296  * Arguments:
1297  *
1298  *      tty     pointer to tty instance data
1299  *      file    pointer to associated file object for device
1300  *      cmd     IOCTL command code
1301  *      arg     command argument/context
1302  *
1303  * Return Value:        0 if success, otherwise error code
1304  */
1305 static int do_ioctl(struct tty_struct *tty, struct file *file,
1306                  unsigned int cmd, unsigned long arg)
1307 {
1308         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1309         int error;
1310         struct mgsl_icount cnow;        /* kernel counter temps */
1311         struct serial_icounter_struct __user *p_cuser;  /* user space */
1312         unsigned long flags;
1313         void __user *argp = (void __user *)arg;
1314
1315         if (debug_level >= DEBUG_LEVEL_INFO)
1316                 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1317                         info->device_name, cmd );
1318
1319         if (sanity_check(info, tty->name, "ioctl"))
1320                 return -ENODEV;
1321
1322         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1323             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1324                 if (tty->flags & (1 << TTY_IO_ERROR))
1325                     return -EIO;
1326         }
1327
1328         switch (cmd) {
1329         case MGSL_IOCGPARAMS:
1330                 return get_params(info, argp);
1331         case MGSL_IOCSPARAMS:
1332                 return set_params(info, argp);
1333         case MGSL_IOCGTXIDLE:
1334                 return get_txidle(info, argp);
1335         case MGSL_IOCSTXIDLE:
1336                 return set_txidle(info, (int)arg);
1337         case MGSL_IOCTXENABLE:
1338                 return tx_enable(info, (int)arg);
1339         case MGSL_IOCRXENABLE:
1340                 return rx_enable(info, (int)arg);
1341         case MGSL_IOCTXABORT:
1342                 return tx_abort(info);
1343         case MGSL_IOCGSTATS:
1344                 return get_stats(info, argp);
1345         case MGSL_IOCWAITEVENT:
1346                 return wait_mgsl_event(info, argp);
1347         case MGSL_IOCLOOPTXDONE:
1348                 return 0; // TODO: Not supported, need to document
1349                 /* Wait for modem input (DCD,RI,DSR,CTS) change
1350                  * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1351                  */
1352         case TIOCMIWAIT:
1353                 return modem_input_wait(info,(int)arg);
1354
1355                 /*
1356                  * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1357                  * Return: write counters to the user passed counter struct
1358                  * NB: both 1->0 and 0->1 transitions are counted except for
1359                  *     RI where only 0->1 is counted.
1360                  */
1361         case TIOCGICOUNT:
1362                 spin_lock_irqsave(&info->lock,flags);
1363                 cnow = info->icount;
1364                 spin_unlock_irqrestore(&info->lock,flags);
1365                 p_cuser = argp;
1366                 PUT_USER(error,cnow.cts, &p_cuser->cts);
1367                 if (error) return error;
1368                 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1369                 if (error) return error;
1370                 PUT_USER(error,cnow.rng, &p_cuser->rng);
1371                 if (error) return error;
1372                 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1373                 if (error) return error;
1374                 PUT_USER(error,cnow.rx, &p_cuser->rx);
1375                 if (error) return error;
1376                 PUT_USER(error,cnow.tx, &p_cuser->tx);
1377                 if (error) return error;
1378                 PUT_USER(error,cnow.frame, &p_cuser->frame);
1379                 if (error) return error;
1380                 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1381                 if (error) return error;
1382                 PUT_USER(error,cnow.parity, &p_cuser->parity);
1383                 if (error) return error;
1384                 PUT_USER(error,cnow.brk, &p_cuser->brk);
1385                 if (error) return error;
1386                 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1387                 if (error) return error;
1388                 return 0;
1389         default:
1390                 return -ENOIOCTLCMD;
1391         }
1392         return 0;
1393 }
1394
1395 static int ioctl(struct tty_struct *tty, struct file *file,
1396                  unsigned int cmd, unsigned long arg)
1397 {
1398         int ret;
1399         lock_kernel();
1400         ret = do_ioctl(tty, file, cmd, arg);
1401         unlock_kernel();
1402         return ret;
1403 }
1404
1405 /*
1406  * /proc fs routines....
1407  */
1408
1409 static inline int line_info(char *buf, SLMP_INFO *info)
1410 {
1411         char    stat_buf[30];
1412         int     ret;
1413         unsigned long flags;
1414
1415         ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1416                        "\tIRQ=%d MaxFrameSize=%u\n",
1417                 info->device_name,
1418                 info->phys_sca_base,
1419                 info->phys_memory_base,
1420                 info->phys_statctrl_base,
1421                 info->phys_lcr_base,
1422                 info->irq_level,
1423                 info->max_frame_size );
1424
1425         /* output current serial signal states */
1426         spin_lock_irqsave(&info->lock,flags);
1427         get_signals(info);
1428         spin_unlock_irqrestore(&info->lock,flags);
1429
1430         stat_buf[0] = 0;
1431         stat_buf[1] = 0;
1432         if (info->serial_signals & SerialSignal_RTS)
1433                 strcat(stat_buf, "|RTS");
1434         if (info->serial_signals & SerialSignal_CTS)
1435                 strcat(stat_buf, "|CTS");
1436         if (info->serial_signals & SerialSignal_DTR)
1437                 strcat(stat_buf, "|DTR");
1438         if (info->serial_signals & SerialSignal_DSR)
1439                 strcat(stat_buf, "|DSR");
1440         if (info->serial_signals & SerialSignal_DCD)
1441                 strcat(stat_buf, "|CD");
1442         if (info->serial_signals & SerialSignal_RI)
1443                 strcat(stat_buf, "|RI");
1444
1445         if (info->params.mode == MGSL_MODE_HDLC) {
1446                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1447                               info->icount.txok, info->icount.rxok);
1448                 if (info->icount.txunder)
1449                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1450                 if (info->icount.txabort)
1451                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1452                 if (info->icount.rxshort)
1453                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1454                 if (info->icount.rxlong)
1455                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1456                 if (info->icount.rxover)
1457                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1458                 if (info->icount.rxcrc)
1459                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
1460         } else {
1461                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1462                               info->icount.tx, info->icount.rx);
1463                 if (info->icount.frame)
1464                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1465                 if (info->icount.parity)
1466                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1467                 if (info->icount.brk)
1468                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1469                 if (info->icount.overrun)
1470                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1471         }
1472
1473         /* Append serial signal status to end */
1474         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1475
1476         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1477          info->tx_active,info->bh_requested,info->bh_running,
1478          info->pending_bh);
1479
1480         return ret;
1481 }
1482
1483 /* Called to print information about devices
1484  */
1485 static int read_proc(char *page, char **start, off_t off, int count,
1486               int *eof, void *data)
1487 {
1488         int len = 0, l;
1489         off_t   begin = 0;
1490         SLMP_INFO *info;
1491
1492         len += sprintf(page, "synclinkmp driver:%s\n", driver_version);
1493
1494         info = synclinkmp_device_list;
1495         while( info ) {
1496                 l = line_info(page + len, info);
1497                 len += l;
1498                 if (len+begin > off+count)
1499                         goto done;
1500                 if (len+begin < off) {
1501                         begin += len;
1502                         len = 0;
1503                 }
1504                 info = info->next_device;
1505         }
1506
1507         *eof = 1;
1508 done:
1509         if (off >= len+begin)
1510                 return 0;
1511         *start = page + (off-begin);
1512         return ((count < begin+len-off) ? count : begin+len-off);
1513 }
1514
1515 /* Return the count of bytes in transmit buffer
1516  */
1517 static int chars_in_buffer(struct tty_struct *tty)
1518 {
1519         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1520
1521         if (sanity_check(info, tty->name, "chars_in_buffer"))
1522                 return 0;
1523
1524         if (debug_level >= DEBUG_LEVEL_INFO)
1525                 printk("%s(%d):%s chars_in_buffer()=%d\n",
1526                        __FILE__, __LINE__, info->device_name, info->tx_count);
1527
1528         return info->tx_count;
1529 }
1530
1531 /* Signal remote device to throttle send data (our receive data)
1532  */
1533 static void throttle(struct tty_struct * tty)
1534 {
1535         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1536         unsigned long flags;
1537
1538         if (debug_level >= DEBUG_LEVEL_INFO)
1539                 printk("%s(%d):%s throttle() entry\n",
1540                          __FILE__,__LINE__, info->device_name );
1541
1542         if (sanity_check(info, tty->name, "throttle"))
1543                 return;
1544
1545         if (I_IXOFF(tty))
1546                 send_xchar(tty, STOP_CHAR(tty));
1547
1548         if (tty->termios->c_cflag & CRTSCTS) {
1549                 spin_lock_irqsave(&info->lock,flags);
1550                 info->serial_signals &= ~SerialSignal_RTS;
1551                 set_signals(info);
1552                 spin_unlock_irqrestore(&info->lock,flags);
1553         }
1554 }
1555
1556 /* Signal remote device to stop throttling send data (our receive data)
1557  */
1558 static void unthrottle(struct tty_struct * tty)
1559 {
1560         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1561         unsigned long flags;
1562
1563         if (debug_level >= DEBUG_LEVEL_INFO)
1564                 printk("%s(%d):%s unthrottle() entry\n",
1565                          __FILE__,__LINE__, info->device_name );
1566
1567         if (sanity_check(info, tty->name, "unthrottle"))
1568                 return;
1569
1570         if (I_IXOFF(tty)) {
1571                 if (info->x_char)
1572                         info->x_char = 0;
1573                 else
1574                         send_xchar(tty, START_CHAR(tty));
1575         }
1576
1577         if (tty->termios->c_cflag & CRTSCTS) {
1578                 spin_lock_irqsave(&info->lock,flags);
1579                 info->serial_signals |= SerialSignal_RTS;
1580                 set_signals(info);
1581                 spin_unlock_irqrestore(&info->lock,flags);
1582         }
1583 }
1584
1585 /* set or clear transmit break condition
1586  * break_state  -1=set break condition, 0=clear
1587  */
1588 static int set_break(struct tty_struct *tty, int break_state)
1589 {
1590         unsigned char RegValue;
1591         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1592         unsigned long flags;
1593
1594         if (debug_level >= DEBUG_LEVEL_INFO)
1595                 printk("%s(%d):%s set_break(%d)\n",
1596                          __FILE__,__LINE__, info->device_name, break_state);
1597
1598         if (sanity_check(info, tty->name, "set_break"))
1599                 return -EINVAL;
1600
1601         spin_lock_irqsave(&info->lock,flags);
1602         RegValue = read_reg(info, CTL);
1603         if (break_state == -1)
1604                 RegValue |= BIT3;
1605         else
1606                 RegValue &= ~BIT3;
1607         write_reg(info, CTL, RegValue);
1608         spin_unlock_irqrestore(&info->lock,flags);
1609         return 0;
1610 }
1611
1612 #if SYNCLINK_GENERIC_HDLC
1613
1614 /**
1615  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1616  * set encoding and frame check sequence (FCS) options
1617  *
1618  * dev       pointer to network device structure
1619  * encoding  serial encoding setting
1620  * parity    FCS setting
1621  *
1622  * returns 0 if success, otherwise error code
1623  */
1624 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1625                           unsigned short parity)
1626 {
1627         SLMP_INFO *info = dev_to_port(dev);
1628         unsigned char  new_encoding;
1629         unsigned short new_crctype;
1630
1631         /* return error if TTY interface open */
1632         if (info->port.count)
1633                 return -EBUSY;
1634
1635         switch (encoding)
1636         {
1637         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1638         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1639         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1640         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1641         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1642         default: return -EINVAL;
1643         }
1644
1645         switch (parity)
1646         {
1647         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1648         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1649         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1650         default: return -EINVAL;
1651         }
1652
1653         info->params.encoding = new_encoding;
1654         info->params.crc_type = new_crctype;
1655
1656         /* if network interface up, reprogram hardware */
1657         if (info->netcount)
1658                 program_hw(info);
1659
1660         return 0;
1661 }
1662
1663 /**
1664  * called by generic HDLC layer to send frame
1665  *
1666  * skb  socket buffer containing HDLC frame
1667  * dev  pointer to network device structure
1668  *
1669  * returns 0 if success, otherwise error code
1670  */
1671 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1672 {
1673         SLMP_INFO *info = dev_to_port(dev);
1674         unsigned long flags;
1675
1676         if (debug_level >= DEBUG_LEVEL_INFO)
1677                 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1678
1679         /* stop sending until this frame completes */
1680         netif_stop_queue(dev);
1681
1682         /* copy data to device buffers */
1683         info->tx_count = skb->len;
1684         tx_load_dma_buffer(info, skb->data, skb->len);
1685
1686         /* update network statistics */
1687         dev->stats.tx_packets++;
1688         dev->stats.tx_bytes += skb->len;
1689
1690         /* done with socket buffer, so free it */
1691         dev_kfree_skb(skb);
1692
1693         /* save start time for transmit timeout detection */
1694         dev->trans_start = jiffies;
1695
1696         /* start hardware transmitter if necessary */
1697         spin_lock_irqsave(&info->lock,flags);
1698         if (!info->tx_active)
1699                 tx_start(info);
1700         spin_unlock_irqrestore(&info->lock,flags);
1701
1702         return 0;
1703 }
1704
1705 /**
1706  * called by network layer when interface enabled
1707  * claim resources and initialize hardware
1708  *
1709  * dev  pointer to network device structure
1710  *
1711  * returns 0 if success, otherwise error code
1712  */
1713 static int hdlcdev_open(struct net_device *dev)
1714 {
1715         SLMP_INFO *info = dev_to_port(dev);
1716         int rc;
1717         unsigned long flags;
1718
1719         if (debug_level >= DEBUG_LEVEL_INFO)
1720                 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1721
1722         /* generic HDLC layer open processing */
1723         if ((rc = hdlc_open(dev)))
1724                 return rc;
1725
1726         /* arbitrate between network and tty opens */
1727         spin_lock_irqsave(&info->netlock, flags);
1728         if (info->port.count != 0 || info->netcount != 0) {
1729                 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1730                 spin_unlock_irqrestore(&info->netlock, flags);
1731                 return -EBUSY;
1732         }
1733         info->netcount=1;
1734         spin_unlock_irqrestore(&info->netlock, flags);
1735
1736         /* claim resources and init adapter */
1737         if ((rc = startup(info)) != 0) {
1738                 spin_lock_irqsave(&info->netlock, flags);
1739                 info->netcount=0;
1740                 spin_unlock_irqrestore(&info->netlock, flags);
1741                 return rc;
1742         }
1743
1744         /* assert DTR and RTS, apply hardware settings */
1745         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1746         program_hw(info);
1747
1748         /* enable network layer transmit */
1749         dev->trans_start = jiffies;
1750         netif_start_queue(dev);
1751
1752         /* inform generic HDLC layer of current DCD status */
1753         spin_lock_irqsave(&info->lock, flags);
1754         get_signals(info);
1755         spin_unlock_irqrestore(&info->lock, flags);
1756         if (info->serial_signals & SerialSignal_DCD)
1757                 netif_carrier_on(dev);
1758         else
1759                 netif_carrier_off(dev);
1760         return 0;
1761 }
1762
1763 /**
1764  * called by network layer when interface is disabled
1765  * shutdown hardware and release resources
1766  *
1767  * dev  pointer to network device structure
1768  *
1769  * returns 0 if success, otherwise error code
1770  */
1771 static int hdlcdev_close(struct net_device *dev)
1772 {
1773         SLMP_INFO *info = dev_to_port(dev);
1774         unsigned long flags;
1775
1776         if (debug_level >= DEBUG_LEVEL_INFO)
1777                 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1778
1779         netif_stop_queue(dev);
1780
1781         /* shutdown adapter and release resources */
1782         shutdown(info);
1783
1784         hdlc_close(dev);
1785
1786         spin_lock_irqsave(&info->netlock, flags);
1787         info->netcount=0;
1788         spin_unlock_irqrestore(&info->netlock, flags);
1789
1790         return 0;
1791 }
1792
1793 /**
1794  * called by network layer to process IOCTL call to network device
1795  *
1796  * dev  pointer to network device structure
1797  * ifr  pointer to network interface request structure
1798  * cmd  IOCTL command code
1799  *
1800  * returns 0 if success, otherwise error code
1801  */
1802 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1803 {
1804         const size_t size = sizeof(sync_serial_settings);
1805         sync_serial_settings new_line;
1806         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1807         SLMP_INFO *info = dev_to_port(dev);
1808         unsigned int flags;
1809
1810         if (debug_level >= DEBUG_LEVEL_INFO)
1811                 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1812
1813         /* return error if TTY interface open */
1814         if (info->port.count)
1815                 return -EBUSY;
1816
1817         if (cmd != SIOCWANDEV)
1818                 return hdlc_ioctl(dev, ifr, cmd);
1819
1820         switch(ifr->ifr_settings.type) {
1821         case IF_GET_IFACE: /* return current sync_serial_settings */
1822
1823                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1824                 if (ifr->ifr_settings.size < size) {
1825                         ifr->ifr_settings.size = size; /* data size wanted */
1826                         return -ENOBUFS;
1827                 }
1828
1829                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1830                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1831                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1832                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1833
1834                 switch (flags){
1835                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1836                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1837                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1838                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1839                 default: new_line.clock_type = CLOCK_DEFAULT;
1840                 }
1841
1842                 new_line.clock_rate = info->params.clock_speed;
1843                 new_line.loopback   = info->params.loopback ? 1:0;
1844
1845                 if (copy_to_user(line, &new_line, size))
1846                         return -EFAULT;
1847                 return 0;
1848
1849         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1850
1851                 if(!capable(CAP_NET_ADMIN))
1852                         return -EPERM;
1853                 if (copy_from_user(&new_line, line, size))
1854                         return -EFAULT;
1855
1856                 switch (new_line.clock_type)
1857                 {
1858                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1859                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1860                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1861                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1862                 case CLOCK_DEFAULT:  flags = info->params.flags &
1863                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1864                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1865                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1866                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1867                 default: return -EINVAL;
1868                 }
1869
1870                 if (new_line.loopback != 0 && new_line.loopback != 1)
1871                         return -EINVAL;
1872
1873                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1874                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1875                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1876                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1877                 info->params.flags |= flags;
1878
1879                 info->params.loopback = new_line.loopback;
1880
1881                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1882                         info->params.clock_speed = new_line.clock_rate;
1883                 else
1884                         info->params.clock_speed = 0;
1885
1886                 /* if network interface up, reprogram hardware */
1887                 if (info->netcount)
1888                         program_hw(info);
1889                 return 0;
1890
1891         default:
1892                 return hdlc_ioctl(dev, ifr, cmd);
1893         }
1894 }
1895
1896 /**
1897  * called by network layer when transmit timeout is detected
1898  *
1899  * dev  pointer to network device structure
1900  */
1901 static void hdlcdev_tx_timeout(struct net_device *dev)
1902 {
1903         SLMP_INFO *info = dev_to_port(dev);
1904         unsigned long flags;
1905
1906         if (debug_level >= DEBUG_LEVEL_INFO)
1907                 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1908
1909         dev->stats.tx_errors++;
1910         dev->stats.tx_aborted_errors++;
1911
1912         spin_lock_irqsave(&info->lock,flags);
1913         tx_stop(info);
1914         spin_unlock_irqrestore(&info->lock,flags);
1915
1916         netif_wake_queue(dev);
1917 }
1918
1919 /**
1920  * called by device driver when transmit completes
1921  * reenable network layer transmit if stopped
1922  *
1923  * info  pointer to device instance information
1924  */
1925 static void hdlcdev_tx_done(SLMP_INFO *info)
1926 {
1927         if (netif_queue_stopped(info->netdev))
1928                 netif_wake_queue(info->netdev);
1929 }
1930
1931 /**
1932  * called by device driver when frame received
1933  * pass frame to network layer
1934  *
1935  * info  pointer to device instance information
1936  * buf   pointer to buffer contianing frame data
1937  * size  count of data bytes in buf
1938  */
1939 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1940 {
1941         struct sk_buff *skb = dev_alloc_skb(size);
1942         struct net_device *dev = info->netdev;
1943
1944         if (debug_level >= DEBUG_LEVEL_INFO)
1945                 printk("hdlcdev_rx(%s)\n",dev->name);
1946
1947         if (skb == NULL) {
1948                 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1949                        dev->name);
1950                 dev->stats.rx_dropped++;
1951                 return;
1952         }
1953
1954         memcpy(skb_put(skb, size), buf, size);
1955
1956         skb->protocol = hdlc_type_trans(skb, dev);
1957
1958         dev->stats.rx_packets++;
1959         dev->stats.rx_bytes += size;
1960
1961         netif_rx(skb);
1962
1963         dev->last_rx = jiffies;
1964 }
1965
1966 /**
1967  * called by device driver when adding device instance
1968  * do generic HDLC initialization
1969  *
1970  * info  pointer to device instance information
1971  *
1972  * returns 0 if success, otherwise error code
1973  */
1974 static int hdlcdev_init(SLMP_INFO *info)
1975 {
1976         int rc;
1977         struct net_device *dev;
1978         hdlc_device *hdlc;
1979
1980         /* allocate and initialize network and HDLC layer objects */
1981
1982         if (!(dev = alloc_hdlcdev(info))) {
1983                 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1984                 return -ENOMEM;
1985         }
1986
1987         /* for network layer reporting purposes only */
1988         dev->mem_start = info->phys_sca_base;
1989         dev->mem_end   = info->phys_sca_base + SCA_BASE_SIZE - 1;
1990         dev->irq       = info->irq_level;
1991
1992         /* network layer callbacks and settings */
1993         dev->do_ioctl       = hdlcdev_ioctl;
1994         dev->open           = hdlcdev_open;
1995         dev->stop           = hdlcdev_close;
1996         dev->tx_timeout     = hdlcdev_tx_timeout;
1997         dev->watchdog_timeo = 10*HZ;
1998         dev->tx_queue_len   = 50;
1999
2000         /* generic HDLC layer callbacks and settings */
2001         hdlc         = dev_to_hdlc(dev);
2002         hdlc->attach = hdlcdev_attach;
2003         hdlc->xmit   = hdlcdev_xmit;
2004
2005         /* register objects with HDLC layer */
2006         if ((rc = register_hdlc_device(dev))) {
2007                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
2008                 free_netdev(dev);
2009                 return rc;
2010         }
2011
2012         info->netdev = dev;
2013         return 0;
2014 }
2015
2016 /**
2017  * called by device driver when removing device instance
2018  * do generic HDLC cleanup
2019  *
2020  * info  pointer to device instance information
2021  */
2022 static void hdlcdev_exit(SLMP_INFO *info)
2023 {
2024         unregister_hdlc_device(info->netdev);
2025         free_netdev(info->netdev);
2026         info->netdev = NULL;
2027 }
2028
2029 #endif /* CONFIG_HDLC */
2030
2031
2032 /* Return next bottom half action to perform.
2033  * Return Value:        BH action code or 0 if nothing to do.
2034  */
2035 static int bh_action(SLMP_INFO *info)
2036 {
2037         unsigned long flags;
2038         int rc = 0;
2039
2040         spin_lock_irqsave(&info->lock,flags);
2041
2042         if (info->pending_bh & BH_RECEIVE) {
2043                 info->pending_bh &= ~BH_RECEIVE;
2044                 rc = BH_RECEIVE;
2045         } else if (info->pending_bh & BH_TRANSMIT) {
2046                 info->pending_bh &= ~BH_TRANSMIT;
2047                 rc = BH_TRANSMIT;
2048         } else if (info->pending_bh & BH_STATUS) {
2049                 info->pending_bh &= ~BH_STATUS;
2050                 rc = BH_STATUS;
2051         }
2052
2053         if (!rc) {
2054                 /* Mark BH routine as complete */
2055                 info->bh_running = false;
2056                 info->bh_requested = false;
2057         }
2058
2059         spin_unlock_irqrestore(&info->lock,flags);
2060
2061         return rc;
2062 }
2063
2064 /* Perform bottom half processing of work items queued by ISR.
2065  */
2066 static void bh_handler(struct work_struct *work)
2067 {
2068         SLMP_INFO *info = container_of(work, SLMP_INFO, task);
2069         int action;
2070
2071         if (!info)
2072                 return;
2073
2074         if ( debug_level >= DEBUG_LEVEL_BH )
2075                 printk( "%s(%d):%s bh_handler() entry\n",
2076                         __FILE__,__LINE__,info->device_name);
2077
2078         info->bh_running = true;
2079
2080         while((action = bh_action(info)) != 0) {
2081
2082                 /* Process work item */
2083                 if ( debug_level >= DEBUG_LEVEL_BH )
2084                         printk( "%s(%d):%s bh_handler() work item action=%d\n",
2085                                 __FILE__,__LINE__,info->device_name, action);
2086
2087                 switch (action) {
2088
2089                 case BH_RECEIVE:
2090                         bh_receive(info);
2091                         break;
2092                 case BH_TRANSMIT:
2093                         bh_transmit(info);
2094                         break;
2095                 case BH_STATUS:
2096                         bh_status(info);
2097                         break;
2098                 default:
2099                         /* unknown work item ID */
2100                         printk("%s(%d):%s Unknown work item ID=%08X!\n",
2101                                 __FILE__,__LINE__,info->device_name,action);
2102                         break;
2103                 }
2104         }
2105
2106         if ( debug_level >= DEBUG_LEVEL_BH )
2107                 printk( "%s(%d):%s bh_handler() exit\n",
2108                         __FILE__,__LINE__,info->device_name);
2109 }
2110
2111 static void bh_receive(SLMP_INFO *info)
2112 {
2113         if ( debug_level >= DEBUG_LEVEL_BH )
2114                 printk( "%s(%d):%s bh_receive()\n",
2115                         __FILE__,__LINE__,info->device_name);
2116
2117         while( rx_get_frame(info) );
2118 }
2119
2120 static void bh_transmit(SLMP_INFO *info)
2121 {
2122         struct tty_struct *tty = info->port.tty;
2123
2124         if ( debug_level >= DEBUG_LEVEL_BH )
2125                 printk( "%s(%d):%s bh_transmit() entry\n",
2126                         __FILE__,__LINE__,info->device_name);
2127
2128         if (tty)
2129                 tty_wakeup(tty);
2130 }
2131
2132 static void bh_status(SLMP_INFO *info)
2133 {
2134         if ( debug_level >= DEBUG_LEVEL_BH )
2135                 printk( "%s(%d):%s bh_status() entry\n",
2136                         __FILE__,__LINE__,info->device_name);
2137
2138         info->ri_chkcount = 0;
2139         info->dsr_chkcount = 0;
2140         info->dcd_chkcount = 0;
2141         info->cts_chkcount = 0;
2142 }
2143
2144 static void isr_timer(SLMP_INFO * info)
2145 {
2146         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2147
2148         /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2149         write_reg(info, IER2, 0);
2150
2151         /* TMCS, Timer Control/Status Register
2152          *
2153          * 07      CMF, Compare match flag (read only) 1=match
2154          * 06      ECMI, CMF Interrupt Enable: 0=disabled
2155          * 05      Reserved, must be 0
2156          * 04      TME, Timer Enable
2157          * 03..00  Reserved, must be 0
2158          *
2159          * 0000 0000
2160          */
2161         write_reg(info, (unsigned char)(timer + TMCS), 0);
2162
2163         info->irq_occurred = true;
2164
2165         if ( debug_level >= DEBUG_LEVEL_ISR )
2166                 printk("%s(%d):%s isr_timer()\n",
2167                         __FILE__,__LINE__,info->device_name);
2168 }
2169
2170 static void isr_rxint(SLMP_INFO * info)
2171 {
2172         struct tty_struct *tty = info->port.tty;
2173         struct  mgsl_icount *icount = &info->icount;
2174         unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2175         unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2176
2177         /* clear status bits */
2178         if (status)
2179                 write_reg(info, SR1, status);
2180
2181         if (status2)
2182                 write_reg(info, SR2, status2);
2183
2184         if ( debug_level >= DEBUG_LEVEL_ISR )
2185                 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2186                         __FILE__,__LINE__,info->device_name,status,status2);
2187
2188         if (info->params.mode == MGSL_MODE_ASYNC) {
2189                 if (status & BRKD) {
2190                         icount->brk++;
2191
2192                         /* process break detection if tty control
2193                          * is not set to ignore it
2194                          */
2195                         if ( tty ) {
2196                                 if (!(status & info->ignore_status_mask1)) {
2197                                         if (info->read_status_mask1 & BRKD) {
2198                                                 tty_insert_flip_char(tty, 0, TTY_BREAK);
2199                                                 if (info->port.flags & ASYNC_SAK)
2200                                                         do_SAK(tty);
2201                                         }
2202                                 }
2203                         }
2204                 }
2205         }
2206         else {
2207                 if (status & (FLGD|IDLD)) {
2208                         if (status & FLGD)
2209                                 info->icount.exithunt++;
2210                         else if (status & IDLD)
2211                                 info->icount.rxidle++;
2212                         wake_up_interruptible(&info->event_wait_q);
2213                 }
2214         }
2215
2216         if (status & CDCD) {
2217                 /* simulate a common modem status change interrupt
2218                  * for our handler
2219                  */
2220                 get_signals( info );
2221                 isr_io_pin(info,
2222                         MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2223         }
2224 }
2225
2226 /*
2227  * handle async rx data interrupts
2228  */
2229 static void isr_rxrdy(SLMP_INFO * info)
2230 {
2231         u16 status;
2232         unsigned char DataByte;
2233         struct tty_struct *tty = info->port.tty;
2234         struct  mgsl_icount *icount = &info->icount;
2235
2236         if ( debug_level >= DEBUG_LEVEL_ISR )
2237                 printk("%s(%d):%s isr_rxrdy\n",
2238                         __FILE__,__LINE__,info->device_name);
2239
2240         while((status = read_reg(info,CST0)) & BIT0)
2241         {
2242                 int flag = 0;
2243                 bool over = false;
2244                 DataByte = read_reg(info,TRB);
2245
2246                 icount->rx++;
2247
2248                 if ( status & (PE + FRME + OVRN) ) {
2249                         printk("%s(%d):%s rxerr=%04X\n",
2250                                 __FILE__,__LINE__,info->device_name,status);
2251
2252                         /* update error statistics */
2253                         if (status & PE)
2254                                 icount->parity++;
2255                         else if (status & FRME)
2256                                 icount->frame++;
2257                         else if (status & OVRN)
2258                                 icount->overrun++;
2259
2260                         /* discard char if tty control flags say so */
2261                         if (status & info->ignore_status_mask2)
2262                                 continue;
2263
2264                         status &= info->read_status_mask2;
2265
2266                         if ( tty ) {
2267                                 if (status & PE)
2268                                         flag = TTY_PARITY;
2269                                 else if (status & FRME)
2270                                         flag = TTY_FRAME;
2271                                 if (status & OVRN) {
2272                                         /* Overrun is special, since it's
2273                                          * reported immediately, and doesn't
2274                                          * affect the current character
2275                                          */
2276                                         over = true;
2277                                 }
2278                         }
2279                 }       /* end of if (error) */
2280
2281                 if ( tty ) {
2282                         tty_insert_flip_char(tty, DataByte, flag);
2283                         if (over)
2284                                 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
2285                 }
2286         }
2287
2288         if ( debug_level >= DEBUG_LEVEL_ISR ) {
2289                 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2290                         __FILE__,__LINE__,info->device_name,
2291                         icount->rx,icount->brk,icount->parity,
2292                         icount->frame,icount->overrun);
2293         }
2294
2295         if ( tty )
2296                 tty_flip_buffer_push(tty);
2297 }
2298
2299 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2300 {
2301         if ( debug_level >= DEBUG_LEVEL_ISR )
2302                 printk("%s(%d):%s isr_txeom status=%02x\n",
2303                         __FILE__,__LINE__,info->device_name,status);
2304
2305         write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2306         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2307         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2308
2309         if (status & UDRN) {
2310                 write_reg(info, CMD, TXRESET);
2311                 write_reg(info, CMD, TXENABLE);
2312         } else
2313                 write_reg(info, CMD, TXBUFCLR);
2314
2315         /* disable and clear tx interrupts */
2316         info->ie0_value &= ~TXRDYE;
2317         info->ie1_value &= ~(IDLE + UDRN);
2318         write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2319         write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2320
2321         if ( info->tx_active ) {
2322                 if (info->params.mode != MGSL_MODE_ASYNC) {
2323                         if (status & UDRN)
2324                                 info->icount.txunder++;
2325                         else if (status & IDLE)
2326                                 info->icount.txok++;
2327                 }
2328
2329                 info->tx_active = false;
2330                 info->tx_count = info->tx_put = info->tx_get = 0;
2331
2332                 del_timer(&info->tx_timer);
2333
2334                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2335                         info->serial_signals &= ~SerialSignal_RTS;
2336                         info->drop_rts_on_tx_done = false;
2337                         set_signals(info);
2338                 }
2339
2340 #if SYNCLINK_GENERIC_HDLC
2341                 if (info->netcount)
2342                         hdlcdev_tx_done(info);
2343                 else
2344 #endif
2345                 {
2346                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2347                                 tx_stop(info);
2348                                 return;
2349                         }
2350                         info->pending_bh |= BH_TRANSMIT;
2351                 }
2352         }
2353 }
2354
2355
2356 /*
2357  * handle tx status interrupts
2358  */
2359 static void isr_txint(SLMP_INFO * info)
2360 {
2361         unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2362
2363         /* clear status bits */
2364         write_reg(info, SR1, status);
2365
2366         if ( debug_level >= DEBUG_LEVEL_ISR )
2367                 printk("%s(%d):%s isr_txint status=%02x\n",
2368                         __FILE__,__LINE__,info->device_name,status);
2369
2370         if (status & (UDRN + IDLE))
2371                 isr_txeom(info, status);
2372
2373         if (status & CCTS) {
2374                 /* simulate a common modem status change interrupt
2375                  * for our handler
2376                  */
2377                 get_signals( info );
2378                 isr_io_pin(info,
2379                         MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2380
2381         }
2382 }
2383
2384 /*
2385  * handle async tx data interrupts
2386  */
2387 static void isr_txrdy(SLMP_INFO * info)
2388 {
2389         if ( debug_level >= DEBUG_LEVEL_ISR )
2390                 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2391                         __FILE__,__LINE__,info->device_name,info->tx_count);
2392
2393         if (info->params.mode != MGSL_MODE_ASYNC) {
2394                 /* disable TXRDY IRQ, enable IDLE IRQ */
2395                 info->ie0_value &= ~TXRDYE;
2396                 info->ie1_value |= IDLE;
2397                 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2398                 return;
2399         }
2400
2401         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2402                 tx_stop(info);
2403                 return;
2404         }
2405
2406         if ( info->tx_count )
2407                 tx_load_fifo( info );
2408         else {
2409                 info->tx_active = false;
2410                 info->ie0_value &= ~TXRDYE;
2411                 write_reg(info, IE0, info->ie0_value);
2412         }
2413
2414         if (info->tx_count < WAKEUP_CHARS)
2415                 info->pending_bh |= BH_TRANSMIT;
2416 }
2417
2418 static void isr_rxdmaok(SLMP_INFO * info)
2419 {
2420         /* BIT7 = EOT (end of transfer)
2421          * BIT6 = EOM (end of message/frame)
2422          */
2423         unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2424
2425         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2426         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2427
2428         if ( debug_level >= DEBUG_LEVEL_ISR )
2429                 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2430                         __FILE__,__LINE__,info->device_name,status);
2431
2432         info->pending_bh |= BH_RECEIVE;
2433 }
2434
2435 static void isr_rxdmaerror(SLMP_INFO * info)
2436 {
2437         /* BIT5 = BOF (buffer overflow)
2438          * BIT4 = COF (counter overflow)
2439          */
2440         unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2441
2442         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2443         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2444
2445         if ( debug_level >= DEBUG_LEVEL_ISR )
2446                 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2447                         __FILE__,__LINE__,info->device_name,status);
2448
2449         info->rx_overflow = true;
2450         info->pending_bh |= BH_RECEIVE;
2451 }
2452
2453 static void isr_txdmaok(SLMP_INFO * info)
2454 {
2455         unsigned char status_reg1 = read_reg(info, SR1);
2456
2457         write_reg(info, TXDMA + DIR, 0x00);     /* disable Tx DMA IRQs */
2458         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2459         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2460
2461         if ( debug_level >= DEBUG_LEVEL_ISR )
2462                 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2463                         __FILE__,__LINE__,info->device_name,status_reg1);
2464
2465         /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2466         write_reg16(info, TRC0, 0);
2467         info->ie0_value |= TXRDYE;
2468         write_reg(info, IE0, info->ie0_value);
2469 }
2470
2471 static void isr_txdmaerror(SLMP_INFO * info)
2472 {
2473         /* BIT5 = BOF (buffer overflow)
2474          * BIT4 = COF (counter overflow)
2475          */
2476         unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2477
2478         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2479         write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2480
2481         if ( debug_level >= DEBUG_LEVEL_ISR )
2482                 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2483                         __FILE__,__LINE__,info->device_name,status);
2484 }
2485
2486 /* handle input serial signal changes
2487  */
2488 static void isr_io_pin( SLMP_INFO *info, u16 status )
2489 {
2490         struct  mgsl_icount *icount;
2491
2492         if ( debug_level >= DEBUG_LEVEL_ISR )
2493                 printk("%s(%d):isr_io_pin status=%04X\n",
2494                         __FILE__,__LINE__,status);
2495
2496         if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2497                       MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2498                 icount = &info->icount;
2499                 /* update input line counters */
2500                 if (status & MISCSTATUS_RI_LATCHED) {
2501                         icount->rng++;
2502                         if ( status & SerialSignal_RI )
2503                                 info->input_signal_events.ri_up++;
2504                         else
2505                                 info->input_signal_events.ri_down++;
2506                 }
2507                 if (status & MISCSTATUS_DSR_LATCHED) {
2508                         icount->dsr++;
2509                         if ( status & SerialSignal_DSR )
2510                                 info->input_signal_events.dsr_up++;
2511                         else
2512                                 info->input_signal_events.dsr_down++;
2513                 }
2514                 if (status & MISCSTATUS_DCD_LATCHED) {
2515                         if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2516                                 info->ie1_value &= ~CDCD;
2517                                 write_reg(info, IE1, info->ie1_value);
2518                         }
2519                         icount->dcd++;
2520                         if (status & SerialSignal_DCD) {
2521                                 info->input_signal_events.dcd_up++;
2522                         } else
2523                                 info->input_signal_events.dcd_down++;
2524 #if SYNCLINK_GENERIC_HDLC
2525                         if (info->netcount) {
2526                                 if (status & SerialSignal_DCD)
2527                                         netif_carrier_on(info->netdev);
2528                                 else
2529                                         netif_carrier_off(info->netdev);
2530                         }
2531 #endif
2532                 }
2533                 if (status & MISCSTATUS_CTS_LATCHED)
2534                 {
2535                         if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2536                                 info->ie1_value &= ~CCTS;
2537                                 write_reg(info, IE1, info->ie1_value);
2538                         }
2539                         icount->cts++;
2540                         if ( status & SerialSignal_CTS )
2541                                 info->input_signal_events.cts_up++;
2542                         else
2543                                 info->input_signal_events.cts_down++;
2544                 }
2545                 wake_up_interruptible(&info->status_event_wait_q);
2546                 wake_up_interruptible(&info->event_wait_q);
2547
2548                 if ( (info->port.flags & ASYNC_CHECK_CD) &&
2549                      (status & MISCSTATUS_DCD_LATCHED) ) {
2550                         if ( debug_level >= DEBUG_LEVEL_ISR )
2551                                 printk("%s CD now %s...", info->device_name,
2552                                        (status & SerialSignal_DCD) ? "on" : "off");
2553                         if (status & SerialSignal_DCD)
2554                                 wake_up_interruptible(&info->port.open_wait);
2555                         else {
2556                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2557                                         printk("doing serial hangup...");
2558                                 if (info->port.tty)
2559                                         tty_hangup(info->port.tty);
2560                         }
2561                 }
2562
2563                 if ( (info->port.flags & ASYNC_CTS_FLOW) &&
2564                      (status & MISCSTATUS_CTS_LATCHED) ) {
2565                         if ( info->port.tty ) {
2566                                 if (info->port.tty->hw_stopped) {
2567                                         if (status & SerialSignal_CTS) {
2568                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2569                                                         printk("CTS tx start...");
2570                                                 info->port.tty->hw_stopped = 0;
2571                                                 tx_start(info);
2572                                                 info->pending_bh |= BH_TRANSMIT;
2573                                                 return;
2574                                         }
2575                                 } else {
2576                                         if (!(status & SerialSignal_CTS)) {
2577                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2578                                                         printk("CTS tx stop...");
2579                                                 info->port.tty->hw_stopped = 1;
2580                                                 tx_stop(info);
2581                                         }
2582                                 }
2583                         }
2584                 }
2585         }
2586
2587         info->pending_bh |= BH_STATUS;
2588 }
2589
2590 /* Interrupt service routine entry point.
2591  *
2592  * Arguments:
2593  *      irq             interrupt number that caused interrupt
2594  *      dev_id          device ID supplied during interrupt registration
2595  *      regs            interrupted processor context
2596  */
2597 static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2598 {
2599         SLMP_INFO *info = dev_id;
2600         unsigned char status, status0, status1=0;
2601         unsigned char dmastatus, dmastatus0, dmastatus1=0;
2602         unsigned char timerstatus0, timerstatus1=0;
2603         unsigned char shift;
2604         unsigned int i;
2605         unsigned short tmp;
2606
2607         if ( debug_level >= DEBUG_LEVEL_ISR )
2608                 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2609                         __FILE__, __LINE__, info->irq_level);
2610
2611         spin_lock(&info->lock);
2612
2613         for(;;) {
2614
2615                 /* get status for SCA0 (ports 0-1) */
2616                 tmp = read_reg16(info, ISR0);   /* get ISR0 and ISR1 in one read */
2617                 status0 = (unsigned char)tmp;
2618                 dmastatus0 = (unsigned char)(tmp>>8);
2619                 timerstatus0 = read_reg(info, ISR2);
2620
2621                 if ( debug_level >= DEBUG_LEVEL_ISR )
2622                         printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2623                                 __FILE__, __LINE__, info->device_name,
2624                                 status0, dmastatus0, timerstatus0);
2625
2626                 if (info->port_count == 4) {
2627                         /* get status for SCA1 (ports 2-3) */
2628                         tmp = read_reg16(info->port_array[2], ISR0);
2629                         status1 = (unsigned char)tmp;
2630                         dmastatus1 = (unsigned char)(tmp>>8);
2631                         timerstatus1 = read_reg(info->port_array[2], ISR2);
2632
2633                         if ( debug_level >= DEBUG_LEVEL_ISR )
2634                                 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2635                                         __FILE__,__LINE__,info->device_name,
2636                                         status1,dmastatus1,timerstatus1);
2637                 }
2638
2639                 if (!status0 && !dmastatus0 && !timerstatus0 &&
2640                          !status1 && !dmastatus1 && !timerstatus1)
2641                         break;
2642
2643                 for(i=0; i < info->port_count ; i++) {
2644                         if (info->port_array[i] == NULL)
2645                                 continue;
2646                         if (i < 2) {
2647                                 status = status0;
2648                                 dmastatus = dmastatus0;
2649                         } else {
2650                                 status = status1;
2651                                 dmastatus = dmastatus1;
2652                         }
2653
2654                         shift = i & 1 ? 4 :0;
2655
2656                         if (status & BIT0 << shift)
2657                                 isr_rxrdy(info->port_array[i]);
2658                         if (status & BIT1 << shift)
2659                                 isr_txrdy(info->port_array[i]);
2660                         if (status & BIT2 << shift)
2661                                 isr_rxint(info->port_array[i]);
2662                         if (status & BIT3 << shift)
2663                                 isr_txint(info->port_array[i]);
2664
2665                         if (dmastatus & BIT0 << shift)
2666                                 isr_rxdmaerror(info->port_array[i]);
2667                         if (dmastatus & BIT1 << shift)
2668                                 isr_rxdmaok(info->port_array[i]);
2669                         if (dmastatus & BIT2 << shift)
2670                                 isr_txdmaerror(info->port_array[i]);
2671                         if (dmastatus & BIT3 << shift)
2672                                 isr_txdmaok(info->port_array[i]);
2673                 }
2674
2675                 if (timerstatus0 & (BIT5 | BIT4))
2676                         isr_timer(info->port_array[0]);
2677                 if (timerstatus0 & (BIT7 | BIT6))
2678                         isr_timer(info->port_array[1]);
2679                 if (timerstatus1 & (BIT5 | BIT4))
2680                         isr_timer(info->port_array[2]);
2681                 if (timerstatus1 & (BIT7 | BIT6))
2682                         isr_timer(info->port_array[3]);
2683         }
2684
2685         for(i=0; i < info->port_count ; i++) {
2686                 SLMP_INFO * port = info->port_array[i];
2687
2688                 /* Request bottom half processing if there's something
2689                  * for it to do and the bh is not already running.
2690                  *
2691                  * Note: startup adapter diags require interrupts.
2692                  * do not request bottom half processing if the
2693                  * device is not open in a normal mode.
2694                  */
2695                 if ( port && (port->port.count || port->netcount) &&
2696                      port->pending_bh && !port->bh_running &&
2697                      !port->bh_requested ) {
2698                         if ( debug_level >= DEBUG_LEVEL_ISR )
2699                                 printk("%s(%d):%s queueing bh task.\n",
2700                                         __FILE__,__LINE__,port->device_name);
2701                         schedule_work(&port->task);
2702                         port->bh_requested = true;
2703                 }
2704         }
2705
2706         spin_unlock(&info->lock);
2707
2708         if ( debug_level >= DEBUG_LEVEL_ISR )
2709                 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2710                         __FILE__, __LINE__, info->irq_level);
2711         return IRQ_HANDLED;
2712 }
2713
2714 /* Initialize and start device.
2715  */
2716 static int startup(SLMP_INFO * info)
2717 {
2718         if ( debug_level >= DEBUG_LEVEL_INFO )
2719                 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2720
2721         if (info->port.flags & ASYNC_INITIALIZED)
2722                 return 0;
2723
2724         if (!info->tx_buf) {
2725                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2726                 if (!info->tx_buf) {
2727                         printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2728                                 __FILE__,__LINE__,info->device_name);
2729                         return -ENOMEM;
2730                 }
2731         }
2732
2733         info->pending_bh = 0;
2734
2735         memset(&info->icount, 0, sizeof(info->icount));
2736
2737         /* program hardware for current parameters */
2738         reset_port(info);
2739
2740         change_params(info);
2741
2742         mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2743
2744         if (info->port.tty)
2745                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2746
2747         info->port.flags |= ASYNC_INITIALIZED;
2748
2749         return 0;
2750 }
2751
2752 /* Called by close() and hangup() to shutdown hardware
2753  */
2754 static void shutdown(SLMP_INFO * info)
2755 {
2756         unsigned long flags;
2757
2758         if (!(info->port.flags & ASYNC_INITIALIZED))
2759                 return;
2760
2761         if (debug_level >= DEBUG_LEVEL_INFO)
2762                 printk("%s(%d):%s synclinkmp_shutdown()\n",
2763                          __FILE__,__LINE__, info->device_name );
2764
2765         /* clear status wait queue because status changes */
2766         /* can't happen after shutting down the hardware */
2767         wake_up_interruptible(&info->status_event_wait_q);
2768         wake_up_interruptible(&info->event_wait_q);
2769
2770         del_timer(&info->tx_timer);
2771         del_timer(&info->status_timer);
2772
2773         kfree(info->tx_buf);
2774         info->tx_buf = NULL;
2775
2776         spin_lock_irqsave(&info->lock,flags);
2777
2778         reset_port(info);
2779
2780         if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2781                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2782                 set_signals(info);
2783         }
2784
2785         spin_unlock_irqrestore(&info->lock,flags);
2786
2787         if (info->port.tty)
2788                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2789
2790         info->port.flags &= ~ASYNC_INITIALIZED;
2791 }
2792
2793 static void program_hw(SLMP_INFO *info)
2794 {
2795         unsigned long flags;
2796
2797         spin_lock_irqsave(&info->lock,flags);
2798
2799         rx_stop(info);
2800         tx_stop(info);
2801
2802         info->tx_count = info->tx_put = info->tx_get = 0;
2803
2804         if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2805                 hdlc_mode(info);
2806         else
2807                 async_mode(info);
2808
2809         set_signals(info);
2810
2811         info->dcd_chkcount = 0;
2812         info->cts_chkcount = 0;
2813         info->ri_chkcount = 0;
2814         info->dsr_chkcount = 0;
2815
2816         info->ie1_value |= (CDCD|CCTS);
2817         write_reg(info, IE1, info->ie1_value);
2818
2819         get_signals(info);
2820
2821         if (info->netcount || (info->port.tty && info->port.tty->termios->c_cflag & CREAD) )
2822                 rx_start(info);
2823
2824         spin_unlock_irqrestore(&info->lock,flags);
2825 }
2826
2827 /* Reconfigure adapter based on new parameters
2828  */
2829 static void change_params(SLMP_INFO *info)
2830 {
2831         unsigned cflag;
2832         int bits_per_char;
2833
2834         if (!info->port.tty || !info->port.tty->termios)
2835                 return;
2836
2837         if (debug_level >= DEBUG_LEVEL_INFO)
2838                 printk("%s(%d):%s change_params()\n",
2839                          __FILE__,__LINE__, info->device_name );
2840
2841         cflag = info->port.tty->termios->c_cflag;
2842
2843         /* if B0 rate (hangup) specified then negate DTR and RTS */
2844         /* otherwise assert DTR and RTS */
2845         if (cflag & CBAUD)
2846                 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2847         else
2848                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2849
2850         /* byte size and parity */
2851
2852         switch (cflag & CSIZE) {
2853               case CS5: info->params.data_bits = 5; break;
2854               case CS6: info->params.data_bits = 6; break;
2855               case CS7: info->params.data_bits = 7; break;
2856               case CS8: info->params.data_bits = 8; break;
2857               /* Never happens, but GCC is too dumb to figure it out */
2858               default:  info->params.data_bits = 7; break;
2859               }
2860
2861         if (cflag & CSTOPB)
2862                 info->params.stop_bits = 2;
2863         else
2864                 info->params.stop_bits = 1;
2865
2866         info->params.parity = ASYNC_PARITY_NONE;
2867         if (cflag & PARENB) {
2868                 if (cflag & PARODD)
2869                         info->params.parity = ASYNC_PARITY_ODD;
2870                 else
2871                         info->params.parity = ASYNC_PARITY_EVEN;
2872 #ifdef CMSPAR
2873                 if (cflag & CMSPAR)
2874                         info->params.parity = ASYNC_PARITY_SPACE;
2875 #endif
2876         }
2877
2878         /* calculate number of jiffies to transmit a full
2879          * FIFO (32 bytes) at specified data rate
2880          */
2881         bits_per_char = info->params.data_bits +
2882                         info->params.stop_bits + 1;
2883
2884         /* if port data rate is set to 460800 or less then
2885          * allow tty settings to override, otherwise keep the
2886          * current data rate.
2887          */
2888         if (info->params.data_rate <= 460800) {
2889                 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2890         }
2891
2892         if ( info->params.data_rate ) {
2893                 info->timeout = (32*HZ*bits_per_char) /
2894                                 info->params.data_rate;
2895         }
2896         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2897
2898         if (cflag & CRTSCTS)
2899                 info->port.flags |= ASYNC_CTS_FLOW;
2900         else
2901                 info->port.flags &= ~ASYNC_CTS_FLOW;
2902
2903         if (cflag & CLOCAL)
2904                 info->port.flags &= ~ASYNC_CHECK_CD;
2905         else
2906                 info->port.flags |= ASYNC_CHECK_CD;
2907
2908         /* process tty input control flags */
2909
2910         info->read_status_mask2 = OVRN;
2911         if (I_INPCK(info->port.tty))
2912                 info->read_status_mask2 |= PE | FRME;
2913         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2914                 info->read_status_mask1 |= BRKD;
2915         if (I_IGNPAR(info->port.tty))
2916                 info->ignore_status_mask2 |= PE | FRME;
2917         if (I_IGNBRK(info->port.tty)) {
2918                 info->ignore_status_mask1 |= BRKD;
2919                 /* If ignoring parity and break indicators, ignore
2920                  * overruns too.  (For real raw support).
2921                  */
2922                 if (I_IGNPAR(info->port.tty))
2923                         info->ignore_status_mask2 |= OVRN;
2924         }
2925
2926         program_hw(info);
2927 }
2928
2929 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2930 {
2931         int err;
2932
2933         if (debug_level >= DEBUG_LEVEL_INFO)
2934                 printk("%s(%d):%s get_params()\n",
2935                          __FILE__,__LINE__, info->device_name);
2936
2937         if (!user_icount) {
2938                 memset(&info->icount, 0, sizeof(info->icount));
2939         } else {
2940                 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2941                 if (err)
2942                         return -EFAULT;
2943         }
2944
2945         return 0;
2946 }
2947
2948 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2949 {
2950         int err;
2951         if (debug_level >= DEBUG_LEVEL_INFO)
2952                 printk("%s(%d):%s get_params()\n",
2953                          __FILE__,__LINE__, info->device_name);
2954
2955         COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2956         if (err) {
2957                 if ( debug_level >= DEBUG_LEVEL_INFO )
2958                         printk( "%s(%d):%s get_params() user buffer copy failed\n",
2959                                 __FILE__,__LINE__,info->device_name);
2960                 return -EFAULT;
2961         }
2962
2963         return 0;
2964 }
2965
2966 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2967 {
2968         unsigned long flags;
2969         MGSL_PARAMS tmp_params;
2970         int err;
2971
2972         if (debug_level >= DEBUG_LEVEL_INFO)
2973                 printk("%s(%d):%s set_params\n",
2974                         __FILE__,__LINE__,info->device_name );
2975         COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2976         if (err) {
2977                 if ( debug_level >= DEBUG_LEVEL_INFO )
2978                         printk( "%s(%d):%s set_params() user buffer copy failed\n",
2979                                 __FILE__,__LINE__,info->device_name);
2980                 return -EFAULT;
2981         }
2982
2983         spin_lock_irqsave(&info->lock,flags);
2984         memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2985         spin_unlock_irqrestore(&info->lock,flags);
2986
2987         change_params(info);
2988
2989         return 0;
2990 }
2991
2992 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2993 {
2994         int err;
2995
2996         if (debug_level >= DEBUG_LEVEL_INFO)
2997                 printk("%s(%d):%s get_txidle()=%d\n",
2998                          __FILE__,__LINE__, info->device_name, info->idle_mode);
2999
3000         COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
3001         if (err) {
3002                 if ( debug_level >= DEBUG_LEVEL_INFO )
3003                         printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
3004                                 __FILE__,__LINE__,info->device_name);
3005                 return -EFAULT;
3006         }
3007
3008         return 0;
3009 }
3010
3011 static int set_txidle(SLMP_INFO * info, int idle_mode)
3012 {
3013         unsigned long flags;
3014
3015         if (debug_level >= DEBUG_LEVEL_INFO)
3016                 printk("%s(%d):%s set_txidle(%d)\n",
3017                         __FILE__,__LINE__,info->device_name, idle_mode );
3018
3019         spin_lock_irqsave(&info->lock,flags);
3020         info->idle_mode = idle_mode;
3021         tx_set_idle( info );
3022         spin_unlock_irqrestore(&info->lock,flags);
3023         return 0;
3024 }
3025
3026 static int tx_enable(SLMP_INFO * info, int enable)
3027 {
3028         unsigned long flags;
3029
3030         if (debug_level >= DEBUG_LEVEL_INFO)
3031                 printk("%s(%d):%s tx_enable(%d)\n",
3032                         __FILE__,__LINE__,info->device_name, enable);
3033
3034         spin_lock_irqsave(&info->lock,flags);
3035         if ( enable ) {
3036                 if ( !info->tx_enabled ) {
3037                         tx_start(info);
3038                 }
3039         } else {
3040                 if ( info->tx_enabled )
3041                         tx_stop(info);
3042         }
3043         spin_unlock_irqrestore(&info->lock,flags);
3044         return 0;
3045 }
3046
3047 /* abort send HDLC frame
3048  */
3049 static int tx_abort(SLMP_INFO * info)
3050 {
3051         unsigned long flags;
3052
3053         if (debug_level >= DEBUG_LEVEL_INFO)
3054                 printk("%s(%d):%s tx_abort()\n",
3055                         __FILE__,__LINE__,info->device_name);
3056
3057         spin_lock_irqsave(&info->lock,flags);
3058         if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
3059                 info->ie1_value &= ~UDRN;
3060                 info->ie1_value |= IDLE;
3061                 write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
3062                 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
3063
3064                 write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
3065                 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3066
3067                 write_reg(info, CMD, TXABORT);
3068         }
3069         spin_unlock_irqrestore(&info->lock,flags);
3070         return 0;
3071 }
3072
3073 static int rx_enable(SLMP_INFO * info, int enable)
3074 {
3075         unsigned long flags;
3076
3077         if (debug_level >= DEBUG_LEVEL_INFO)
3078                 printk("%s(%d):%s rx_enable(%d)\n",
3079                         __FILE__,__LINE__,info->device_name,enable);
3080
3081         spin_lock_irqsave(&info->lock,flags);
3082         if ( enable ) {
3083                 if ( !info->rx_enabled )
3084                         rx_start(info);
3085         } else {
3086                 if ( info->rx_enabled )
3087                         rx_stop(info);
3088         }
3089         spin_unlock_irqrestore(&info->lock,flags);
3090         return 0;
3091 }
3092
3093 /* wait for specified event to occur
3094  */
3095 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3096 {
3097         unsigned long flags;
3098         int s;
3099         int rc=0;
3100         struct mgsl_icount cprev, cnow;
3101         int events;
3102         int mask;
3103         struct  _input_signal_events oldsigs, newsigs;
3104         DECLARE_WAITQUEUE(wait, current);
3105
3106         COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3107         if (rc) {
3108                 return  -EFAULT;
3109         }
3110
3111         if (debug_level >= DEBUG_LEVEL_INFO)
3112                 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3113                         __FILE__,__LINE__,info->device_name,mask);
3114
3115         spin_lock_irqsave(&info->lock,flags);
3116
3117         /* return immediately if state matches requested events */
3118         get_signals(info);
3119         s = info->serial_signals;
3120
3121         events = mask &
3122                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3123                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3124                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3125                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3126         if (events) {
3127                 spin_unlock_irqrestore(&info->lock,flags);
3128                 goto exit;
3129         }
3130
3131         /* save current irq counts */
3132         cprev = info->icount;
3133         oldsigs = info->input_signal_events;
3134
3135         /* enable hunt and idle irqs if needed */
3136         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3137                 unsigned char oldval = info->ie1_value;
3138                 unsigned char newval = oldval +
3139                          (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3140                          (mask & MgslEvent_IdleReceived ? IDLD:0);
3141                 if ( oldval != newval ) {
3142                         info->ie1_value = newval;
3143                         write_reg(info, IE1, info->ie1_value);
3144                 }
3145         }
3146
3147         set_current_state(TASK_INTERRUPTIBLE);
3148         add_wait_queue(&info->event_wait_q, &wait);
3149
3150         spin_unlock_irqrestore(&info->lock,flags);
3151
3152         for(;;) {
3153                 schedule();
3154                 if (signal_pending(current)) {
3155                         rc = -ERESTARTSYS;
3156                         break;
3157                 }
3158
3159                 /* get current irq counts */
3160                 spin_lock_irqsave(&info->lock,flags);
3161                 cnow = info->icount;
3162                 newsigs = info->input_signal_events;
3163                 set_current_state(TASK_INTERRUPTIBLE);
3164                 spin_unlock_irqrestore(&info->lock,flags);
3165
3166                 /* if no change, wait aborted for some reason */
3167                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
3168                     newsigs.dsr_down == oldsigs.dsr_down &&
3169                     newsigs.dcd_up   == oldsigs.dcd_up   &&
3170                     newsigs.dcd_down == oldsigs.dcd_down &&
3171                     newsigs.cts_up   == oldsigs.cts_up   &&
3172                     newsigs.cts_down == oldsigs.cts_down &&
3173                     newsigs.ri_up    == oldsigs.ri_up    &&
3174                     newsigs.ri_down  == oldsigs.ri_down  &&
3175                     cnow.exithunt    == cprev.exithunt   &&
3176                     cnow.rxidle      == cprev.rxidle) {
3177                         rc = -EIO;
3178                         break;
3179                 }
3180
3181                 events = mask &
3182                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
3183                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3184                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
3185                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3186                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
3187                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3188                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
3189                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
3190                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
3191                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
3192                 if (events)
3193                         break;
3194
3195                 cprev = cnow;
3196                 oldsigs = newsigs;
3197         }
3198
3199         remove_wait_queue(&info->event_wait_q, &wait);
3200         set_current_state(TASK_RUNNING);
3201
3202
3203         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3204                 spin_lock_irqsave(&info->lock,flags);
3205                 if (!waitqueue_active(&info->event_wait_q)) {
3206                         /* disable enable exit hunt mode/idle rcvd IRQs */
3207                         info->ie1_value &= ~(FLGD|IDLD);
3208                         write_reg(info, IE1, info->ie1_value);
3209                 }
3210                 spin_unlock_irqrestore(&info->lock,flags);
3211         }
3212 exit:
3213         if ( rc == 0 )
3214                 PUT_USER(rc, events, mask_ptr);
3215
3216         return rc;
3217 }
3218
3219 static int modem_input_wait(SLMP_INFO *info,int arg)
3220 {
3221         unsigned long flags;
3222         int rc;
3223         struct mgsl_icount cprev, cnow;
3224         DECLARE_WAITQUEUE(wait, current);
3225
3226         /* save current irq counts */
3227         spin_lock_irqsave(&info->lock,flags);
3228         cprev = info->icount;
3229         add_wait_queue(&info->status_event_wait_q, &wait);
3230         set_current_state(TASK_INTERRUPTIBLE);
3231         spin_unlock_irqrestore(&info->lock,flags);
3232
3233         for(;;) {
3234                 schedule();
3235                 if (signal_pending(current)) {
3236                         rc = -ERESTARTSYS;
3237                         break;
3238                 }
3239
3240                 /* get new irq counts */
3241                 spin_lock_irqsave(&info->lock,flags);
3242                 cnow = info->icount;
3243                 set_current_state(TASK_INTERRUPTIBLE);
3244                 spin_unlock_irqrestore(&info->lock,flags);
3245
3246                 /* if no change, wait aborted for some reason */
3247                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3248                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3249                         rc = -EIO;
3250                         break;
3251                 }
3252
3253                 /* check for change in caller specified modem input */
3254                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3255                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3256                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3257                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3258                         rc = 0;
3259                         break;
3260                 }
3261
3262                 cprev = cnow;
3263         }
3264         remove_wait_queue(&info->status_event_wait_q, &wait);
3265         set_current_state(TASK_RUNNING);
3266         return rc;
3267 }
3268
3269 /* return the state of the serial control and status signals
3270  */
3271 static int tiocmget(struct tty_struct *tty, struct file *file)
3272 {
3273         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3274         unsigned int result;
3275         unsigned long flags;
3276
3277         spin_lock_irqsave(&info->lock,flags);
3278         get_signals(info);
3279         spin_unlock_irqrestore(&info->lock,flags);
3280
3281         result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3282                 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3283                 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3284                 ((info->serial_signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3285                 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3286                 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3287
3288         if (debug_level >= DEBUG_LEVEL_INFO)
3289                 printk("%s(%d):%s tiocmget() value=%08X\n",
3290                          __FILE__,__LINE__, info->device_name, result );
3291         return result;
3292 }
3293
3294 /* set modem control signals (DTR/RTS)
3295  */
3296 static int tiocmset(struct tty_struct *tty, struct file *file,
3297                     unsigned int set, unsigned int clear)
3298 {
3299         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3300         unsigned long flags;
3301
3302         if (debug_level >= DEBUG_LEVEL_INFO)
3303                 printk("%s(%d):%s tiocmset(%x,%x)\n",
3304                         __FILE__,__LINE__,info->device_name, set, clear);
3305
3306         if (set & TIOCM_RTS)
3307                 info->serial_signals |= SerialSignal_RTS;
3308         if (set & TIOCM_DTR)
3309                 info->serial_signals |= SerialSignal_DTR;
3310         if (clear & TIOCM_RTS)
3311                 info->serial_signals &= ~SerialSignal_RTS;
3312         if (clear & TIOCM_DTR)
3313                 info->serial_signals &= ~SerialSignal_DTR;
3314
3315         spin_lock_irqsave(&info->lock,flags);
3316         set_signals(info);
3317         spin_unlock_irqrestore(&info->lock,flags);
3318
3319         return 0;
3320 }
3321
3322 static int carrier_raised(struct tty_port *port)
3323 {
3324         SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3325         unsigned long flags;
3326
3327         spin_lock_irqsave(&info->lock,flags);
3328         get_signals(info);
3329         spin_unlock_irqrestore(&info->lock,flags);
3330
3331         return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3332 }
3333
3334 static void raise_dtr_rts(struct tty_port *port)
3335 {
3336         SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3337         unsigned long flags;
3338
3339         spin_lock_irqsave(&info->lock,flags);
3340         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3341         set_signals(info);
3342         spin_unlock_irqrestore(&info->lock,flags);
3343 }
3344
3345 /* Block the current process until the specified port is ready to open.
3346  */
3347 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3348                            SLMP_INFO *info)
3349 {
3350         DECLARE_WAITQUEUE(wait, current);
3351         int             retval;
3352         bool            do_clocal = false;
3353         bool            extra_count = false;
3354         unsigned long   flags;
3355         int             cd;
3356         struct tty_port *port = &info->port;
3357
3358         if (debug_level >= DEBUG_LEVEL_INFO)
3359                 printk("%s(%d):%s block_til_ready()\n",
3360                          __FILE__,__LINE__, tty->driver->name );
3361
3362         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3363                 /* nonblock mode is set or port is not enabled */
3364                 /* just verify that callout device is not active */
3365                 port->flags |= ASYNC_NORMAL_ACTIVE;
3366                 return 0;
3367         }
3368
3369         if (tty->termios->c_cflag & CLOCAL)
3370                 do_clocal = true;
3371
3372         /* Wait for carrier detect and the line to become
3373          * free (i.e., not in use by the callout).  While we are in
3374          * this loop, port->count is dropped by one, so that
3375          * close() knows when to free things.  We restore it upon
3376          * exit, either normal or abnormal.
3377          */
3378
3379         retval = 0;
3380         add_wait_queue(&port->open_wait, &wait);
3381
3382         if (debug_level >= DEBUG_LEVEL_INFO)
3383                 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3384                          __FILE__,__LINE__, tty->driver->name, port->count );
3385
3386         spin_lock_irqsave(&info->lock, flags);
3387         if (!tty_hung_up_p(filp)) {
3388                 extra_count = true;
3389                 port->count--;
3390         }
3391         spin_unlock_irqrestore(&info->lock, flags);
3392         port->blocked_open++;
3393
3394         while (1) {
3395                 if (tty->termios->c_cflag & CBAUD)
3396                         tty_port_raise_dtr_rts(port);
3397
3398                 set_current_state(TASK_INTERRUPTIBLE);
3399
3400                 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3401                         retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3402                                         -EAGAIN : -ERESTARTSYS;
3403                         break;
3404                 }
3405
3406                 cd = tty_port_carrier_raised(port);
3407
3408                 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd))
3409                         break;
3410
3411                 if (signal_pending(current)) {
3412                         retval = -ERESTARTSYS;
3413                         break;
3414                 }
3415
3416                 if (debug_level >= DEBUG_LEVEL_INFO)
3417                         printk("%s(%d):%s block_til_ready() count=%d\n",
3418                                  __FILE__,__LINE__, tty->driver->name, port->count );
3419
3420                 schedule();
3421         }
3422
3423         set_current_state(TASK_RUNNING);
3424         remove_wait_queue(&port->open_wait, &wait);
3425
3426         if (extra_count)
3427                 port->count++;
3428         port->blocked_open--;
3429
3430         if (debug_level >= DEBUG_LEVEL_INFO)
3431                 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3432                          __FILE__,__LINE__, tty->driver->name, port->count );
3433
3434         if (!retval)
3435                 port->flags |= ASYNC_NORMAL_ACTIVE;
3436
3437         return retval;
3438 }
3439
3440 static int alloc_dma_bufs(SLMP_INFO *info)
3441 {
3442         unsigned short BuffersPerFrame;
3443         unsigned short BufferCount;
3444
3445         // Force allocation to start at 64K boundary for each port.
3446         // This is necessary because *all* buffer descriptors for a port
3447         // *must* be in the same 64K block. All descriptors on a port
3448         // share a common 'base' address (upper 8 bits of 24 bits) programmed
3449         // into the CBP register.
3450         info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3451
3452         /* Calculate the number of DMA buffers necessary to hold the */
3453         /* largest allowable frame size. Note: If the max frame size is */
3454         /* not an even multiple of the DMA buffer size then we need to */
3455         /* round the buffer count per frame up one. */
3456
3457         BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3458         if ( info->max_frame_size % SCABUFSIZE )
3459                 BuffersPerFrame++;
3460
3461         /* calculate total number of data buffers (SCABUFSIZE) possible
3462          * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3463          * for the descriptor list (BUFFERLISTSIZE).
3464          */
3465         BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3466
3467         /* limit number of buffers to maximum amount of descriptors */
3468         if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3469                 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3470
3471         /* use enough buffers to transmit one max size frame */
3472         info->tx_buf_count = BuffersPerFrame + 1;
3473
3474         /* never use more than half the available buffers for transmit */
3475         if (info->tx_buf_count > (BufferCount/2))
3476                 info->tx_buf_count = BufferCount/2;
3477
3478         if (info->tx_buf_count > SCAMAXDESC)
3479                 info->tx_buf_count = SCAMAXDESC;
3480
3481         /* use remaining buffers for receive */
3482         info->rx_buf_count = BufferCount - info->tx_buf_count;
3483
3484         if (info->rx_buf_count > SCAMAXDESC)
3485                 info->rx_buf_count = SCAMAXDESC;
3486
3487         if ( debug_level >= DEBUG_LEVEL_INFO )
3488                 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3489                         __FILE__,__LINE__, info->device_name,
3490                         info->tx_buf_count,info->rx_buf_count);
3491
3492         if ( alloc_buf_list( info ) < 0 ||
3493                 alloc_frame_bufs(info,
3494                                         info->rx_buf_list,
3495                                         info->rx_buf_list_ex,
3496                                         info->rx_buf_count) < 0 ||
3497                 alloc_frame_bufs(info,
3498                                         info->tx_buf_list,
3499                                         info->tx_buf_list_ex,
3500                                         info->tx_buf_count) < 0 ||
3501                 alloc_tmp_rx_buf(info) < 0 ) {
3502                 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3503                         __FILE__,__LINE__, info->device_name);
3504                 return -ENOMEM;
3505         }
3506
3507         rx_reset_buffers( info );
3508
3509         return 0;
3510 }
3511
3512 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3513  */
3514 static int alloc_buf_list(SLMP_INFO *info)
3515 {
3516         unsigned int i;
3517
3518         /* build list in adapter shared memory */
3519         info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3520         info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3521         info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3522
3523         memset(info->buffer_list, 0, BUFFERLISTSIZE);
3524
3525         /* Save virtual address pointers to the receive and */
3526         /* transmit buffer lists. (Receive 1st). These pointers will */
3527         /* be used by the processor to access the lists. */
3528         info->rx_buf_list = (SCADESC *)info->buffer_list;
3529
3530         info->tx_buf_list = (SCADESC *)info->buffer_list;
3531         info->tx_buf_list += info->rx_buf_count;
3532
3533         /* Build links for circular buffer entry lists (tx and rx)
3534          *
3535          * Note: links are physical addresses read by the SCA device
3536          * to determine the next buffer entry to use.
3537          */
3538
3539         for ( i = 0; i < info->rx_buf_count; i++ ) {
3540                 /* calculate and store physical address of this buffer entry */
3541                 info->rx_buf_list_ex[i].phys_entry =
3542                         info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3543
3544                 /* calculate and store physical address of */
3545                 /* next entry in cirular list of entries */
3546                 info->rx_buf_list[i].next = info->buffer_list_phys;
3547                 if ( i < info->rx_buf_count - 1 )
3548                         info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3549
3550                 info->rx_buf_list[i].length = SCABUFSIZE;
3551         }
3552
3553         for ( i = 0; i < info->tx_buf_count; i++ ) {
3554                 /* calculate and store physical address of this buffer entry */
3555                 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3556                         ((info->rx_buf_count + i) * sizeof(SCADESC));
3557
3558                 /* calculate and store physical address of */
3559                 /* next entry in cirular list of entries */
3560
3561                 info->tx_buf_list[i].next = info->buffer_list_phys +
3562                         info->rx_buf_count * sizeof(SCADESC);
3563
3564                 if ( i < info->tx_buf_count - 1 )
3565                         info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3566         }
3567
3568         return 0;
3569 }
3570
3571 /* Allocate the frame DMA buffers used by the specified buffer list.
3572  */
3573 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3574 {
3575         int i;
3576         unsigned long phys_addr;
3577
3578         for ( i = 0; i < count; i++ ) {
3579                 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3580                 phys_addr = info->port_array[0]->last_mem_alloc;
3581                 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3582
3583                 buf_list[i].buf_ptr  = (unsigned short)phys_addr;
3584                 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3585         }
3586
3587         return 0;
3588 }
3589
3590 static void free_dma_bufs(SLMP_INFO *info)
3591 {
3592         info->buffer_list = NULL;
3593         info->rx_buf_list = NULL;
3594         info->tx_buf_list = NULL;
3595 }
3596
3597 /* allocate buffer large enough to hold max_frame_size.
3598  * This buffer is used to pass an assembled frame to the line discipline.
3599  */
3600 static int alloc_tmp_rx_buf(SLMP_INFO *info)
3601 {
3602         info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3603         if (info->tmp_rx_buf == NULL)
3604                 return -ENOMEM;
3605         return 0;
3606 }
3607
3608 static void free_tmp_rx_buf(SLMP_INFO *info)
3609 {
3610         kfree(info->tmp_rx_buf);
3611         info->tmp_rx_buf = NULL;
3612 }
3613
3614 static int claim_resources(SLMP_INFO *info)
3615 {
3616         if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3617                 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3618                         __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3619                 info->init_error = DiagStatus_AddressConflict;
3620                 goto errout;
3621         }
3622         else
3623                 info->shared_mem_requested = true;
3624
3625         if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3626                 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3627                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3628                 info->init_error = DiagStatus_AddressConflict;
3629                 goto errout;
3630         }
3631         else
3632                 info->lcr_mem_requested = true;
3633
3634         if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3635                 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3636                         __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3637                 info->init_error = DiagStatus_AddressConflict;
3638                 goto errout;
3639         }
3640         else
3641                 info->sca_base_requested = true;
3642
3643         if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3644                 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3645                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3646                 info->init_error = DiagStatus_AddressConflict;
3647                 goto errout;
3648         }
3649         else
3650                 info->sca_statctrl_requested = true;
3651
3652         info->memory_base = ioremap_nocache(info->phys_memory_base,
3653                                                                 SCA_MEM_SIZE);
3654         if (!info->memory_base) {
3655                 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3656                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3657                 info->init_error = DiagStatus_CantAssignPciResources;
3658                 goto errout;
3659         }
3660
3661         info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE);
3662         if (!info->lcr_base) {
3663                 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3664                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3665                 info->init_error = DiagStatus_CantAssignPciResources;
3666                 goto errout;
3667         }
3668         info->lcr_base += info->lcr_offset;
3669
3670         info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE);
3671         if (!info->sca_base) {
3672                 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3673                         __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3674                 info->init_error = DiagStatus_CantAssignPciResources;
3675                 goto errout;
3676         }
3677         info->sca_base += info->sca_offset;
3678
3679         info->statctrl_base = ioremap_nocache(info->phys_statctrl_base,
3680                                                                 PAGE_SIZE);
3681         if (!info->statctrl_base) {
3682                 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3683                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3684                 info->init_error = DiagStatus_CantAssignPciResources;
3685                 goto errout;
3686         }
3687         info->statctrl_base += info->statctrl_offset;
3688
3689         if ( !memory_test(info) ) {
3690                 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3691                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3692                 info->init_error = DiagStatus_MemoryError;
3693                 goto errout;
3694         }
3695
3696         return 0;
3697
3698 errout:
3699         release_resources( info );
3700         return -ENODEV;
3701 }
3702
3703 static void release_resources(SLMP_INFO *info)
3704 {
3705         if ( debug_level >= DEBUG_LEVEL_INFO )
3706                 printk( "%s(%d):%s release_resources() entry\n",
3707                         __FILE__,__LINE__,info->device_name );
3708
3709         if ( info->irq_requested ) {
3710                 free_irq(info->irq_level, info);
3711                 info->irq_requested = false;
3712         }
3713
3714         if ( info->shared_mem_requested ) {
3715                 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3716                 info->shared_mem_requested = false;
3717         }
3718         if ( info->lcr_mem_requested ) {
3719                 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3720                 info->lcr_mem_requested = false;
3721         }
3722         if ( info->sca_base_requested ) {
3723                 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3724                 info->sca_base_requested = false;
3725         }
3726         if ( info->sca_statctrl_requested ) {
3727                 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3728                 info->sca_statctrl_requested = false;
3729         }
3730
3731         if (info->memory_base){
3732                 iounmap(info->memory_base);
3733                 info->memory_base = NULL;
3734         }
3735
3736         if (info->sca_base) {
3737                 iounmap(info->sca_base - info->sca_offset);
3738                 info->sca_base=NULL;
3739         }
3740
3741         if (info->statctrl_base) {
3742                 iounmap(info->statctrl_base - info->statctrl_offset);
3743                 info->statctrl_base=NULL;
3744         }
3745
3746         if (info->lcr_base){
3747                 iounmap(info->lcr_base - info->lcr_offset);
3748                 info->lcr_base = NULL;
3749         }
3750
3751         if ( debug_level >= DEBUG_LEVEL_INFO )
3752                 printk( "%s(%d):%s release_resources() exit\n",
3753                         __FILE__,__LINE__,info->device_name );
3754 }
3755
3756 /* Add the specified device instance data structure to the
3757  * global linked list of devices and increment the device count.
3758  */
3759 static void add_device(SLMP_INFO *info)
3760 {
3761         info->next_device = NULL;
3762         info->line = synclinkmp_device_count;
3763         sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3764
3765         if (info->line < MAX_DEVICES) {
3766                 if (maxframe[info->line])
3767                         info->max_frame_size = maxframe[info->line];
3768         }
3769
3770         synclinkmp_device_count++;
3771
3772         if ( !synclinkmp_device_list )
3773                 synclinkmp_device_list = info;
3774         else {
3775                 SLMP_INFO *current_dev = synclinkmp_device_list;
3776                 while( current_dev->next_device )
3777                         current_dev = current_dev->next_device;
3778                 current_dev->next_device = info;
3779         }
3780
3781         if ( info->max_frame_size < 4096 )
3782                 info->max_frame_size = 4096;
3783         else if ( info->max_frame_size > 65535 )
3784                 info->max_frame_size = 65535;
3785
3786         printk( "SyncLink MultiPort %s: "
3787                 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3788                 info->device_name,
3789                 info->phys_sca_base,
3790                 info->phys_memory_base,
3791                 info->phys_statctrl_base,
3792                 info->phys_lcr_base,
3793                 info->irq_level,
3794                 info->max_frame_size );
3795
3796 #if SYNCLINK_GENERIC_HDLC
3797         hdlcdev_init(info);
3798 #endif
3799 }
3800
3801 static const struct tty_port_operations port_ops = {
3802         .carrier_raised = carrier_raised,
3803         .raise_dtr_rts = raise_dtr_rts,
3804 };
3805
3806 /* Allocate and initialize a device instance structure
3807  *
3808  * Return Value:        pointer to SLMP_INFO if success, otherwise NULL
3809  */
3810 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3811 {
3812         SLMP_INFO *info;
3813
3814         info = kzalloc(sizeof(SLMP_INFO),
3815                  GFP_KERNEL);
3816
3817         if (!info) {
3818                 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3819                         __FILE__,__LINE__, adapter_num, port_num);
3820         } else {
3821                 tty_port_init(&info->port);
3822                 info->port.ops = &port_ops;
3823                 info->magic = MGSL_MAGIC;
3824                 INIT_WORK(&info->task, bh_handler);
3825                 info->max_frame_size = 4096;
3826                 info->port.close_delay = 5*HZ/10;
3827                 info->port.closing_wait = 30*HZ;
3828                 init_waitqueue_head(&info->status_event_wait_q);
3829                 init_waitqueue_head(&info->event_wait_q);
3830                 spin_lock_init(&info->netlock);
3831                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3832                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3833                 info->adapter_num = adapter_num;
3834                 info->port_num = port_num;
3835
3836                 /* Copy configuration info to device instance data */
3837                 info->irq_level = pdev->irq;
3838                 info->phys_lcr_base = pci_resource_start(pdev,0);
3839                 info->phys_sca_base = pci_resource_start(pdev,2);
3840                 info->phys_memory_base = pci_resource_start(pdev,3);
3841                 info->phys_statctrl_base = pci_resource_start(pdev,4);
3842
3843                 /* Because veremap only works on page boundaries we must map
3844                  * a larger area than is actually implemented for the LCR
3845                  * memory range. We map a full page starting at the page boundary.
3846                  */
3847                 info->lcr_offset    = info->phys_lcr_base & (PAGE_SIZE-1);
3848                 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3849
3850                 info->sca_offset    = info->phys_sca_base & (PAGE_SIZE-1);
3851                 info->phys_sca_base &= ~(PAGE_SIZE-1);
3852
3853                 info->statctrl_offset    = info->phys_statctrl_base & (PAGE_SIZE-1);
3854                 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3855
3856                 info->bus_type = MGSL_BUS_TYPE_PCI;
3857                 info->irq_flags = IRQF_SHARED;
3858
3859                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3860                 setup_timer(&info->status_timer, status_timeout,
3861                                 (unsigned long)info);
3862
3863                 /* Store the PCI9050 misc control register value because a flaw
3864                  * in the PCI9050 prevents LCR registers from being read if
3865                  * BIOS assigns an LCR base address with bit 7 set.
3866                  *
3867                  * Only the misc control register is accessed for which only
3868                  * write access is needed, so set an initial value and change
3869                  * bits to the device instance data as we write the value
3870                  * to the actual misc control register.
3871                  */
3872                 info->misc_ctrl_value = 0x087e4546;
3873
3874                 /* initial port state is unknown - if startup errors
3875                  * occur, init_error will be set to indicate the
3876                  * problem. Once the port is fully initialized,
3877                  * this value will be set to 0 to indicate the
3878                  * port is available.
3879                  */
3880                 info->init_error = -1;
3881         }
3882
3883         return info;
3884 }
3885
3886 static void device_init(int adapter_num, struct pci_dev *pdev)
3887 {
3888         SLMP_INFO *port_array[SCA_MAX_PORTS];
3889         int port;
3890
3891         /* allocate device instances for up to SCA_MAX_PORTS devices */
3892         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3893                 port_array[port] = alloc_dev(adapter_num,port,pdev);
3894                 if( port_array[port] == NULL ) {
3895                         for ( --port; port >= 0; --port )
3896                                 kfree(port_array[port]);
3897                         return;
3898                 }
3899         }
3900
3901         /* give copy of port_array to all ports and add to device list  */
3902         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3903                 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3904                 add_device( port_array[port] );
3905                 spin_lock_init(&port_array[port]->lock);
3906         }
3907
3908         /* Allocate and claim adapter resources */
3909         if ( !claim_resources(port_array[0]) ) {
3910
3911                 alloc_dma_bufs(port_array[0]);
3912
3913                 /* copy resource information from first port to others */
3914                 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3915                         port_array[port]->lock  = port_array[0]->lock;
3916                         port_array[port]->irq_level     = port_array[0]->irq_level;
3917                         port_array[port]->memory_base   = port_array[0]->memory_base;
3918                         port_array[port]->sca_base      = port_array[0]->sca_base;
3919                         port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3920                         port_array[port]->lcr_base      = port_array[0]->lcr_base;
3921                         alloc_dma_bufs(port_array[port]);
3922                 }
3923
3924                 if ( request_irq(port_array[0]->irq_level,
3925                                         synclinkmp_interrupt,
3926                                         port_array[0]->irq_flags,
3927                                         port_array[0]->device_name,
3928                                         port_array[0]) < 0 ) {
3929                         printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3930                                 __FILE__,__LINE__,
3931                                 port_array[0]->device_name,
3932                                 port_array[0]->irq_level );
3933                 }
3934                 else {
3935                         port_array[0]->irq_requested = true;
3936                         adapter_test(port_array[0]);
3937                 }
3938         }
3939 }
3940
3941 static const struct tty_operations ops = {
3942         .open = open,
3943         .close = close,
3944         .write = write,
3945         .put_char = put_char,
3946         .flush_chars = flush_chars,
3947         .write_room = write_room,
3948         .chars_in_buffer = chars_in_buffer,
3949         .flush_buffer = flush_buffer,
3950         .ioctl = ioctl,
3951         .throttle = throttle,
3952         .unthrottle = unthrottle,
3953         .send_xchar = send_xchar,
3954         .break_ctl = set_break,
3955         .wait_until_sent = wait_until_sent,
3956         .read_proc = read_proc,
3957         .set_termios = set_termios,
3958         .stop = tx_hold,
3959         .start = tx_release,
3960         .hangup = hangup,
3961         .tiocmget = tiocmget,
3962         .tiocmset = tiocmset,
3963 };
3964
3965
3966 static void synclinkmp_cleanup(void)
3967 {
3968         int rc;
3969         SLMP_INFO *info;
3970         SLMP_INFO *tmp;
3971
3972         printk("Unloading %s %s\n", driver_name, driver_version);
3973
3974         if (serial_driver) {
3975                 if ((rc = tty_unregister_driver(serial_driver)))
3976                         printk("%s(%d) failed to unregister tty driver err=%d\n",
3977                                __FILE__,__LINE__,rc);
3978                 put_tty_driver(serial_driver);
3979         }
3980
3981         /* reset devices */
3982         info = synclinkmp_device_list;
3983         while(info) {
3984                 reset_port(info);
3985                 info = info->next_device;
3986         }
3987
3988         /* release devices */
3989         info = synclinkmp_device_list;
3990         while(info) {
3991 #if SYNCLINK_GENERIC_HDLC
3992                 hdlcdev_exit(info);
3993 #endif
3994                 free_dma_bufs(info);
3995                 free_tmp_rx_buf(info);
3996                 if ( info->port_num == 0 ) {
3997                         if (info->sca_base)
3998                                 write_reg(info, LPR, 1); /* set low power mode */
3999                         release_resources(info);
4000                 }
4001                 tmp = info;
4002                 info = info->next_device;
4003                 kfree(tmp);
4004         }
4005
4006         pci_unregister_driver(&synclinkmp_pci_driver);
4007 }
4008
4009 /* Driver initialization entry point.
4010  */
4011
4012 static int __init synclinkmp_init(void)
4013 {
4014         int rc;
4015
4016         if (break_on_load) {
4017                 synclinkmp_get_text_ptr();
4018                 BREAKPOINT();
4019         }
4020
4021         printk("%s %s\n", driver_name, driver_version);
4022
4023         if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
4024                 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4025                 return rc;
4026         }
4027
4028         serial_driver = alloc_tty_driver(128);
4029         if (!serial_driver) {
4030                 rc = -ENOMEM;
4031                 goto error;
4032         }
4033
4034         /* Initialize the tty_driver structure */
4035
4036         serial_driver->owner = THIS_MODULE;
4037         serial_driver->driver_name = "synclinkmp";
4038         serial_driver->name = "ttySLM";
4039         serial_driver->major = ttymajor;
4040         serial_driver->minor_start = 64;
4041         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4042         serial_driver->subtype = SERIAL_TYPE_NORMAL;
4043         serial_driver->init_termios = tty_std_termios;
4044         serial_driver->init_termios.c_cflag =
4045                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4046         serial_driver->init_termios.c_ispeed = 9600;
4047         serial_driver->init_termios.c_ospeed = 9600;
4048         serial_driver->flags = TTY_DRIVER_REAL_RAW;
4049         tty_set_operations(serial_driver, &ops);
4050         if ((rc = tty_register_driver(serial_driver)) < 0) {
4051                 printk("%s(%d):Couldn't register serial driver\n",
4052                         __FILE__,__LINE__);
4053                 put_tty_driver(serial_driver);
4054                 serial_driver = NULL;
4055                 goto error;
4056         }
4057
4058         printk("%s %s, tty major#%d\n",
4059                 driver_name, driver_version,
4060                 serial_driver->major);
4061
4062         return 0;
4063
4064 error:
4065         synclinkmp_cleanup();
4066         return rc;
4067 }
4068
4069 static void __exit synclinkmp_exit(void)
4070 {
4071         synclinkmp_cleanup();
4072 }
4073
4074 module_init(synclinkmp_init);
4075 module_exit(synclinkmp_exit);
4076
4077 /* Set the port for internal loopback mode.
4078  * The TxCLK and RxCLK signals are generated from the BRG and
4079  * the TxD is looped back to the RxD internally.
4080  */
4081 static void enable_loopback(SLMP_INFO *info, int enable)
4082 {
4083         if (enable) {
4084                 /* MD2 (Mode Register 2)
4085                  * 01..00  CNCT<1..0> Channel Connection 11=Local Loopback
4086                  */
4087                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4088
4089                 /* degate external TxC clock source */
4090                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4091                 write_control_reg(info);
4092
4093                 /* RXS/TXS (Rx/Tx clock source)
4094                  * 07      Reserved, must be 0
4095                  * 06..04  Clock Source, 100=BRG
4096                  * 03..00  Clock Divisor, 0000=1
4097                  */
4098                 write_reg(info, RXS, 0x40);
4099                 write_reg(info, TXS, 0x40);
4100
4101         } else {
4102                 /* MD2 (Mode Register 2)
4103                  * 01..00  CNCT<1..0> Channel connection, 0=normal
4104                  */
4105                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4106
4107                 /* RXS/TXS (Rx/Tx clock source)
4108                  * 07      Reserved, must be 0
4109                  * 06..04  Clock Source, 000=RxC/TxC Pin
4110                  * 03..00  Clock Divisor, 0000=1
4111                  */
4112                 write_reg(info, RXS, 0x00);
4113                 write_reg(info, TXS, 0x00);
4114         }
4115
4116         /* set LinkSpeed if available, otherwise default to 2Mbps */
4117         if (info->params.clock_speed)
4118                 set_rate(info, info->params.clock_speed);
4119         else
4120                 set_rate(info, 3686400);
4121 }
4122
4123 /* Set the baud rate register to the desired speed
4124  *
4125  *      data_rate       data rate of clock in bits per second
4126  *                      A data rate of 0 disables the AUX clock.
4127  */
4128 static void set_rate( SLMP_INFO *info, u32 data_rate )
4129 {
4130         u32 TMCValue;
4131         unsigned char BRValue;
4132         u32 Divisor=0;
4133
4134         /* fBRG = fCLK/(TMC * 2^BR)
4135          */
4136         if (data_rate != 0) {
4137                 Divisor = 14745600/data_rate;
4138                 if (!Divisor)
4139                         Divisor = 1;
4140
4141                 TMCValue = Divisor;
4142
4143                 BRValue = 0;
4144                 if (TMCValue != 1 && TMCValue != 2) {
4145                         /* BRValue of 0 provides 50/50 duty cycle *only* when
4146                          * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4147                          * 50/50 duty cycle.
4148                          */
4149                         BRValue = 1;
4150                         TMCValue >>= 1;
4151                 }
4152
4153                 /* while TMCValue is too big for TMC register, divide
4154                  * by 2 and increment BR exponent.
4155                  */
4156                 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4157                         TMCValue >>= 1;
4158
4159                 write_reg(info, TXS,
4160                         (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4161                 write_reg(info, RXS,
4162                         (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4163                 write_reg(info, TMC, (unsigned char)TMCValue);
4164         }
4165         else {
4166                 write_reg(info, TXS,0);
4167                 write_reg(info, RXS,0);
4168                 write_reg(info, TMC, 0);
4169         }
4170 }
4171
4172 /* Disable receiver
4173  */
4174 static void rx_stop(SLMP_INFO *info)
4175 {
4176         if (debug_level >= DEBUG_LEVEL_ISR)
4177                 printk("%s(%d):%s rx_stop()\n",
4178                          __FILE__,__LINE__, info->device_name );
4179
4180         write_reg(info, CMD, RXRESET);
4181
4182         info->ie0_value &= ~RXRDYE;
4183         write_reg(info, IE0, info->ie0_value);  /* disable Rx data interrupts */
4184
4185         write_reg(info, RXDMA + DSR, 0);        /* disable Rx DMA */
4186         write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4187         write_reg(info, RXDMA + DIR, 0);        /* disable Rx DMA interrupts */
4188
4189         info->rx_enabled = false;
4190         info->rx_overflow = false;
4191 }
4192
4193 /* enable the receiver
4194  */
4195 static void rx_start(SLMP_INFO *info)
4196 {
4197         int i;
4198
4199         if (debug_level >= DEBUG_LEVEL_ISR)
4200                 printk("%s(%d):%s rx_start()\n",
4201                          __FILE__,__LINE__, info->device_name );
4202
4203         write_reg(info, CMD, RXRESET);
4204
4205         if ( info->params.mode == MGSL_MODE_HDLC ) {
4206                 /* HDLC, disabe IRQ on rxdata */
4207                 info->ie0_value &= ~RXRDYE;
4208                 write_reg(info, IE0, info->ie0_value);
4209
4210                 /* Reset all Rx DMA buffers and program rx dma */
4211                 write_reg(info, RXDMA + DSR, 0);                /* disable Rx DMA */
4212                 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4213
4214                 for (i = 0; i < info->rx_buf_count; i++) {
4215                         info->rx_buf_list[i].status = 0xff;
4216
4217                         // throttle to 4 shared memory writes at a time to prevent
4218                         // hogging local bus (keep latency time for DMA requests low).
4219                         if (!(i % 4))
4220                                 read_status_reg(info);
4221                 }
4222                 info->current_rx_buf = 0;
4223
4224                 /* set current/1st descriptor address */
4225                 write_reg16(info, RXDMA + CDA,
4226                         info->rx_buf_list_ex[0].phys_entry);
4227
4228                 /* set new last rx descriptor address */
4229                 write_reg16(info, RXDMA + EDA,
4230                         info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4231
4232                 /* set buffer length (shared by all rx dma data buffers) */
4233                 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4234
4235                 write_reg(info, RXDMA + DIR, 0x60);     /* enable Rx DMA interrupts (EOM/BOF) */
4236                 write_reg(info, RXDMA + DSR, 0xf2);     /* clear Rx DMA IRQs, enable Rx DMA */
4237         } else {
4238                 /* async, enable IRQ on rxdata */
4239                 info->ie0_value |= RXRDYE;
4240                 write_reg(info, IE0, info->ie0_value);
4241         }
4242
4243         write_reg(info, CMD, RXENABLE);
4244
4245         info->rx_overflow = false;
4246         info->rx_enabled = true;
4247 }
4248
4249 /* Enable the transmitter and send a transmit frame if
4250  * one is loaded in the DMA buffers.
4251  */
4252 static void tx_start(SLMP_INFO *info)
4253 {
4254         if (debug_level >= DEBUG_LEVEL_ISR)
4255                 printk("%s(%d):%s tx_start() tx_count=%d\n",
4256                          __FILE__,__LINE__, info->device_name,info->tx_count );
4257
4258         if (!info->tx_enabled ) {
4259                 write_reg(info, CMD, TXRESET);
4260                 write_reg(info, CMD, TXENABLE);
4261                 info->tx_enabled = true;
4262         }
4263
4264         if ( info->tx_count ) {
4265
4266                 /* If auto RTS enabled and RTS is inactive, then assert */
4267                 /* RTS and set a flag indicating that the driver should */
4268                 /* negate RTS when the transmission completes. */
4269
4270                 info->drop_rts_on_tx_done = false;
4271
4272                 if (info->params.mode != MGSL_MODE_ASYNC) {
4273
4274                         if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4275                                 get_signals( info );
4276                                 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4277                                         info->serial_signals |= SerialSignal_RTS;
4278                                         set_signals( info );
4279                                         info->drop_rts_on_tx_done = true;
4280                                 }
4281                         }
4282
4283                         write_reg16(info, TRC0,
4284                                 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4285
4286                         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4287                         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4288
4289                         /* set TX CDA (current descriptor address) */
4290                         write_reg16(info, TXDMA + CDA,
4291                                 info->tx_buf_list_ex[0].phys_entry);
4292
4293                         /* set TX EDA (last descriptor address) */
4294                         write_reg16(info, TXDMA + EDA,
4295                                 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4296
4297                         /* enable underrun IRQ */
4298                         info->ie1_value &= ~IDLE;
4299                         info->ie1_value |= UDRN;
4300                         write_reg(info, IE1, info->ie1_value);
4301                         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4302
4303                         write_reg(info, TXDMA + DIR, 0x40);             /* enable Tx DMA interrupts (EOM) */
4304                         write_reg(info, TXDMA + DSR, 0xf2);             /* clear Tx DMA IRQs, enable Tx DMA */
4305
4306                         mod_timer(&info->tx_timer, jiffies +
4307                                         msecs_to_jiffies(5000));
4308                 }
4309                 else {
4310                         tx_load_fifo(info);
4311                         /* async, enable IRQ on txdata */
4312                         info->ie0_value |= TXRDYE;
4313                         write_reg(info, IE0, info->ie0_value);
4314                 }
4315
4316                 info->tx_active = true;
4317         }
4318 }
4319
4320 /* stop the transmitter and DMA
4321  */
4322 static void tx_stop( SLMP_INFO *info )
4323 {
4324         if (debug_level >= DEBUG_LEVEL_ISR)
4325                 printk("%s(%d):%s tx_stop()\n",
4326                          __FILE__,__LINE__, info->device_name );
4327
4328         del_timer(&info->tx_timer);
4329
4330         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4331         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4332
4333         write_reg(info, CMD, TXRESET);
4334
4335         info->ie1_value &= ~(UDRN + IDLE);
4336         write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
4337         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
4338
4339         info->ie0_value &= ~TXRDYE;
4340         write_reg(info, IE0, info->ie0_value);  /* disable tx data interrupts */
4341
4342         info->tx_enabled = false;
4343         info->tx_active = false;
4344 }
4345
4346 /* Fill the transmit FIFO until the FIFO is full or
4347  * there is no more data to load.
4348  */
4349 static void tx_load_fifo(SLMP_INFO *info)
4350 {
4351         u8 TwoBytes[2];
4352
4353         /* do nothing is now tx data available and no XON/XOFF pending */
4354
4355         if ( !info->tx_count && !info->x_char )
4356                 return;
4357
4358         /* load the Transmit FIFO until FIFOs full or all data sent */
4359
4360         while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4361
4362                 /* there is more space in the transmit FIFO and */
4363                 /* there is more data in transmit buffer */
4364
4365                 if ( (info->tx_count > 1) && !info->x_char ) {
4366                         /* write 16-bits */
4367                         TwoBytes[0] = info->tx_buf[info->tx_get++];
4368                         if (info->tx_get >= info->max_frame_size)
4369                                 info->tx_get -= info->max_frame_size;
4370                         TwoBytes[1] = info->tx_buf[info->tx_get++];
4371                         if (info->tx_get >= info->max_frame_size)
4372                                 info->tx_get -= info->max_frame_size;
4373
4374                         write_reg16(info, TRB, *((u16 *)TwoBytes));
4375
4376                         info->tx_count -= 2;
4377                         info->icount.tx += 2;
4378                 } else {
4379                         /* only 1 byte left to transmit or 1 FIFO slot left */
4380
4381                         if (info->x_char) {
4382                                 /* transmit pending high priority char */
4383                                 write_reg(info, TRB, info->x_char);
4384                                 info->x_char = 0;
4385                         } else {
4386                                 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4387                                 if (info->tx_get >= info->max_frame_size)
4388                                         info->tx_get -= info->max_frame_size;
4389                                 info->tx_count--;
4390                         }
4391                         info->icount.tx++;
4392                 }
4393         }
4394 }
4395
4396 /* Reset a port to a known state
4397  */
4398 static void reset_port(SLMP_INFO *info)
4399 {
4400         if (info->sca_base) {
4401
4402                 tx_stop(info);
4403                 rx_stop(info);
4404
4405                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4406                 set_signals(info);
4407
4408                 /* disable all port interrupts */
4409                 info->ie0_value = 0;
4410                 info->ie1_value = 0;
4411                 info->ie2_value = 0;
4412                 write_reg(info, IE0, info->ie0_value);
4413                 write_reg(info, IE1, info->ie1_value);
4414                 write_reg(info, IE2, info->ie2_value);
4415
4416                 write_reg(info, CMD, CHRESET);
4417         }
4418 }
4419
4420 /* Reset all the ports to a known state.
4421  */
4422 static void reset_adapter(SLMP_INFO *info)
4423 {
4424         int i;
4425
4426         for ( i=0; i < SCA_MAX_PORTS; ++i) {
4427                 if (info->port_array[i])
4428                         reset_port(info->port_array[i]);
4429         }
4430 }
4431
4432 /* Program port for asynchronous communications.
4433  */
4434 static void async_mode(SLMP_INFO *info)
4435 {
4436
4437         unsigned char RegValue;
4438
4439         tx_stop(info);
4440         rx_stop(info);
4441
4442         /* MD0, Mode Register 0
4443          *
4444          * 07..05  PRCTL<2..0>, Protocol Mode, 000=async
4445          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4446          * 03      Reserved, must be 0
4447          * 02      CRCCC, CRC Calculation, 0=disabled
4448          * 01..00  STOP<1..0> Stop bits (00=1,10=2)
4449          *
4450          * 0000 0000
4451          */
4452         RegValue = 0x00;
4453         if (info->params.stop_bits != 1)
4454                 RegValue |= BIT1;
4455         write_reg(info, MD0, RegValue);
4456
4457         /* MD1, Mode Register 1
4458          *
4459          * 07..06  BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4460          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4461          * 03..02  RXCHR<1..0>, rx char size
4462          * 01..00  PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4463          *
4464          * 0100 0000
4465          */
4466         RegValue = 0x40;
4467         switch (info->params.data_bits) {
4468         case 7: RegValue |= BIT4 + BIT2; break;
4469         case 6: RegValue |= BIT5 + BIT3; break;
4470         case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4471         }
4472         if (info->params.parity != ASYNC_PARITY_NONE) {
4473                 RegValue |= BIT1;
4474                 if (info->params.parity == ASYNC_PARITY_ODD)
4475                         RegValue |= BIT0;
4476         }
4477         write_reg(info, MD1, RegValue);
4478
4479         /* MD2, Mode Register 2
4480          *
4481          * 07..02  Reserved, must be 0
4482          * 01..00  CNCT<1..0> Channel connection, 00=normal 11=local loopback
4483          *
4484          * 0000 0000
4485          */
4486         RegValue = 0x00;
4487         if (info->params.loopback)
4488                 RegValue |= (BIT1 + BIT0);
4489         write_reg(info, MD2, RegValue);
4490
4491         /* RXS, Receive clock source
4492          *
4493          * 07      Reserved, must be 0
4494          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4495          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4496          */
4497         RegValue=BIT6;
4498         write_reg(info, RXS, RegValue);
4499
4500         /* TXS, Transmit clock source
4501          *
4502          * 07      Reserved, must be 0
4503          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4504          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4505          */
4506         RegValue=BIT6;
4507         write_reg(info, TXS, RegValue);
4508
4509         /* Control Register
4510          *
4511          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4512          */
4513         info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4514         write_control_reg(info);
4515
4516         tx_set_idle(info);
4517
4518         /* RRC Receive Ready Control 0
4519          *
4520          * 07..05  Reserved, must be 0
4521          * 04..00  RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4522          */
4523         write_reg(info, RRC, 0x00);
4524
4525         /* TRC0 Transmit Ready Control 0
4526          *
4527          * 07..05  Reserved, must be 0
4528          * 04..00  TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4529          */
4530         write_reg(info, TRC0, 0x10);
4531
4532         /* TRC1 Transmit Ready Control 1
4533          *
4534          * 07..05  Reserved, must be 0
4535          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4536          */
4537         write_reg(info, TRC1, 0x1e);
4538
4539         /* CTL, MSCI control register
4540          *
4541          * 07..06  Reserved, set to 0
4542          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4543          * 04      IDLC, idle control, 0=mark 1=idle register
4544          * 03      BRK, break, 0=off 1 =on (async)
4545          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4546          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4547          * 00      RTS, RTS output control, 0=active 1=inactive
4548          *
4549          * 0001 0001
4550          */
4551         RegValue = 0x10;
4552         if (!(info->serial_signals & SerialSignal_RTS))
4553                 RegValue |= 0x01;
4554         write_reg(info, CTL, RegValue);
4555
4556         /* enable status interrupts */
4557         info->ie0_value |= TXINTE + RXINTE;
4558         write_reg(info, IE0, info->ie0_value);
4559
4560         /* enable break detect interrupt */
4561         info->ie1_value = BRKD;
4562         write_reg(info, IE1, info->ie1_value);
4563
4564         /* enable rx overrun interrupt */
4565         info->ie2_value = OVRN;
4566         write_reg(info, IE2, info->ie2_value);
4567
4568         set_rate( info, info->params.data_rate * 16 );
4569 }
4570
4571 /* Program the SCA for HDLC communications.
4572  */
4573 static void hdlc_mode(SLMP_INFO *info)
4574 {
4575         unsigned char RegValue;
4576         u32 DpllDivisor;
4577
4578         // Can't use DPLL because SCA outputs recovered clock on RxC when
4579         // DPLL mode selected. This causes output contention with RxC receiver.
4580         // Use of DPLL would require external hardware to disable RxC receiver
4581         // when DPLL mode selected.
4582         info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4583
4584         /* disable DMA interrupts */
4585         write_reg(info, TXDMA + DIR, 0);
4586         write_reg(info, RXDMA + DIR, 0);
4587
4588         /* MD0, Mode Register 0
4589          *
4590          * 07..05  PRCTL<2..0>, Protocol Mode, 100=HDLC
4591          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4592          * 03      Reserved, must be 0
4593          * 02      CRCCC, CRC Calculation, 1=enabled
4594          * 01      CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4595          * 00      CRC0, CRC initial value, 1 = all 1s
4596          *
4597          * 1000 0001
4598          */
4599         RegValue = 0x81;
4600         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4601                 RegValue |= BIT4;
4602         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4603                 RegValue |= BIT4;
4604         if (info->params.crc_type == HDLC_CRC_16_CCITT)
4605                 RegValue |= BIT2 + BIT1;
4606         write_reg(info, MD0, RegValue);
4607
4608         /* MD1, Mode Register 1
4609          *
4610          * 07..06  ADDRS<1..0>, Address detect, 00=no addr check
4611          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits
4612          * 03..02  RXCHR<1..0>, rx char size, 00=8 bits
4613          * 01..00  PMPM<1..0>, Parity mode, 00=no parity
4614          *
4615          * 0000 0000
4616          */
4617         RegValue = 0x00;
4618         write_reg(info, MD1, RegValue);
4619
4620         /* MD2, Mode Register 2
4621          *
4622          * 07      NRZFM, 0=NRZ, 1=FM
4623          * 06..05  CODE<1..0> Encoding, 00=NRZ
4624          * 04..03  DRATE<1..0> DPLL Divisor, 00=8
4625          * 02      Reserved, must be 0
4626          * 01..00  CNCT<1..0> Channel connection, 0=normal
4627          *
4628          * 0000 0000
4629          */
4630         RegValue = 0x00;
4631         switch(info->params.encoding) {
4632         case HDLC_ENCODING_NRZI:          RegValue |= BIT5; break;
4633         case HDLC_ENCODING_BIPHASE_MARK:  RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4634         case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4635         case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break;      /* aka Manchester */
4636 #if 0
4637         case HDLC_ENCODING_NRZB:                                        /* not supported */
4638         case HDLC_ENCODING_NRZI_MARK:                                   /* not supported */
4639         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:                          /* not supported */
4640 #endif
4641         }
4642         if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4643                 DpllDivisor = 16;
4644                 RegValue |= BIT3;
4645         } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4646                 DpllDivisor = 8;
4647         } else {
4648                 DpllDivisor = 32;
4649                 RegValue |= BIT4;
4650         }
4651         write_reg(info, MD2, RegValue);
4652
4653
4654         /* RXS, Receive clock source
4655          *
4656          * 07      Reserved, must be 0
4657          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4658          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4659          */
4660         RegValue=0;
4661         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4662                 RegValue |= BIT6;
4663         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4664                 RegValue |= BIT6 + BIT5;
4665         write_reg(info, RXS, RegValue);
4666
4667         /* TXS, Transmit clock source
4668          *
4669          * 07      Reserved, must be 0
4670          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4671          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4672          */
4673         RegValue=0;
4674         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4675                 RegValue |= BIT6;
4676         if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4677                 RegValue |= BIT6 + BIT5;
4678         write_reg(info, TXS, RegValue);
4679
4680         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4681                 set_rate(info, info->params.clock_speed * DpllDivisor);
4682         else
4683                 set_rate(info, info->params.clock_speed);
4684
4685         /* GPDATA (General Purpose I/O Data Register)
4686          *
4687          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4688          */
4689         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4690                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4691         else
4692                 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4693         write_control_reg(info);
4694
4695         /* RRC Receive Ready Control 0
4696          *
4697          * 07..05  Reserved, must be 0
4698          * 04..00  RRC<4..0> Rx FIFO trigger active
4699          */
4700         write_reg(info, RRC, rx_active_fifo_level);
4701
4702         /* TRC0 Transmit Ready Control 0
4703          *
4704          * 07..05  Reserved, must be 0
4705          * 04..00  TRC<4..0> Tx FIFO trigger active
4706          */
4707         write_reg(info, TRC0, tx_active_fifo_level);
4708
4709         /* TRC1 Transmit Ready Control 1
4710          *
4711          * 07..05  Reserved, must be 0
4712          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4713          */
4714         write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4715
4716         /* DMR, DMA Mode Register
4717          *
4718          * 07..05  Reserved, must be 0
4719          * 04      TMOD, Transfer Mode: 1=chained-block
4720          * 03      Reserved, must be 0
4721          * 02      NF, Number of Frames: 1=multi-frame
4722          * 01      CNTE, Frame End IRQ Counter enable: 0=disabled
4723          * 00      Reserved, must be 0
4724          *
4725          * 0001 0100
4726          */
4727         write_reg(info, TXDMA + DMR, 0x14);
4728         write_reg(info, RXDMA + DMR, 0x14);
4729
4730         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4731         write_reg(info, RXDMA + CPB,
4732                 (unsigned char)(info->buffer_list_phys >> 16));
4733
4734         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4735         write_reg(info, TXDMA + CPB,
4736                 (unsigned char)(info->buffer_list_phys >> 16));
4737
4738         /* enable status interrupts. other code enables/disables
4739          * the individual sources for these two interrupt classes.
4740          */
4741         info->ie0_value |= TXINTE + RXINTE;
4742         write_reg(info, IE0, info->ie0_value);
4743
4744         /* CTL, MSCI control register
4745          *
4746          * 07..06  Reserved, set to 0
4747          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4748          * 04      IDLC, idle control, 0=mark 1=idle register
4749          * 03      BRK, break, 0=off 1 =on (async)
4750          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4751          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4752          * 00      RTS, RTS output control, 0=active 1=inactive
4753          *
4754          * 0001 0001
4755          */
4756         RegValue = 0x10;
4757         if (!(info->serial_signals & SerialSignal_RTS))
4758                 RegValue |= 0x01;
4759         write_reg(info, CTL, RegValue);
4760
4761         /* preamble not supported ! */
4762
4763         tx_set_idle(info);
4764         tx_stop(info);
4765         rx_stop(info);
4766
4767         set_rate(info, info->params.clock_speed);
4768
4769         if (info->params.loopback)
4770                 enable_loopback(info,1);
4771 }
4772
4773 /* Set the transmit HDLC idle mode
4774  */
4775 static void tx_set_idle(SLMP_INFO *info)
4776 {
4777         unsigned char RegValue = 0xff;
4778
4779         /* Map API idle mode to SCA register bits */
4780         switch(info->idle_mode) {
4781         case HDLC_TXIDLE_FLAGS:                 RegValue = 0x7e; break;
4782         case HDLC_TXIDLE_ALT_ZEROS_ONES:        RegValue = 0xaa; break;
4783         case HDLC_TXIDLE_ZEROS:                 RegValue = 0x00; break;
4784         case HDLC_TXIDLE_ONES:                  RegValue = 0xff; break;
4785         case HDLC_TXIDLE_ALT_MARK_SPACE:        RegValue = 0xaa; break;
4786         case HDLC_TXIDLE_SPACE:                 RegValue = 0x00; break;
4787         case HDLC_TXIDLE_MARK:                  RegValue = 0xff; break;
4788         }
4789
4790         write_reg(info, IDL, RegValue);
4791 }
4792
4793 /* Query the adapter for the state of the V24 status (input) signals.
4794  */
4795 static void get_signals(SLMP_INFO *info)
4796 {
4797         u16 status = read_reg(info, SR3);
4798         u16 gpstatus = read_status_reg(info);
4799         u16 testbit;
4800
4801         /* clear all serial signals except DTR and RTS */
4802         info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4803
4804         /* set serial signal bits to reflect MISR */
4805
4806         if (!(status & BIT3))
4807                 info->serial_signals |= SerialSignal_CTS;
4808
4809         if ( !(status & BIT2))
4810                 info->serial_signals |= SerialSignal_DCD;
4811
4812         testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4813         if (!(gpstatus & testbit))
4814                 info->serial_signals |= SerialSignal_RI;
4815
4816         testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4817         if (!(gpstatus & testbit))
4818                 info->serial_signals |= SerialSignal_DSR;
4819 }
4820
4821 /* Set the state of DTR and RTS based on contents of
4822  * serial_signals member of device context.
4823  */
4824 static void set_signals(SLMP_INFO *info)
4825 {
4826         unsigned char RegValue;
4827         u16 EnableBit;
4828
4829         RegValue = read_reg(info, CTL);
4830         if (info->serial_signals & SerialSignal_RTS)
4831                 RegValue &= ~BIT0;
4832         else
4833                 RegValue |= BIT0;
4834         write_reg(info, CTL, RegValue);
4835
4836         // Port 0..3 DTR is ctrl reg <1,3,5,7>
4837         EnableBit = BIT1 << (info->port_num*2);
4838         if (info->serial_signals & SerialSignal_DTR)
4839                 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4840         else
4841                 info->port_array[0]->ctrlreg_value |= EnableBit;
4842         write_control_reg(info);
4843 }
4844
4845 /*******************/
4846 /* DMA Buffer Code */
4847 /*******************/
4848
4849 /* Set the count for all receive buffers to SCABUFSIZE
4850  * and set the current buffer to the first buffer. This effectively
4851  * makes all buffers free and discards any data in buffers.
4852  */
4853 static void rx_reset_buffers(SLMP_INFO *info)
4854 {
4855         rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4856 }
4857
4858 /* Free the buffers used by a received frame
4859  *
4860  * info   pointer to device instance data
4861  * first  index of 1st receive buffer of frame
4862  * last   index of last receive buffer of frame
4863  */
4864 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4865 {
4866         bool done = false;
4867
4868         while(!done) {
4869                 /* reset current buffer for reuse */
4870                 info->rx_buf_list[first].status = 0xff;
4871
4872                 if (first == last) {
4873                         done = true;
4874                         /* set new last rx descriptor address */
4875                         write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4876                 }
4877
4878                 first++;
4879                 if (first == info->rx_buf_count)
4880                         first = 0;
4881         }
4882
4883         /* set current buffer to next buffer after last buffer of frame */
4884         info->current_rx_buf = first;
4885 }
4886
4887 /* Return a received frame from the receive DMA buffers.
4888  * Only frames received without errors are returned.
4889  *
4890  * Return Value:        true if frame returned, otherwise false
4891  */
4892 static bool rx_get_frame(SLMP_INFO *info)
4893 {
4894         unsigned int StartIndex, EndIndex;      /* index of 1st and last buffers of Rx frame */
4895         unsigned short status;
4896         unsigned int framesize = 0;
4897         bool ReturnCode = false;
4898         unsigned long flags;
4899         struct tty_struct *tty = info->port.tty;
4900         unsigned char addr_field = 0xff;
4901         SCADESC *desc;
4902         SCADESC_EX *desc_ex;
4903
4904 CheckAgain:
4905         /* assume no frame returned, set zero length */
4906         framesize = 0;
4907         addr_field = 0xff;
4908
4909         /*
4910          * current_rx_buf points to the 1st buffer of the next available
4911          * receive frame. To find the last buffer of the frame look for
4912          * a non-zero status field in the buffer entries. (The status
4913          * field is set by the 16C32 after completing a receive frame.
4914          */
4915         StartIndex = EndIndex = info->current_rx_buf;
4916
4917         for ( ;; ) {
4918                 desc = &info->rx_buf_list[EndIndex];
4919                 desc_ex = &info->rx_buf_list_ex[EndIndex];
4920
4921                 if (desc->status == 0xff)
4922                         goto Cleanup;   /* current desc still in use, no frames available */
4923
4924                 if (framesize == 0 && info->params.addr_filter != 0xff)
4925                         addr_field = desc_ex->virt_addr[0];
4926
4927                 framesize += desc->length;
4928
4929                 /* Status != 0 means last buffer of frame */
4930                 if (desc->status)
4931                         break;
4932
4933                 EndIndex++;
4934                 if (EndIndex == info->rx_buf_count)
4935                         EndIndex = 0;
4936
4937                 if (EndIndex == info->current_rx_buf) {
4938                         /* all buffers have been 'used' but none mark      */
4939                         /* the end of a frame. Reset buffers and receiver. */
4940                         if ( info->rx_enabled ){
4941                                 spin_lock_irqsave(&info->lock,flags);
4942                                 rx_start(info);
4943                                 spin_unlock_irqrestore(&info->lock,flags);
4944                         }
4945                         goto Cleanup;
4946                 }
4947
4948         }
4949
4950         /* check status of receive frame */
4951
4952         /* frame status is byte stored after frame data
4953          *
4954          * 7 EOM (end of msg), 1 = last buffer of frame
4955          * 6 Short Frame, 1 = short frame
4956          * 5 Abort, 1 = frame aborted
4957          * 4 Residue, 1 = last byte is partial
4958          * 3 Overrun, 1 = overrun occurred during frame reception
4959          * 2 CRC,     1 = CRC error detected
4960          *
4961          */
4962         status = desc->status;
4963
4964         /* ignore CRC bit if not using CRC (bit is undefined) */
4965         /* Note:CRC is not save to data buffer */
4966         if (info->params.crc_type == HDLC_CRC_NONE)
4967                 status &= ~BIT2;
4968
4969         if (framesize == 0 ||
4970                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4971                 /* discard 0 byte frames, this seems to occur sometime
4972                  * when remote is idling flags.
4973                  */
4974                 rx_free_frame_buffers(info, StartIndex, EndIndex);
4975                 goto CheckAgain;
4976         }
4977
4978         if (framesize < 2)
4979                 status |= BIT6;
4980
4981         if (status & (BIT6+BIT5+BIT3+BIT2)) {
4982                 /* received frame has errors,
4983                  * update counts and mark frame size as 0
4984                  */
4985                 if (status & BIT6)
4986                         info->icount.rxshort++;
4987                 else if (status & BIT5)
4988                         info->icount.rxabort++;
4989                 else if (status & BIT3)
4990                         info->icount.rxover++;
4991                 else
4992                         info->icount.rxcrc++;
4993
4994                 framesize = 0;
4995 #if SYNCLINK_GENERIC_HDLC
4996                 {
4997                         info->netdev->stats.rx_errors++;
4998                         info->netdev->stats.rx_frame_errors++;
4999                 }
5000 #endif
5001         }
5002
5003         if ( debug_level >= DEBUG_LEVEL_BH )
5004                 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
5005                         __FILE__,__LINE__,info->device_name,status,framesize);
5006
5007         if ( debug_level >= DEBUG_LEVEL_DATA )
5008                 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
5009                         min_t(int, framesize,SCABUFSIZE),0);
5010
5011         if (framesize) {
5012                 if (framesize > info->max_frame_size)
5013                         info->icount.rxlong++;
5014                 else {
5015                         /* copy dma buffer(s) to contiguous intermediate buffer */
5016                         int copy_count = framesize;
5017                         int index = StartIndex;
5018                         unsigned char *ptmp = info->tmp_rx_buf;
5019                         info->tmp_rx_buf_count = framesize;
5020
5021                         info->icount.rxok++;
5022
5023                         while(copy_count) {
5024                                 int partial_count = min(copy_count,SCABUFSIZE);
5025                                 memcpy( ptmp,
5026                                         info->rx_buf_list_ex[index].virt_addr,
5027                                         partial_count );
5028                                 ptmp += partial_count;
5029                                 copy_count -= partial_count;
5030
5031                                 if ( ++index == info->rx_buf_count )
5032                                         index = 0;
5033                         }
5034
5035 #if SYNCLINK_GENERIC_HDLC
5036                         if (info->netcount)
5037                                 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
5038                         else
5039 #endif
5040                                 ldisc_receive_buf(tty,info->tmp_rx_buf,
5041                                                   info->flag_buf, framesize);
5042                 }
5043         }
5044         /* Free the buffers used by this frame. */
5045         rx_free_frame_buffers( info, StartIndex, EndIndex );
5046
5047         ReturnCode = true;
5048
5049 Cleanup:
5050         if ( info->rx_enabled && info->rx_overflow ) {
5051                 /* Receiver is enabled, but needs to restarted due to
5052                  * rx buffer overflow. If buffers are empty, restart receiver.
5053                  */
5054                 if (info->rx_buf_list[EndIndex].status == 0xff) {
5055                         spin_lock_irqsave(&info->lock,flags);
5056                         rx_start(info);
5057                         spin_unlock_irqrestore(&info->lock,flags);
5058                 }
5059         }
5060
5061         return ReturnCode;
5062 }
5063
5064 /* load the transmit DMA buffer with data
5065  */
5066 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5067 {
5068         unsigned short copy_count;
5069         unsigned int i = 0;
5070         SCADESC *desc;
5071         SCADESC_EX *desc_ex;
5072
5073         if ( debug_level >= DEBUG_LEVEL_DATA )
5074                 trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
5075
5076         /* Copy source buffer to one or more DMA buffers, starting with
5077          * the first transmit dma buffer.
5078          */
5079         for(i=0;;)
5080         {
5081                 copy_count = min_t(unsigned short,count,SCABUFSIZE);
5082
5083                 desc = &info->tx_buf_list[i];
5084                 desc_ex = &info->tx_buf_list_ex[i];
5085
5086                 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5087
5088                 desc->length = copy_count;
5089                 desc->status = 0;
5090
5091                 buf += copy_count;
5092                 count -= copy_count;
5093
5094                 if (!count)
5095                         break;
5096
5097                 i++;
5098                 if (i >= info->tx_buf_count)
5099                         i = 0;
5100         }
5101
5102         info->tx_buf_list[i].status = 0x81;     /* set EOM and EOT status */
5103         info->last_tx_buf = ++i;
5104 }
5105
5106 static bool register_test(SLMP_INFO *info)
5107 {
5108         static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5109         static unsigned int count = ARRAY_SIZE(testval);
5110         unsigned int i;
5111         bool rc = true;
5112         unsigned long flags;
5113
5114         spin_lock_irqsave(&info->lock,flags);
5115         reset_port(info);
5116
5117         /* assume failure */
5118         info->init_error = DiagStatus_AddressFailure;
5119
5120         /* Write bit patterns to various registers but do it out of */
5121         /* sync, then read back and verify values. */
5122
5123         for (i = 0 ; i < count ; i++) {
5124                 write_reg(info, TMC, testval[i]);
5125                 write_reg(info, IDL, testval[(i+1)%count]);
5126                 write_reg(info, SA0, testval[(i+2)%count]);
5127                 write_reg(info, SA1, testval[(i+3)%count]);
5128
5129                 if ( (read_reg(info, TMC) != testval[i]) ||
5130                           (read_reg(info, IDL) != testval[(i+1)%count]) ||
5131                           (read_reg(info, SA0) != testval[(i+2)%count]) ||
5132                           (read_reg(info, SA1) != testval[(i+3)%count]) )
5133                 {
5134                         rc = false;
5135                         break;
5136                 }
5137         }
5138
5139         reset_port(info);
5140         spin_unlock_irqrestore(&info->lock,flags);
5141
5142         return rc;
5143 }
5144
5145 static bool irq_test(SLMP_INFO *info)
5146 {
5147         unsigned long timeout;
5148         unsigned long flags;
5149
5150         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5151
5152         spin_lock_irqsave(&info->lock,flags);
5153         reset_port(info);
5154
5155         /* assume failure */
5156         info->init_error = DiagStatus_IrqFailure;
5157         info->irq_occurred = false;
5158
5159         /* setup timer0 on SCA0 to interrupt */
5160
5161         /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5162         write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5163
5164         write_reg(info, (unsigned char)(timer + TEPR), 0);      /* timer expand prescale */
5165         write_reg16(info, (unsigned char)(timer + TCONR), 1);   /* timer constant */
5166
5167
5168         /* TMCS, Timer Control/Status Register
5169          *
5170          * 07      CMF, Compare match flag (read only) 1=match
5171          * 06      ECMI, CMF Interrupt Enable: 1=enabled
5172          * 05      Reserved, must be 0
5173          * 04      TME, Timer Enable
5174          * 03..00  Reserved, must be 0
5175          *
5176          * 0101 0000
5177          */
5178         write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5179
5180         spin_unlock_irqrestore(&info->lock,flags);
5181
5182         timeout=100;
5183         while( timeout-- && !info->irq_occurred ) {
5184                 msleep_interruptible(10);
5185         }
5186
5187         spin_lock_irqsave(&info->lock,flags);
5188         reset_port(info);
5189         spin_unlock_irqrestore(&info->lock,flags);
5190
5191         return info->irq_occurred;
5192 }
5193
5194 /* initialize individual SCA device (2 ports)
5195  */
5196 static bool sca_init(SLMP_INFO *info)
5197 {
5198         /* set wait controller to single mem partition (low), no wait states */
5199         write_reg(info, PABR0, 0);      /* wait controller addr boundary 0 */
5200         write_reg(info, PABR1, 0);      /* wait controller addr boundary 1 */
5201         write_reg(info, WCRL, 0);       /* wait controller low range */
5202         write_reg(info, WCRM, 0);       /* wait controller mid range */
5203         write_reg(info, WCRH, 0);       /* wait controller high range */
5204
5205         /* DPCR, DMA Priority Control
5206          *
5207          * 07..05  Not used, must be 0
5208          * 04      BRC, bus release condition: 0=all transfers complete
5209          * 03      CCC, channel change condition: 0=every cycle
5210          * 02..00  PR<2..0>, priority 100=round robin
5211          *
5212          * 00000100 = 0x04
5213          */
5214         write_reg(info, DPCR, dma_priority);
5215
5216         /* DMA Master Enable, BIT7: 1=enable all channels */
5217         write_reg(info, DMER, 0x80);
5218
5219         /* enable all interrupt classes */
5220         write_reg(info, IER0, 0xff);    /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5221         write_reg(info, IER1, 0xff);    /* DMIB,DMIA (channels 0-3) */
5222         write_reg(info, IER2, 0xf0);    /* TIRQ (timers 0-3) */
5223
5224         /* ITCR, interrupt control register
5225          * 07      IPC, interrupt priority, 0=MSCI->DMA
5226          * 06..05  IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5227          * 04      VOS, Vector Output, 0=unmodified vector
5228          * 03..00  Reserved, must be 0
5229          */
5230         write_reg(info, ITCR, 0);
5231
5232         return true;
5233 }
5234
5235 /* initialize adapter hardware
5236  */
5237 static bool init_adapter(SLMP_INFO *info)
5238 {
5239         int i;
5240
5241         /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5242         volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5243         u32 readval;
5244
5245         info->misc_ctrl_value |= BIT30;
5246         *MiscCtrl = info->misc_ctrl_value;
5247
5248         /*
5249          * Force at least 170ns delay before clearing
5250          * reset bit. Each read from LCR takes at least
5251          * 30ns so 10 times for 300ns to be safe.
5252          */
5253         for(i=0;i<10;i++)
5254                 readval = *MiscCtrl;
5255
5256         info->misc_ctrl_value &= ~BIT30;
5257         *MiscCtrl = info->misc_ctrl_value;
5258
5259         /* init control reg (all DTRs off, all clksel=input) */
5260         info->ctrlreg_value = 0xaa;
5261         write_control_reg(info);
5262
5263         {
5264                 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5265                 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5266
5267                 switch(read_ahead_count)
5268                 {
5269                 case 16:
5270                         lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5271                         break;
5272                 case 8:
5273                         lcr1_brdr_value |= BIT5 + BIT4;
5274                         break;
5275                 case 4:
5276                         lcr1_brdr_value |= BIT5 + BIT3;
5277                         break;
5278                 case 0:
5279                         lcr1_brdr_value |= BIT5;
5280                         break;
5281                 }
5282
5283                 *LCR1BRDR = lcr1_brdr_value;
5284                 *MiscCtrl = misc_ctrl_value;
5285         }
5286
5287         sca_init(info->port_array[0]);
5288         sca_init(info->port_array[2]);
5289
5290         return true;
5291 }
5292
5293 /* Loopback an HDLC frame to test the hardware
5294  * interrupt and DMA functions.
5295  */
5296 static bool loopback_test(SLMP_INFO *info)
5297 {
5298 #define TESTFRAMESIZE 20
5299
5300         unsigned long timeout;
5301         u16 count = TESTFRAMESIZE;
5302         unsigned char buf[TESTFRAMESIZE];
5303         bool rc = false;
5304         unsigned long flags;
5305
5306         struct tty_struct *oldtty = info->port.tty;
5307         u32 speed = info->params.clock_speed;
5308
5309         info->params.clock_speed = 3686400;
5310         info->port.tty = NULL;
5311
5312         /* assume failure */
5313         info->init_error = DiagStatus_DmaFailure;
5314
5315         /* build and send transmit frame */
5316         for (count = 0; count < TESTFRAMESIZE;++count)
5317                 buf[count] = (unsigned char)count;
5318
5319         memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5320
5321         /* program hardware for HDLC and enabled receiver */
5322         spin_lock_irqsave(&info->lock,flags);
5323         hdlc_mode(info);
5324         enable_loopback(info,1);
5325         rx_start(info);
5326         info->tx_count = count;
5327         tx_load_dma_buffer(info,buf,count);
5328         tx_start(info);
5329         spin_unlock_irqrestore(&info->lock,flags);
5330
5331         /* wait for receive complete */
5332         /* Set a timeout for waiting for interrupt. */
5333         for ( timeout = 100; timeout; --timeout ) {
5334                 msleep_interruptible(10);
5335
5336                 if (rx_get_frame(info)) {
5337                         rc = true;
5338                         break;
5339                 }
5340         }
5341
5342         /* verify received frame length and contents */
5343         if (rc &&
5344             ( info->tmp_rx_buf_count != count ||
5345               memcmp(buf, info->tmp_rx_buf,count))) {
5346                 rc = false;
5347         }
5348
5349         spin_lock_irqsave(&info->lock,flags);
5350         reset_adapter(info);
5351         spin_unlock_irqrestore(&info->lock,flags);
5352
5353         info->params.clock_speed = speed;
5354         info->port.tty = oldtty;
5355
5356         return rc;
5357 }
5358
5359 /* Perform diagnostics on hardware
5360  */
5361 static int adapter_test( SLMP_INFO *info )
5362 {
5363         unsigned long flags;
5364         if ( debug_level >= DEBUG_LEVEL_INFO )
5365                 printk( "%s(%d):Testing device %s\n",
5366                         __FILE__,__LINE__,info->device_name );
5367
5368         spin_lock_irqsave(&info->lock,flags);
5369         init_adapter(info);
5370         spin_unlock_irqrestore(&info->lock,flags);
5371
5372         info->port_array[0]->port_count = 0;
5373
5374         if ( register_test(info->port_array[0]) &&
5375                 register_test(info->port_array[1])) {
5376
5377                 info->port_array[0]->port_count = 2;
5378
5379                 if ( register_test(info->port_array[2]) &&
5380                         register_test(info->port_array[3]) )
5381                         info->port_array[0]->port_count += 2;
5382         }
5383         else {
5384                 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5385                         __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5386                 return -ENODEV;
5387         }
5388
5389         if ( !irq_test(info->port_array[0]) ||
5390                 !irq_test(info->port_array[1]) ||
5391                  (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5392                  (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5393                 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5394                         __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5395                 return -ENODEV;
5396         }
5397
5398         if (!loopback_test(info->port_array[0]) ||
5399                 !loopback_test(info->port_array[1]) ||
5400                  (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5401                  (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5402                 printk( "%s(%d):DMA test failure for device %s\n",
5403                         __FILE__,__LINE__,info->device_name);
5404                 return -ENODEV;
5405         }
5406
5407         if ( debug_level >= DEBUG_LEVEL_INFO )
5408                 printk( "%s(%d):device %s passed diagnostics\n",
5409                         __FILE__,__LINE__,info->device_name );
5410
5411         info->port_array[0]->init_error = 0;
5412         info->port_array[1]->init_error = 0;
5413         if ( info->port_count > 2 ) {
5414                 info->port_array[2]->init_error = 0;
5415                 info->port_array[3]->init_error = 0;
5416         }
5417
5418         return 0;
5419 }
5420
5421 /* Test the shared memory on a PCI adapter.
5422  */
5423 static bool memory_test(SLMP_INFO *info)
5424 {
5425         static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5426                 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5427         unsigned long count = ARRAY_SIZE(testval);
5428         unsigned long i;
5429         unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5430         unsigned long * addr = (unsigned long *)info->memory_base;
5431
5432         /* Test data lines with test pattern at one location. */
5433
5434         for ( i = 0 ; i < count ; i++ ) {
5435                 *addr = testval[i];
5436                 if ( *addr != testval[i] )
5437                         return false;
5438         }
5439
5440         /* Test address lines with incrementing pattern over */
5441         /* entire address range. */
5442
5443         for ( i = 0 ; i < limit ; i++ ) {
5444                 *addr = i * 4;
5445                 addr++;
5446         }
5447
5448         addr = (unsigned long *)info->memory_base;
5449
5450         for ( i = 0 ; i < limit ; i++ ) {
5451                 if ( *addr != i * 4 )
5452                         return false;
5453                 addr++;
5454         }
5455
5456         memset( info->memory_base, 0, SCA_MEM_SIZE );
5457         return true;
5458 }
5459
5460 /* Load data into PCI adapter shared memory.
5461  *
5462  * The PCI9050 releases control of the local bus
5463  * after completing the current read or write operation.
5464  *
5465  * While the PCI9050 write FIFO not empty, the
5466  * PCI9050 treats all of the writes as a single transaction
5467  * and does not release the bus. This causes DMA latency problems
5468  * at high speeds when copying large data blocks to the shared memory.
5469  *
5470  * This function breaks a write into multiple transations by
5471  * interleaving a read which flushes the write FIFO and 'completes'
5472  * the write transation. This allows any pending DMA request to gain control
5473  * of the local bus in a timely fasion.
5474  */
5475 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5476 {
5477         /* A load interval of 16 allows for 4 32-bit writes at */
5478         /* 136ns each for a maximum latency of 542ns on the local bus.*/
5479
5480         unsigned short interval = count / sca_pci_load_interval;
5481         unsigned short i;
5482
5483         for ( i = 0 ; i < interval ; i++ )
5484         {
5485                 memcpy(dest, src, sca_pci_load_interval);
5486                 read_status_reg(info);
5487                 dest += sca_pci_load_interval;
5488                 src += sca_pci_load_interval;
5489         }
5490
5491         memcpy(dest, src, count % sca_pci_load_interval);
5492 }
5493
5494 static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5495 {
5496         int i;
5497         int linecount;
5498         if (xmit)
5499                 printk("%s tx data:\n",info->device_name);
5500         else
5501                 printk("%s rx data:\n",info->device_name);
5502
5503         while(count) {
5504                 if (count > 16)
5505                         linecount = 16;
5506                 else
5507                         linecount = count;
5508
5509                 for(i=0;i<linecount;i++)
5510                         printk("%02X ",(unsigned char)data[i]);
5511                 for(;i<17;i++)
5512                         printk("   ");
5513                 for(i=0;i<linecount;i++) {
5514                         if (data[i]>=040 && data[i]<=0176)
5515                                 printk("%c",data[i]);
5516                         else
5517                                 printk(".");
5518                 }
5519                 printk("\n");
5520
5521                 data  += linecount;
5522                 count -= linecount;
5523         }
5524 }       /* end of trace_block() */
5525
5526 /* called when HDLC frame times out
5527  * update stats and do tx completion processing
5528  */
5529 static void tx_timeout(unsigned long context)
5530 {
5531         SLMP_INFO *info = (SLMP_INFO*)context;
5532         unsigned long flags;
5533
5534         if ( debug_level >= DEBUG_LEVEL_INFO )
5535                 printk( "%s(%d):%s tx_timeout()\n",
5536                         __FILE__,__LINE__,info->device_name);
5537         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5538                 info->icount.txtimeout++;
5539         }
5540         spin_lock_irqsave(&info->lock,flags);
5541         info->tx_active = false;
5542         info->tx_count = info->tx_put = info->tx_get = 0;
5543
5544         spin_unlock_irqrestore(&info->lock,flags);
5545
5546 #if SYNCLINK_GENERIC_HDLC
5547         if (info->netcount)
5548                 hdlcdev_tx_done(info);
5549         else
5550 #endif
5551                 bh_transmit(info);
5552 }
5553
5554 /* called to periodically check the DSR/RI modem signal input status
5555  */
5556 static void status_timeout(unsigned long context)
5557 {
5558         u16 status = 0;
5559         SLMP_INFO *info = (SLMP_INFO*)context;
5560         unsigned long flags;
5561         unsigned char delta;
5562
5563
5564         spin_lock_irqsave(&info->lock,flags);
5565         get_signals(info);
5566         spin_unlock_irqrestore(&info->lock,flags);
5567
5568         /* check for DSR/RI state change */
5569
5570         delta = info->old_signals ^ info->serial_signals;
5571         info->old_signals = info->serial_signals;
5572
5573         if (delta & SerialSignal_DSR)
5574                 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5575
5576         if (delta & SerialSignal_RI)
5577                 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5578
5579         if (delta & SerialSignal_DCD)
5580                 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5581
5582         if (delta & SerialSignal_CTS)
5583                 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5584
5585         if (status)
5586                 isr_io_pin(info,status);
5587
5588         mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5589 }
5590
5591
5592 /* Register Access Routines -
5593  * All registers are memory mapped
5594  */
5595 #define CALC_REGADDR() \
5596         unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5597         if (info->port_num > 1) \
5598                 RegAddr += 256;                 /* port 0-1 SCA0, 2-3 SCA1 */ \
5599         if ( info->port_num & 1) { \
5600                 if (Addr > 0x7f) \
5601                         RegAddr += 0x40;        /* DMA access */ \
5602                 else if (Addr > 0x1f && Addr < 0x60) \
5603                         RegAddr += 0x20;        /* MSCI access */ \
5604         }
5605
5606
5607 static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5608 {
5609         CALC_REGADDR();
5610         return *RegAddr;
5611 }
5612 static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5613 {
5614         CALC_REGADDR();
5615         *RegAddr = Value;
5616 }
5617
5618 static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5619 {
5620         CALC_REGADDR();
5621         return *((u16 *)RegAddr);
5622 }
5623
5624 static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5625 {
5626         CALC_REGADDR();
5627         *((u16 *)RegAddr) = Value;
5628 }
5629
5630 static unsigned char read_status_reg(SLMP_INFO * info)
5631 {
5632         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5633         return *RegAddr;
5634 }
5635
5636 static void write_control_reg(SLMP_INFO * info)
5637 {
5638         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5639         *RegAddr = info->port_array[0]->ctrlreg_value;
5640 }
5641
5642
5643 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5644                                           const struct pci_device_id *ent)
5645 {
5646         if (pci_enable_device(dev)) {
5647                 printk("error enabling pci device %p\n", dev);
5648                 return -EIO;
5649         }
5650         device_init( ++synclinkmp_adapter_count, dev );
5651         return 0;
5652 }
5653
5654 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5655 {
5656 }