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   1 /*
   2  * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink Multiport
   5  * high speed multiprotocol serial adapter.
   6  *
   7  * written by Paul Fulghum for Microgate Corporation
   8  * paulkf@microgate.com
   9  *
  10  * Microgate and SyncLink are trademarks of Microgate Corporation
  11  *
  12  * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
  13  * This code is released under the GNU General Public License (GPL)
  14  *
  15  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  25  * OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29 #if defined(__i386__)
  30 #  define BREAKPOINT() asm("   int $3");
  31 #else
  32 #  define BREAKPOINT() { }
  33 #endif
  34
  35 #define MAX_DEVICES 12
  36
  37 #include <linux/module.h>
  38 #include <linux/errno.h>
  39 #include <linux/signal.h>
  40 #include <linux/sched.h>
  41 #include <linux/timer.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/pci.h>
  44 #include <linux/tty.h>
  45 #include <linux/tty_flip.h>
  46 #include <linux/serial.h>
  47 #include <linux/major.h>
  48 #include <linux/string.h>
  49 #include <linux/fcntl.h>
  50 #include <linux/ptrace.h>
  51 #include <linux/ioport.h>
  52 #include <linux/mm.h>
  53 #include <linux/slab.h>
  54 #include <linux/netdevice.h>
  55 #include <linux/vmalloc.h>
  56 #include <linux/init.h>
  57 #include <linux/delay.h>
  58 #include <linux/ioctl.h>
  59
  60 #include <asm/system.h>
  61 #include <asm/io.h>
  62 #include <asm/irq.h>
  63 #include <asm/dma.h>
  64 #include <linux/bitops.h>
  65 #include <asm/types.h>
  66 #include <linux/termios.h>
  67 #include <linux/workqueue.h>
  68 #include <linux/hdlc.h>
  69 #include <linux/synclink.h>
  70
  71 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
  72 #define SYNCLINK_GENERIC_HDLC 1
  73 #else
  74 #define SYNCLINK_GENERIC_HDLC 0
  75 #endif
  76
  77 #define GET_USER(error,value,addr) error = get_user(value,addr)
  78 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  79 #define PUT_USER(error,value,addr) error = put_user(value,addr)
  80 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  81
  82 #include <asm/uaccess.h>
  83
  84 static MGSL_PARAMS default_params = {
  85         MGSL_MODE_HDLC,                 /* unsigned long mode */
  86         0,                              /* unsigned char loopback; */
  87         HDLC_FLAG_UNDERRUN_ABORT15,     /* unsigned short flags; */
  88         HDLC_ENCODING_NRZI_SPACE,       /* unsigned char encoding; */
  89         0,                              /* unsigned long clock_speed; */
  90         0xff,                           /* unsigned char addr_filter; */
  91         HDLC_CRC_16_CCITT,              /* unsigned short crc_type; */
  92         HDLC_PREAMBLE_LENGTH_8BITS,     /* unsigned char preamble_length; */
  93         HDLC_PREAMBLE_PATTERN_NONE,     /* unsigned char preamble; */
  94         9600,                           /* unsigned long data_rate; */
  95         8,                              /* unsigned char data_bits; */
  96         1,                              /* unsigned char stop_bits; */
  97         ASYNC_PARITY_NONE               /* unsigned char parity; */
  98 };
  99
 100 /* size in bytes of DMA data buffers */
 101 #define SCABUFSIZE      1024
 102 #define SCA_MEM_SIZE    0x40000
 103 #define SCA_BASE_SIZE   512
 104 #define SCA_REG_SIZE    16
 105 #define SCA_MAX_PORTS   4
 106 #define SCAMAXDESC      128
 107
 108 #define BUFFERLISTSIZE  4096
 109
 110 /* SCA-I style DMA buffer descriptor */
 111 typedef struct _SCADESC
 112 {
 113         u16     next;           /* lower l6 bits of next descriptor addr */
 114         u16     buf_ptr;        /* lower 16 bits of buffer addr */
 115         u8      buf_base;       /* upper 8 bits of buffer addr */
 116         u8      pad1;
 117         u16     length;         /* length of buffer */
 118         u8      status;         /* status of buffer */
 119         u8      pad2;
 120 } SCADESC, *PSCADESC;
 121
 122 typedef struct _SCADESC_EX
 123 {
 124         /* device driver bookkeeping section */
 125         char    *virt_addr;     /* virtual address of data buffer */
 126         u16     phys_entry;     /* lower 16-bits of physical address of this descriptor */
 127 } SCADESC_EX, *PSCADESC_EX;
 128
 129 /* The queue of BH actions to be performed */
 130
 131 #define BH_RECEIVE  1
 132 #define BH_TRANSMIT 2
 133 #define BH_STATUS   4
 134
 135 #define IO_PIN_SHUTDOWN_LIMIT 100
 136
 137 struct  _input_signal_events {
 138         int     ri_up;
 139         int     ri_down;
 140         int     dsr_up;
 141         int     dsr_down;
 142         int     dcd_up;
 143         int     dcd_down;
 144         int     cts_up;
 145         int     cts_down;
 146 };
 147
 148 /*
 149  * Device instance data structure
 150  */
 151 typedef struct _synclinkmp_info {
 152         void *if_ptr;                           /* General purpose pointer (used by SPPP) */
 153         int                     magic;
 154         struct tty_port         port;
 155         int                     line;
 156         unsigned short          close_delay;
 157         unsigned short          closing_wait;   /* time to wait before closing */
 158
 159         struct mgsl_icount      icount;
 160
 161         int                     timeout;
 162         int                     x_char;         /* xon/xoff character */
 163         u16                     read_status_mask1;  /* break detection (SR1 indications) */
 164         u16                     read_status_mask2;  /* parity/framing/overun (SR2 indications) */
 165         unsigned char           ignore_status_mask1;  /* break detection (SR1 indications) */
 166         unsigned char           ignore_status_mask2;  /* parity/framing/overun (SR2 indications) */
 167         unsigned char           *tx_buf;
 168         int                     tx_put;
 169         int                     tx_get;
 170         int                     tx_count;
 171
 172         wait_queue_head_t       status_event_wait_q;
 173         wait_queue_head_t       event_wait_q;
 174         struct timer_list       tx_timer;       /* HDLC transmit timeout timer */
 175         struct _synclinkmp_info *next_device;   /* device list link */
 176         struct timer_list       status_timer;   /* input signal status check timer */
 177
 178         spinlock_t lock;                /* spinlock for synchronizing with ISR */
 179         struct work_struct task;                        /* task structure for scheduling bh */
 180
 181         u32 max_frame_size;                     /* as set by device config */
 182
 183         u32 pending_bh;
 184
 185         bool bh_running;                                /* Protection from multiple */
 186         int isr_overflow;
 187         bool bh_requested;
 188
 189         int dcd_chkcount;                       /* check counts to prevent */
 190         int cts_chkcount;                       /* too many IRQs if a signal */
 191         int dsr_chkcount;                       /* is floating */
 192         int ri_chkcount;
 193
 194         char *buffer_list;                      /* virtual address of Rx & Tx buffer lists */
 195         unsigned long buffer_list_phys;
 196
 197         unsigned int rx_buf_count;              /* count of total allocated Rx buffers */
 198         SCADESC *rx_buf_list;                   /* list of receive buffer entries */
 199         SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
 200         unsigned int current_rx_buf;
 201
 202         unsigned int tx_buf_count;              /* count of total allocated Tx buffers */
 203         SCADESC *tx_buf_list;           /* list of transmit buffer entries */
 204         SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
 205         unsigned int last_tx_buf;
 206
 207         unsigned char *tmp_rx_buf;
 208         unsigned int tmp_rx_buf_count;
 209
 210         bool rx_enabled;
 211         bool rx_overflow;
 212
 213         bool tx_enabled;
 214         bool tx_active;
 215         u32 idle_mode;
 216
 217         unsigned char ie0_value;
 218         unsigned char ie1_value;
 219         unsigned char ie2_value;
 220         unsigned char ctrlreg_value;
 221         unsigned char old_signals;
 222
 223         char device_name[25];                   /* device instance name */
 224
 225         int port_count;
 226         int adapter_num;
 227         int port_num;
 228
 229         struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
 230
 231         unsigned int bus_type;                  /* expansion bus type (ISA,EISA,PCI) */
 232
 233         unsigned int irq_level;                 /* interrupt level */
 234         unsigned long irq_flags;
 235         bool irq_requested;                     /* true if IRQ requested */
 236
 237         MGSL_PARAMS params;                     /* communications parameters */
 238
 239         unsigned char serial_signals;           /* current serial signal states */
 240
 241         bool irq_occurred;                      /* for diagnostics use */
 242         unsigned int init_error;                /* Initialization startup error */
 243
 244         u32 last_mem_alloc;
 245         unsigned char* memory_base;             /* shared memory address (PCI only) */
 246         u32 phys_memory_base;
 247         int shared_mem_requested;
 248
 249         unsigned char* sca_base;                /* HD64570 SCA Memory address */
 250         u32 phys_sca_base;
 251         u32 sca_offset;
 252         bool sca_base_requested;
 253
 254         unsigned char* lcr_base;                /* local config registers (PCI only) */
 255         u32 phys_lcr_base;
 256         u32 lcr_offset;
 257         int lcr_mem_requested;
 258
 259         unsigned char* statctrl_base;           /* status/control register memory */
 260         u32 phys_statctrl_base;
 261         u32 statctrl_offset;
 262         bool sca_statctrl_requested;
 263
 264         u32 misc_ctrl_value;
 265         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 266         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 267         bool drop_rts_on_tx_done;
 268
 269         struct  _input_signal_events    input_signal_events;
 270
 271         /* SPPP/Cisco HDLC device parts */
 272         int netcount;
 273         spinlock_t netlock;
 274
 275 #if SYNCLINK_GENERIC_HDLC
 276         struct net_device *netdev;
 277 #endif
 278
 279 } SLMP_INFO;
 280
 281 #define MGSL_MAGIC 0x5401
 282
 283 /*
 284  * define serial signal status change macros
 285  */
 286 #define MISCSTATUS_DCD_LATCHED  (SerialSignal_DCD<<8)   /* indicates change in DCD */
 287 #define MISCSTATUS_RI_LATCHED   (SerialSignal_RI<<8)    /* indicates change in RI */
 288 #define MISCSTATUS_CTS_LATCHED  (SerialSignal_CTS<<8)   /* indicates change in CTS */
 289 #define MISCSTATUS_DSR_LATCHED  (SerialSignal_DSR<<8)   /* change in DSR */
 290
 291 /* Common Register macros */
 292 #define LPR     0x00
 293 #define PABR0   0x02
 294 #define PABR1   0x03
 295 #define WCRL    0x04
 296 #define WCRM    0x05
 297 #define WCRH    0x06
 298 #define DPCR    0x08
 299 #define DMER    0x09
 300 #define ISR0    0x10
 301 #define ISR1    0x11
 302 #define ISR2    0x12
 303 #define IER0    0x14
 304 #define IER1    0x15
 305 #define IER2    0x16
 306 #define ITCR    0x18
 307 #define INTVR   0x1a
 308 #define IMVR    0x1c
 309
 310 /* MSCI Register macros */
 311 #define TRB     0x20
 312 #define TRBL    0x20
 313 #define TRBH    0x21
 314 #define SR0     0x22
 315 #define SR1     0x23
 316 #define SR2     0x24
 317 #define SR3     0x25
 318 #define FST     0x26
 319 #define IE0     0x28
 320 #define IE1     0x29
 321 #define IE2     0x2a
 322 #define FIE     0x2b
 323 #define CMD     0x2c
 324 #define MD0     0x2e
 325 #define MD1     0x2f
 326 #define MD2     0x30
 327 #define CTL     0x31
 328 #define SA0     0x32
 329 #define SA1     0x33
 330 #define IDL     0x34
 331 #define TMC     0x35
 332 #define RXS     0x36
 333 #define TXS     0x37
 334 #define TRC0    0x38
 335 #define TRC1    0x39
 336 #define RRC     0x3a
 337 #define CST0    0x3c
 338 #define CST1    0x3d
 339
 340 /* Timer Register Macros */
 341 #define TCNT    0x60
 342 #define TCNTL   0x60
 343 #define TCNTH   0x61
 344 #define TCONR   0x62
 345 #define TCONRL  0x62
 346 #define TCONRH  0x63
 347 #define TMCS    0x64
 348 #define TEPR    0x65
 349
 350 /* DMA Controller Register macros */
 351 #define DARL    0x80
 352 #define DARH    0x81
 353 #define DARB    0x82
 354 #define BAR     0x80
 355 #define BARL    0x80
 356 #define BARH    0x81
 357 #define BARB    0x82
 358 #define SAR     0x84
 359 #define SARL    0x84
 360 #define SARH    0x85
 361 #define SARB    0x86
 362 #define CPB     0x86
 363 #define CDA     0x88
 364 #define CDAL    0x88
 365 #define CDAH    0x89
 366 #define EDA     0x8a
 367 #define EDAL    0x8a
 368 #define EDAH    0x8b
 369 #define BFL     0x8c
 370 #define BFLL    0x8c
 371 #define BFLH    0x8d
 372 #define BCR     0x8e
 373 #define BCRL    0x8e
 374 #define BCRH    0x8f
 375 #define DSR     0x90
 376 #define DMR     0x91
 377 #define FCT     0x93
 378 #define DIR     0x94
 379 #define DCMD    0x95
 380
 381 /* combine with timer or DMA register address */
 382 #define TIMER0  0x00
 383 #define TIMER1  0x08
 384 #define TIMER2  0x10
 385 #define TIMER3  0x18
 386 #define RXDMA   0x00
 387 #define TXDMA   0x20
 388
 389 /* SCA Command Codes */
 390 #define NOOP            0x00
 391 #define TXRESET         0x01
 392 #define TXENABLE        0x02
 393 #define TXDISABLE       0x03
 394 #define TXCRCINIT       0x04
 395 #define TXCRCEXCL       0x05
 396 #define TXEOM           0x06
 397 #define TXABORT         0x07
 398 #define MPON            0x08
 399 #define TXBUFCLR        0x09
 400 #define RXRESET         0x11
 401 #define RXENABLE        0x12
 402 #define RXDISABLE       0x13
 403 #define RXCRCINIT       0x14
 404 #define RXREJECT        0x15
 405 #define SEARCHMP        0x16
 406 #define RXCRCEXCL       0x17
 407 #define RXCRCCALC       0x18
 408 #define CHRESET         0x21
 409 #define HUNT            0x31
 410
 411 /* DMA command codes */
 412 #define SWABORT         0x01
 413 #define FEICLEAR        0x02
 414
 415 /* IE0 */
 416 #define TXINTE          BIT7
 417 #define RXINTE          BIT6
 418 #define TXRDYE          BIT1
 419 #define RXRDYE          BIT0
 420
 421 /* IE1 & SR1 */
 422 #define UDRN    BIT7
 423 #define IDLE    BIT6
 424 #define SYNCD   BIT4
 425 #define FLGD    BIT4
 426 #define CCTS    BIT3
 427 #define CDCD    BIT2
 428 #define BRKD    BIT1
 429 #define ABTD    BIT1
 430 #define GAPD    BIT1
 431 #define BRKE    BIT0
 432 #define IDLD    BIT0
 433
 434 /* IE2 & SR2 */
 435 #define EOM     BIT7
 436 #define PMP     BIT6
 437 #define SHRT    BIT6
 438 #define PE      BIT5
 439 #define ABT     BIT5
 440 #define FRME    BIT4
 441 #define RBIT    BIT4
 442 #define OVRN    BIT3
 443 #define CRCE    BIT2
 444
 445
 446 /*
 447  * Global linked list of SyncLink devices
 448  */
 449 static SLMP_INFO *synclinkmp_device_list = NULL;
 450 static int synclinkmp_adapter_count = -1;
 451 static int synclinkmp_device_count = 0;
 452
 453 /*
 454  * Set this param to non-zero to load eax with the
 455  * .text section address and breakpoint on module load.
 456  * This is useful for use with gdb and add-symbol-file command.
 457  */
 458 static int break_on_load = 0;
 459
 460 /*
 461  * Driver major number, defaults to zero to get auto
 462  * assigned major number. May be forced as module parameter.
 463  */
 464 static int ttymajor = 0;
 465
 466 /*
 467  * Array of user specified options for ISA adapters.
 468  */
 469 static int debug_level = 0;
 470 static int maxframe[MAX_DEVICES] = {0,};
 471
 472 module_param(break_on_load, bool, 0);
 473 module_param(ttymajor, int, 0);
 474 module_param(debug_level, int, 0);
 475 module_param_array(maxframe, int, NULL, 0);
 476
 477 static char *driver_name = "SyncLink MultiPort driver";
 478 static char *driver_version = "$Revision: 4.38 $";
 479
 480 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 481 static void synclinkmp_remove_one(struct pci_dev *dev);
 482
 483 static struct pci_device_id synclinkmp_pci_tbl[] = {
 484         { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
 485         { 0, }, /* terminate list */
 486 };
 487 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
 488
 489 MODULE_LICENSE("GPL");
 490
 491 static struct pci_driver synclinkmp_pci_driver = {
 492         .name           = "synclinkmp",
 493         .id_table       = synclinkmp_pci_tbl,
 494         .probe          = synclinkmp_init_one,
 495         .remove         = __devexit_p(synclinkmp_remove_one),
 496 };
 497
 498
 499 static struct tty_driver *serial_driver;
 500
 501 /* number of characters left in xmit buffer before we ask for more */
 502 #define WAKEUP_CHARS 256
 503
 504
 505 /* tty callbacks */
 506
 507 static int  open(struct tty_struct *tty, struct file * filp);
 508 static void close(struct tty_struct *tty, struct file * filp);
 509 static void hangup(struct tty_struct *tty);
 510 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 511
 512 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 513 static int put_char(struct tty_struct *tty, unsigned char ch);
 514 static void send_xchar(struct tty_struct *tty, char ch);
 515 static void wait_until_sent(struct tty_struct *tty, int timeout);
 516 static int  write_room(struct tty_struct *tty);
 517 static void flush_chars(struct tty_struct *tty);
 518 static void flush_buffer(struct tty_struct *tty);
 519 static void tx_hold(struct tty_struct *tty);
 520 static void tx_release(struct tty_struct *tty);
 521
 522 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 523 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 524 static int  chars_in_buffer(struct tty_struct *tty);
 525 static void throttle(struct tty_struct * tty);
 526 static void unthrottle(struct tty_struct * tty);
 527 static int set_break(struct tty_struct *tty, int break_state);
 528
 529 #if SYNCLINK_GENERIC_HDLC
 530 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 531 static void hdlcdev_tx_done(SLMP_INFO *info);
 532 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
 533 static int  hdlcdev_init(SLMP_INFO *info);
 534 static void hdlcdev_exit(SLMP_INFO *info);
 535 #endif
 536
 537 /* ioctl handlers */
 538
 539 static int  get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
 540 static int  get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 541 static int  set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 542 static int  get_txidle(SLMP_INFO *info, int __user *idle_mode);
 543 static int  set_txidle(SLMP_INFO *info, int idle_mode);
 544 static int  tx_enable(SLMP_INFO *info, int enable);
 545 static int  tx_abort(SLMP_INFO *info);
 546 static int  rx_enable(SLMP_INFO *info, int enable);
 547 static int  modem_input_wait(SLMP_INFO *info,int arg);
 548 static int  wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
 549 static int  tiocmget(struct tty_struct *tty, struct file *file);
 550 static int  tiocmset(struct tty_struct *tty, struct file *file,
 551                      unsigned int set, unsigned int clear);
 552 static int  set_break(struct tty_struct *tty, int break_state);
 553
 554 static void add_device(SLMP_INFO *info);
 555 static void device_init(int adapter_num, struct pci_dev *pdev);
 556 static int  claim_resources(SLMP_INFO *info);
 557 static void release_resources(SLMP_INFO *info);
 558
 559 static int  startup(SLMP_INFO *info);
 560 static int  block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
 561 static int carrier_raised(struct tty_port *port);
 562 static void shutdown(SLMP_INFO *info);
 563 static void program_hw(SLMP_INFO *info);
 564 static void change_params(SLMP_INFO *info);
 565
 566 static bool init_adapter(SLMP_INFO *info);
 567 static bool register_test(SLMP_INFO *info);
 568 static bool irq_test(SLMP_INFO *info);
 569 static bool loopback_test(SLMP_INFO *info);
 570 static int  adapter_test(SLMP_INFO *info);
 571 static bool memory_test(SLMP_INFO *info);
 572
 573 static void reset_adapter(SLMP_INFO *info);
 574 static void reset_port(SLMP_INFO *info);
 575 static void async_mode(SLMP_INFO *info);
 576 static void hdlc_mode(SLMP_INFO *info);
 577
 578 static void rx_stop(SLMP_INFO *info);
 579 static void rx_start(SLMP_INFO *info);
 580 static void rx_reset_buffers(SLMP_INFO *info);
 581 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
 582 static bool rx_get_frame(SLMP_INFO *info);
 583
 584 static void tx_start(SLMP_INFO *info);
 585 static void tx_stop(SLMP_INFO *info);
 586 static void tx_load_fifo(SLMP_INFO *info);
 587 static void tx_set_idle(SLMP_INFO *info);
 588 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
 589
 590 static void get_signals(SLMP_INFO *info);
 591 static void set_signals(SLMP_INFO *info);
 592 static void enable_loopback(SLMP_INFO *info, int enable);
 593 static void set_rate(SLMP_INFO *info, u32 data_rate);
 594
 595 static int  bh_action(SLMP_INFO *info);
 596 static void bh_handler(struct work_struct *work);
 597 static void bh_receive(SLMP_INFO *info);
 598 static void bh_transmit(SLMP_INFO *info);
 599 static void bh_status(SLMP_INFO *info);
 600 static void isr_timer(SLMP_INFO *info);
 601 static void isr_rxint(SLMP_INFO *info);
 602 static void isr_rxrdy(SLMP_INFO *info);
 603 static void isr_txint(SLMP_INFO *info);
 604 static void isr_txrdy(SLMP_INFO *info);
 605 static void isr_rxdmaok(SLMP_INFO *info);
 606 static void isr_rxdmaerror(SLMP_INFO *info);
 607 static void isr_txdmaok(SLMP_INFO *info);
 608 static void isr_txdmaerror(SLMP_INFO *info);
 609 static void isr_io_pin(SLMP_INFO *info, u16 status);
 610
 611 static int  alloc_dma_bufs(SLMP_INFO *info);
 612 static void free_dma_bufs(SLMP_INFO *info);
 613 static int  alloc_buf_list(SLMP_INFO *info);
 614 static int  alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
 615 static int  alloc_tmp_rx_buf(SLMP_INFO *info);
 616 static void free_tmp_rx_buf(SLMP_INFO *info);
 617
 618 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
 619 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
 620 static void tx_timeout(unsigned long context);
 621 static void status_timeout(unsigned long context);
 622
 623 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
 624 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
 625 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
 626 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
 627 static unsigned char read_status_reg(SLMP_INFO * info);
 628 static void write_control_reg(SLMP_INFO * info);
 629
 630
 631 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
 632 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
 633 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
 634
 635 static u32 misc_ctrl_value = 0x007e4040;
 636 static u32 lcr1_brdr_value = 0x00800028;
 637
 638 static u32 read_ahead_count = 8;
 639
 640 /* DPCR, DMA Priority Control
 641  *
 642  * 07..05  Not used, must be 0
 643  * 04      BRC, bus release condition: 0=all transfers complete
 644  *              1=release after 1 xfer on all channels
 645  * 03      CCC, channel change condition: 0=every cycle
 646  *              1=after each channel completes all xfers
 647  * 02..00  PR<2..0>, priority 100=round robin
 648  *
 649  * 00000100 = 0x00
 650  */
 651 static unsigned char dma_priority = 0x04;
 652
 653 // Number of bytes that can be written to shared RAM
 654 // in a single write operation
 655 static u32 sca_pci_load_interval = 64;
 656
 657 /*
 658  * 1st function defined in .text section. Calling this function in
 659  * init_module() followed by a breakpoint allows a remote debugger
 660  * (gdb) to get the .text address for the add-symbol-file command.
 661  * This allows remote debugging of dynamically loadable modules.
 662  */
 663 static void* synclinkmp_get_text_ptr(void);
 664 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
 665
 666 static inline int sanity_check(SLMP_INFO *info,
 667                                char *name, const char *routine)
 668 {
 669 #ifdef SANITY_CHECK
 670         static const char *badmagic =
 671                 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
 672         static const char *badinfo =
 673                 "Warning: null synclinkmp_struct for (%s) in %s\n";
 674
 675         if (!info) {
 676                 printk(badinfo, name, routine);
 677                 return 1;
 678         }
 679         if (info->magic != MGSL_MAGIC) {
 680                 printk(badmagic, name, routine);
 681                 return 1;
 682         }
 683 #else
 684         if (!info)
 685                 return 1;
 686 #endif
 687         return 0;
 688 }
 689
 690 /**
 691  * line discipline callback wrappers
 692  *
 693  * The wrappers maintain line discipline references
 694  * while calling into the line discipline.
 695  *
 696  * ldisc_receive_buf  - pass receive data to line discipline
 697  */
 698
 699 static void ldisc_receive_buf(struct tty_struct *tty,
 700                               const __u8 *data, char *flags, int count)
 701 {
 702         struct tty_ldisc *ld;
 703         if (!tty)
 704                 return;
 705         ld = tty_ldisc_ref(tty);
 706         if (ld) {
 707                 if (ld->ops->receive_buf)
 708                         ld->ops->receive_buf(tty, data, flags, count);
 709                 tty_ldisc_deref(ld);
 710         }
 711 }
 712
 713 /* tty callbacks */
 714
 715 /* Called when a port is opened.  Init and enable port.
 716  */
 717 static int open(struct tty_struct *tty, struct file *filp)
 718 {
 719         SLMP_INFO *info;
 720         int retval, line;
 721         unsigned long flags;
 722
 723         line = tty->index;
 724         if ((line < 0) || (line >= synclinkmp_device_count)) {
 725                 printk("%s(%d): open with invalid line #%d.\n",
 726                         __FILE__,__LINE__,line);
 727                 return -ENODEV;
 728         }
 729
 730         info = synclinkmp_device_list;
 731         while(info && info->line != line)
 732                 info = info->next_device;
 733         if (sanity_check(info, tty->name, "open"))
 734                 return -ENODEV;
 735         if ( info->init_error ) {
 736                 printk("%s(%d):%s device is not allocated, init error=%d\n",
 737                         __FILE__,__LINE__,info->device_name,info->init_error);
 738                 return -ENODEV;
 739         }
 740
 741         tty->driver_data = info;
 742         info->port.tty = tty;
 743
 744         if (debug_level >= DEBUG_LEVEL_INFO)
 745                 printk("%s(%d):%s open(), old ref count = %d\n",
 746                          __FILE__,__LINE__,tty->driver->name, info->port.count);
 747
 748         /* If port is closing, signal caller to try again */
 749         if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
 750                 if (info->port.flags & ASYNC_CLOSING)
 751                         interruptible_sleep_on(&info->port.close_wait);
 752                 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
 753                         -EAGAIN : -ERESTARTSYS);
 754                 goto cleanup;
 755         }
 756
 757         info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 758
 759         spin_lock_irqsave(&info->netlock, flags);
 760         if (info->netcount) {
 761                 retval = -EBUSY;
 762                 spin_unlock_irqrestore(&info->netlock, flags);
 763                 goto cleanup;
 764         }
 765         info->port.count++;
 766         spin_unlock_irqrestore(&info->netlock, flags);
 767
 768         if (info->port.count == 1) {
 769                 /* 1st open on this device, init hardware */
 770                 retval = startup(info);
 771                 if (retval < 0)
 772                         goto cleanup;
 773         }
 774
 775         retval = block_til_ready(tty, filp, info);
 776         if (retval) {
 777                 if (debug_level >= DEBUG_LEVEL_INFO)
 778                         printk("%s(%d):%s block_til_ready() returned %d\n",
 779                                  __FILE__,__LINE__, info->device_name, retval);
 780                 goto cleanup;
 781         }
 782
 783         if (debug_level >= DEBUG_LEVEL_INFO)
 784                 printk("%s(%d):%s open() success\n",
 785                          __FILE__,__LINE__, info->device_name);
 786         retval = 0;
 787
 788 cleanup:
 789         if (retval) {
 790                 if (tty->count == 1)
 791                         info->port.tty = NULL; /* tty layer will release tty struct */
 792                 if(info->port.count)
 793                         info->port.count--;
 794         }
 795
 796         return retval;
 797 }
 798
 799 /* Called when port is closed. Wait for remaining data to be
 800  * sent. Disable port and free resources.
 801  */
 802 static void close(struct tty_struct *tty, struct file *filp)
 803 {
 804         SLMP_INFO * info = tty->driver_data;
 805
 806         if (sanity_check(info, tty->name, "close"))
 807                 return;
 808
 809         if (debug_level >= DEBUG_LEVEL_INFO)
 810                 printk("%s(%d):%s close() entry, count=%d\n",
 811                          __FILE__,__LINE__, info->device_name, info->port.count);
 812
 813         if (tty_port_close_start(&info->port, tty, filp) == 0)
 814                 goto cleanup;
 815
 816         if (info->port.flags & ASYNC_INITIALIZED)
 817                 wait_until_sent(tty, info->timeout);
 818
 819         flush_buffer(tty);
 820         tty_ldisc_flush(tty);
 821         shutdown(info);
 822
 823         tty_port_close_end(&info->port, tty);
 824         info->port.tty = NULL;
 825 cleanup:
 826         if (debug_level >= DEBUG_LEVEL_INFO)
 827                 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
 828                         tty->driver->name, info->port.count);
 829 }
 830
 831 /* Called by tty_hangup() when a hangup is signaled.
 832  * This is the same as closing all open descriptors for the port.
 833  */
 834 static void hangup(struct tty_struct *tty)
 835 {
 836         SLMP_INFO *info = tty->driver_data;
 837
 838         if (debug_level >= DEBUG_LEVEL_INFO)
 839                 printk("%s(%d):%s hangup()\n",
 840                          __FILE__,__LINE__, info->device_name );
 841
 842         if (sanity_check(info, tty->name, "hangup"))
 843                 return;
 844
 845         flush_buffer(tty);
 846         shutdown(info);
 847
 848         info->port.count = 0;
 849         info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
 850         info->port.tty = NULL;
 851
 852         wake_up_interruptible(&info->port.open_wait);
 853 }
 854
 855 /* Set new termios settings
 856  */
 857 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 858 {
 859         SLMP_INFO *info = tty->driver_data;
 860         unsigned long flags;
 861
 862         if (debug_level >= DEBUG_LEVEL_INFO)
 863                 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
 864                         tty->driver->name );
 865
 866         change_params(info);
 867
 868         /* Handle transition to B0 status */
 869         if (old_termios->c_cflag & CBAUD &&
 870             !(tty->termios->c_cflag & CBAUD)) {
 871                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 872                 spin_lock_irqsave(&info->lock,flags);
 873                 set_signals(info);
 874                 spin_unlock_irqrestore(&info->lock,flags);
 875         }
 876
 877         /* Handle transition away from B0 status */
 878         if (!(old_termios->c_cflag & CBAUD) &&
 879             tty->termios->c_cflag & CBAUD) {
 880                 info->serial_signals |= SerialSignal_DTR;
 881                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 882                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 883                         info->serial_signals |= SerialSignal_RTS;
 884                 }
 885                 spin_lock_irqsave(&info->lock,flags);
 886                 set_signals(info);
 887                 spin_unlock_irqrestore(&info->lock,flags);
 888         }
 889
 890         /* Handle turning off CRTSCTS */
 891         if (old_termios->c_cflag & CRTSCTS &&
 892             !(tty->termios->c_cflag & CRTSCTS)) {
 893                 tty->hw_stopped = 0;
 894                 tx_release(tty);
 895         }
 896 }
 897
 898 /* Send a block of data
 899  *
 900  * Arguments:
 901  *
 902  *      tty             pointer to tty information structure
 903  *      buf             pointer to buffer containing send data
 904  *      count           size of send data in bytes
 905  *
 906  * Return Value:        number of characters written
 907  */
 908 static int write(struct tty_struct *tty,
 909                  const unsigned char *buf, int count)
 910 {
 911         int     c, ret = 0;
 912         SLMP_INFO *info = tty->driver_data;
 913         unsigned long flags;
 914
 915         if (debug_level >= DEBUG_LEVEL_INFO)
 916                 printk("%s(%d):%s write() count=%d\n",
 917                        __FILE__,__LINE__,info->device_name,count);
 918
 919         if (sanity_check(info, tty->name, "write"))
 920                 goto cleanup;
 921
 922         if (!info->tx_buf)
 923                 goto cleanup;
 924
 925         if (info->params.mode == MGSL_MODE_HDLC) {
 926                 if (count > info->max_frame_size) {
 927                         ret = -EIO;
 928                         goto cleanup;
 929                 }
 930                 if (info->tx_active)
 931                         goto cleanup;
 932                 if (info->tx_count) {
 933                         /* send accumulated data from send_char() calls */
 934                         /* as frame and wait before accepting more data. */
 935                         tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
 936                         goto start;
 937                 }
 938                 ret = info->tx_count = count;
 939                 tx_load_dma_buffer(info, buf, count);
 940                 goto start;
 941         }
 942
 943         for (;;) {
 944                 c = min_t(int, count,
 945                         min(info->max_frame_size - info->tx_count - 1,
 946                             info->max_frame_size - info->tx_put));
 947                 if (c <= 0)
 948                         break;
 949
 950                 memcpy(info->tx_buf + info->tx_put, buf, c);
 951
 952                 spin_lock_irqsave(&info->lock,flags);
 953                 info->tx_put += c;
 954                 if (info->tx_put >= info->max_frame_size)
 955                         info->tx_put -= info->max_frame_size;
 956                 info->tx_count += c;
 957                 spin_unlock_irqrestore(&info->lock,flags);
 958
 959                 buf += c;
 960                 count -= c;
 961                 ret += c;
 962         }
 963
 964         if (info->params.mode == MGSL_MODE_HDLC) {
 965                 if (count) {
 966                         ret = info->tx_count = 0;
 967                         goto cleanup;
 968                 }
 969                 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
 970         }
 971 start:
 972         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
 973                 spin_lock_irqsave(&info->lock,flags);
 974                 if (!info->tx_active)
 975                         tx_start(info);
 976                 spin_unlock_irqrestore(&info->lock,flags);
 977         }
 978
 979 cleanup:
 980         if (debug_level >= DEBUG_LEVEL_INFO)
 981                 printk( "%s(%d):%s write() returning=%d\n",
 982                         __FILE__,__LINE__,info->device_name,ret);
 983         return ret;
 984 }
 985
 986 /* Add a character to the transmit buffer.
 987  */
 988 static int put_char(struct tty_struct *tty, unsigned char ch)
 989 {
 990         SLMP_INFO *info = tty->driver_data;
 991         unsigned long flags;
 992         int ret = 0;
 993
 994         if ( debug_level >= DEBUG_LEVEL_INFO ) {
 995                 printk( "%s(%d):%s put_char(%d)\n",
 996                         __FILE__,__LINE__,info->device_name,ch);
 997         }
 998
 999         if (sanity_check(info, tty->name, "put_char"))
1000                 return 0;
1001
1002         if (!info->tx_buf)
1003                 return 0;
1004
1005         spin_lock_irqsave(&info->lock,flags);
1006
1007         if ( (info->params.mode != MGSL_MODE_HDLC) ||
1008              !info->tx_active ) {
1009
1010                 if (info->tx_count < info->max_frame_size - 1) {
1011                         info->tx_buf[info->tx_put++] = ch;
1012                         if (info->tx_put >= info->max_frame_size)
1013                                 info->tx_put -= info->max_frame_size;
1014                         info->tx_count++;
1015                         ret = 1;
1016                 }
1017         }
1018
1019         spin_unlock_irqrestore(&info->lock,flags);
1020         return ret;
1021 }
1022
1023 /* Send a high-priority XON/XOFF character
1024  */
1025 static void send_xchar(struct tty_struct *tty, char ch)
1026 {
1027         SLMP_INFO *info = tty->driver_data;
1028         unsigned long flags;
1029
1030         if (debug_level >= DEBUG_LEVEL_INFO)
1031                 printk("%s(%d):%s send_xchar(%d)\n",
1032                          __FILE__,__LINE__, info->device_name, ch );
1033
1034         if (sanity_check(info, tty->name, "send_xchar"))
1035                 return;
1036
1037         info->x_char = ch;
1038         if (ch) {
1039                 /* Make sure transmit interrupts are on */
1040                 spin_lock_irqsave(&info->lock,flags);
1041                 if (!info->tx_enabled)
1042                         tx_start(info);
1043                 spin_unlock_irqrestore(&info->lock,flags);
1044         }
1045 }
1046
1047 /* Wait until the transmitter is empty.
1048  */
1049 static void wait_until_sent(struct tty_struct *tty, int timeout)
1050 {
1051         SLMP_INFO * info = tty->driver_data;
1052         unsigned long orig_jiffies, char_time;
1053
1054         if (!info )
1055                 return;
1056
1057         if (debug_level >= DEBUG_LEVEL_INFO)
1058                 printk("%s(%d):%s wait_until_sent() entry\n",
1059                          __FILE__,__LINE__, info->device_name );
1060
1061         if (sanity_check(info, tty->name, "wait_until_sent"))
1062                 return;
1063
1064         lock_kernel();
1065
1066         if (!(info->port.flags & ASYNC_INITIALIZED))
1067                 goto exit;
1068
1069         orig_jiffies = jiffies;
1070
1071         /* Set check interval to 1/5 of estimated time to
1072          * send a character, and make it at least 1. The check
1073          * interval should also be less than the timeout.
1074          * Note: use tight timings here to satisfy the NIST-PCTS.
1075          */
1076
1077         if ( info->params.data_rate ) {
1078                 char_time = info->timeout/(32 * 5);
1079                 if (!char_time)
1080                         char_time++;
1081         } else
1082                 char_time = 1;
1083
1084         if (timeout)
1085                 char_time = min_t(unsigned long, char_time, timeout);
1086
1087         if ( info->params.mode == MGSL_MODE_HDLC ) {
1088                 while (info->tx_active) {
1089                         msleep_interruptible(jiffies_to_msecs(char_time));
1090                         if (signal_pending(current))
1091                                 break;
1092                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1093                                 break;
1094                 }
1095         } else {
1096                 //TODO: determine if there is something similar to USC16C32
1097                 //      TXSTATUS_ALL_SENT status
1098                 while ( info->tx_active && info->tx_enabled) {
1099                         msleep_interruptible(jiffies_to_msecs(char_time));
1100                         if (signal_pending(current))
1101                                 break;
1102                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1103                                 break;
1104                 }
1105         }
1106
1107 exit:
1108         unlock_kernel();
1109         if (debug_level >= DEBUG_LEVEL_INFO)
1110                 printk("%s(%d):%s wait_until_sent() exit\n",
1111                          __FILE__,__LINE__, info->device_name );
1112 }
1113
1114 /* Return the count of free bytes in transmit buffer
1115  */
1116 static int write_room(struct tty_struct *tty)
1117 {
1118         SLMP_INFO *info = tty->driver_data;
1119         int ret;
1120
1121         if (sanity_check(info, tty->name, "write_room"))
1122                 return 0;
1123
1124         lock_kernel();
1125         if (info->params.mode == MGSL_MODE_HDLC) {
1126                 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1127         } else {
1128                 ret = info->max_frame_size - info->tx_count - 1;
1129                 if (ret < 0)
1130                         ret = 0;
1131         }
1132         unlock_kernel();
1133
1134         if (debug_level >= DEBUG_LEVEL_INFO)
1135                 printk("%s(%d):%s write_room()=%d\n",
1136                        __FILE__, __LINE__, info->device_name, ret);
1137
1138         return ret;
1139 }
1140
1141 /* enable transmitter and send remaining buffered characters
1142  */
1143 static void flush_chars(struct tty_struct *tty)
1144 {
1145         SLMP_INFO *info = tty->driver_data;
1146         unsigned long flags;
1147
1148         if ( debug_level >= DEBUG_LEVEL_INFO )
1149                 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1150                         __FILE__,__LINE__,info->device_name,info->tx_count);
1151
1152         if (sanity_check(info, tty->name, "flush_chars"))
1153                 return;
1154
1155         if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1156             !info->tx_buf)
1157                 return;
1158
1159         if ( debug_level >= DEBUG_LEVEL_INFO )
1160                 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1161                         __FILE__,__LINE__,info->device_name );
1162
1163         spin_lock_irqsave(&info->lock,flags);
1164
1165         if (!info->tx_active) {
1166                 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1167                         info->tx_count ) {
1168                         /* operating in synchronous (frame oriented) mode */
1169                         /* copy data from circular tx_buf to */
1170                         /* transmit DMA buffer. */
1171                         tx_load_dma_buffer(info,
1172                                  info->tx_buf,info->tx_count);
1173                 }
1174                 tx_start(info);
1175         }
1176
1177         spin_unlock_irqrestore(&info->lock,flags);
1178 }
1179
1180 /* Discard all data in the send buffer
1181  */
1182 static void flush_buffer(struct tty_struct *tty)
1183 {
1184         SLMP_INFO *info = tty->driver_data;
1185         unsigned long flags;
1186
1187         if (debug_level >= DEBUG_LEVEL_INFO)
1188                 printk("%s(%d):%s flush_buffer() entry\n",
1189                          __FILE__,__LINE__, info->device_name );
1190
1191         if (sanity_check(info, tty->name, "flush_buffer"))
1192                 return;
1193
1194         spin_lock_irqsave(&info->lock,flags);
1195         info->tx_count = info->tx_put = info->tx_get = 0;
1196         del_timer(&info->tx_timer);
1197         spin_unlock_irqrestore(&info->lock,flags);
1198
1199         tty_wakeup(tty);
1200 }
1201
1202 /* throttle (stop) transmitter
1203  */
1204 static void tx_hold(struct tty_struct *tty)
1205 {
1206         SLMP_INFO *info = tty->driver_data;
1207         unsigned long flags;
1208
1209         if (sanity_check(info, tty->name, "tx_hold"))
1210                 return;
1211
1212         if ( debug_level >= DEBUG_LEVEL_INFO )
1213                 printk("%s(%d):%s tx_hold()\n",
1214                         __FILE__,__LINE__,info->device_name);
1215
1216         spin_lock_irqsave(&info->lock,flags);
1217         if (info->tx_enabled)
1218                 tx_stop(info);
1219         spin_unlock_irqrestore(&info->lock,flags);
1220 }
1221
1222 /* release (start) transmitter
1223  */
1224 static void tx_release(struct tty_struct *tty)
1225 {
1226         SLMP_INFO *info = tty->driver_data;
1227         unsigned long flags;
1228
1229         if (sanity_check(info, tty->name, "tx_release"))
1230                 return;
1231
1232         if ( debug_level >= DEBUG_LEVEL_INFO )
1233                 printk("%s(%d):%s tx_release()\n",
1234                         __FILE__,__LINE__,info->device_name);
1235
1236         spin_lock_irqsave(&info->lock,flags);
1237         if (!info->tx_enabled)
1238                 tx_start(info);
1239         spin_unlock_irqrestore(&info->lock,flags);
1240 }
1241
1242 /* Service an IOCTL request
1243  *
1244  * Arguments:
1245  *
1246  *      tty     pointer to tty instance data
1247  *      file    pointer to associated file object for device
1248  *      cmd     IOCTL command code
1249  *      arg     command argument/context
1250  *
1251  * Return Value:        0 if success, otherwise error code
1252  */
1253 static int do_ioctl(struct tty_struct *tty, struct file *file,
1254                  unsigned int cmd, unsigned long arg)
1255 {
1256         SLMP_INFO *info = tty->driver_data;
1257         int error;
1258         struct mgsl_icount cnow;        /* kernel counter temps */
1259         struct serial_icounter_struct __user *p_cuser;  /* user space */
1260         unsigned long flags;
1261         void __user *argp = (void __user *)arg;
1262
1263         if (debug_level >= DEBUG_LEVEL_INFO)
1264                 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1265                         info->device_name, cmd );
1266
1267         if (sanity_check(info, tty->name, "ioctl"))
1268                 return -ENODEV;
1269
1270         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1271             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1272                 if (tty->flags & (1 << TTY_IO_ERROR))
1273                     return -EIO;
1274         }
1275
1276         switch (cmd) {
1277         case MGSL_IOCGPARAMS:
1278                 return get_params(info, argp);
1279         case MGSL_IOCSPARAMS:
1280                 return set_params(info, argp);
1281         case MGSL_IOCGTXIDLE:
1282                 return get_txidle(info, argp);
1283         case MGSL_IOCSTXIDLE:
1284                 return set_txidle(info, (int)arg);
1285         case MGSL_IOCTXENABLE:
1286                 return tx_enable(info, (int)arg);
1287         case MGSL_IOCRXENABLE:
1288                 return rx_enable(info, (int)arg);
1289         case MGSL_IOCTXABORT:
1290                 return tx_abort(info);
1291         case MGSL_IOCGSTATS:
1292                 return get_stats(info, argp);
1293         case MGSL_IOCWAITEVENT:
1294                 return wait_mgsl_event(info, argp);
1295         case MGSL_IOCLOOPTXDONE:
1296                 return 0; // TODO: Not supported, need to document
1297                 /* Wait for modem input (DCD,RI,DSR,CTS) change
1298                  * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1299                  */
1300         case TIOCMIWAIT:
1301                 return modem_input_wait(info,(int)arg);
1302
1303                 /*
1304                  * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1305                  * Return: write counters to the user passed counter struct
1306                  * NB: both 1->0 and 0->1 transitions are counted except for
1307                  *     RI where only 0->1 is counted.
1308                  */
1309         case TIOCGICOUNT:
1310                 spin_lock_irqsave(&info->lock,flags);
1311                 cnow = info->icount;
1312                 spin_unlock_irqrestore(&info->lock,flags);
1313                 p_cuser = argp;
1314                 PUT_USER(error,cnow.cts, &p_cuser->cts);
1315                 if (error) return error;
1316                 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1317                 if (error) return error;
1318                 PUT_USER(error,cnow.rng, &p_cuser->rng);
1319                 if (error) return error;
1320                 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1321                 if (error) return error;
1322                 PUT_USER(error,cnow.rx, &p_cuser->rx);
1323                 if (error) return error;
1324                 PUT_USER(error,cnow.tx, &p_cuser->tx);
1325                 if (error) return error;
1326                 PUT_USER(error,cnow.frame, &p_cuser->frame);
1327                 if (error) return error;
1328                 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1329                 if (error) return error;
1330                 PUT_USER(error,cnow.parity, &p_cuser->parity);
1331                 if (error) return error;
1332                 PUT_USER(error,cnow.brk, &p_cuser->brk);
1333                 if (error) return error;
1334                 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1335                 if (error) return error;
1336                 return 0;
1337         default:
1338                 return -ENOIOCTLCMD;
1339         }
1340         return 0;
1341 }
1342
1343 static int ioctl(struct tty_struct *tty, struct file *file,
1344                  unsigned int cmd, unsigned long arg)
1345 {
1346         int ret;
1347         lock_kernel();
1348         ret = do_ioctl(tty, file, cmd, arg);
1349         unlock_kernel();
1350         return ret;
1351 }
1352
1353 /*
1354  * /proc fs routines....
1355  */
1356
1357 static inline int line_info(char *buf, SLMP_INFO *info)
1358 {
1359         char    stat_buf[30];
1360         int     ret;
1361         unsigned long flags;
1362
1363         ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1364                        "\tIRQ=%d MaxFrameSize=%u\n",
1365                 info->device_name,
1366                 info->phys_sca_base,
1367                 info->phys_memory_base,
1368                 info->phys_statctrl_base,
1369                 info->phys_lcr_base,
1370                 info->irq_level,
1371                 info->max_frame_size );
1372
1373         /* output current serial signal states */
1374         spin_lock_irqsave(&info->lock,flags);
1375         get_signals(info);
1376         spin_unlock_irqrestore(&info->lock,flags);
1377
1378         stat_buf[0] = 0;
1379         stat_buf[1] = 0;
1380         if (info->serial_signals & SerialSignal_RTS)
1381                 strcat(stat_buf, "|RTS");
1382         if (info->serial_signals & SerialSignal_CTS)
1383                 strcat(stat_buf, "|CTS");
1384         if (info->serial_signals & SerialSignal_DTR)
1385                 strcat(stat_buf, "|DTR");
1386         if (info->serial_signals & SerialSignal_DSR)
1387                 strcat(stat_buf, "|DSR");
1388         if (info->serial_signals & SerialSignal_DCD)
1389                 strcat(stat_buf, "|CD");
1390         if (info->serial_signals & SerialSignal_RI)
1391                 strcat(stat_buf, "|RI");
1392
1393         if (info->params.mode == MGSL_MODE_HDLC) {
1394                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1395                               info->icount.txok, info->icount.rxok);
1396                 if (info->icount.txunder)
1397                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1398                 if (info->icount.txabort)
1399                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1400                 if (info->icount.rxshort)
1401                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1402                 if (info->icount.rxlong)
1403                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1404                 if (info->icount.rxover)
1405                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1406                 if (info->icount.rxcrc)
1407                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
1408         } else {
1409                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1410                               info->icount.tx, info->icount.rx);
1411                 if (info->icount.frame)
1412                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1413                 if (info->icount.parity)
1414                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1415                 if (info->icount.brk)
1416                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1417                 if (info->icount.overrun)
1418                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1419         }
1420
1421         /* Append serial signal status to end */
1422         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1423
1424         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1425          info->tx_active,info->bh_requested,info->bh_running,
1426          info->pending_bh);
1427
1428         return ret;
1429 }
1430
1431 /* Called to print information about devices
1432  */
1433 static int read_proc(char *page, char **start, off_t off, int count,
1434               int *eof, void *data)
1435 {
1436         int len = 0, l;
1437         off_t   begin = 0;
1438         SLMP_INFO *info;
1439
1440         len += sprintf(page, "synclinkmp driver:%s\n", driver_version);
1441
1442         info = synclinkmp_device_list;
1443         while( info ) {
1444                 l = line_info(page + len, info);
1445                 len += l;
1446                 if (len+begin > off+count)
1447                         goto done;
1448                 if (len+begin < off) {
1449                         begin += len;
1450                         len = 0;
1451                 }
1452                 info = info->next_device;
1453         }
1454
1455         *eof = 1;
1456 done:
1457         if (off >= len+begin)
1458                 return 0;
1459         *start = page + (off-begin);
1460         return ((count < begin+len-off) ? count : begin+len-off);
1461 }
1462
1463 /* Return the count of bytes in transmit buffer
1464  */
1465 static int chars_in_buffer(struct tty_struct *tty)
1466 {
1467         SLMP_INFO *info = tty->driver_data;
1468
1469         if (sanity_check(info, tty->name, "chars_in_buffer"))
1470                 return 0;
1471
1472         if (debug_level >= DEBUG_LEVEL_INFO)
1473                 printk("%s(%d):%s chars_in_buffer()=%d\n",
1474                        __FILE__, __LINE__, info->device_name, info->tx_count);
1475
1476         return info->tx_count;
1477 }
1478
1479 /* Signal remote device to throttle send data (our receive data)
1480  */
1481 static void throttle(struct tty_struct * tty)
1482 {
1483         SLMP_INFO *info = tty->driver_data;
1484         unsigned long flags;
1485
1486         if (debug_level >= DEBUG_LEVEL_INFO)
1487                 printk("%s(%d):%s throttle() entry\n",
1488                          __FILE__,__LINE__, info->device_name );
1489
1490         if (sanity_check(info, tty->name, "throttle"))
1491                 return;
1492
1493         if (I_IXOFF(tty))
1494                 send_xchar(tty, STOP_CHAR(tty));
1495
1496         if (tty->termios->c_cflag & CRTSCTS) {
1497                 spin_lock_irqsave(&info->lock,flags);
1498                 info->serial_signals &= ~SerialSignal_RTS;
1499                 set_signals(info);
1500                 spin_unlock_irqrestore(&info->lock,flags);
1501         }
1502 }
1503
1504 /* Signal remote device to stop throttling send data (our receive data)
1505  */
1506 static void unthrottle(struct tty_struct * tty)
1507 {
1508         SLMP_INFO *info = tty->driver_data;
1509         unsigned long flags;
1510
1511         if (debug_level >= DEBUG_LEVEL_INFO)
1512                 printk("%s(%d):%s unthrottle() entry\n",
1513                          __FILE__,__LINE__, info->device_name );
1514
1515         if (sanity_check(info, tty->name, "unthrottle"))
1516                 return;
1517
1518         if (I_IXOFF(tty)) {
1519                 if (info->x_char)
1520                         info->x_char = 0;
1521                 else
1522                         send_xchar(tty, START_CHAR(tty));
1523         }
1524
1525         if (tty->termios->c_cflag & CRTSCTS) {
1526                 spin_lock_irqsave(&info->lock,flags);
1527                 info->serial_signals |= SerialSignal_RTS;
1528                 set_signals(info);
1529                 spin_unlock_irqrestore(&info->lock,flags);
1530         }
1531 }
1532
1533 /* set or clear transmit break condition
1534  * break_state  -1=set break condition, 0=clear
1535  */
1536 static int set_break(struct tty_struct *tty, int break_state)
1537 {
1538         unsigned char RegValue;
1539         SLMP_INFO * info = tty->driver_data;
1540         unsigned long flags;
1541
1542         if (debug_level >= DEBUG_LEVEL_INFO)
1543                 printk("%s(%d):%s set_break(%d)\n",
1544                          __FILE__,__LINE__, info->device_name, break_state);
1545
1546         if (sanity_check(info, tty->name, "set_break"))
1547                 return -EINVAL;
1548
1549         spin_lock_irqsave(&info->lock,flags);
1550         RegValue = read_reg(info, CTL);
1551         if (break_state == -1)
1552                 RegValue |= BIT3;
1553         else
1554                 RegValue &= ~BIT3;
1555         write_reg(info, CTL, RegValue);
1556         spin_unlock_irqrestore(&info->lock,flags);
1557         return 0;
1558 }
1559
1560 #if SYNCLINK_GENERIC_HDLC
1561
1562 /**
1563  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1564  * set encoding and frame check sequence (FCS) options
1565  *
1566  * dev       pointer to network device structure
1567  * encoding  serial encoding setting
1568  * parity    FCS setting
1569  *
1570  * returns 0 if success, otherwise error code
1571  */
1572 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1573                           unsigned short parity)
1574 {
1575         SLMP_INFO *info = dev_to_port(dev);
1576         unsigned char  new_encoding;
1577         unsigned short new_crctype;
1578
1579         /* return error if TTY interface open */
1580         if (info->port.count)
1581                 return -EBUSY;
1582
1583         switch (encoding)
1584         {
1585         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1586         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1587         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1588         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1589         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1590         default: return -EINVAL;
1591         }
1592
1593         switch (parity)
1594         {
1595         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1596         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1597         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1598         default: return -EINVAL;
1599         }
1600
1601         info->params.encoding = new_encoding;
1602         info->params.crc_type = new_crctype;
1603
1604         /* if network interface up, reprogram hardware */
1605         if (info->netcount)
1606                 program_hw(info);
1607
1608         return 0;
1609 }
1610
1611 /**
1612  * called by generic HDLC layer to send frame
1613  *
1614  * skb  socket buffer containing HDLC frame
1615  * dev  pointer to network device structure
1616  *
1617  * returns 0 if success, otherwise error code
1618  */
1619 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1620 {
1621         SLMP_INFO *info = dev_to_port(dev);
1622         unsigned long flags;
1623
1624         if (debug_level >= DEBUG_LEVEL_INFO)
1625                 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1626
1627         /* stop sending until this frame completes */
1628         netif_stop_queue(dev);
1629
1630         /* copy data to device buffers */
1631         info->tx_count = skb->len;
1632         tx_load_dma_buffer(info, skb->data, skb->len);
1633
1634         /* update network statistics */
1635         dev->stats.tx_packets++;
1636         dev->stats.tx_bytes += skb->len;
1637
1638         /* done with socket buffer, so free it */
1639         dev_kfree_skb(skb);
1640
1641         /* save start time for transmit timeout detection */
1642         dev->trans_start = jiffies;
1643
1644         /* start hardware transmitter if necessary */
1645         spin_lock_irqsave(&info->lock,flags);
1646         if (!info->tx_active)
1647                 tx_start(info);
1648         spin_unlock_irqrestore(&info->lock,flags);
1649
1650         return 0;
1651 }
1652
1653 /**
1654  * called by network layer when interface enabled
1655  * claim resources and initialize hardware
1656  *
1657  * dev  pointer to network device structure
1658  *
1659  * returns 0 if success, otherwise error code
1660  */
1661 static int hdlcdev_open(struct net_device *dev)
1662 {
1663         SLMP_INFO *info = dev_to_port(dev);
1664         int rc;
1665         unsigned long flags;
1666
1667         if (debug_level >= DEBUG_LEVEL_INFO)
1668                 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1669
1670         /* generic HDLC layer open processing */
1671         if ((rc = hdlc_open(dev)))
1672                 return rc;
1673
1674         /* arbitrate between network and tty opens */
1675         spin_lock_irqsave(&info->netlock, flags);
1676         if (info->port.count != 0 || info->netcount != 0) {
1677                 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1678                 spin_unlock_irqrestore(&info->netlock, flags);
1679                 return -EBUSY;
1680         }
1681         info->netcount=1;
1682         spin_unlock_irqrestore(&info->netlock, flags);
1683
1684         /* claim resources and init adapter */
1685         if ((rc = startup(info)) != 0) {
1686                 spin_lock_irqsave(&info->netlock, flags);
1687                 info->netcount=0;
1688                 spin_unlock_irqrestore(&info->netlock, flags);
1689                 return rc;
1690         }
1691
1692         /* assert DTR and RTS, apply hardware settings */
1693         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1694         program_hw(info);
1695
1696         /* enable network layer transmit */
1697         dev->trans_start = jiffies;
1698         netif_start_queue(dev);
1699
1700         /* inform generic HDLC layer of current DCD status */
1701         spin_lock_irqsave(&info->lock, flags);
1702         get_signals(info);
1703         spin_unlock_irqrestore(&info->lock, flags);
1704         if (info->serial_signals & SerialSignal_DCD)
1705                 netif_carrier_on(dev);
1706         else
1707                 netif_carrier_off(dev);
1708         return 0;
1709 }
1710
1711 /**
1712  * called by network layer when interface is disabled
1713  * shutdown hardware and release resources
1714  *
1715  * dev  pointer to network device structure
1716  *
1717  * returns 0 if success, otherwise error code
1718  */
1719 static int hdlcdev_close(struct net_device *dev)
1720 {
1721         SLMP_INFO *info = dev_to_port(dev);
1722         unsigned long flags;
1723
1724         if (debug_level >= DEBUG_LEVEL_INFO)
1725                 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1726
1727         netif_stop_queue(dev);
1728
1729         /* shutdown adapter and release resources */
1730         shutdown(info);
1731
1732         hdlc_close(dev);
1733
1734         spin_lock_irqsave(&info->netlock, flags);
1735         info->netcount=0;
1736         spin_unlock_irqrestore(&info->netlock, flags);
1737
1738         return 0;
1739 }
1740
1741 /**
1742  * called by network layer to process IOCTL call to network device
1743  *
1744  * dev  pointer to network device structure
1745  * ifr  pointer to network interface request structure
1746  * cmd  IOCTL command code
1747  *
1748  * returns 0 if success, otherwise error code
1749  */
1750 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1751 {
1752         const size_t size = sizeof(sync_serial_settings);
1753         sync_serial_settings new_line;
1754         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1755         SLMP_INFO *info = dev_to_port(dev);
1756         unsigned int flags;
1757
1758         if (debug_level >= DEBUG_LEVEL_INFO)
1759                 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1760
1761         /* return error if TTY interface open */
1762         if (info->port.count)
1763                 return -EBUSY;
1764
1765         if (cmd != SIOCWANDEV)
1766                 return hdlc_ioctl(dev, ifr, cmd);
1767
1768         switch(ifr->ifr_settings.type) {
1769         case IF_GET_IFACE: /* return current sync_serial_settings */
1770
1771                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1772                 if (ifr->ifr_settings.size < size) {
1773                         ifr->ifr_settings.size = size; /* data size wanted */
1774                         return -ENOBUFS;
1775                 }
1776
1777                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1778                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1779                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1780                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1781
1782                 switch (flags){
1783                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1784                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1785                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1786                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1787                 default: new_line.clock_type = CLOCK_DEFAULT;
1788                 }
1789
1790                 new_line.clock_rate = info->params.clock_speed;
1791                 new_line.loopback   = info->params.loopback ? 1:0;
1792
1793                 if (copy_to_user(line, &new_line, size))
1794                         return -EFAULT;
1795                 return 0;
1796
1797         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1798
1799                 if(!capable(CAP_NET_ADMIN))
1800                         return -EPERM;
1801                 if (copy_from_user(&new_line, line, size))
1802                         return -EFAULT;
1803
1804                 switch (new_line.clock_type)
1805                 {
1806                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1807                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1808                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1809                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1810                 case CLOCK_DEFAULT:  flags = info->params.flags &
1811                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1812                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1813                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1814                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1815                 default: return -EINVAL;
1816                 }
1817
1818                 if (new_line.loopback != 0 && new_line.loopback != 1)
1819                         return -EINVAL;
1820
1821                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1822                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1823                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1824                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1825                 info->params.flags |= flags;
1826
1827                 info->params.loopback = new_line.loopback;
1828
1829                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1830                         info->params.clock_speed = new_line.clock_rate;
1831                 else
1832                         info->params.clock_speed = 0;
1833
1834                 /* if network interface up, reprogram hardware */
1835                 if (info->netcount)
1836                         program_hw(info);
1837                 return 0;
1838
1839         default:
1840                 return hdlc_ioctl(dev, ifr, cmd);
1841         }
1842 }
1843
1844 /**
1845  * called by network layer when transmit timeout is detected
1846  *
1847  * dev  pointer to network device structure
1848  */
1849 static void hdlcdev_tx_timeout(struct net_device *dev)
1850 {
1851         SLMP_INFO *info = dev_to_port(dev);
1852         unsigned long flags;
1853
1854         if (debug_level >= DEBUG_LEVEL_INFO)
1855                 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1856
1857         dev->stats.tx_errors++;
1858         dev->stats.tx_aborted_errors++;
1859
1860         spin_lock_irqsave(&info->lock,flags);
1861         tx_stop(info);
1862         spin_unlock_irqrestore(&info->lock,flags);
1863
1864         netif_wake_queue(dev);
1865 }
1866
1867 /**
1868  * called by device driver when transmit completes
1869  * reenable network layer transmit if stopped
1870  *
1871  * info  pointer to device instance information
1872  */
1873 static void hdlcdev_tx_done(SLMP_INFO *info)
1874 {
1875         if (netif_queue_stopped(info->netdev))
1876                 netif_wake_queue(info->netdev);
1877 }
1878
1879 /**
1880  * called by device driver when frame received
1881  * pass frame to network layer
1882  *
1883  * info  pointer to device instance information
1884  * buf   pointer to buffer contianing frame data
1885  * size  count of data bytes in buf
1886  */
1887 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1888 {
1889         struct sk_buff *skb = dev_alloc_skb(size);
1890         struct net_device *dev = info->netdev;
1891
1892         if (debug_level >= DEBUG_LEVEL_INFO)
1893                 printk("hdlcdev_rx(%s)\n",dev->name);
1894
1895         if (skb == NULL) {
1896                 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1897                        dev->name);
1898                 dev->stats.rx_dropped++;
1899                 return;
1900         }
1901
1902         memcpy(skb_put(skb, size), buf, size);
1903
1904         skb->protocol = hdlc_type_trans(skb, dev);
1905
1906         dev->stats.rx_packets++;
1907         dev->stats.rx_bytes += size;
1908
1909         netif_rx(skb);
1910 }
1911
1912 static const struct net_device_ops hdlcdev_ops = {
1913         .ndo_open       = hdlcdev_open,
1914         .ndo_stop       = hdlcdev_close,
1915         .ndo_change_mtu = hdlc_change_mtu,
1916         .ndo_start_xmit = hdlc_start_xmit,
1917         .ndo_do_ioctl   = hdlcdev_ioctl,
1918         .ndo_tx_timeout = hdlcdev_tx_timeout,
1919 };
1920
1921 /**
1922  * called by device driver when adding device instance
1923  * do generic HDLC initialization
1924  *
1925  * info  pointer to device instance information
1926  *
1927  * returns 0 if success, otherwise error code
1928  */
1929 static int hdlcdev_init(SLMP_INFO *info)
1930 {
1931         int rc;
1932         struct net_device *dev;
1933         hdlc_device *hdlc;
1934
1935         /* allocate and initialize network and HDLC layer objects */
1936
1937         if (!(dev = alloc_hdlcdev(info))) {
1938                 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1939                 return -ENOMEM;
1940         }
1941
1942         /* for network layer reporting purposes only */
1943         dev->mem_start = info->phys_sca_base;
1944         dev->mem_end   = info->phys_sca_base + SCA_BASE_SIZE - 1;
1945         dev->irq       = info->irq_level;
1946
1947         /* network layer callbacks and settings */
1948         dev->netdev_ops     = &hdlcdev_ops;
1949         dev->watchdog_timeo = 10 * HZ;
1950         dev->tx_queue_len   = 50;
1951
1952         /* generic HDLC layer callbacks and settings */
1953         hdlc         = dev_to_hdlc(dev);
1954         hdlc->attach = hdlcdev_attach;
1955         hdlc->xmit   = hdlcdev_xmit;
1956
1957         /* register objects with HDLC layer */
1958         if ((rc = register_hdlc_device(dev))) {
1959                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1960                 free_netdev(dev);
1961                 return rc;
1962         }
1963
1964         info->netdev = dev;
1965         return 0;
1966 }
1967
1968 /**
1969  * called by device driver when removing device instance
1970  * do generic HDLC cleanup
1971  *
1972  * info  pointer to device instance information
1973  */
1974 static void hdlcdev_exit(SLMP_INFO *info)
1975 {
1976         unregister_hdlc_device(info->netdev);
1977         free_netdev(info->netdev);
1978         info->netdev = NULL;
1979 }
1980
1981 #endif /* CONFIG_HDLC */
1982
1983
1984 /* Return next bottom half action to perform.
1985  * Return Value:        BH action code or 0 if nothing to do.
1986  */
1987 static int bh_action(SLMP_INFO *info)
1988 {
1989         unsigned long flags;
1990         int rc = 0;
1991
1992         spin_lock_irqsave(&info->lock,flags);
1993
1994         if (info->pending_bh & BH_RECEIVE) {
1995                 info->pending_bh &= ~BH_RECEIVE;
1996                 rc = BH_RECEIVE;
1997         } else if (info->pending_bh & BH_TRANSMIT) {
1998                 info->pending_bh &= ~BH_TRANSMIT;
1999                 rc = BH_TRANSMIT;
2000         } else if (info->pending_bh & BH_STATUS) {
2001                 info->pending_bh &= ~BH_STATUS;
2002                 rc = BH_STATUS;
2003         }
2004
2005         if (!rc) {
2006                 /* Mark BH routine as complete */
2007                 info->bh_running = false;
2008                 info->bh_requested = false;
2009         }
2010
2011         spin_unlock_irqrestore(&info->lock,flags);
2012
2013         return rc;
2014 }
2015
2016 /* Perform bottom half processing of work items queued by ISR.
2017  */
2018 static void bh_handler(struct work_struct *work)
2019 {
2020         SLMP_INFO *info = container_of(work, SLMP_INFO, task);
2021         int action;
2022
2023         if (!info)
2024                 return;
2025
2026         if ( debug_level >= DEBUG_LEVEL_BH )
2027                 printk( "%s(%d):%s bh_handler() entry\n",
2028                         __FILE__,__LINE__,info->device_name);
2029
2030         info->bh_running = true;
2031
2032         while((action = bh_action(info)) != 0) {
2033
2034                 /* Process work item */
2035                 if ( debug_level >= DEBUG_LEVEL_BH )
2036                         printk( "%s(%d):%s bh_handler() work item action=%d\n",
2037                                 __FILE__,__LINE__,info->device_name, action);
2038
2039                 switch (action) {
2040
2041                 case BH_RECEIVE:
2042                         bh_receive(info);
2043                         break;
2044                 case BH_TRANSMIT:
2045                         bh_transmit(info);
2046                         break;
2047                 case BH_STATUS:
2048                         bh_status(info);
2049                         break;
2050                 default:
2051                         /* unknown work item ID */
2052                         printk("%s(%d):%s Unknown work item ID=%08X!\n",
2053                                 __FILE__,__LINE__,info->device_name,action);
2054                         break;
2055                 }
2056         }
2057
2058         if ( debug_level >= DEBUG_LEVEL_BH )
2059                 printk( "%s(%d):%s bh_handler() exit\n",
2060                         __FILE__,__LINE__,info->device_name);
2061 }
2062
2063 static void bh_receive(SLMP_INFO *info)
2064 {
2065         if ( debug_level >= DEBUG_LEVEL_BH )
2066                 printk( "%s(%d):%s bh_receive()\n",
2067                         __FILE__,__LINE__,info->device_name);
2068
2069         while( rx_get_frame(info) );
2070 }
2071
2072 static void bh_transmit(SLMP_INFO *info)
2073 {
2074         struct tty_struct *tty = info->port.tty;
2075
2076         if ( debug_level >= DEBUG_LEVEL_BH )
2077                 printk( "%s(%d):%s bh_transmit() entry\n",
2078                         __FILE__,__LINE__,info->device_name);
2079
2080         if (tty)
2081                 tty_wakeup(tty);
2082 }
2083
2084 static void bh_status(SLMP_INFO *info)
2085 {
2086         if ( debug_level >= DEBUG_LEVEL_BH )
2087                 printk( "%s(%d):%s bh_status() entry\n",
2088                         __FILE__,__LINE__,info->device_name);
2089
2090         info->ri_chkcount = 0;
2091         info->dsr_chkcount = 0;
2092         info->dcd_chkcount = 0;
2093         info->cts_chkcount = 0;
2094 }
2095
2096 static void isr_timer(SLMP_INFO * info)
2097 {
2098         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2099
2100         /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2101         write_reg(info, IER2, 0);
2102
2103         /* TMCS, Timer Control/Status Register
2104          *
2105          * 07      CMF, Compare match flag (read only) 1=match
2106          * 06      ECMI, CMF Interrupt Enable: 0=disabled
2107          * 05      Reserved, must be 0
2108          * 04      TME, Timer Enable
2109          * 03..00  Reserved, must be 0
2110          *
2111          * 0000 0000
2112          */
2113         write_reg(info, (unsigned char)(timer + TMCS), 0);
2114
2115         info->irq_occurred = true;
2116
2117         if ( debug_level >= DEBUG_LEVEL_ISR )
2118                 printk("%s(%d):%s isr_timer()\n",
2119                         __FILE__,__LINE__,info->device_name);
2120 }
2121
2122 static void isr_rxint(SLMP_INFO * info)
2123 {
2124         struct tty_struct *tty = info->port.tty;
2125         struct  mgsl_icount *icount = &info->icount;
2126         unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2127         unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2128
2129         /* clear status bits */
2130         if (status)
2131                 write_reg(info, SR1, status);
2132
2133         if (status2)
2134                 write_reg(info, SR2, status2);
2135
2136         if ( debug_level >= DEBUG_LEVEL_ISR )
2137                 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2138                         __FILE__,__LINE__,info->device_name,status,status2);
2139
2140         if (info->params.mode == MGSL_MODE_ASYNC) {
2141                 if (status & BRKD) {
2142                         icount->brk++;
2143
2144                         /* process break detection if tty control
2145                          * is not set to ignore it
2146                          */
2147                         if ( tty ) {
2148                                 if (!(status & info->ignore_status_mask1)) {
2149                                         if (info->read_status_mask1 & BRKD) {
2150                                                 tty_insert_flip_char(tty, 0, TTY_BREAK);
2151                                                 if (info->port.flags & ASYNC_SAK)
2152                                                         do_SAK(tty);
2153                                         }
2154                                 }
2155                         }
2156                 }
2157         }
2158         else {
2159                 if (status & (FLGD|IDLD)) {
2160                         if (status & FLGD)
2161                                 info->icount.exithunt++;
2162                         else if (status & IDLD)
2163                                 info->icount.rxidle++;
2164                         wake_up_interruptible(&info->event_wait_q);
2165                 }
2166         }
2167
2168         if (status & CDCD) {
2169                 /* simulate a common modem status change interrupt
2170                  * for our handler
2171                  */
2172                 get_signals( info );
2173                 isr_io_pin(info,
2174                         MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2175         }
2176 }
2177
2178 /*
2179  * handle async rx data interrupts
2180  */
2181 static void isr_rxrdy(SLMP_INFO * info)
2182 {
2183         u16 status;
2184         unsigned char DataByte;
2185         struct tty_struct *tty = info->port.tty;
2186         struct  mgsl_icount *icount = &info->icount;
2187
2188         if ( debug_level >= DEBUG_LEVEL_ISR )
2189                 printk("%s(%d):%s isr_rxrdy\n",
2190                         __FILE__,__LINE__,info->device_name);
2191
2192         while((status = read_reg(info,CST0)) & BIT0)
2193         {
2194                 int flag = 0;
2195                 bool over = false;
2196                 DataByte = read_reg(info,TRB);
2197
2198                 icount->rx++;
2199
2200                 if ( status & (PE + FRME + OVRN) ) {
2201                         printk("%s(%d):%s rxerr=%04X\n",
2202                                 __FILE__,__LINE__,info->device_name,status);
2203
2204                         /* update error statistics */
2205                         if (status & PE)
2206                                 icount->parity++;
2207                         else if (status & FRME)
2208                                 icount->frame++;
2209                         else if (status & OVRN)
2210                                 icount->overrun++;
2211
2212                         /* discard char if tty control flags say so */
2213                         if (status & info->ignore_status_mask2)
2214                                 continue;
2215
2216                         status &= info->read_status_mask2;
2217
2218                         if ( tty ) {
2219                                 if (status & PE)
2220                                         flag = TTY_PARITY;
2221                                 else if (status & FRME)
2222                                         flag = TTY_FRAME;
2223                                 if (status & OVRN) {
2224                                         /* Overrun is special, since it's
2225                                          * reported immediately, and doesn't
2226                                          * affect the current character
2227                                          */
2228                                         over = true;
2229                                 }
2230                         }
2231                 }       /* end of if (error) */
2232
2233                 if ( tty ) {
2234                         tty_insert_flip_char(tty, DataByte, flag);
2235                         if (over)
2236                                 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
2237                 }
2238         }
2239
2240         if ( debug_level >= DEBUG_LEVEL_ISR ) {
2241                 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2242                         __FILE__,__LINE__,info->device_name,
2243                         icount->rx,icount->brk,icount->parity,
2244                         icount->frame,icount->overrun);
2245         }
2246
2247         if ( tty )
2248                 tty_flip_buffer_push(tty);
2249 }
2250
2251 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2252 {
2253         if ( debug_level >= DEBUG_LEVEL_ISR )
2254                 printk("%s(%d):%s isr_txeom status=%02x\n",
2255                         __FILE__,__LINE__,info->device_name,status);
2256
2257         write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2258         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2259         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2260
2261         if (status & UDRN) {
2262                 write_reg(info, CMD, TXRESET);
2263                 write_reg(info, CMD, TXENABLE);
2264         } else
2265                 write_reg(info, CMD, TXBUFCLR);
2266
2267         /* disable and clear tx interrupts */
2268         info->ie0_value &= ~TXRDYE;
2269         info->ie1_value &= ~(IDLE + UDRN);
2270         write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2271         write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2272
2273         if ( info->tx_active ) {
2274                 if (info->params.mode != MGSL_MODE_ASYNC) {
2275                         if (status & UDRN)
2276                                 info->icount.txunder++;
2277                         else if (status & IDLE)
2278                                 info->icount.txok++;
2279                 }
2280
2281                 info->tx_active = false;
2282                 info->tx_count = info->tx_put = info->tx_get = 0;
2283
2284                 del_timer(&info->tx_timer);
2285
2286                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2287                         info->serial_signals &= ~SerialSignal_RTS;
2288                         info->drop_rts_on_tx_done = false;
2289                         set_signals(info);
2290                 }
2291
2292 #if SYNCLINK_GENERIC_HDLC
2293                 if (info->netcount)
2294                         hdlcdev_tx_done(info);
2295                 else
2296 #endif
2297                 {
2298                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2299                                 tx_stop(info);
2300                                 return;
2301                         }
2302                         info->pending_bh |= BH_TRANSMIT;
2303                 }
2304         }
2305 }
2306
2307
2308 /*
2309  * handle tx status interrupts
2310  */
2311 static void isr_txint(SLMP_INFO * info)
2312 {
2313         unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2314
2315         /* clear status bits */
2316         write_reg(info, SR1, status);
2317
2318         if ( debug_level >= DEBUG_LEVEL_ISR )
2319                 printk("%s(%d):%s isr_txint status=%02x\n",
2320                         __FILE__,__LINE__,info->device_name,status);
2321
2322         if (status & (UDRN + IDLE))
2323                 isr_txeom(info, status);
2324
2325         if (status & CCTS) {
2326                 /* simulate a common modem status change interrupt
2327                  * for our handler
2328                  */
2329                 get_signals( info );
2330                 isr_io_pin(info,
2331                         MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2332
2333         }
2334 }
2335
2336 /*
2337  * handle async tx data interrupts
2338  */
2339 static void isr_txrdy(SLMP_INFO * info)
2340 {
2341         if ( debug_level >= DEBUG_LEVEL_ISR )
2342                 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2343                         __FILE__,__LINE__,info->device_name,info->tx_count);
2344
2345         if (info->params.mode != MGSL_MODE_ASYNC) {
2346                 /* disable TXRDY IRQ, enable IDLE IRQ */
2347                 info->ie0_value &= ~TXRDYE;
2348                 info->ie1_value |= IDLE;
2349                 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2350                 return;
2351         }
2352
2353         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2354                 tx_stop(info);
2355                 return;
2356         }
2357
2358         if ( info->tx_count )
2359                 tx_load_fifo( info );
2360         else {
2361                 info->tx_active = false;
2362                 info->ie0_value &= ~TXRDYE;
2363                 write_reg(info, IE0, info->ie0_value);
2364         }
2365
2366         if (info->tx_count < WAKEUP_CHARS)
2367                 info->pending_bh |= BH_TRANSMIT;
2368 }
2369
2370 static void isr_rxdmaok(SLMP_INFO * info)
2371 {
2372         /* BIT7 = EOT (end of transfer)
2373          * BIT6 = EOM (end of message/frame)
2374          */
2375         unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2376
2377         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2378         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2379
2380         if ( debug_level >= DEBUG_LEVEL_ISR )
2381                 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2382                         __FILE__,__LINE__,info->device_name,status);
2383
2384         info->pending_bh |= BH_RECEIVE;
2385 }
2386
2387 static void isr_rxdmaerror(SLMP_INFO * info)
2388 {
2389         /* BIT5 = BOF (buffer overflow)
2390          * BIT4 = COF (counter overflow)
2391          */
2392         unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2393
2394         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2395         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2396
2397         if ( debug_level >= DEBUG_LEVEL_ISR )
2398                 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2399                         __FILE__,__LINE__,info->device_name,status);
2400
2401         info->rx_overflow = true;
2402         info->pending_bh |= BH_RECEIVE;
2403 }
2404
2405 static void isr_txdmaok(SLMP_INFO * info)
2406 {
2407         unsigned char status_reg1 = read_reg(info, SR1);
2408
2409         write_reg(info, TXDMA + DIR, 0x00);     /* disable Tx DMA IRQs */
2410         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2411         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2412
2413         if ( debug_level >= DEBUG_LEVEL_ISR )
2414                 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2415                         __FILE__,__LINE__,info->device_name,status_reg1);
2416
2417         /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2418         write_reg16(info, TRC0, 0);
2419         info->ie0_value |= TXRDYE;
2420         write_reg(info, IE0, info->ie0_value);
2421 }
2422
2423 static void isr_txdmaerror(SLMP_INFO * info)
2424 {
2425         /* BIT5 = BOF (buffer overflow)
2426          * BIT4 = COF (counter overflow)
2427          */
2428         unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2429
2430         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2431         write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2432
2433         if ( debug_level >= DEBUG_LEVEL_ISR )
2434                 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2435                         __FILE__,__LINE__,info->device_name,status);
2436 }
2437
2438 /* handle input serial signal changes
2439  */
2440 static void isr_io_pin( SLMP_INFO *info, u16 status )
2441 {
2442         struct  mgsl_icount *icount;
2443
2444         if ( debug_level >= DEBUG_LEVEL_ISR )
2445                 printk("%s(%d):isr_io_pin status=%04X\n",
2446                         __FILE__,__LINE__,status);
2447
2448         if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2449                       MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2450                 icount = &info->icount;
2451                 /* update input line counters */
2452                 if (status & MISCSTATUS_RI_LATCHED) {
2453                         icount->rng++;
2454                         if ( status & SerialSignal_RI )
2455                                 info->input_signal_events.ri_up++;
2456                         else
2457                                 info->input_signal_events.ri_down++;
2458                 }
2459                 if (status & MISCSTATUS_DSR_LATCHED) {
2460                         icount->dsr++;
2461                         if ( status & SerialSignal_DSR )
2462                                 info->input_signal_events.dsr_up++;
2463                         else
2464                                 info->input_signal_events.dsr_down++;
2465                 }
2466                 if (status & MISCSTATUS_DCD_LATCHED) {
2467                         if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2468                                 info->ie1_value &= ~CDCD;
2469                                 write_reg(info, IE1, info->ie1_value);
2470                         }
2471                         icount->dcd++;
2472                         if (status & SerialSignal_DCD) {
2473                                 info->input_signal_events.dcd_up++;
2474                         } else
2475                                 info->input_signal_events.dcd_down++;
2476 #if SYNCLINK_GENERIC_HDLC
2477                         if (info->netcount) {
2478                                 if (status & SerialSignal_DCD)
2479                                         netif_carrier_on(info->netdev);
2480                                 else
2481                                         netif_carrier_off(info->netdev);
2482                         }
2483 #endif
2484                 }
2485                 if (status & MISCSTATUS_CTS_LATCHED)
2486                 {
2487                         if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2488                                 info->ie1_value &= ~CCTS;
2489                                 write_reg(info, IE1, info->ie1_value);
2490                         }
2491                         icount->cts++;
2492                         if ( status & SerialSignal_CTS )
2493                                 info->input_signal_events.cts_up++;
2494                         else
2495                                 info->input_signal_events.cts_down++;
2496                 }
2497                 wake_up_interruptible(&info->status_event_wait_q);
2498                 wake_up_interruptible(&info->event_wait_q);
2499
2500                 if ( (info->port.flags & ASYNC_CHECK_CD) &&
2501                      (status & MISCSTATUS_DCD_LATCHED) ) {
2502                         if ( debug_level >= DEBUG_LEVEL_ISR )
2503                                 printk("%s CD now %s...", info->device_name,
2504                                        (status & SerialSignal_DCD) ? "on" : "off");
2505                         if (status & SerialSignal_DCD)
2506                                 wake_up_interruptible(&info->port.open_wait);
2507                         else {
2508                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2509                                         printk("doing serial hangup...");
2510                                 if (info->port.tty)
2511                                         tty_hangup(info->port.tty);
2512                         }
2513                 }
2514
2515                 if ( (info->port.flags & ASYNC_CTS_FLOW) &&
2516                      (status & MISCSTATUS_CTS_LATCHED) ) {
2517                         if ( info->port.tty ) {
2518                                 if (info->port.tty->hw_stopped) {
2519                                         if (status & SerialSignal_CTS) {
2520                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2521                                                         printk("CTS tx start...");
2522                                                 info->port.tty->hw_stopped = 0;
2523                                                 tx_start(info);
2524                                                 info->pending_bh |= BH_TRANSMIT;
2525                                                 return;
2526                                         }
2527                                 } else {
2528                                         if (!(status & SerialSignal_CTS)) {
2529                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2530                                                         printk("CTS tx stop...");
2531                                                 info->port.tty->hw_stopped = 1;
2532                                                 tx_stop(info);
2533                                         }
2534                                 }
2535                         }
2536                 }
2537         }
2538
2539         info->pending_bh |= BH_STATUS;
2540 }
2541
2542 /* Interrupt service routine entry point.
2543  *
2544  * Arguments:
2545  *      irq             interrupt number that caused interrupt
2546  *      dev_id          device ID supplied during interrupt registration
2547  *      regs            interrupted processor context
2548  */
2549 static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2550 {
2551         SLMP_INFO *info = dev_id;
2552         unsigned char status, status0, status1=0;
2553         unsigned char dmastatus, dmastatus0, dmastatus1=0;
2554         unsigned char timerstatus0, timerstatus1=0;
2555         unsigned char shift;
2556         unsigned int i;
2557         unsigned short tmp;
2558
2559         if ( debug_level >= DEBUG_LEVEL_ISR )
2560                 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2561                         __FILE__, __LINE__, info->irq_level);
2562
2563         spin_lock(&info->lock);
2564
2565         for(;;) {
2566
2567                 /* get status for SCA0 (ports 0-1) */
2568                 tmp = read_reg16(info, ISR0);   /* get ISR0 and ISR1 in one read */
2569                 status0 = (unsigned char)tmp;
2570                 dmastatus0 = (unsigned char)(tmp>>8);
2571                 timerstatus0 = read_reg(info, ISR2);
2572
2573                 if ( debug_level >= DEBUG_LEVEL_ISR )
2574                         printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2575                                 __FILE__, __LINE__, info->device_name,
2576                                 status0, dmastatus0, timerstatus0);
2577
2578                 if (info->port_count == 4) {
2579                         /* get status for SCA1 (ports 2-3) */
2580                         tmp = read_reg16(info->port_array[2], ISR0);
2581                         status1 = (unsigned char)tmp;
2582                         dmastatus1 = (unsigned char)(tmp>>8);
2583                         timerstatus1 = read_reg(info->port_array[2], ISR2);
2584
2585                         if ( debug_level >= DEBUG_LEVEL_ISR )
2586                                 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2587                                         __FILE__,__LINE__,info->device_name,
2588                                         status1,dmastatus1,timerstatus1);
2589                 }
2590
2591                 if (!status0 && !dmastatus0 && !timerstatus0 &&
2592                          !status1 && !dmastatus1 && !timerstatus1)
2593                         break;
2594
2595                 for(i=0; i < info->port_count ; i++) {
2596                         if (info->port_array[i] == NULL)
2597                                 continue;
2598                         if (i < 2) {
2599                                 status = status0;
2600                                 dmastatus = dmastatus0;
2601                         } else {
2602                                 status = status1;
2603                                 dmastatus = dmastatus1;
2604                         }
2605
2606                         shift = i & 1 ? 4 :0;
2607
2608                         if (status & BIT0 << shift)
2609                                 isr_rxrdy(info->port_array[i]);
2610                         if (status & BIT1 << shift)
2611                                 isr_txrdy(info->port_array[i]);
2612                         if (status & BIT2 << shift)
2613                                 isr_rxint(info->port_array[i]);
2614                         if (status & BIT3 << shift)
2615                                 isr_txint(info->port_array[i]);
2616
2617                         if (dmastatus & BIT0 << shift)
2618                                 isr_rxdmaerror(info->port_array[i]);
2619                         if (dmastatus & BIT1 << shift)
2620                                 isr_rxdmaok(info->port_array[i]);
2621                         if (dmastatus & BIT2 << shift)
2622                                 isr_txdmaerror(info->port_array[i]);
2623                         if (dmastatus & BIT3 << shift)
2624                                 isr_txdmaok(info->port_array[i]);
2625                 }
2626
2627                 if (timerstatus0 & (BIT5 | BIT4))
2628                         isr_timer(info->port_array[0]);
2629                 if (timerstatus0 & (BIT7 | BIT6))
2630                         isr_timer(info->port_array[1]);
2631                 if (timerstatus1 & (BIT5 | BIT4))
2632                         isr_timer(info->port_array[2]);
2633                 if (timerstatus1 & (BIT7 | BIT6))
2634                         isr_timer(info->port_array[3]);
2635         }
2636
2637         for(i=0; i < info->port_count ; i++) {
2638                 SLMP_INFO * port = info->port_array[i];
2639
2640                 /* Request bottom half processing if there's something
2641                  * for it to do and the bh is not already running.
2642                  *
2643                  * Note: startup adapter diags require interrupts.
2644                  * do not request bottom half processing if the
2645                  * device is not open in a normal mode.
2646                  */
2647                 if ( port && (port->port.count || port->netcount) &&
2648                      port->pending_bh && !port->bh_running &&
2649                      !port->bh_requested ) {
2650                         if ( debug_level >= DEBUG_LEVEL_ISR )
2651                                 printk("%s(%d):%s queueing bh task.\n",
2652                                         __FILE__,__LINE__,port->device_name);
2653                         schedule_work(&port->task);
2654                         port->bh_requested = true;
2655                 }
2656         }
2657
2658         spin_unlock(&info->lock);
2659
2660         if ( debug_level >= DEBUG_LEVEL_ISR )
2661                 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2662                         __FILE__, __LINE__, info->irq_level);
2663         return IRQ_HANDLED;
2664 }
2665
2666 /* Initialize and start device.
2667  */
2668 static int startup(SLMP_INFO * info)
2669 {
2670         if ( debug_level >= DEBUG_LEVEL_INFO )
2671                 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2672
2673         if (info->port.flags & ASYNC_INITIALIZED)
2674                 return 0;
2675
2676         if (!info->tx_buf) {
2677                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2678                 if (!info->tx_buf) {
2679                         printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2680                                 __FILE__,__LINE__,info->device_name);
2681                         return -ENOMEM;
2682                 }
2683         }
2684
2685         info->pending_bh = 0;
2686
2687         memset(&info->icount, 0, sizeof(info->icount));
2688
2689         /* program hardware for current parameters */
2690         reset_port(info);
2691
2692         change_params(info);
2693
2694         mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2695
2696         if (info->port.tty)
2697                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2698
2699         info->port.flags |= ASYNC_INITIALIZED;
2700
2701         return 0;
2702 }
2703
2704 /* Called by close() and hangup() to shutdown hardware
2705  */
2706 static void shutdown(SLMP_INFO * info)
2707 {
2708         unsigned long flags;
2709
2710         if (!(info->port.flags & ASYNC_INITIALIZED))
2711                 return;
2712
2713         if (debug_level >= DEBUG_LEVEL_INFO)
2714                 printk("%s(%d):%s synclinkmp_shutdown()\n",
2715                          __FILE__,__LINE__, info->device_name );
2716
2717         /* clear status wait queue because status changes */
2718         /* can't happen after shutting down the hardware */
2719         wake_up_interruptible(&info->status_event_wait_q);
2720         wake_up_interruptible(&info->event_wait_q);
2721
2722         del_timer(&info->tx_timer);
2723         del_timer(&info->status_timer);
2724
2725         kfree(info->tx_buf);
2726         info->tx_buf = NULL;
2727
2728         spin_lock_irqsave(&info->lock,flags);
2729
2730         reset_port(info);
2731
2732         if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2733                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2734                 set_signals(info);
2735         }
2736
2737         spin_unlock_irqrestore(&info->lock,flags);
2738
2739         if (info->port.tty)
2740                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2741
2742         info->port.flags &= ~ASYNC_INITIALIZED;
2743 }
2744
2745 static void program_hw(SLMP_INFO *info)
2746 {
2747         unsigned long flags;
2748
2749         spin_lock_irqsave(&info->lock,flags);
2750
2751         rx_stop(info);
2752         tx_stop(info);
2753
2754         info->tx_count = info->tx_put = info->tx_get = 0;
2755
2756         if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2757                 hdlc_mode(info);
2758         else
2759                 async_mode(info);
2760
2761         set_signals(info);
2762
2763         info->dcd_chkcount = 0;
2764         info->cts_chkcount = 0;
2765         info->ri_chkcount = 0;
2766         info->dsr_chkcount = 0;
2767
2768         info->ie1_value |= (CDCD|CCTS);
2769         write_reg(info, IE1, info->ie1_value);
2770
2771         get_signals(info);
2772
2773         if (info->netcount || (info->port.tty && info->port.tty->termios->c_cflag & CREAD) )
2774                 rx_start(info);
2775
2776         spin_unlock_irqrestore(&info->lock,flags);
2777 }
2778
2779 /* Reconfigure adapter based on new parameters
2780  */
2781 static void change_params(SLMP_INFO *info)
2782 {
2783         unsigned cflag;
2784         int bits_per_char;
2785
2786         if (!info->port.tty || !info->port.tty->termios)
2787                 return;
2788
2789         if (debug_level >= DEBUG_LEVEL_INFO)
2790                 printk("%s(%d):%s change_params()\n",
2791                          __FILE__,__LINE__, info->device_name );
2792
2793         cflag = info->port.tty->termios->c_cflag;
2794
2795         /* if B0 rate (hangup) specified then negate DTR and RTS */
2796         /* otherwise assert DTR and RTS */
2797         if (cflag & CBAUD)
2798                 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2799         else
2800                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2801
2802         /* byte size and parity */
2803
2804         switch (cflag & CSIZE) {
2805               case CS5: info->params.data_bits = 5; break;
2806               case CS6: info->params.data_bits = 6; break;
2807               case CS7: info->params.data_bits = 7; break;
2808               case CS8: info->params.data_bits = 8; break;
2809               /* Never happens, but GCC is too dumb to figure it out */
2810               default:  info->params.data_bits = 7; break;
2811               }
2812
2813         if (cflag & CSTOPB)
2814                 info->params.stop_bits = 2;
2815         else
2816                 info->params.stop_bits = 1;
2817
2818         info->params.parity = ASYNC_PARITY_NONE;
2819         if (cflag & PARENB) {
2820                 if (cflag & PARODD)
2821                         info->params.parity = ASYNC_PARITY_ODD;
2822                 else
2823                         info->params.parity = ASYNC_PARITY_EVEN;
2824 #ifdef CMSPAR
2825                 if (cflag & CMSPAR)
2826                         info->params.parity = ASYNC_PARITY_SPACE;
2827 #endif
2828         }
2829
2830         /* calculate number of jiffies to transmit a full
2831          * FIFO (32 bytes) at specified data rate
2832          */
2833         bits_per_char = info->params.data_bits +
2834                         info->params.stop_bits + 1;
2835
2836         /* if port data rate is set to 460800 or less then
2837          * allow tty settings to override, otherwise keep the
2838          * current data rate.
2839          */
2840         if (info->params.data_rate <= 460800) {
2841                 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2842         }
2843
2844         if ( info->params.data_rate ) {
2845                 info->timeout = (32*HZ*bits_per_char) /
2846                                 info->params.data_rate;
2847         }
2848         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2849
2850         if (cflag & CRTSCTS)
2851                 info->port.flags |= ASYNC_CTS_FLOW;
2852         else
2853                 info->port.flags &= ~ASYNC_CTS_FLOW;
2854
2855         if (cflag & CLOCAL)
2856                 info->port.flags &= ~ASYNC_CHECK_CD;
2857         else
2858                 info->port.flags |= ASYNC_CHECK_CD;
2859
2860         /* process tty input control flags */
2861
2862         info->read_status_mask2 = OVRN;
2863         if (I_INPCK(info->port.tty))
2864                 info->read_status_mask2 |= PE | FRME;
2865         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2866                 info->read_status_mask1 |= BRKD;
2867         if (I_IGNPAR(info->port.tty))
2868                 info->ignore_status_mask2 |= PE | FRME;
2869         if (I_IGNBRK(info->port.tty)) {
2870                 info->ignore_status_mask1 |= BRKD;
2871                 /* If ignoring parity and break indicators, ignore
2872                  * overruns too.  (For real raw support).
2873                  */
2874                 if (I_IGNPAR(info->port.tty))
2875                         info->ignore_status_mask2 |= OVRN;
2876         }
2877
2878         program_hw(info);
2879 }
2880
2881 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2882 {
2883         int err;
2884
2885         if (debug_level >= DEBUG_LEVEL_INFO)
2886                 printk("%s(%d):%s get_params()\n",
2887                          __FILE__,__LINE__, info->device_name);
2888
2889         if (!user_icount) {
2890                 memset(&info->icount, 0, sizeof(info->icount));
2891         } else {
2892                 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2893                 if (err)
2894                         return -EFAULT;
2895         }
2896
2897         return 0;
2898 }
2899
2900 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2901 {
2902         int err;
2903         if (debug_level >= DEBUG_LEVEL_INFO)
2904                 printk("%s(%d):%s get_params()\n",
2905                          __FILE__,__LINE__, info->device_name);
2906
2907         COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2908         if (err) {
2909                 if ( debug_level >= DEBUG_LEVEL_INFO )
2910                         printk( "%s(%d):%s get_params() user buffer copy failed\n",
2911                                 __FILE__,__LINE__,info->device_name);
2912                 return -EFAULT;
2913         }
2914
2915         return 0;
2916 }
2917
2918 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2919 {
2920         unsigned long flags;
2921         MGSL_PARAMS tmp_params;
2922         int err;
2923
2924         if (debug_level >= DEBUG_LEVEL_INFO)
2925                 printk("%s(%d):%s set_params\n",
2926                         __FILE__,__LINE__,info->device_name );
2927         COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2928         if (err) {
2929                 if ( debug_level >= DEBUG_LEVEL_INFO )
2930                         printk( "%s(%d):%s set_params() user buffer copy failed\n",
2931                                 __FILE__,__LINE__,info->device_name);
2932                 return -EFAULT;
2933         }
2934
2935         spin_lock_irqsave(&info->lock,flags);
2936         memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2937         spin_unlock_irqrestore(&info->lock,flags);
2938
2939         change_params(info);
2940
2941         return 0;
2942 }
2943
2944 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2945 {
2946         int err;
2947
2948         if (debug_level >= DEBUG_LEVEL_INFO)
2949                 printk("%s(%d):%s get_txidle()=%d\n",
2950                          __FILE__,__LINE__, info->device_name, info->idle_mode);
2951
2952         COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2953         if (err) {
2954                 if ( debug_level >= DEBUG_LEVEL_INFO )
2955                         printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2956                                 __FILE__,__LINE__,info->device_name);
2957                 return -EFAULT;
2958         }
2959
2960         return 0;
2961 }
2962
2963 static int set_txidle(SLMP_INFO * info, int idle_mode)
2964 {
2965         unsigned long flags;
2966
2967         if (debug_level >= DEBUG_LEVEL_INFO)
2968                 printk("%s(%d):%s set_txidle(%d)\n",
2969                         __FILE__,__LINE__,info->device_name, idle_mode );
2970
2971         spin_lock_irqsave(&info->lock,flags);
2972         info->idle_mode = idle_mode;
2973         tx_set_idle( info );
2974         spin_unlock_irqrestore(&info->lock,flags);
2975         return 0;
2976 }
2977
2978 static int tx_enable(SLMP_INFO * info, int enable)
2979 {
2980         unsigned long flags;
2981
2982         if (debug_level >= DEBUG_LEVEL_INFO)
2983                 printk("%s(%d):%s tx_enable(%d)\n",
2984                         __FILE__,__LINE__,info->device_name, enable);
2985
2986         spin_lock_irqsave(&info->lock,flags);
2987         if ( enable ) {
2988                 if ( !info->tx_enabled ) {
2989                         tx_start(info);
2990                 }
2991         } else {
2992                 if ( info->tx_enabled )
2993                         tx_stop(info);
2994         }
2995         spin_unlock_irqrestore(&info->lock,flags);
2996         return 0;
2997 }
2998
2999 /* abort send HDLC frame
3000  */
3001 static int tx_abort(SLMP_INFO * info)
3002 {
3003         unsigned long flags;
3004
3005         if (debug_level >= DEBUG_LEVEL_INFO)
3006                 printk("%s(%d):%s tx_abort()\n",
3007                         __FILE__,__LINE__,info->device_name);
3008
3009         spin_lock_irqsave(&info->lock,flags);
3010         if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
3011                 info->ie1_value &= ~UDRN;
3012                 info->ie1_value |= IDLE;
3013                 write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
3014                 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
3015
3016                 write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
3017                 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3018
3019                 write_reg(info, CMD, TXABORT);
3020         }
3021         spin_unlock_irqrestore(&info->lock,flags);
3022         return 0;
3023 }
3024
3025 static int rx_enable(SLMP_INFO * info, int enable)
3026 {
3027         unsigned long flags;
3028
3029         if (debug_level >= DEBUG_LEVEL_INFO)
3030                 printk("%s(%d):%s rx_enable(%d)\n",
3031                         __FILE__,__LINE__,info->device_name,enable);
3032
3033         spin_lock_irqsave(&info->lock,flags);
3034         if ( enable ) {
3035                 if ( !info->rx_enabled )
3036                         rx_start(info);
3037         } else {
3038                 if ( info->rx_enabled )
3039                         rx_stop(info);
3040         }
3041         spin_unlock_irqrestore(&info->lock,flags);
3042         return 0;
3043 }
3044
3045 /* wait for specified event to occur
3046  */
3047 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3048 {
3049         unsigned long flags;
3050         int s;
3051         int rc=0;
3052         struct mgsl_icount cprev, cnow;
3053         int events;
3054         int mask;
3055         struct  _input_signal_events oldsigs, newsigs;
3056         DECLARE_WAITQUEUE(wait, current);
3057
3058         COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3059         if (rc) {
3060                 return  -EFAULT;
3061         }
3062
3063         if (debug_level >= DEBUG_LEVEL_INFO)
3064                 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3065                         __FILE__,__LINE__,info->device_name,mask);
3066
3067         spin_lock_irqsave(&info->lock,flags);
3068
3069         /* return immediately if state matches requested events */
3070         get_signals(info);
3071         s = info->serial_signals;
3072
3073         events = mask &
3074                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3075                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3076                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3077                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3078         if (events) {
3079                 spin_unlock_irqrestore(&info->lock,flags);
3080                 goto exit;
3081         }
3082
3083         /* save current irq counts */
3084         cprev = info->icount;
3085         oldsigs = info->input_signal_events;
3086
3087         /* enable hunt and idle irqs if needed */
3088         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3089                 unsigned char oldval = info->ie1_value;
3090                 unsigned char newval = oldval +
3091                          (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3092                          (mask & MgslEvent_IdleReceived ? IDLD:0);
3093                 if ( oldval != newval ) {
3094                         info->ie1_value = newval;
3095                         write_reg(info, IE1, info->ie1_value);
3096                 }
3097         }
3098
3099         set_current_state(TASK_INTERRUPTIBLE);
3100         add_wait_queue(&info->event_wait_q, &wait);
3101
3102         spin_unlock_irqrestore(&info->lock,flags);
3103
3104         for(;;) {
3105                 schedule();
3106                 if (signal_pending(current)) {
3107                         rc = -ERESTARTSYS;
3108                         break;
3109                 }
3110
3111                 /* get current irq counts */
3112                 spin_lock_irqsave(&info->lock,flags);
3113                 cnow = info->icount;
3114                 newsigs = info->input_signal_events;
3115                 set_current_state(TASK_INTERRUPTIBLE);
3116                 spin_unlock_irqrestore(&info->lock,flags);
3117
3118                 /* if no change, wait aborted for some reason */
3119                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
3120                     newsigs.dsr_down == oldsigs.dsr_down &&
3121                     newsigs.dcd_up   == oldsigs.dcd_up   &&
3122                     newsigs.dcd_down == oldsigs.dcd_down &&
3123                     newsigs.cts_up   == oldsigs.cts_up   &&
3124                     newsigs.cts_down == oldsigs.cts_down &&
3125                     newsigs.ri_up    == oldsigs.ri_up    &&
3126                     newsigs.ri_down  == oldsigs.ri_down  &&
3127                     cnow.exithunt    == cprev.exithunt   &&
3128                     cnow.rxidle      == cprev.rxidle) {
3129                         rc = -EIO;
3130                         break;
3131                 }
3132
3133                 events = mask &
3134                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
3135                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3136                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
3137                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3138                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
3139                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3140                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
3141                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
3142                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
3143                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
3144                 if (events)
3145                         break;
3146
3147                 cprev = cnow;
3148                 oldsigs = newsigs;
3149         }
3150
3151         remove_wait_queue(&info->event_wait_q, &wait);
3152         set_current_state(TASK_RUNNING);
3153
3154
3155         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3156                 spin_lock_irqsave(&info->lock,flags);
3157                 if (!waitqueue_active(&info->event_wait_q)) {
3158                         /* disable enable exit hunt mode/idle rcvd IRQs */
3159                         info->ie1_value &= ~(FLGD|IDLD);
3160                         write_reg(info, IE1, info->ie1_value);
3161                 }
3162                 spin_unlock_irqrestore(&info->lock,flags);
3163         }
3164 exit:
3165         if ( rc == 0 )
3166                 PUT_USER(rc, events, mask_ptr);
3167
3168         return rc;
3169 }
3170
3171 static int modem_input_wait(SLMP_INFO *info,int arg)
3172 {
3173         unsigned long flags;
3174         int rc;
3175         struct mgsl_icount cprev, cnow;
3176         DECLARE_WAITQUEUE(wait, current);
3177
3178         /* save current irq counts */
3179         spin_lock_irqsave(&info->lock,flags);
3180         cprev = info->icount;
3181         add_wait_queue(&info->status_event_wait_q, &wait);
3182         set_current_state(TASK_INTERRUPTIBLE);
3183         spin_unlock_irqrestore(&info->lock,flags);
3184
3185         for(;;) {
3186                 schedule();
3187                 if (signal_pending(current)) {
3188                         rc = -ERESTARTSYS;
3189                         break;
3190                 }
3191
3192                 /* get new irq counts */
3193                 spin_lock_irqsave(&info->lock,flags);
3194                 cnow = info->icount;
3195                 set_current_state(TASK_INTERRUPTIBLE);
3196                 spin_unlock_irqrestore(&info->lock,flags);
3197
3198                 /* if no change, wait aborted for some reason */
3199                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3200                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3201                         rc = -EIO;
3202                         break;
3203                 }
3204
3205                 /* check for change in caller specified modem input */
3206                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3207                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3208                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3209                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3210                         rc = 0;
3211                         break;
3212                 }
3213
3214                 cprev = cnow;
3215         }
3216         remove_wait_queue(&info->status_event_wait_q, &wait);
3217         set_current_state(TASK_RUNNING);
3218         return rc;
3219 }
3220
3221 /* return the state of the serial control and status signals
3222  */
3223 static int tiocmget(struct tty_struct *tty, struct file *file)
3224 {
3225         SLMP_INFO *info = tty->driver_data;
3226         unsigned int result;
3227         unsigned long flags;
3228
3229         spin_lock_irqsave(&info->lock,flags);
3230         get_signals(info);
3231         spin_unlock_irqrestore(&info->lock,flags);
3232
3233         result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3234                 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3235                 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3236                 ((info->serial_signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3237                 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3238                 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3239
3240         if (debug_level >= DEBUG_LEVEL_INFO)
3241                 printk("%s(%d):%s tiocmget() value=%08X\n",
3242                          __FILE__,__LINE__, info->device_name, result );
3243         return result;
3244 }
3245
3246 /* set modem control signals (DTR/RTS)
3247  */
3248 static int tiocmset(struct tty_struct *tty, struct file *file,
3249                     unsigned int set, unsigned int clear)
3250 {
3251         SLMP_INFO *info = tty->driver_data;
3252         unsigned long flags;
3253
3254         if (debug_level >= DEBUG_LEVEL_INFO)
3255                 printk("%s(%d):%s tiocmset(%x,%x)\n",
3256                         __FILE__,__LINE__,info->device_name, set, clear);
3257
3258         if (set & TIOCM_RTS)
3259                 info->serial_signals |= SerialSignal_RTS;
3260         if (set & TIOCM_DTR)
3261                 info->serial_signals |= SerialSignal_DTR;
3262         if (clear & TIOCM_RTS)
3263                 info->serial_signals &= ~SerialSignal_RTS;
3264         if (clear & TIOCM_DTR)
3265                 info->serial_signals &= ~SerialSignal_DTR;
3266
3267         spin_lock_irqsave(&info->lock,flags);
3268         set_signals(info);
3269         spin_unlock_irqrestore(&info->lock,flags);
3270
3271         return 0;
3272 }
3273
3274 static int carrier_raised(struct tty_port *port)
3275 {
3276         SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3277         unsigned long flags;
3278
3279         spin_lock_irqsave(&info->lock,flags);
3280         get_signals(info);
3281         spin_unlock_irqrestore(&info->lock,flags);
3282
3283         return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3284 }
3285
3286 static void raise_dtr_rts(struct tty_port *port)
3287 {
3288         SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3289         unsigned long flags;
3290
3291         spin_lock_irqsave(&info->lock,flags);
3292         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3293         set_signals(info);
3294         spin_unlock_irqrestore(&info->lock,flags);
3295 }
3296
3297 /* Block the current process until the specified port is ready to open.
3298  */
3299 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3300                            SLMP_INFO *info)
3301 {
3302         DECLARE_WAITQUEUE(wait, current);
3303         int             retval;
3304         bool            do_clocal = false;
3305         bool            extra_count = false;
3306         unsigned long   flags;
3307         int             cd;
3308         struct tty_port *port = &info->port;
3309
3310         if (debug_level >= DEBUG_LEVEL_INFO)
3311                 printk("%s(%d):%s block_til_ready()\n",
3312                          __FILE__,__LINE__, tty->driver->name );
3313
3314         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3315                 /* nonblock mode is set or port is not enabled */
3316                 /* just verify that callout device is not active */
3317                 port->flags |= ASYNC_NORMAL_ACTIVE;
3318                 return 0;
3319         }
3320
3321         if (tty->termios->c_cflag & CLOCAL)
3322                 do_clocal = true;
3323
3324         /* Wait for carrier detect and the line to become
3325          * free (i.e., not in use by the callout).  While we are in
3326          * this loop, port->count is dropped by one, so that
3327          * close() knows when to free things.  We restore it upon
3328          * exit, either normal or abnormal.
3329          */
3330
3331         retval = 0;
3332         add_wait_queue(&port->open_wait, &wait);
3333
3334         if (debug_level >= DEBUG_LEVEL_INFO)
3335                 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3336                          __FILE__,__LINE__, tty->driver->name, port->count );
3337
3338         spin_lock_irqsave(&info->lock, flags);
3339         if (!tty_hung_up_p(filp)) {
3340                 extra_count = true;
3341                 port->count--;
3342         }
3343         spin_unlock_irqrestore(&info->lock, flags);
3344         port->blocked_open++;
3345
3346         while (1) {
3347                 if (tty->termios->c_cflag & CBAUD)
3348                         tty_port_raise_dtr_rts(port);
3349
3350                 set_current_state(TASK_INTERRUPTIBLE);
3351
3352                 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3353                         retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3354                                         -EAGAIN : -ERESTARTSYS;
3355                         break;
3356                 }
3357
3358                 cd = tty_port_carrier_raised(port);
3359
3360                 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd))
3361                         break;
3362
3363                 if (signal_pending(current)) {
3364                         retval = -ERESTARTSYS;
3365                         break;
3366                 }
3367
3368                 if (debug_level >= DEBUG_LEVEL_INFO)
3369                         printk("%s(%d):%s block_til_ready() count=%d\n",
3370                                  __FILE__,__LINE__, tty->driver->name, port->count );
3371
3372                 schedule();
3373         }
3374
3375         set_current_state(TASK_RUNNING);
3376         remove_wait_queue(&port->open_wait, &wait);
3377
3378         if (extra_count)
3379                 port->count++;
3380         port->blocked_open--;
3381
3382         if (debug_level >= DEBUG_LEVEL_INFO)
3383                 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3384                          __FILE__,__LINE__, tty->driver->name, port->count );
3385
3386         if (!retval)
3387                 port->flags |= ASYNC_NORMAL_ACTIVE;
3388
3389         return retval;
3390 }
3391
3392 static int alloc_dma_bufs(SLMP_INFO *info)
3393 {
3394         unsigned short BuffersPerFrame;
3395         unsigned short BufferCount;
3396
3397         // Force allocation to start at 64K boundary for each port.
3398         // This is necessary because *all* buffer descriptors for a port
3399         // *must* be in the same 64K block. All descriptors on a port
3400         // share a common 'base' address (upper 8 bits of 24 bits) programmed
3401         // into the CBP register.
3402         info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3403
3404         /* Calculate the number of DMA buffers necessary to hold the */
3405         /* largest allowable frame size. Note: If the max frame size is */
3406         /* not an even multiple of the DMA buffer size then we need to */
3407         /* round the buffer count per frame up one. */
3408
3409         BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3410         if ( info->max_frame_size % SCABUFSIZE )
3411                 BuffersPerFrame++;
3412
3413         /* calculate total number of data buffers (SCABUFSIZE) possible
3414          * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3415          * for the descriptor list (BUFFERLISTSIZE).
3416          */
3417         BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3418
3419         /* limit number of buffers to maximum amount of descriptors */
3420         if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3421                 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3422
3423         /* use enough buffers to transmit one max size frame */
3424         info->tx_buf_count = BuffersPerFrame + 1;
3425
3426         /* never use more than half the available buffers for transmit */
3427         if (info->tx_buf_count > (BufferCount/2))
3428                 info->tx_buf_count = BufferCount/2;
3429
3430         if (info->tx_buf_count > SCAMAXDESC)
3431                 info->tx_buf_count = SCAMAXDESC;
3432
3433         /* use remaining buffers for receive */
3434         info->rx_buf_count = BufferCount - info->tx_buf_count;
3435
3436         if (info->rx_buf_count > SCAMAXDESC)
3437                 info->rx_buf_count = SCAMAXDESC;
3438
3439         if ( debug_level >= DEBUG_LEVEL_INFO )
3440                 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3441                         __FILE__,__LINE__, info->device_name,
3442                         info->tx_buf_count,info->rx_buf_count);
3443
3444         if ( alloc_buf_list( info ) < 0 ||
3445                 alloc_frame_bufs(info,
3446                                         info->rx_buf_list,
3447                                         info->rx_buf_list_ex,
3448                                         info->rx_buf_count) < 0 ||
3449                 alloc_frame_bufs(info,
3450                                         info->tx_buf_list,
3451                                         info->tx_buf_list_ex,
3452                                         info->tx_buf_count) < 0 ||
3453                 alloc_tmp_rx_buf(info) < 0 ) {
3454                 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3455                         __FILE__,__LINE__, info->device_name);
3456                 return -ENOMEM;
3457         }
3458
3459         rx_reset_buffers( info );
3460
3461         return 0;
3462 }
3463
3464 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3465  */
3466 static int alloc_buf_list(SLMP_INFO *info)
3467 {
3468         unsigned int i;
3469
3470         /* build list in adapter shared memory */
3471         info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3472         info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3473         info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3474
3475         memset(info->buffer_list, 0, BUFFERLISTSIZE);
3476
3477         /* Save virtual address pointers to the receive and */
3478         /* transmit buffer lists. (Receive 1st). These pointers will */
3479         /* be used by the processor to access the lists. */
3480         info->rx_buf_list = (SCADESC *)info->buffer_list;
3481
3482         info->tx_buf_list = (SCADESC *)info->buffer_list;
3483         info->tx_buf_list += info->rx_buf_count;
3484
3485         /* Build links for circular buffer entry lists (tx and rx)
3486          *
3487          * Note: links are physical addresses read by the SCA device
3488          * to determine the next buffer entry to use.
3489          */
3490
3491         for ( i = 0; i < info->rx_buf_count; i++ ) {
3492                 /* calculate and store physical address of this buffer entry */
3493                 info->rx_buf_list_ex[i].phys_entry =
3494                         info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3495
3496                 /* calculate and store physical address of */
3497                 /* next entry in cirular list of entries */
3498                 info->rx_buf_list[i].next = info->buffer_list_phys;
3499                 if ( i < info->rx_buf_count - 1 )
3500                         info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3501
3502                 info->rx_buf_list[i].length = SCABUFSIZE;
3503         }
3504
3505         for ( i = 0; i < info->tx_buf_count; i++ ) {
3506                 /* calculate and store physical address of this buffer entry */
3507                 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3508                         ((info->rx_buf_count + i) * sizeof(SCADESC));
3509
3510                 /* calculate and store physical address of */
3511                 /* next entry in cirular list of entries */
3512
3513                 info->tx_buf_list[i].next = info->buffer_list_phys +
3514                         info->rx_buf_count * sizeof(SCADESC);
3515
3516                 if ( i < info->tx_buf_count - 1 )
3517                         info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3518         }
3519
3520         return 0;
3521 }
3522
3523 /* Allocate the frame DMA buffers used by the specified buffer list.
3524  */
3525 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3526 {
3527         int i;
3528         unsigned long phys_addr;
3529
3530         for ( i = 0; i < count; i++ ) {
3531                 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3532                 phys_addr = info->port_array[0]->last_mem_alloc;
3533                 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3534
3535                 buf_list[i].buf_ptr  = (unsigned short)phys_addr;
3536                 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3537         }
3538
3539         return 0;
3540 }
3541
3542 static void free_dma_bufs(SLMP_INFO *info)
3543 {
3544         info->buffer_list = NULL;
3545         info->rx_buf_list = NULL;
3546         info->tx_buf_list = NULL;
3547 }
3548
3549 /* allocate buffer large enough to hold max_frame_size.
3550  * This buffer is used to pass an assembled frame to the line discipline.
3551  */
3552 static int alloc_tmp_rx_buf(SLMP_INFO *info)
3553 {
3554         info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3555         if (info->tmp_rx_buf == NULL)
3556                 return -ENOMEM;
3557         return 0;
3558 }
3559
3560 static void free_tmp_rx_buf(SLMP_INFO *info)
3561 {
3562         kfree(info->tmp_rx_buf);
3563         info->tmp_rx_buf = NULL;
3564 }
3565
3566 static int claim_resources(SLMP_INFO *info)
3567 {
3568         if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3569                 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3570                         __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3571                 info->init_error = DiagStatus_AddressConflict;
3572                 goto errout;
3573         }
3574         else
3575                 info->shared_mem_requested = true;
3576
3577         if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3578                 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3579                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3580                 info->init_error = DiagStatus_AddressConflict;
3581                 goto errout;
3582         }
3583         else
3584                 info->lcr_mem_requested = true;
3585
3586         if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3587                 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3588                         __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3589                 info->init_error = DiagStatus_AddressConflict;
3590                 goto errout;
3591         }
3592         else
3593                 info->sca_base_requested = true;
3594
3595         if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3596                 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3597                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3598                 info->init_error = DiagStatus_AddressConflict;
3599                 goto errout;
3600         }
3601         else
3602                 info->sca_statctrl_requested = true;
3603
3604         info->memory_base = ioremap_nocache(info->phys_memory_base,
3605                                                                 SCA_MEM_SIZE);
3606         if (!info->memory_base) {
3607                 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3608                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3609                 info->init_error = DiagStatus_CantAssignPciResources;
3610                 goto errout;
3611         }
3612
3613         info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE);
3614         if (!info->lcr_base) {
3615                 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3616                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3617                 info->init_error = DiagStatus_CantAssignPciResources;
3618                 goto errout;
3619         }
3620         info->lcr_base += info->lcr_offset;
3621
3622         info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE);
3623         if (!info->sca_base) {
3624                 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3625                         __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3626                 info->init_error = DiagStatus_CantAssignPciResources;
3627                 goto errout;
3628         }
3629         info->sca_base += info->sca_offset;
3630
3631         info->statctrl_base = ioremap_nocache(info->phys_statctrl_base,
3632                                                                 PAGE_SIZE);
3633         if (!info->statctrl_base) {
3634                 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3635                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3636                 info->init_error = DiagStatus_CantAssignPciResources;
3637                 goto errout;
3638         }
3639         info->statctrl_base += info->statctrl_offset;
3640
3641         if ( !memory_test(info) ) {
3642                 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3643                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3644                 info->init_error = DiagStatus_MemoryError;
3645                 goto errout;
3646         }
3647
3648         return 0;
3649
3650 errout:
3651         release_resources( info );
3652         return -ENODEV;
3653 }
3654
3655 static void release_resources(SLMP_INFO *info)
3656 {
3657         if ( debug_level >= DEBUG_LEVEL_INFO )
3658                 printk( "%s(%d):%s release_resources() entry\n",
3659                         __FILE__,__LINE__,info->device_name );
3660
3661         if ( info->irq_requested ) {
3662                 free_irq(info->irq_level, info);
3663                 info->irq_requested = false;
3664         }
3665
3666         if ( info->shared_mem_requested ) {
3667                 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3668                 info->shared_mem_requested = false;
3669         }
3670         if ( info->lcr_mem_requested ) {
3671                 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3672                 info->lcr_mem_requested = false;
3673         }
3674         if ( info->sca_base_requested ) {
3675                 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3676                 info->sca_base_requested = false;
3677         }
3678         if ( info->sca_statctrl_requested ) {
3679                 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3680                 info->sca_statctrl_requested = false;
3681         }
3682
3683         if (info->memory_base){
3684                 iounmap(info->memory_base);
3685                 info->memory_base = NULL;
3686         }
3687
3688         if (info->sca_base) {
3689                 iounmap(info->sca_base - info->sca_offset);
3690                 info->sca_base=NULL;
3691         }
3692
3693         if (info->statctrl_base) {
3694                 iounmap(info->statctrl_base - info->statctrl_offset);
3695                 info->statctrl_base=NULL;
3696         }
3697
3698         if (info->lcr_base){
3699                 iounmap(info->lcr_base - info->lcr_offset);
3700                 info->lcr_base = NULL;
3701         }
3702
3703         if ( debug_level >= DEBUG_LEVEL_INFO )
3704                 printk( "%s(%d):%s release_resources() exit\n",
3705                         __FILE__,__LINE__,info->device_name );
3706 }
3707
3708 /* Add the specified device instance data structure to the
3709  * global linked list of devices and increment the device count.
3710  */
3711 static void add_device(SLMP_INFO *info)
3712 {
3713         info->next_device = NULL;
3714         info->line = synclinkmp_device_count;
3715         sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3716
3717         if (info->line < MAX_DEVICES) {
3718                 if (maxframe[info->line])
3719                         info->max_frame_size = maxframe[info->line];
3720         }
3721
3722         synclinkmp_device_count++;
3723
3724         if ( !synclinkmp_device_list )
3725                 synclinkmp_device_list = info;
3726         else {
3727                 SLMP_INFO *current_dev = synclinkmp_device_list;
3728                 while( current_dev->next_device )
3729                         current_dev = current_dev->next_device;
3730                 current_dev->next_device = info;
3731         }
3732
3733         if ( info->max_frame_size < 4096 )
3734                 info->max_frame_size = 4096;
3735         else if ( info->max_frame_size > 65535 )
3736                 info->max_frame_size = 65535;
3737
3738         printk( "SyncLink MultiPort %s: "
3739                 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3740                 info->device_name,
3741                 info->phys_sca_base,
3742                 info->phys_memory_base,
3743                 info->phys_statctrl_base,
3744                 info->phys_lcr_base,
3745                 info->irq_level,
3746                 info->max_frame_size );
3747
3748 #if SYNCLINK_GENERIC_HDLC
3749         hdlcdev_init(info);
3750 #endif
3751 }
3752
3753 static const struct tty_port_operations port_ops = {
3754         .carrier_raised = carrier_raised,
3755         .raise_dtr_rts = raise_dtr_rts,
3756 };
3757
3758 /* Allocate and initialize a device instance structure
3759  *
3760  * Return Value:        pointer to SLMP_INFO if success, otherwise NULL
3761  */
3762 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3763 {
3764         SLMP_INFO *info;
3765
3766         info = kzalloc(sizeof(SLMP_INFO),
3767                  GFP_KERNEL);
3768
3769         if (!info) {
3770                 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3771                         __FILE__,__LINE__, adapter_num, port_num);
3772         } else {
3773                 tty_port_init(&info->port);
3774                 info->port.ops = &port_ops;
3775                 info->magic = MGSL_MAGIC;
3776                 INIT_WORK(&info->task, bh_handler);
3777                 info->max_frame_size = 4096;
3778                 info->port.close_delay = 5*HZ/10;
3779                 info->port.closing_wait = 30*HZ;
3780                 init_waitqueue_head(&info->status_event_wait_q);
3781                 init_waitqueue_head(&info->event_wait_q);
3782                 spin_lock_init(&info->netlock);
3783                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3784                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3785                 info->adapter_num = adapter_num;
3786                 info->port_num = port_num;
3787
3788                 /* Copy configuration info to device instance data */
3789                 info->irq_level = pdev->irq;
3790                 info->phys_lcr_base = pci_resource_start(pdev,0);
3791                 info->phys_sca_base = pci_resource_start(pdev,2);
3792                 info->phys_memory_base = pci_resource_start(pdev,3);
3793                 info->phys_statctrl_base = pci_resource_start(pdev,4);
3794
3795                 /* Because veremap only works on page boundaries we must map
3796                  * a larger area than is actually implemented for the LCR
3797                  * memory range. We map a full page starting at the page boundary.
3798                  */
3799                 info->lcr_offset    = info->phys_lcr_base & (PAGE_SIZE-1);
3800                 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3801
3802                 info->sca_offset    = info->phys_sca_base & (PAGE_SIZE-1);
3803                 info->phys_sca_base &= ~(PAGE_SIZE-1);
3804
3805                 info->statctrl_offset    = info->phys_statctrl_base & (PAGE_SIZE-1);
3806                 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3807
3808                 info->bus_type = MGSL_BUS_TYPE_PCI;
3809                 info->irq_flags = IRQF_SHARED;
3810
3811                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3812                 setup_timer(&info->status_timer, status_timeout,
3813                                 (unsigned long)info);
3814
3815                 /* Store the PCI9050 misc control register value because a flaw
3816                  * in the PCI9050 prevents LCR registers from being read if
3817                  * BIOS assigns an LCR base address with bit 7 set.
3818                  *
3819                  * Only the misc control register is accessed for which only
3820                  * write access is needed, so set an initial value and change
3821                  * bits to the device instance data as we write the value
3822                  * to the actual misc control register.
3823                  */
3824                 info->misc_ctrl_value = 0x087e4546;
3825
3826                 /* initial port state is unknown - if startup errors
3827                  * occur, init_error will be set to indicate the
3828                  * problem. Once the port is fully initialized,
3829                  * this value will be set to 0 to indicate the
3830                  * port is available.
3831                  */
3832                 info->init_error = -1;
3833         }
3834
3835         return info;
3836 }
3837
3838 static void device_init(int adapter_num, struct pci_dev *pdev)
3839 {
3840         SLMP_INFO *port_array[SCA_MAX_PORTS];
3841         int port;
3842
3843         /* allocate device instances for up to SCA_MAX_PORTS devices */
3844         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3845                 port_array[port] = alloc_dev(adapter_num,port,pdev);
3846                 if( port_array[port] == NULL ) {
3847                         for ( --port; port >= 0; --port )
3848                                 kfree(port_array[port]);
3849                         return;
3850                 }
3851         }
3852
3853         /* give copy of port_array to all ports and add to device list  */
3854         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3855                 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3856                 add_device( port_array[port] );
3857                 spin_lock_init(&port_array[port]->lock);
3858         }
3859
3860         /* Allocate and claim adapter resources */
3861         if ( !claim_resources(port_array[0]) ) {
3862
3863                 alloc_dma_bufs(port_array[0]);
3864
3865                 /* copy resource information from first port to others */
3866                 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3867                         port_array[port]->lock  = port_array[0]->lock;
3868                         port_array[port]->irq_level     = port_array[0]->irq_level;
3869                         port_array[port]->memory_base   = port_array[0]->memory_base;
3870                         port_array[port]->sca_base      = port_array[0]->sca_base;
3871                         port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3872                         port_array[port]->lcr_base      = port_array[0]->lcr_base;
3873                         alloc_dma_bufs(port_array[port]);
3874                 }
3875
3876                 if ( request_irq(port_array[0]->irq_level,
3877                                         synclinkmp_interrupt,
3878                                         port_array[0]->irq_flags,
3879                                         port_array[0]->device_name,
3880                                         port_array[0]) < 0 ) {
3881                         printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3882                                 __FILE__,__LINE__,
3883                                 port_array[0]->device_name,
3884                                 port_array[0]->irq_level );
3885                 }
3886                 else {
3887                         port_array[0]->irq_requested = true;
3888                         adapter_test(port_array[0]);
3889                 }
3890         }
3891 }
3892
3893 static const struct tty_operations ops = {
3894         .open = open,
3895         .close = close,
3896         .write = write,
3897         .put_char = put_char,
3898         .flush_chars = flush_chars,
3899         .write_room = write_room,
3900         .chars_in_buffer = chars_in_buffer,
3901         .flush_buffer = flush_buffer,
3902         .ioctl = ioctl,
3903         .throttle = throttle,
3904         .unthrottle = unthrottle,
3905         .send_xchar = send_xchar,
3906         .break_ctl = set_break,
3907         .wait_until_sent = wait_until_sent,
3908         .read_proc = read_proc,
3909         .set_termios = set_termios,
3910         .stop = tx_hold,
3911         .start = tx_release,
3912         .hangup = hangup,
3913         .tiocmget = tiocmget,
3914         .tiocmset = tiocmset,
3915 };
3916
3917
3918 static void synclinkmp_cleanup(void)
3919 {
3920         int rc;
3921         SLMP_INFO *info;
3922         SLMP_INFO *tmp;
3923
3924         printk("Unloading %s %s\n", driver_name, driver_version);
3925
3926         if (serial_driver) {
3927                 if ((rc = tty_unregister_driver(serial_driver)))
3928                         printk("%s(%d) failed to unregister tty driver err=%d\n",
3929                                __FILE__,__LINE__,rc);
3930                 put_tty_driver(serial_driver);
3931         }
3932
3933         /* reset devices */
3934         info = synclinkmp_device_list;
3935         while(info) {
3936                 reset_port(info);
3937                 info = info->next_device;
3938         }
3939
3940         /* release devices */
3941         info = synclinkmp_device_list;
3942         while(info) {
3943 #if SYNCLINK_GENERIC_HDLC
3944                 hdlcdev_exit(info);
3945 #endif
3946                 free_dma_bufs(info);
3947                 free_tmp_rx_buf(info);
3948                 if ( info->port_num == 0 ) {
3949                         if (info->sca_base)
3950                                 write_reg(info, LPR, 1); /* set low power mode */
3951                         release_resources(info);
3952                 }
3953                 tmp = info;
3954                 info = info->next_device;
3955                 kfree(tmp);
3956         }
3957
3958         pci_unregister_driver(&synclinkmp_pci_driver);
3959 }
3960
3961 /* Driver initialization entry point.
3962  */
3963
3964 static int __init synclinkmp_init(void)
3965 {
3966         int rc;
3967
3968         if (break_on_load) {
3969                 synclinkmp_get_text_ptr();
3970                 BREAKPOINT();
3971         }
3972
3973         printk("%s %s\n", driver_name, driver_version);
3974
3975         if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
3976                 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
3977                 return rc;
3978         }
3979
3980         serial_driver = alloc_tty_driver(128);
3981         if (!serial_driver) {
3982                 rc = -ENOMEM;
3983                 goto error;
3984         }
3985
3986         /* Initialize the tty_driver structure */
3987
3988         serial_driver->owner = THIS_MODULE;
3989         serial_driver->driver_name = "synclinkmp";
3990         serial_driver->name = "ttySLM";
3991         serial_driver->major = ttymajor;
3992         serial_driver->minor_start = 64;
3993         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3994         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3995         serial_driver->init_termios = tty_std_termios;
3996         serial_driver->init_termios.c_cflag =
3997                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3998         serial_driver->init_termios.c_ispeed = 9600;
3999         serial_driver->init_termios.c_ospeed = 9600;
4000         serial_driver->flags = TTY_DRIVER_REAL_RAW;
4001         tty_set_operations(serial_driver, &ops);
4002         if ((rc = tty_register_driver(serial_driver)) < 0) {
4003                 printk("%s(%d):Couldn't register serial driver\n",
4004                         __FILE__,__LINE__);
4005                 put_tty_driver(serial_driver);
4006                 serial_driver = NULL;
4007                 goto error;
4008         }
4009
4010         printk("%s %s, tty major#%d\n",
4011                 driver_name, driver_version,
4012                 serial_driver->major);
4013
4014         return 0;
4015
4016 error:
4017         synclinkmp_cleanup();
4018         return rc;
4019 }
4020
4021 static void __exit synclinkmp_exit(void)
4022 {
4023         synclinkmp_cleanup();
4024 }
4025
4026 module_init(synclinkmp_init);
4027 module_exit(synclinkmp_exit);
4028
4029 /* Set the port for internal loopback mode.
4030  * The TxCLK and RxCLK signals are generated from the BRG and
4031  * the TxD is looped back to the RxD internally.
4032  */
4033 static void enable_loopback(SLMP_INFO *info, int enable)
4034 {
4035         if (enable) {
4036                 /* MD2 (Mode Register 2)
4037                  * 01..00  CNCT<1..0> Channel Connection 11=Local Loopback
4038                  */
4039                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4040
4041                 /* degate external TxC clock source */
4042                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4043                 write_control_reg(info);
4044
4045                 /* RXS/TXS (Rx/Tx clock source)
4046                  * 07      Reserved, must be 0
4047                  * 06..04  Clock Source, 100=BRG
4048                  * 03..00  Clock Divisor, 0000=1
4049                  */
4050                 write_reg(info, RXS, 0x40);
4051                 write_reg(info, TXS, 0x40);
4052
4053         } else {
4054                 /* MD2 (Mode Register 2)
4055                  * 01..00  CNCT<1..0> Channel connection, 0=normal
4056                  */
4057                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4058
4059                 /* RXS/TXS (Rx/Tx clock source)
4060                  * 07      Reserved, must be 0
4061                  * 06..04  Clock Source, 000=RxC/TxC Pin
4062                  * 03..00  Clock Divisor, 0000=1
4063                  */
4064                 write_reg(info, RXS, 0x00);
4065                 write_reg(info, TXS, 0x00);
4066         }
4067
4068         /* set LinkSpeed if available, otherwise default to 2Mbps */
4069         if (info->params.clock_speed)
4070                 set_rate(info, info->params.clock_speed);
4071         else
4072                 set_rate(info, 3686400);
4073 }
4074
4075 /* Set the baud rate register to the desired speed
4076  *
4077  *      data_rate       data rate of clock in bits per second
4078  *                      A data rate of 0 disables the AUX clock.
4079  */
4080 static void set_rate( SLMP_INFO *info, u32 data_rate )
4081 {
4082         u32 TMCValue;
4083         unsigned char BRValue;
4084         u32 Divisor=0;
4085
4086         /* fBRG = fCLK/(TMC * 2^BR)
4087          */
4088         if (data_rate != 0) {
4089                 Divisor = 14745600/data_rate;
4090                 if (!Divisor)
4091                         Divisor = 1;
4092
4093                 TMCValue = Divisor;
4094
4095                 BRValue = 0;
4096                 if (TMCValue != 1 && TMCValue != 2) {
4097                         /* BRValue of 0 provides 50/50 duty cycle *only* when
4098                          * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4099                          * 50/50 duty cycle.
4100                          */
4101                         BRValue = 1;
4102                         TMCValue >>= 1;
4103                 }
4104
4105                 /* while TMCValue is too big for TMC register, divide
4106                  * by 2 and increment BR exponent.
4107                  */
4108                 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4109                         TMCValue >>= 1;
4110
4111                 write_reg(info, TXS,
4112                         (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4113                 write_reg(info, RXS,
4114                         (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4115                 write_reg(info, TMC, (unsigned char)TMCValue);
4116         }
4117         else {
4118                 write_reg(info, TXS,0);
4119                 write_reg(info, RXS,0);
4120                 write_reg(info, TMC, 0);
4121         }
4122 }
4123
4124 /* Disable receiver
4125  */
4126 static void rx_stop(SLMP_INFO *info)
4127 {
4128         if (debug_level >= DEBUG_LEVEL_ISR)
4129                 printk("%s(%d):%s rx_stop()\n",
4130                          __FILE__,__LINE__, info->device_name );
4131
4132         write_reg(info, CMD, RXRESET);
4133
4134         info->ie0_value &= ~RXRDYE;
4135         write_reg(info, IE0, info->ie0_value);  /* disable Rx data interrupts */
4136
4137         write_reg(info, RXDMA + DSR, 0);        /* disable Rx DMA */
4138         write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4139         write_reg(info, RXDMA + DIR, 0);        /* disable Rx DMA interrupts */
4140
4141         info->rx_enabled = false;
4142         info->rx_overflow = false;
4143 }
4144
4145 /* enable the receiver
4146  */
4147 static void rx_start(SLMP_INFO *info)
4148 {
4149         int i;
4150
4151         if (debug_level >= DEBUG_LEVEL_ISR)
4152                 printk("%s(%d):%s rx_start()\n",
4153                          __FILE__,__LINE__, info->device_name );
4154
4155         write_reg(info, CMD, RXRESET);
4156
4157         if ( info->params.mode == MGSL_MODE_HDLC ) {
4158                 /* HDLC, disabe IRQ on rxdata */
4159                 info->ie0_value &= ~RXRDYE;
4160                 write_reg(info, IE0, info->ie0_value);
4161
4162                 /* Reset all Rx DMA buffers and program rx dma */
4163                 write_reg(info, RXDMA + DSR, 0);                /* disable Rx DMA */
4164                 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4165
4166                 for (i = 0; i < info->rx_buf_count; i++) {
4167                         info->rx_buf_list[i].status = 0xff;
4168
4169                         // throttle to 4 shared memory writes at a time to prevent
4170                         // hogging local bus (keep latency time for DMA requests low).
4171                         if (!(i % 4))
4172                                 read_status_reg(info);
4173                 }
4174                 info->current_rx_buf = 0;
4175
4176                 /* set current/1st descriptor address */
4177                 write_reg16(info, RXDMA + CDA,
4178                         info->rx_buf_list_ex[0].phys_entry);
4179
4180                 /* set new last rx descriptor address */
4181                 write_reg16(info, RXDMA + EDA,
4182                         info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4183
4184                 /* set buffer length (shared by all rx dma data buffers) */
4185                 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4186
4187                 write_reg(info, RXDMA + DIR, 0x60);     /* enable Rx DMA interrupts (EOM/BOF) */
4188                 write_reg(info, RXDMA + DSR, 0xf2);     /* clear Rx DMA IRQs, enable Rx DMA */
4189         } else {
4190                 /* async, enable IRQ on rxdata */
4191                 info->ie0_value |= RXRDYE;
4192                 write_reg(info, IE0, info->ie0_value);
4193         }
4194
4195         write_reg(info, CMD, RXENABLE);
4196
4197         info->rx_overflow = false;
4198         info->rx_enabled = true;
4199 }
4200
4201 /* Enable the transmitter and send a transmit frame if
4202  * one is loaded in the DMA buffers.
4203  */
4204 static void tx_start(SLMP_INFO *info)
4205 {
4206         if (debug_level >= DEBUG_LEVEL_ISR)
4207                 printk("%s(%d):%s tx_start() tx_count=%d\n",
4208                          __FILE__,__LINE__, info->device_name,info->tx_count );
4209
4210         if (!info->tx_enabled ) {
4211                 write_reg(info, CMD, TXRESET);
4212                 write_reg(info, CMD, TXENABLE);
4213                 info->tx_enabled = true;
4214         }
4215
4216         if ( info->tx_count ) {
4217
4218                 /* If auto RTS enabled and RTS is inactive, then assert */
4219                 /* RTS and set a flag indicating that the driver should */
4220                 /* negate RTS when the transmission completes. */
4221
4222                 info->drop_rts_on_tx_done = false;
4223
4224                 if (info->params.mode != MGSL_MODE_ASYNC) {
4225
4226                         if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4227                                 get_signals( info );
4228                                 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4229                                         info->serial_signals |= SerialSignal_RTS;
4230                                         set_signals( info );
4231                                         info->drop_rts_on_tx_done = true;
4232                                 }
4233                         }
4234
4235                         write_reg16(info, TRC0,
4236                                 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4237
4238                         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4239                         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4240
4241                         /* set TX CDA (current descriptor address) */
4242                         write_reg16(info, TXDMA + CDA,
4243                                 info->tx_buf_list_ex[0].phys_entry);
4244
4245                         /* set TX EDA (last descriptor address) */
4246                         write_reg16(info, TXDMA + EDA,
4247                                 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4248
4249                         /* enable underrun IRQ */
4250                         info->ie1_value &= ~IDLE;
4251                         info->ie1_value |= UDRN;
4252                         write_reg(info, IE1, info->ie1_value);
4253                         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4254
4255                         write_reg(info, TXDMA + DIR, 0x40);             /* enable Tx DMA interrupts (EOM) */
4256                         write_reg(info, TXDMA + DSR, 0xf2);             /* clear Tx DMA IRQs, enable Tx DMA */
4257
4258                         mod_timer(&info->tx_timer, jiffies +
4259                                         msecs_to_jiffies(5000));
4260                 }
4261                 else {
4262                         tx_load_fifo(info);
4263                         /* async, enable IRQ on txdata */
4264                         info->ie0_value |= TXRDYE;
4265                         write_reg(info, IE0, info->ie0_value);
4266                 }
4267
4268                 info->tx_active = true;
4269         }
4270 }
4271
4272 /* stop the transmitter and DMA
4273  */
4274 static void tx_stop( SLMP_INFO *info )
4275 {
4276         if (debug_level >= DEBUG_LEVEL_ISR)
4277                 printk("%s(%d):%s tx_stop()\n",
4278                          __FILE__,__LINE__, info->device_name );
4279
4280         del_timer(&info->tx_timer);
4281
4282         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4283         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4284
4285         write_reg(info, CMD, TXRESET);
4286
4287         info->ie1_value &= ~(UDRN + IDLE);
4288         write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
4289         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
4290
4291         info->ie0_value &= ~TXRDYE;
4292         write_reg(info, IE0, info->ie0_value);  /* disable tx data interrupts */
4293
4294         info->tx_enabled = false;
4295         info->tx_active = false;
4296 }
4297
4298 /* Fill the transmit FIFO until the FIFO is full or
4299  * there is no more data to load.
4300  */
4301 static void tx_load_fifo(SLMP_INFO *info)
4302 {
4303         u8 TwoBytes[2];
4304
4305         /* do nothing is now tx data available and no XON/XOFF pending */
4306
4307         if ( !info->tx_count && !info->x_char )
4308                 return;
4309
4310         /* load the Transmit FIFO until FIFOs full or all data sent */
4311
4312         while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4313
4314                 /* there is more space in the transmit FIFO and */
4315                 /* there is more data in transmit buffer */
4316
4317                 if ( (info->tx_count > 1) && !info->x_char ) {
4318                         /* write 16-bits */
4319                         TwoBytes[0] = info->tx_buf[info->tx_get++];
4320                         if (info->tx_get >= info->max_frame_size)
4321                                 info->tx_get -= info->max_frame_size;
4322                         TwoBytes[1] = info->tx_buf[info->tx_get++];
4323                         if (info->tx_get >= info->max_frame_size)
4324                                 info->tx_get -= info->max_frame_size;
4325
4326                         write_reg16(info, TRB, *((u16 *)TwoBytes));
4327
4328                         info->tx_count -= 2;
4329                         info->icount.tx += 2;
4330                 } else {
4331                         /* only 1 byte left to transmit or 1 FIFO slot left */
4332
4333                         if (info->x_char) {
4334                                 /* transmit pending high priority char */
4335                                 write_reg(info, TRB, info->x_char);
4336                                 info->x_char = 0;
4337                         } else {
4338                                 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4339                                 if (info->tx_get >= info->max_frame_size)
4340                                         info->tx_get -= info->max_frame_size;
4341                                 info->tx_count--;
4342                         }
4343                         info->icount.tx++;
4344                 }
4345         }
4346 }
4347
4348 /* Reset a port to a known state
4349  */
4350 static void reset_port(SLMP_INFO *info)
4351 {
4352         if (info->sca_base) {
4353
4354                 tx_stop(info);
4355                 rx_stop(info);
4356
4357                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4358                 set_signals(info);
4359
4360                 /* disable all port interrupts */
4361                 info->ie0_value = 0;
4362                 info->ie1_value = 0;
4363                 info->ie2_value = 0;
4364                 write_reg(info, IE0, info->ie0_value);
4365                 write_reg(info, IE1, info->ie1_value);
4366                 write_reg(info, IE2, info->ie2_value);
4367
4368                 write_reg(info, CMD, CHRESET);
4369         }
4370 }
4371
4372 /* Reset all the ports to a known state.
4373  */
4374 static void reset_adapter(SLMP_INFO *info)
4375 {
4376         int i;
4377
4378         for ( i=0; i < SCA_MAX_PORTS; ++i) {
4379                 if (info->port_array[i])
4380                         reset_port(info->port_array[i]);
4381         }
4382 }
4383
4384 /* Program port for asynchronous communications.
4385  */
4386 static void async_mode(SLMP_INFO *info)
4387 {
4388
4389         unsigned char RegValue;
4390
4391         tx_stop(info);
4392         rx_stop(info);
4393
4394         /* MD0, Mode Register 0
4395          *
4396          * 07..05  PRCTL<2..0>, Protocol Mode, 000=async
4397          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4398          * 03      Reserved, must be 0
4399          * 02      CRCCC, CRC Calculation, 0=disabled
4400          * 01..00  STOP<1..0> Stop bits (00=1,10=2)
4401          *
4402          * 0000 0000
4403          */
4404         RegValue = 0x00;
4405         if (info->params.stop_bits != 1)
4406                 RegValue |= BIT1;
4407         write_reg(info, MD0, RegValue);
4408
4409         /* MD1, Mode Register 1
4410          *
4411          * 07..06  BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4412          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4413          * 03..02  RXCHR<1..0>, rx char size
4414          * 01..00  PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4415          *
4416          * 0100 0000
4417          */
4418         RegValue = 0x40;
4419         switch (info->params.data_bits) {
4420         case 7: RegValue |= BIT4 + BIT2; break;
4421         case 6: RegValue |= BIT5 + BIT3; break;
4422         case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4423         }
4424         if (info->params.parity != ASYNC_PARITY_NONE) {
4425                 RegValue |= BIT1;
4426                 if (info->params.parity == ASYNC_PARITY_ODD)
4427                         RegValue |= BIT0;
4428         }
4429         write_reg(info, MD1, RegValue);
4430
4431         /* MD2, Mode Register 2
4432          *
4433          * 07..02  Reserved, must be 0
4434          * 01..00  CNCT<1..0> Channel connection, 00=normal 11=local loopback
4435          *
4436          * 0000 0000
4437          */
4438         RegValue = 0x00;
4439         if (info->params.loopback)
4440                 RegValue |= (BIT1 + BIT0);
4441         write_reg(info, MD2, RegValue);
4442
4443         /* RXS, Receive clock source
4444          *
4445          * 07      Reserved, must be 0
4446          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4447          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4448          */
4449         RegValue=BIT6;
4450         write_reg(info, RXS, RegValue);
4451
4452         /* TXS, Transmit clock source
4453          *
4454          * 07      Reserved, must be 0
4455          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4456          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4457          */
4458         RegValue=BIT6;
4459         write_reg(info, TXS, RegValue);
4460
4461         /* Control Register
4462          *
4463          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4464          */
4465         info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4466         write_control_reg(info);
4467
4468         tx_set_idle(info);
4469
4470         /* RRC Receive Ready Control 0
4471          *
4472          * 07..05  Reserved, must be 0
4473          * 04..00  RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4474          */
4475         write_reg(info, RRC, 0x00);
4476
4477         /* TRC0 Transmit Ready Control 0
4478          *
4479          * 07..05  Reserved, must be 0
4480          * 04..00  TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4481          */
4482         write_reg(info, TRC0, 0x10);
4483
4484         /* TRC1 Transmit Ready Control 1
4485          *
4486          * 07..05  Reserved, must be 0
4487          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4488          */
4489         write_reg(info, TRC1, 0x1e);
4490
4491         /* CTL, MSCI control register
4492          *
4493          * 07..06  Reserved, set to 0
4494          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4495          * 04      IDLC, idle control, 0=mark 1=idle register
4496          * 03      BRK, break, 0=off 1 =on (async)
4497          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4498          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4499          * 00      RTS, RTS output control, 0=active 1=inactive
4500          *
4501          * 0001 0001
4502          */
4503         RegValue = 0x10;
4504         if (!(info->serial_signals & SerialSignal_RTS))
4505                 RegValue |= 0x01;
4506         write_reg(info, CTL, RegValue);
4507
4508         /* enable status interrupts */
4509         info->ie0_value |= TXINTE + RXINTE;
4510         write_reg(info, IE0, info->ie0_value);
4511
4512         /* enable break detect interrupt */
4513         info->ie1_value = BRKD;
4514         write_reg(info, IE1, info->ie1_value);
4515
4516         /* enable rx overrun interrupt */
4517         info->ie2_value = OVRN;
4518         write_reg(info, IE2, info->ie2_value);
4519
4520         set_rate( info, info->params.data_rate * 16 );
4521 }
4522
4523 /* Program the SCA for HDLC communications.
4524  */
4525 static void hdlc_mode(SLMP_INFO *info)
4526 {
4527         unsigned char RegValue;
4528         u32 DpllDivisor;
4529
4530         // Can't use DPLL because SCA outputs recovered clock on RxC when
4531         // DPLL mode selected. This causes output contention with RxC receiver.
4532         // Use of DPLL would require external hardware to disable RxC receiver
4533         // when DPLL mode selected.
4534         info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4535
4536         /* disable DMA interrupts */
4537         write_reg(info, TXDMA + DIR, 0);
4538         write_reg(info, RXDMA + DIR, 0);
4539
4540         /* MD0, Mode Register 0
4541          *
4542          * 07..05  PRCTL<2..0>, Protocol Mode, 100=HDLC
4543          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4544          * 03      Reserved, must be 0
4545          * 02      CRCCC, CRC Calculation, 1=enabled
4546          * 01      CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4547          * 00      CRC0, CRC initial value, 1 = all 1s
4548          *
4549          * 1000 0001
4550          */
4551         RegValue = 0x81;
4552         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4553                 RegValue |= BIT4;
4554         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4555                 RegValue |= BIT4;
4556         if (info->params.crc_type == HDLC_CRC_16_CCITT)
4557                 RegValue |= BIT2 + BIT1;
4558         write_reg(info, MD0, RegValue);
4559
4560         /* MD1, Mode Register 1
4561          *
4562          * 07..06  ADDRS<1..0>, Address detect, 00=no addr check
4563          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits
4564          * 03..02  RXCHR<1..0>, rx char size, 00=8 bits
4565          * 01..00  PMPM<1..0>, Parity mode, 00=no parity
4566          *
4567          * 0000 0000
4568          */
4569         RegValue = 0x00;
4570         write_reg(info, MD1, RegValue);
4571
4572         /* MD2, Mode Register 2
4573          *
4574          * 07      NRZFM, 0=NRZ, 1=FM
4575          * 06..05  CODE<1..0> Encoding, 00=NRZ
4576          * 04..03  DRATE<1..0> DPLL Divisor, 00=8
4577          * 02      Reserved, must be 0
4578          * 01..00  CNCT<1..0> Channel connection, 0=normal
4579          *
4580          * 0000 0000
4581          */
4582         RegValue = 0x00;
4583         switch(info->params.encoding) {
4584         case HDLC_ENCODING_NRZI:          RegValue |= BIT5; break;
4585         case HDLC_ENCODING_BIPHASE_MARK:  RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4586         case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4587         case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break;      /* aka Manchester */
4588 #if 0
4589         case HDLC_ENCODING_NRZB:                                        /* not supported */
4590         case HDLC_ENCODING_NRZI_MARK:                                   /* not supported */
4591         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:                          /* not supported */
4592 #endif
4593         }
4594         if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4595                 DpllDivisor = 16;
4596                 RegValue |= BIT3;
4597         } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4598                 DpllDivisor = 8;
4599         } else {
4600                 DpllDivisor = 32;
4601                 RegValue |= BIT4;
4602         }
4603         write_reg(info, MD2, RegValue);
4604
4605
4606         /* RXS, Receive clock source
4607          *
4608          * 07      Reserved, must be 0
4609          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4610          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4611          */
4612         RegValue=0;
4613         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4614                 RegValue |= BIT6;
4615         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4616                 RegValue |= BIT6 + BIT5;
4617         write_reg(info, RXS, RegValue);
4618
4619         /* TXS, Transmit clock source
4620          *
4621          * 07      Reserved, must be 0
4622          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4623          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4624          */
4625         RegValue=0;
4626         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4627                 RegValue |= BIT6;
4628         if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4629                 RegValue |= BIT6 + BIT5;
4630         write_reg(info, TXS, RegValue);
4631
4632         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4633                 set_rate(info, info->params.clock_speed * DpllDivisor);
4634         else
4635                 set_rate(info, info->params.clock_speed);
4636
4637         /* GPDATA (General Purpose I/O Data Register)
4638          *
4639          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4640          */
4641         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4642                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4643         else
4644                 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4645         write_control_reg(info);
4646
4647         /* RRC Receive Ready Control 0
4648          *
4649          * 07..05  Reserved, must be 0
4650          * 04..00  RRC<4..0> Rx FIFO trigger active
4651          */
4652         write_reg(info, RRC, rx_active_fifo_level);
4653
4654         /* TRC0 Transmit Ready Control 0
4655          *
4656          * 07..05  Reserved, must be 0
4657          * 04..00  TRC<4..0> Tx FIFO trigger active
4658          */
4659         write_reg(info, TRC0, tx_active_fifo_level);
4660
4661         /* TRC1 Transmit Ready Control 1
4662          *
4663          * 07..05  Reserved, must be 0
4664          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4665          */
4666         write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4667
4668         /* DMR, DMA Mode Register
4669          *
4670          * 07..05  Reserved, must be 0
4671          * 04      TMOD, Transfer Mode: 1=chained-block
4672          * 03      Reserved, must be 0
4673          * 02      NF, Number of Frames: 1=multi-frame
4674          * 01      CNTE, Frame End IRQ Counter enable: 0=disabled
4675          * 00      Reserved, must be 0
4676          *
4677          * 0001 0100
4678          */
4679         write_reg(info, TXDMA + DMR, 0x14);
4680         write_reg(info, RXDMA + DMR, 0x14);
4681
4682         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4683         write_reg(info, RXDMA + CPB,
4684                 (unsigned char)(info->buffer_list_phys >> 16));
4685
4686         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4687         write_reg(info, TXDMA + CPB,
4688                 (unsigned char)(info->buffer_list_phys >> 16));
4689
4690         /* enable status interrupts. other code enables/disables
4691          * the individual sources for these two interrupt classes.
4692          */
4693         info->ie0_value |= TXINTE + RXINTE;
4694         write_reg(info, IE0, info->ie0_value);
4695
4696         /* CTL, MSCI control register
4697          *
4698          * 07..06  Reserved, set to 0
4699          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4700          * 04      IDLC, idle control, 0=mark 1=idle register
4701          * 03      BRK, break, 0=off 1 =on (async)
4702          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4703          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4704          * 00      RTS, RTS output control, 0=active 1=inactive
4705          *
4706          * 0001 0001
4707          */
4708         RegValue = 0x10;
4709         if (!(info->serial_signals & SerialSignal_RTS))
4710                 RegValue |= 0x01;
4711         write_reg(info, CTL, RegValue);
4712
4713         /* preamble not supported ! */
4714
4715         tx_set_idle(info);
4716         tx_stop(info);
4717         rx_stop(info);
4718
4719         set_rate(info, info->params.clock_speed);
4720
4721         if (info->params.loopback)
4722                 enable_loopback(info,1);
4723 }
4724
4725 /* Set the transmit HDLC idle mode
4726  */
4727 static void tx_set_idle(SLMP_INFO *info)
4728 {
4729         unsigned char RegValue = 0xff;
4730
4731         /* Map API idle mode to SCA register bits */
4732         switch(info->idle_mode) {
4733         case HDLC_TXIDLE_FLAGS:                 RegValue = 0x7e; break;
4734         case HDLC_TXIDLE_ALT_ZEROS_ONES:        RegValue = 0xaa; break;
4735         case HDLC_TXIDLE_ZEROS:                 RegValue = 0x00; break;
4736         case HDLC_TXIDLE_ONES:                  RegValue = 0xff; break;
4737         case HDLC_TXIDLE_ALT_MARK_SPACE:        RegValue = 0xaa; break;
4738         case HDLC_TXIDLE_SPACE:                 RegValue = 0x00; break;
4739         case HDLC_TXIDLE_MARK:                  RegValue = 0xff; break;
4740         }
4741
4742         write_reg(info, IDL, RegValue);
4743 }
4744
4745 /* Query the adapter for the state of the V24 status (input) signals.
4746  */
4747 static void get_signals(SLMP_INFO *info)
4748 {
4749         u16 status = read_reg(info, SR3);
4750         u16 gpstatus = read_status_reg(info);
4751         u16 testbit;
4752
4753         /* clear all serial signals except DTR and RTS */
4754         info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4755
4756         /* set serial signal bits to reflect MISR */
4757
4758         if (!(status & BIT3))
4759                 info->serial_signals |= SerialSignal_CTS;
4760
4761         if ( !(status & BIT2))
4762                 info->serial_signals |= SerialSignal_DCD;
4763
4764         testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4765         if (!(gpstatus & testbit))
4766                 info->serial_signals |= SerialSignal_RI;
4767
4768         testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4769         if (!(gpstatus & testbit))
4770                 info->serial_signals |= SerialSignal_DSR;
4771 }
4772
4773 /* Set the state of DTR and RTS based on contents of
4774  * serial_signals member of device context.
4775  */
4776 static void set_signals(SLMP_INFO *info)
4777 {
4778         unsigned char RegValue;
4779         u16 EnableBit;
4780
4781         RegValue = read_reg(info, CTL);
4782         if (info->serial_signals & SerialSignal_RTS)
4783                 RegValue &= ~BIT0;
4784         else
4785                 RegValue |= BIT0;
4786         write_reg(info, CTL, RegValue);
4787
4788         // Port 0..3 DTR is ctrl reg <1,3,5,7>
4789         EnableBit = BIT1 << (info->port_num*2);
4790         if (info->serial_signals & SerialSignal_DTR)
4791                 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4792         else
4793                 info->port_array[0]->ctrlreg_value |= EnableBit;
4794         write_control_reg(info);
4795 }
4796
4797 /*******************/
4798 /* DMA Buffer Code */
4799 /*******************/
4800
4801 /* Set the count for all receive buffers to SCABUFSIZE
4802  * and set the current buffer to the first buffer. This effectively
4803  * makes all buffers free and discards any data in buffers.
4804  */
4805 static void rx_reset_buffers(SLMP_INFO *info)
4806 {
4807         rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4808 }
4809
4810 /* Free the buffers used by a received frame
4811  *
4812  * info   pointer to device instance data
4813  * first  index of 1st receive buffer of frame
4814  * last   index of last receive buffer of frame
4815  */
4816 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4817 {
4818         bool done = false;
4819
4820         while(!done) {
4821                 /* reset current buffer for reuse */
4822                 info->rx_buf_list[first].status = 0xff;
4823
4824                 if (first == last) {
4825                         done = true;
4826                         /* set new last rx descriptor address */
4827                         write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4828                 }
4829
4830                 first++;
4831                 if (first == info->rx_buf_count)
4832                         first = 0;
4833         }
4834
4835         /* set current buffer to next buffer after last buffer of frame */
4836         info->current_rx_buf = first;
4837 }
4838
4839 /* Return a received frame from the receive DMA buffers.
4840  * Only frames received without errors are returned.
4841  *
4842  * Return Value:        true if frame returned, otherwise false
4843  */
4844 static bool rx_get_frame(SLMP_INFO *info)
4845 {
4846         unsigned int StartIndex, EndIndex;      /* index of 1st and last buffers of Rx frame */
4847         unsigned short status;
4848         unsigned int framesize = 0;
4849         bool ReturnCode = false;
4850         unsigned long flags;
4851         struct tty_struct *tty = info->port.tty;
4852         unsigned char addr_field = 0xff;
4853         SCADESC *desc;
4854         SCADESC_EX *desc_ex;
4855
4856 CheckAgain:
4857         /* assume no frame returned, set zero length */
4858         framesize = 0;
4859         addr_field = 0xff;
4860
4861         /*
4862          * current_rx_buf points to the 1st buffer of the next available
4863          * receive frame. To find the last buffer of the frame look for
4864          * a non-zero status field in the buffer entries. (The status
4865          * field is set by the 16C32 after completing a receive frame.
4866          */
4867         StartIndex = EndIndex = info->current_rx_buf;
4868
4869         for ( ;; ) {
4870                 desc = &info->rx_buf_list[EndIndex];
4871                 desc_ex = &info->rx_buf_list_ex[EndIndex];
4872
4873                 if (desc->status == 0xff)
4874                         goto Cleanup;   /* current desc still in use, no frames available */
4875
4876                 if (framesize == 0 && info->params.addr_filter != 0xff)
4877                         addr_field = desc_ex->virt_addr[0];
4878
4879                 framesize += desc->length;
4880
4881                 /* Status != 0 means last buffer of frame */
4882                 if (desc->status)
4883                         break;
4884
4885                 EndIndex++;
4886                 if (EndIndex == info->rx_buf_count)
4887                         EndIndex = 0;
4888
4889                 if (EndIndex == info->current_rx_buf) {
4890                         /* all buffers have been 'used' but none mark      */
4891                         /* the end of a frame. Reset buffers and receiver. */
4892                         if ( info->rx_enabled ){
4893                                 spin_lock_irqsave(&info->lock,flags);
4894                                 rx_start(info);
4895                                 spin_unlock_irqrestore(&info->lock,flags);
4896                         }
4897                         goto Cleanup;
4898                 }
4899
4900         }
4901
4902         /* check status of receive frame */
4903
4904         /* frame status is byte stored after frame data
4905          *
4906          * 7 EOM (end of msg), 1 = last buffer of frame
4907          * 6 Short Frame, 1 = short frame
4908          * 5 Abort, 1 = frame aborted
4909          * 4 Residue, 1 = last byte is partial
4910          * 3 Overrun, 1 = overrun occurred during frame reception
4911          * 2 CRC,     1 = CRC error detected
4912          *
4913          */
4914         status = desc->status;
4915
4916         /* ignore CRC bit if not using CRC (bit is undefined) */
4917         /* Note:CRC is not save to data buffer */
4918         if (info->params.crc_type == HDLC_CRC_NONE)
4919                 status &= ~BIT2;
4920
4921         if (framesize == 0 ||
4922                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4923                 /* discard 0 byte frames, this seems to occur sometime
4924                  * when remote is idling flags.
4925                  */
4926                 rx_free_frame_buffers(info, StartIndex, EndIndex);
4927                 goto CheckAgain;
4928         }
4929
4930         if (framesize < 2)
4931                 status |= BIT6;
4932
4933         if (status & (BIT6+BIT5+BIT3+BIT2)) {
4934                 /* received frame has errors,
4935                  * update counts and mark frame size as 0
4936                  */
4937                 if (status & BIT6)
4938                         info->icount.rxshort++;
4939                 else if (status & BIT5)
4940                         info->icount.rxabort++;
4941                 else if (status & BIT3)
4942                         info->icount.rxover++;
4943                 else
4944                         info->icount.rxcrc++;
4945
4946                 framesize = 0;
4947 #if SYNCLINK_GENERIC_HDLC
4948                 {
4949                         info->netdev->stats.rx_errors++;
4950                         info->netdev->stats.rx_frame_errors++;
4951                 }
4952 #endif
4953         }
4954
4955         if ( debug_level >= DEBUG_LEVEL_BH )
4956                 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4957                         __FILE__,__LINE__,info->device_name,status,framesize);
4958
4959         if ( debug_level >= DEBUG_LEVEL_DATA )
4960                 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4961                         min_t(int, framesize,SCABUFSIZE),0);
4962
4963         if (framesize) {
4964                 if (framesize > info->max_frame_size)
4965                         info->icount.rxlong++;
4966                 else {
4967                         /* copy dma buffer(s) to contiguous intermediate buffer */
4968                         int copy_count = framesize;
4969                         int index = StartIndex;
4970                         unsigned char *ptmp = info->tmp_rx_buf;
4971                         info->tmp_rx_buf_count = framesize;
4972
4973                         info->icount.rxok++;
4974
4975                         while(copy_count) {
4976                                 int partial_count = min(copy_count,SCABUFSIZE);
4977                                 memcpy( ptmp,
4978                                         info->rx_buf_list_ex[index].virt_addr,
4979                                         partial_count );
4980                                 ptmp += partial_count;
4981                                 copy_count -= partial_count;
4982
4983                                 if ( ++index == info->rx_buf_count )
4984                                         index = 0;
4985                         }
4986
4987 #if SYNCLINK_GENERIC_HDLC
4988                         if (info->netcount)
4989                                 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
4990                         else
4991 #endif
4992                                 ldisc_receive_buf(tty,info->tmp_rx_buf,
4993                                                   info->flag_buf, framesize);
4994                 }
4995         }
4996         /* Free the buffers used by this frame. */
4997         rx_free_frame_buffers( info, StartIndex, EndIndex );
4998
4999         ReturnCode = true;
5000
5001 Cleanup:
5002         if ( info->rx_enabled && info->rx_overflow ) {
5003                 /* Receiver is enabled, but needs to restarted due to
5004                  * rx buffer overflow. If buffers are empty, restart receiver.
5005                  */
5006                 if (info->rx_buf_list[EndIndex].status == 0xff) {
5007                         spin_lock_irqsave(&info->lock,flags);
5008                         rx_start(info);
5009                         spin_unlock_irqrestore(&info->lock,flags);
5010                 }
5011         }
5012
5013         return ReturnCode;
5014 }
5015
5016 /* load the transmit DMA buffer with data
5017  */
5018 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5019 {
5020         unsigned short copy_count;
5021         unsigned int i = 0;
5022         SCADESC *desc;
5023         SCADESC_EX *desc_ex;
5024
5025         if ( debug_level >= DEBUG_LEVEL_DATA )
5026                 trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
5027
5028         /* Copy source buffer to one or more DMA buffers, starting with
5029          * the first transmit dma buffer.
5030          */
5031         for(i=0;;)
5032         {
5033                 copy_count = min_t(unsigned short,count,SCABUFSIZE);
5034
5035                 desc = &info->tx_buf_list[i];
5036                 desc_ex = &info->tx_buf_list_ex[i];
5037
5038                 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5039
5040                 desc->length = copy_count;
5041                 desc->status = 0;
5042
5043                 buf += copy_count;
5044                 count -= copy_count;
5045
5046                 if (!count)
5047                         break;
5048
5049                 i++;
5050                 if (i >= info->tx_buf_count)
5051                         i = 0;
5052         }
5053
5054         info->tx_buf_list[i].status = 0x81;     /* set EOM and EOT status */
5055         info->last_tx_buf = ++i;
5056 }
5057
5058 static bool register_test(SLMP_INFO *info)
5059 {
5060         static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5061         static unsigned int count = ARRAY_SIZE(testval);
5062         unsigned int i;
5063         bool rc = true;
5064         unsigned long flags;
5065
5066         spin_lock_irqsave(&info->lock,flags);
5067         reset_port(info);
5068
5069         /* assume failure */
5070         info->init_error = DiagStatus_AddressFailure;
5071
5072         /* Write bit patterns to various registers but do it out of */
5073         /* sync, then read back and verify values. */
5074
5075         for (i = 0 ; i < count ; i++) {
5076                 write_reg(info, TMC, testval[i]);
5077                 write_reg(info, IDL, testval[(i+1)%count]);
5078                 write_reg(info, SA0, testval[(i+2)%count]);
5079                 write_reg(info, SA1, testval[(i+3)%count]);
5080
5081                 if ( (read_reg(info, TMC) != testval[i]) ||
5082                           (read_reg(info, IDL) != testval[(i+1)%count]) ||
5083                           (read_reg(info, SA0) != testval[(i+2)%count]) ||
5084                           (read_reg(info, SA1) != testval[(i+3)%count]) )
5085                 {
5086                         rc = false;
5087                         break;
5088                 }
5089         }
5090
5091         reset_port(info);
5092         spin_unlock_irqrestore(&info->lock,flags);
5093
5094         return rc;
5095 }
5096
5097 static bool irq_test(SLMP_INFO *info)
5098 {
5099         unsigned long timeout;
5100         unsigned long flags;
5101
5102         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5103
5104         spin_lock_irqsave(&info->lock,flags);
5105         reset_port(info);
5106
5107         /* assume failure */
5108         info->init_error = DiagStatus_IrqFailure;
5109         info->irq_occurred = false;
5110
5111         /* setup timer0 on SCA0 to interrupt */
5112
5113         /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5114         write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5115
5116         write_reg(info, (unsigned char)(timer + TEPR), 0);      /* timer expand prescale */
5117         write_reg16(info, (unsigned char)(timer + TCONR), 1);   /* timer constant */
5118
5119
5120         /* TMCS, Timer Control/Status Register
5121          *
5122          * 07      CMF, Compare match flag (read only) 1=match
5123          * 06      ECMI, CMF Interrupt Enable: 1=enabled
5124          * 05      Reserved, must be 0
5125          * 04      TME, Timer Enable
5126          * 03..00  Reserved, must be 0
5127          *
5128          * 0101 0000
5129          */
5130         write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5131
5132         spin_unlock_irqrestore(&info->lock,flags);
5133
5134         timeout=100;
5135         while( timeout-- && !info->irq_occurred ) {
5136                 msleep_interruptible(10);
5137         }
5138
5139         spin_lock_irqsave(&info->lock,flags);
5140         reset_port(info);
5141         spin_unlock_irqrestore(&info->lock,flags);
5142
5143         return info->irq_occurred;
5144 }
5145
5146 /* initialize individual SCA device (2 ports)
5147  */
5148 static bool sca_init(SLMP_INFO *info)
5149 {
5150         /* set wait controller to single mem partition (low), no wait states */
5151         write_reg(info, PABR0, 0);      /* wait controller addr boundary 0 */
5152         write_reg(info, PABR1, 0);      /* wait controller addr boundary 1 */
5153         write_reg(info, WCRL, 0);       /* wait controller low range */
5154         write_reg(info, WCRM, 0);       /* wait controller mid range */
5155         write_reg(info, WCRH, 0);       /* wait controller high range */
5156
5157         /* DPCR, DMA Priority Control
5158          *
5159          * 07..05  Not used, must be 0
5160          * 04      BRC, bus release condition: 0=all transfers complete
5161          * 03      CCC, channel change condition: 0=every cycle
5162          * 02..00  PR<2..0>, priority 100=round robin
5163          *
5164          * 00000100 = 0x04
5165          */
5166         write_reg(info, DPCR, dma_priority);
5167
5168         /* DMA Master Enable, BIT7: 1=enable all channels */
5169         write_reg(info, DMER, 0x80);
5170
5171         /* enable all interrupt classes */
5172         write_reg(info, IER0, 0xff);    /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5173         write_reg(info, IER1, 0xff);    /* DMIB,DMIA (channels 0-3) */
5174         write_reg(info, IER2, 0xf0);    /* TIRQ (timers 0-3) */
5175
5176         /* ITCR, interrupt control register
5177          * 07      IPC, interrupt priority, 0=MSCI->DMA
5178          * 06..05  IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5179          * 04      VOS, Vector Output, 0=unmodified vector
5180          * 03..00  Reserved, must be 0
5181          */
5182         write_reg(info, ITCR, 0);
5183
5184         return true;
5185 }
5186
5187 /* initialize adapter hardware
5188  */
5189 static bool init_adapter(SLMP_INFO *info)
5190 {
5191         int i;
5192
5193         /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5194         volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5195         u32 readval;
5196
5197         info->misc_ctrl_value |= BIT30;
5198         *MiscCtrl = info->misc_ctrl_value;
5199
5200         /*
5201          * Force at least 170ns delay before clearing
5202          * reset bit. Each read from LCR takes at least
5203          * 30ns so 10 times for 300ns to be safe.
5204          */
5205         for(i=0;i<10;i++)
5206                 readval = *MiscCtrl;
5207
5208         info->misc_ctrl_value &= ~BIT30;
5209         *MiscCtrl = info->misc_ctrl_value;
5210
5211         /* init control reg (all DTRs off, all clksel=input) */
5212         info->ctrlreg_value = 0xaa;
5213         write_control_reg(info);
5214
5215         {
5216                 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5217                 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5218
5219                 switch(read_ahead_count)
5220                 {
5221                 case 16:
5222                         lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5223                         break;
5224                 case 8:
5225                         lcr1_brdr_value |= BIT5 + BIT4;
5226                         break;
5227                 case 4:
5228                         lcr1_brdr_value |= BIT5 + BIT3;
5229                         break;
5230                 case 0:
5231                         lcr1_brdr_value |= BIT5;
5232                         break;
5233                 }
5234
5235                 *LCR1BRDR = lcr1_brdr_value;
5236                 *MiscCtrl = misc_ctrl_value;
5237         }
5238
5239         sca_init(info->port_array[0]);
5240         sca_init(info->port_array[2]);
5241
5242         return true;
5243 }
5244
5245 /* Loopback an HDLC frame to test the hardware
5246  * interrupt and DMA functions.
5247  */
5248 static bool loopback_test(SLMP_INFO *info)
5249 {
5250 #define TESTFRAMESIZE 20
5251
5252         unsigned long timeout;
5253         u16 count = TESTFRAMESIZE;
5254         unsigned char buf[TESTFRAMESIZE];
5255         bool rc = false;
5256         unsigned long flags;
5257
5258         struct tty_struct *oldtty = info->port.tty;
5259         u32 speed = info->params.clock_speed;
5260
5261         info->params.clock_speed = 3686400;
5262         info->port.tty = NULL;
5263
5264         /* assume failure */
5265         info->init_error = DiagStatus_DmaFailure;
5266
5267         /* build and send transmit frame */
5268         for (count = 0; count < TESTFRAMESIZE;++count)
5269                 buf[count] = (unsigned char)count;
5270
5271         memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5272
5273         /* program hardware for HDLC and enabled receiver */
5274         spin_lock_irqsave(&info->lock,flags);
5275         hdlc_mode(info);
5276         enable_loopback(info,1);
5277         rx_start(info);
5278         info->tx_count = count;
5279         tx_load_dma_buffer(info,buf,count);
5280         tx_start(info);
5281         spin_unlock_irqrestore(&info->lock,flags);
5282
5283         /* wait for receive complete */
5284         /* Set a timeout for waiting for interrupt. */
5285         for ( timeout = 100; timeout; --timeout ) {
5286                 msleep_interruptible(10);
5287
5288                 if (rx_get_frame(info)) {
5289                         rc = true;
5290                         break;
5291                 }
5292         }
5293
5294         /* verify received frame length and contents */
5295         if (rc &&
5296             ( info->tmp_rx_buf_count != count ||
5297               memcmp(buf, info->tmp_rx_buf,count))) {
5298                 rc = false;
5299         }
5300
5301         spin_lock_irqsave(&info->lock,flags);
5302         reset_adapter(info);
5303         spin_unlock_irqrestore(&info->lock,flags);
5304
5305         info->params.clock_speed = speed;
5306         info->port.tty = oldtty;
5307
5308         return rc;
5309 }
5310
5311 /* Perform diagnostics on hardware
5312  */
5313 static int adapter_test( SLMP_INFO *info )
5314 {
5315         unsigned long flags;
5316         if ( debug_level >= DEBUG_LEVEL_INFO )
5317                 printk( "%s(%d):Testing device %s\n",
5318                         __FILE__,__LINE__,info->device_name );
5319
5320         spin_lock_irqsave(&info->lock,flags);
5321         init_adapter(info);
5322         spin_unlock_irqrestore(&info->lock,flags);
5323
5324         info->port_array[0]->port_count = 0;
5325
5326         if ( register_test(info->port_array[0]) &&
5327                 register_test(info->port_array[1])) {
5328
5329                 info->port_array[0]->port_count = 2;
5330
5331                 if ( register_test(info->port_array[2]) &&
5332                         register_test(info->port_array[3]) )
5333                         info->port_array[0]->port_count += 2;
5334         }
5335         else {
5336                 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5337                         __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5338                 return -ENODEV;
5339         }
5340
5341         if ( !irq_test(info->port_array[0]) ||
5342                 !irq_test(info->port_array[1]) ||
5343                  (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5344                  (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5345                 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5346                         __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5347                 return -ENODEV;
5348         }
5349
5350         if (!loopback_test(info->port_array[0]) ||
5351                 !loopback_test(info->port_array[1]) ||
5352                  (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5353                  (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5354                 printk( "%s(%d):DMA test failure for device %s\n",
5355                         __FILE__,__LINE__,info->device_name);
5356                 return -ENODEV;
5357         }
5358
5359         if ( debug_level >= DEBUG_LEVEL_INFO )
5360                 printk( "%s(%d):device %s passed diagnostics\n",
5361                         __FILE__,__LINE__,info->device_name );
5362
5363         info->port_array[0]->init_error = 0;
5364         info->port_array[1]->init_error = 0;
5365         if ( info->port_count > 2 ) {
5366                 info->port_array[2]->init_error = 0;
5367                 info->port_array[3]->init_error = 0;
5368         }
5369
5370         return 0;
5371 }
5372
5373 /* Test the shared memory on a PCI adapter.
5374  */
5375 static bool memory_test(SLMP_INFO *info)
5376 {
5377         static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5378                 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5379         unsigned long count = ARRAY_SIZE(testval);
5380         unsigned long i;
5381         unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5382         unsigned long * addr = (unsigned long *)info->memory_base;
5383
5384         /* Test data lines with test pattern at one location. */
5385
5386         for ( i = 0 ; i < count ; i++ ) {
5387                 *addr = testval[i];
5388                 if ( *addr != testval[i] )
5389                         return false;
5390         }
5391
5392         /* Test address lines with incrementing pattern over */
5393         /* entire address range. */
5394
5395         for ( i = 0 ; i < limit ; i++ ) {
5396                 *addr = i * 4;
5397                 addr++;
5398         }
5399
5400         addr = (unsigned long *)info->memory_base;
5401
5402         for ( i = 0 ; i < limit ; i++ ) {
5403                 if ( *addr != i * 4 )
5404                         return false;
5405                 addr++;
5406         }
5407
5408         memset( info->memory_base, 0, SCA_MEM_SIZE );
5409         return true;
5410 }
5411
5412 /* Load data into PCI adapter shared memory.
5413  *
5414  * The PCI9050 releases control of the local bus
5415  * after completing the current read or write operation.
5416  *
5417  * While the PCI9050 write FIFO not empty, the
5418  * PCI9050 treats all of the writes as a single transaction
5419  * and does not release the bus. This causes DMA latency problems
5420  * at high speeds when copying large data blocks to the shared memory.
5421  *
5422  * This function breaks a write into multiple transations by
5423  * interleaving a read which flushes the write FIFO and 'completes'
5424  * the write transation. This allows any pending DMA request to gain control
5425  * of the local bus in a timely fasion.
5426  */
5427 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5428 {
5429         /* A load interval of 16 allows for 4 32-bit writes at */
5430         /* 136ns each for a maximum latency of 542ns on the local bus.*/
5431
5432         unsigned short interval = count / sca_pci_load_interval;
5433         unsigned short i;
5434
5435         for ( i = 0 ; i < interval ; i++ )
5436         {
5437                 memcpy(dest, src, sca_pci_load_interval);
5438                 read_status_reg(info);
5439                 dest += sca_pci_load_interval;
5440                 src += sca_pci_load_interval;
5441         }
5442
5443         memcpy(dest, src, count % sca_pci_load_interval);
5444 }
5445
5446 static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5447 {
5448         int i;
5449         int linecount;
5450         if (xmit)
5451                 printk("%s tx data:\n",info->device_name);
5452         else
5453                 printk("%s rx data:\n",info->device_name);
5454
5455         while(count) {
5456                 if (count > 16)
5457                         linecount = 16;
5458                 else
5459                         linecount = count;
5460
5461                 for(i=0;i<linecount;i++)
5462                         printk("%02X ",(unsigned char)data[i]);
5463                 for(;i<17;i++)
5464                         printk("   ");
5465                 for(i=0;i<linecount;i++) {
5466                         if (data[i]>=040 && data[i]<=0176)
5467                                 printk("%c",data[i]);
5468                         else
5469                                 printk(".");
5470                 }
5471                 printk("\n");
5472
5473                 data  += linecount;
5474                 count -= linecount;
5475         }
5476 }       /* end of trace_block() */
5477
5478 /* called when HDLC frame times out
5479  * update stats and do tx completion processing
5480  */
5481 static void tx_timeout(unsigned long context)
5482 {
5483         SLMP_INFO *info = (SLMP_INFO*)context;
5484         unsigned long flags;
5485
5486         if ( debug_level >= DEBUG_LEVEL_INFO )
5487                 printk( "%s(%d):%s tx_timeout()\n",
5488                         __FILE__,__LINE__,info->device_name);
5489         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5490                 info->icount.txtimeout++;
5491         }
5492         spin_lock_irqsave(&info->lock,flags);
5493         info->tx_active = false;
5494         info->tx_count = info->tx_put = info->tx_get = 0;
5495
5496         spin_unlock_irqrestore(&info->lock,flags);
5497
5498 #if SYNCLINK_GENERIC_HDLC
5499         if (info->netcount)
5500                 hdlcdev_tx_done(info);
5501         else
5502 #endif
5503                 bh_transmit(info);
5504 }
5505
5506 /* called to periodically check the DSR/RI modem signal input status
5507  */
5508 static void status_timeout(unsigned long context)
5509 {
5510         u16 status = 0;
5511         SLMP_INFO *info = (SLMP_INFO*)context;
5512         unsigned long flags;
5513         unsigned char delta;
5514
5515
5516         spin_lock_irqsave(&info->lock,flags);
5517         get_signals(info);
5518         spin_unlock_irqrestore(&info->lock,flags);
5519
5520         /* check for DSR/RI state change */
5521
5522         delta = info->old_signals ^ info->serial_signals;
5523         info->old_signals = info->serial_signals;
5524
5525         if (delta & SerialSignal_DSR)
5526                 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5527
5528         if (delta & SerialSignal_RI)
5529                 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5530
5531         if (delta & SerialSignal_DCD)
5532                 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5533
5534         if (delta & SerialSignal_CTS)
5535                 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5536
5537         if (status)
5538                 isr_io_pin(info,status);
5539
5540         mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5541 }
5542
5543
5544 /* Register Access Routines -
5545  * All registers are memory mapped
5546  */
5547 #define CALC_REGADDR() \
5548         unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5549         if (info->port_num > 1) \
5550                 RegAddr += 256;                 /* port 0-1 SCA0, 2-3 SCA1 */ \
5551         if ( info->port_num & 1) { \
5552                 if (Addr > 0x7f) \
5553                         RegAddr += 0x40;        /* DMA access */ \
5554                 else if (Addr > 0x1f && Addr < 0x60) \
5555                         RegAddr += 0x20;        /* MSCI access */ \
5556         }
5557
5558
5559 static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5560 {
5561         CALC_REGADDR();
5562         return *RegAddr;
5563 }
5564 static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5565 {
5566         CALC_REGADDR();
5567         *RegAddr = Value;
5568 }
5569
5570 static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5571 {
5572         CALC_REGADDR();
5573         return *((u16 *)RegAddr);
5574 }
5575
5576 static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5577 {
5578         CALC_REGADDR();
5579         *((u16 *)RegAddr) = Value;
5580 }
5581
5582 static unsigned char read_status_reg(SLMP_INFO * info)
5583 {
5584         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5585         return *RegAddr;
5586 }
5587
5588 static void write_control_reg(SLMP_INFO * info)
5589 {
5590         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5591         *RegAddr = info->port_array[0]->ctrlreg_value;
5592 }
5593
5594
5595 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5596                                           const struct pci_device_id *ent)
5597 {
5598         if (pci_enable_device(dev)) {
5599                 printk("error enabling pci device %p\n", dev);
5600                 return -EIO;
5601         }
5602         device_init( ++synclinkmp_adapter_count, dev );
5603         return 0;
5604 }
5605
5606 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5607 {
5608 }