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   1 /*
   2  * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink Multiport
   5  * high speed multiprotocol serial adapter.
   6  *
   7  * written by Paul Fulghum for Microgate Corporation
   8  * paulkf@microgate.com
   9  *
  10  * Microgate and SyncLink are trademarks of Microgate Corporation
  11  *
  12  * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
  13  * This code is released under the GNU General Public License (GPL)
  14  *
  15  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  25  * OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29 #if defined(__i386__)
  30 #  define BREAKPOINT() asm("   int $3");
  31 #else
  32 #  define BREAKPOINT() { }
  33 #endif
  34
  35 #define MAX_DEVICES 12
  36
  37 #include <linux/module.h>
  38 #include <linux/errno.h>
  39 #include <linux/signal.h>
  40 #include <linux/sched.h>
  41 #include <linux/timer.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/pci.h>
  44 #include <linux/tty.h>
  45 #include <linux/tty_flip.h>
  46 #include <linux/serial.h>
  47 #include <linux/major.h>
  48 #include <linux/string.h>
  49 #include <linux/fcntl.h>
  50 #include <linux/ptrace.h>
  51 #include <linux/ioport.h>
  52 #include <linux/mm.h>
  53 #include <linux/seq_file.h>
  54 #include <linux/slab.h>
  55 #include <linux/netdevice.h>
  56 #include <linux/vmalloc.h>
  57 #include <linux/init.h>
  58 #include <linux/delay.h>
  59 #include <linux/ioctl.h>
  60
  61 #include <asm/system.h>
  62 #include <asm/io.h>
  63 #include <asm/irq.h>
  64 #include <asm/dma.h>
  65 #include <linux/bitops.h>
  66 #include <asm/types.h>
  67 #include <linux/termios.h>
  68 #include <linux/workqueue.h>
  69 #include <linux/hdlc.h>
  70 #include <linux/synclink.h>
  71
  72 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
  73 #define SYNCLINK_GENERIC_HDLC 1
  74 #else
  75 #define SYNCLINK_GENERIC_HDLC 0
  76 #endif
  77
  78 #define GET_USER(error,value,addr) error = get_user(value,addr)
  79 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  80 #define PUT_USER(error,value,addr) error = put_user(value,addr)
  81 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  82
  83 #include <asm/uaccess.h>
  84
  85 static MGSL_PARAMS default_params = {
  86         MGSL_MODE_HDLC,                 /* unsigned long mode */
  87         0,                              /* unsigned char loopback; */
  88         HDLC_FLAG_UNDERRUN_ABORT15,     /* unsigned short flags; */
  89         HDLC_ENCODING_NRZI_SPACE,       /* unsigned char encoding; */
  90         0,                              /* unsigned long clock_speed; */
  91         0xff,                           /* unsigned char addr_filter; */
  92         HDLC_CRC_16_CCITT,              /* unsigned short crc_type; */
  93         HDLC_PREAMBLE_LENGTH_8BITS,     /* unsigned char preamble_length; */
  94         HDLC_PREAMBLE_PATTERN_NONE,     /* unsigned char preamble; */
  95         9600,                           /* unsigned long data_rate; */
  96         8,                              /* unsigned char data_bits; */
  97         1,                              /* unsigned char stop_bits; */
  98         ASYNC_PARITY_NONE               /* unsigned char parity; */
  99 };
 100
 101 /* size in bytes of DMA data buffers */
 102 #define SCABUFSIZE      1024
 103 #define SCA_MEM_SIZE    0x40000
 104 #define SCA_BASE_SIZE   512
 105 #define SCA_REG_SIZE    16
 106 #define SCA_MAX_PORTS   4
 107 #define SCAMAXDESC      128
 108
 109 #define BUFFERLISTSIZE  4096
 110
 111 /* SCA-I style DMA buffer descriptor */
 112 typedef struct _SCADESC
 113 {
 114         u16     next;           /* lower l6 bits of next descriptor addr */
 115         u16     buf_ptr;        /* lower 16 bits of buffer addr */
 116         u8      buf_base;       /* upper 8 bits of buffer addr */
 117         u8      pad1;
 118         u16     length;         /* length of buffer */
 119         u8      status;         /* status of buffer */
 120         u8      pad2;
 121 } SCADESC, *PSCADESC;
 122
 123 typedef struct _SCADESC_EX
 124 {
 125         /* device driver bookkeeping section */
 126         char    *virt_addr;     /* virtual address of data buffer */
 127         u16     phys_entry;     /* lower 16-bits of physical address of this descriptor */
 128 } SCADESC_EX, *PSCADESC_EX;
 129
 130 /* The queue of BH actions to be performed */
 131
 132 #define BH_RECEIVE  1
 133 #define BH_TRANSMIT 2
 134 #define BH_STATUS   4
 135
 136 #define IO_PIN_SHUTDOWN_LIMIT 100
 137
 138 struct  _input_signal_events {
 139         int     ri_up;
 140         int     ri_down;
 141         int     dsr_up;
 142         int     dsr_down;
 143         int     dcd_up;
 144         int     dcd_down;
 145         int     cts_up;
 146         int     cts_down;
 147 };
 148
 149 /*
 150  * Device instance data structure
 151  */
 152 typedef struct _synclinkmp_info {
 153         void *if_ptr;                           /* General purpose pointer (used by SPPP) */
 154         int                     magic;
 155         struct tty_port         port;
 156         int                     line;
 157         unsigned short          close_delay;
 158         unsigned short          closing_wait;   /* time to wait before closing */
 159
 160         struct mgsl_icount      icount;
 161
 162         int                     timeout;
 163         int                     x_char;         /* xon/xoff character */
 164         u16                     read_status_mask1;  /* break detection (SR1 indications) */
 165         u16                     read_status_mask2;  /* parity/framing/overun (SR2 indications) */
 166         unsigned char           ignore_status_mask1;  /* break detection (SR1 indications) */
 167         unsigned char           ignore_status_mask2;  /* parity/framing/overun (SR2 indications) */
 168         unsigned char           *tx_buf;
 169         int                     tx_put;
 170         int                     tx_get;
 171         int                     tx_count;
 172
 173         wait_queue_head_t       status_event_wait_q;
 174         wait_queue_head_t       event_wait_q;
 175         struct timer_list       tx_timer;       /* HDLC transmit timeout timer */
 176         struct _synclinkmp_info *next_device;   /* device list link */
 177         struct timer_list       status_timer;   /* input signal status check timer */
 178
 179         spinlock_t lock;                /* spinlock for synchronizing with ISR */
 180         struct work_struct task;                        /* task structure for scheduling bh */
 181
 182         u32 max_frame_size;                     /* as set by device config */
 183
 184         u32 pending_bh;
 185
 186         bool bh_running;                                /* Protection from multiple */
 187         int isr_overflow;
 188         bool bh_requested;
 189
 190         int dcd_chkcount;                       /* check counts to prevent */
 191         int cts_chkcount;                       /* too many IRQs if a signal */
 192         int dsr_chkcount;                       /* is floating */
 193         int ri_chkcount;
 194
 195         char *buffer_list;                      /* virtual address of Rx & Tx buffer lists */
 196         unsigned long buffer_list_phys;
 197
 198         unsigned int rx_buf_count;              /* count of total allocated Rx buffers */
 199         SCADESC *rx_buf_list;                   /* list of receive buffer entries */
 200         SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
 201         unsigned int current_rx_buf;
 202
 203         unsigned int tx_buf_count;              /* count of total allocated Tx buffers */
 204         SCADESC *tx_buf_list;           /* list of transmit buffer entries */
 205         SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
 206         unsigned int last_tx_buf;
 207
 208         unsigned char *tmp_rx_buf;
 209         unsigned int tmp_rx_buf_count;
 210
 211         bool rx_enabled;
 212         bool rx_overflow;
 213
 214         bool tx_enabled;
 215         bool tx_active;
 216         u32 idle_mode;
 217
 218         unsigned char ie0_value;
 219         unsigned char ie1_value;
 220         unsigned char ie2_value;
 221         unsigned char ctrlreg_value;
 222         unsigned char old_signals;
 223
 224         char device_name[25];                   /* device instance name */
 225
 226         int port_count;
 227         int adapter_num;
 228         int port_num;
 229
 230         struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
 231
 232         unsigned int bus_type;                  /* expansion bus type (ISA,EISA,PCI) */
 233
 234         unsigned int irq_level;                 /* interrupt level */
 235         unsigned long irq_flags;
 236         bool irq_requested;                     /* true if IRQ requested */
 237
 238         MGSL_PARAMS params;                     /* communications parameters */
 239
 240         unsigned char serial_signals;           /* current serial signal states */
 241
 242         bool irq_occurred;                      /* for diagnostics use */
 243         unsigned int init_error;                /* Initialization startup error */
 244
 245         u32 last_mem_alloc;
 246         unsigned char* memory_base;             /* shared memory address (PCI only) */
 247         u32 phys_memory_base;
 248         int shared_mem_requested;
 249
 250         unsigned char* sca_base;                /* HD64570 SCA Memory address */
 251         u32 phys_sca_base;
 252         u32 sca_offset;
 253         bool sca_base_requested;
 254
 255         unsigned char* lcr_base;                /* local config registers (PCI only) */
 256         u32 phys_lcr_base;
 257         u32 lcr_offset;
 258         int lcr_mem_requested;
 259
 260         unsigned char* statctrl_base;           /* status/control register memory */
 261         u32 phys_statctrl_base;
 262         u32 statctrl_offset;
 263         bool sca_statctrl_requested;
 264
 265         u32 misc_ctrl_value;
 266         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 267         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 268         bool drop_rts_on_tx_done;
 269
 270         struct  _input_signal_events    input_signal_events;
 271
 272         /* SPPP/Cisco HDLC device parts */
 273         int netcount;
 274         spinlock_t netlock;
 275
 276 #if SYNCLINK_GENERIC_HDLC
 277         struct net_device *netdev;
 278 #endif
 279
 280 } SLMP_INFO;
 281
 282 #define MGSL_MAGIC 0x5401
 283
 284 /*
 285  * define serial signal status change macros
 286  */
 287 #define MISCSTATUS_DCD_LATCHED  (SerialSignal_DCD<<8)   /* indicates change in DCD */
 288 #define MISCSTATUS_RI_LATCHED   (SerialSignal_RI<<8)    /* indicates change in RI */
 289 #define MISCSTATUS_CTS_LATCHED  (SerialSignal_CTS<<8)   /* indicates change in CTS */
 290 #define MISCSTATUS_DSR_LATCHED  (SerialSignal_DSR<<8)   /* change in DSR */
 291
 292 /* Common Register macros */
 293 #define LPR     0x00
 294 #define PABR0   0x02
 295 #define PABR1   0x03
 296 #define WCRL    0x04
 297 #define WCRM    0x05
 298 #define WCRH    0x06
 299 #define DPCR    0x08
 300 #define DMER    0x09
 301 #define ISR0    0x10
 302 #define ISR1    0x11
 303 #define ISR2    0x12
 304 #define IER0    0x14
 305 #define IER1    0x15
 306 #define IER2    0x16
 307 #define ITCR    0x18
 308 #define INTVR   0x1a
 309 #define IMVR    0x1c
 310
 311 /* MSCI Register macros */
 312 #define TRB     0x20
 313 #define TRBL    0x20
 314 #define TRBH    0x21
 315 #define SR0     0x22
 316 #define SR1     0x23
 317 #define SR2     0x24
 318 #define SR3     0x25
 319 #define FST     0x26
 320 #define IE0     0x28
 321 #define IE1     0x29
 322 #define IE2     0x2a
 323 #define FIE     0x2b
 324 #define CMD     0x2c
 325 #define MD0     0x2e
 326 #define MD1     0x2f
 327 #define MD2     0x30
 328 #define CTL     0x31
 329 #define SA0     0x32
 330 #define SA1     0x33
 331 #define IDL     0x34
 332 #define TMC     0x35
 333 #define RXS     0x36
 334 #define TXS     0x37
 335 #define TRC0    0x38
 336 #define TRC1    0x39
 337 #define RRC     0x3a
 338 #define CST0    0x3c
 339 #define CST1    0x3d
 340
 341 /* Timer Register Macros */
 342 #define TCNT    0x60
 343 #define TCNTL   0x60
 344 #define TCNTH   0x61
 345 #define TCONR   0x62
 346 #define TCONRL  0x62
 347 #define TCONRH  0x63
 348 #define TMCS    0x64
 349 #define TEPR    0x65
 350
 351 /* DMA Controller Register macros */
 352 #define DARL    0x80
 353 #define DARH    0x81
 354 #define DARB    0x82
 355 #define BAR     0x80
 356 #define BARL    0x80
 357 #define BARH    0x81
 358 #define BARB    0x82
 359 #define SAR     0x84
 360 #define SARL    0x84
 361 #define SARH    0x85
 362 #define SARB    0x86
 363 #define CPB     0x86
 364 #define CDA     0x88
 365 #define CDAL    0x88
 366 #define CDAH    0x89
 367 #define EDA     0x8a
 368 #define EDAL    0x8a
 369 #define EDAH    0x8b
 370 #define BFL     0x8c
 371 #define BFLL    0x8c
 372 #define BFLH    0x8d
 373 #define BCR     0x8e
 374 #define BCRL    0x8e
 375 #define BCRH    0x8f
 376 #define DSR     0x90
 377 #define DMR     0x91
 378 #define FCT     0x93
 379 #define DIR     0x94
 380 #define DCMD    0x95
 381
 382 /* combine with timer or DMA register address */
 383 #define TIMER0  0x00
 384 #define TIMER1  0x08
 385 #define TIMER2  0x10
 386 #define TIMER3  0x18
 387 #define RXDMA   0x00
 388 #define TXDMA   0x20
 389
 390 /* SCA Command Codes */
 391 #define NOOP            0x00
 392 #define TXRESET         0x01
 393 #define TXENABLE        0x02
 394 #define TXDISABLE       0x03
 395 #define TXCRCINIT       0x04
 396 #define TXCRCEXCL       0x05
 397 #define TXEOM           0x06
 398 #define TXABORT         0x07
 399 #define MPON            0x08
 400 #define TXBUFCLR        0x09
 401 #define RXRESET         0x11
 402 #define RXENABLE        0x12
 403 #define RXDISABLE       0x13
 404 #define RXCRCINIT       0x14
 405 #define RXREJECT        0x15
 406 #define SEARCHMP        0x16
 407 #define RXCRCEXCL       0x17
 408 #define RXCRCCALC       0x18
 409 #define CHRESET         0x21
 410 #define HUNT            0x31
 411
 412 /* DMA command codes */
 413 #define SWABORT         0x01
 414 #define FEICLEAR        0x02
 415
 416 /* IE0 */
 417 #define TXINTE          BIT7
 418 #define RXINTE          BIT6
 419 #define TXRDYE          BIT1
 420 #define RXRDYE          BIT0
 421
 422 /* IE1 & SR1 */
 423 #define UDRN    BIT7
 424 #define IDLE    BIT6
 425 #define SYNCD   BIT4
 426 #define FLGD    BIT4
 427 #define CCTS    BIT3
 428 #define CDCD    BIT2
 429 #define BRKD    BIT1
 430 #define ABTD    BIT1
 431 #define GAPD    BIT1
 432 #define BRKE    BIT0
 433 #define IDLD    BIT0
 434
 435 /* IE2 & SR2 */
 436 #define EOM     BIT7
 437 #define PMP     BIT6
 438 #define SHRT    BIT6
 439 #define PE      BIT5
 440 #define ABT     BIT5
 441 #define FRME    BIT4
 442 #define RBIT    BIT4
 443 #define OVRN    BIT3
 444 #define CRCE    BIT2
 445
 446
 447 /*
 448  * Global linked list of SyncLink devices
 449  */
 450 static SLMP_INFO *synclinkmp_device_list = NULL;
 451 static int synclinkmp_adapter_count = -1;
 452 static int synclinkmp_device_count = 0;
 453
 454 /*
 455  * Set this param to non-zero to load eax with the
 456  * .text section address and breakpoint on module load.
 457  * This is useful for use with gdb and add-symbol-file command.
 458  */
 459 static int break_on_load = 0;
 460
 461 /*
 462  * Driver major number, defaults to zero to get auto
 463  * assigned major number. May be forced as module parameter.
 464  */
 465 static int ttymajor = 0;
 466
 467 /*
 468  * Array of user specified options for ISA adapters.
 469  */
 470 static int debug_level = 0;
 471 static int maxframe[MAX_DEVICES] = {0,};
 472
 473 module_param(break_on_load, bool, 0);
 474 module_param(ttymajor, int, 0);
 475 module_param(debug_level, int, 0);
 476 module_param_array(maxframe, int, NULL, 0);
 477
 478 static char *driver_name = "SyncLink MultiPort driver";
 479 static char *driver_version = "$Revision: 4.38 $";
 480
 481 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 482 static void synclinkmp_remove_one(struct pci_dev *dev);
 483
 484 static struct pci_device_id synclinkmp_pci_tbl[] = {
 485         { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
 486         { 0, }, /* terminate list */
 487 };
 488 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
 489
 490 MODULE_LICENSE("GPL");
 491
 492 static struct pci_driver synclinkmp_pci_driver = {
 493         .name           = "synclinkmp",
 494         .id_table       = synclinkmp_pci_tbl,
 495         .probe          = synclinkmp_init_one,
 496         .remove         = __devexit_p(synclinkmp_remove_one),
 497 };
 498
 499
 500 static struct tty_driver *serial_driver;
 501
 502 /* number of characters left in xmit buffer before we ask for more */
 503 #define WAKEUP_CHARS 256
 504
 505
 506 /* tty callbacks */
 507
 508 static int  open(struct tty_struct *tty, struct file * filp);
 509 static void close(struct tty_struct *tty, struct file * filp);
 510 static void hangup(struct tty_struct *tty);
 511 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 512
 513 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 514 static int put_char(struct tty_struct *tty, unsigned char ch);
 515 static void send_xchar(struct tty_struct *tty, char ch);
 516 static void wait_until_sent(struct tty_struct *tty, int timeout);
 517 static int  write_room(struct tty_struct *tty);
 518 static void flush_chars(struct tty_struct *tty);
 519 static void flush_buffer(struct tty_struct *tty);
 520 static void tx_hold(struct tty_struct *tty);
 521 static void tx_release(struct tty_struct *tty);
 522
 523 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 524 static int  chars_in_buffer(struct tty_struct *tty);
 525 static void throttle(struct tty_struct * tty);
 526 static void unthrottle(struct tty_struct * tty);
 527 static int set_break(struct tty_struct *tty, int break_state);
 528
 529 #if SYNCLINK_GENERIC_HDLC
 530 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 531 static void hdlcdev_tx_done(SLMP_INFO *info);
 532 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
 533 static int  hdlcdev_init(SLMP_INFO *info);
 534 static void hdlcdev_exit(SLMP_INFO *info);
 535 #endif
 536
 537 /* ioctl handlers */
 538
 539 static int  get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
 540 static int  get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 541 static int  set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 542 static int  get_txidle(SLMP_INFO *info, int __user *idle_mode);
 543 static int  set_txidle(SLMP_INFO *info, int idle_mode);
 544 static int  tx_enable(SLMP_INFO *info, int enable);
 545 static int  tx_abort(SLMP_INFO *info);
 546 static int  rx_enable(SLMP_INFO *info, int enable);
 547 static int  modem_input_wait(SLMP_INFO *info,int arg);
 548 static int  wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
 549 static int  tiocmget(struct tty_struct *tty, struct file *file);
 550 static int  tiocmset(struct tty_struct *tty, struct file *file,
 551                      unsigned int set, unsigned int clear);
 552 static int  set_break(struct tty_struct *tty, int break_state);
 553
 554 static void add_device(SLMP_INFO *info);
 555 static void device_init(int adapter_num, struct pci_dev *pdev);
 556 static int  claim_resources(SLMP_INFO *info);
 557 static void release_resources(SLMP_INFO *info);
 558
 559 static int  startup(SLMP_INFO *info);
 560 static int  block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
 561 static int carrier_raised(struct tty_port *port);
 562 static void shutdown(SLMP_INFO *info);
 563 static void program_hw(SLMP_INFO *info);
 564 static void change_params(SLMP_INFO *info);
 565
 566 static bool init_adapter(SLMP_INFO *info);
 567 static bool register_test(SLMP_INFO *info);
 568 static bool irq_test(SLMP_INFO *info);
 569 static bool loopback_test(SLMP_INFO *info);
 570 static int  adapter_test(SLMP_INFO *info);
 571 static bool memory_test(SLMP_INFO *info);
 572
 573 static void reset_adapter(SLMP_INFO *info);
 574 static void reset_port(SLMP_INFO *info);
 575 static void async_mode(SLMP_INFO *info);
 576 static void hdlc_mode(SLMP_INFO *info);
 577
 578 static void rx_stop(SLMP_INFO *info);
 579 static void rx_start(SLMP_INFO *info);
 580 static void rx_reset_buffers(SLMP_INFO *info);
 581 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
 582 static bool rx_get_frame(SLMP_INFO *info);
 583
 584 static void tx_start(SLMP_INFO *info);
 585 static void tx_stop(SLMP_INFO *info);
 586 static void tx_load_fifo(SLMP_INFO *info);
 587 static void tx_set_idle(SLMP_INFO *info);
 588 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
 589
 590 static void get_signals(SLMP_INFO *info);
 591 static void set_signals(SLMP_INFO *info);
 592 static void enable_loopback(SLMP_INFO *info, int enable);
 593 static void set_rate(SLMP_INFO *info, u32 data_rate);
 594
 595 static int  bh_action(SLMP_INFO *info);
 596 static void bh_handler(struct work_struct *work);
 597 static void bh_receive(SLMP_INFO *info);
 598 static void bh_transmit(SLMP_INFO *info);
 599 static void bh_status(SLMP_INFO *info);
 600 static void isr_timer(SLMP_INFO *info);
 601 static void isr_rxint(SLMP_INFO *info);
 602 static void isr_rxrdy(SLMP_INFO *info);
 603 static void isr_txint(SLMP_INFO *info);
 604 static void isr_txrdy(SLMP_INFO *info);
 605 static void isr_rxdmaok(SLMP_INFO *info);
 606 static void isr_rxdmaerror(SLMP_INFO *info);
 607 static void isr_txdmaok(SLMP_INFO *info);
 608 static void isr_txdmaerror(SLMP_INFO *info);
 609 static void isr_io_pin(SLMP_INFO *info, u16 status);
 610
 611 static int  alloc_dma_bufs(SLMP_INFO *info);
 612 static void free_dma_bufs(SLMP_INFO *info);
 613 static int  alloc_buf_list(SLMP_INFO *info);
 614 static int  alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
 615 static int  alloc_tmp_rx_buf(SLMP_INFO *info);
 616 static void free_tmp_rx_buf(SLMP_INFO *info);
 617
 618 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
 619 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
 620 static void tx_timeout(unsigned long context);
 621 static void status_timeout(unsigned long context);
 622
 623 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
 624 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
 625 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
 626 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
 627 static unsigned char read_status_reg(SLMP_INFO * info);
 628 static void write_control_reg(SLMP_INFO * info);
 629
 630
 631 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
 632 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
 633 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
 634
 635 static u32 misc_ctrl_value = 0x007e4040;
 636 static u32 lcr1_brdr_value = 0x00800028;
 637
 638 static u32 read_ahead_count = 8;
 639
 640 /* DPCR, DMA Priority Control
 641  *
 642  * 07..05  Not used, must be 0
 643  * 04      BRC, bus release condition: 0=all transfers complete
 644  *              1=release after 1 xfer on all channels
 645  * 03      CCC, channel change condition: 0=every cycle
 646  *              1=after each channel completes all xfers
 647  * 02..00  PR<2..0>, priority 100=round robin
 648  *
 649  * 00000100 = 0x00
 650  */
 651 static unsigned char dma_priority = 0x04;
 652
 653 // Number of bytes that can be written to shared RAM
 654 // in a single write operation
 655 static u32 sca_pci_load_interval = 64;
 656
 657 /*
 658  * 1st function defined in .text section. Calling this function in
 659  * init_module() followed by a breakpoint allows a remote debugger
 660  * (gdb) to get the .text address for the add-symbol-file command.
 661  * This allows remote debugging of dynamically loadable modules.
 662  */
 663 static void* synclinkmp_get_text_ptr(void);
 664 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
 665
 666 static inline int sanity_check(SLMP_INFO *info,
 667                                char *name, const char *routine)
 668 {
 669 #ifdef SANITY_CHECK
 670         static const char *badmagic =
 671                 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
 672         static const char *badinfo =
 673                 "Warning: null synclinkmp_struct for (%s) in %s\n";
 674
 675         if (!info) {
 676                 printk(badinfo, name, routine);
 677                 return 1;
 678         }
 679         if (info->magic != MGSL_MAGIC) {
 680                 printk(badmagic, name, routine);
 681                 return 1;
 682         }
 683 #else
 684         if (!info)
 685                 return 1;
 686 #endif
 687         return 0;
 688 }
 689
 690 /**
 691  * line discipline callback wrappers
 692  *
 693  * The wrappers maintain line discipline references
 694  * while calling into the line discipline.
 695  *
 696  * ldisc_receive_buf  - pass receive data to line discipline
 697  */
 698
 699 static void ldisc_receive_buf(struct tty_struct *tty,
 700                               const __u8 *data, char *flags, int count)
 701 {
 702         struct tty_ldisc *ld;
 703         if (!tty)
 704                 return;
 705         ld = tty_ldisc_ref(tty);
 706         if (ld) {
 707                 if (ld->ops->receive_buf)
 708                         ld->ops->receive_buf(tty, data, flags, count);
 709                 tty_ldisc_deref(ld);
 710         }
 711 }
 712
 713 /* tty callbacks */
 714
 715 /* Called when a port is opened.  Init and enable port.
 716  */
 717 static int open(struct tty_struct *tty, struct file *filp)
 718 {
 719         SLMP_INFO *info;
 720         int retval, line;
 721         unsigned long flags;
 722
 723         line = tty->index;
 724         if ((line < 0) || (line >= synclinkmp_device_count)) {
 725                 printk("%s(%d): open with invalid line #%d.\n",
 726                         __FILE__,__LINE__,line);
 727                 return -ENODEV;
 728         }
 729
 730         info = synclinkmp_device_list;
 731         while(info && info->line != line)
 732                 info = info->next_device;
 733         if (sanity_check(info, tty->name, "open"))
 734                 return -ENODEV;
 735         if ( info->init_error ) {
 736                 printk("%s(%d):%s device is not allocated, init error=%d\n",
 737                         __FILE__,__LINE__,info->device_name,info->init_error);
 738                 return -ENODEV;
 739         }
 740
 741         tty->driver_data = info;
 742         info->port.tty = tty;
 743
 744         if (debug_level >= DEBUG_LEVEL_INFO)
 745                 printk("%s(%d):%s open(), old ref count = %d\n",
 746                          __FILE__,__LINE__,tty->driver->name, info->port.count);
 747
 748         /* If port is closing, signal caller to try again */
 749         if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
 750                 if (info->port.flags & ASYNC_CLOSING)
 751                         interruptible_sleep_on(&info->port.close_wait);
 752                 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
 753                         -EAGAIN : -ERESTARTSYS);
 754                 goto cleanup;
 755         }
 756
 757         info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 758
 759         spin_lock_irqsave(&info->netlock, flags);
 760         if (info->netcount) {
 761                 retval = -EBUSY;
 762                 spin_unlock_irqrestore(&info->netlock, flags);
 763                 goto cleanup;
 764         }
 765         info->port.count++;
 766         spin_unlock_irqrestore(&info->netlock, flags);
 767
 768         if (info->port.count == 1) {
 769                 /* 1st open on this device, init hardware */
 770                 retval = startup(info);
 771                 if (retval < 0)
 772                         goto cleanup;
 773         }
 774
 775         retval = block_til_ready(tty, filp, info);
 776         if (retval) {
 777                 if (debug_level >= DEBUG_LEVEL_INFO)
 778                         printk("%s(%d):%s block_til_ready() returned %d\n",
 779                                  __FILE__,__LINE__, info->device_name, retval);
 780                 goto cleanup;
 781         }
 782
 783         if (debug_level >= DEBUG_LEVEL_INFO)
 784                 printk("%s(%d):%s open() success\n",
 785                          __FILE__,__LINE__, info->device_name);
 786         retval = 0;
 787
 788 cleanup:
 789         if (retval) {
 790                 if (tty->count == 1)
 791                         info->port.tty = NULL; /* tty layer will release tty struct */
 792                 if(info->port.count)
 793                         info->port.count--;
 794         }
 795
 796         return retval;
 797 }
 798
 799 /* Called when port is closed. Wait for remaining data to be
 800  * sent. Disable port and free resources.
 801  */
 802 static void close(struct tty_struct *tty, struct file *filp)
 803 {
 804         SLMP_INFO * info = tty->driver_data;
 805
 806         if (sanity_check(info, tty->name, "close"))
 807                 return;
 808
 809         if (debug_level >= DEBUG_LEVEL_INFO)
 810                 printk("%s(%d):%s close() entry, count=%d\n",
 811                          __FILE__,__LINE__, info->device_name, info->port.count);
 812
 813         if (tty_port_close_start(&info->port, tty, filp) == 0)
 814                 goto cleanup;
 815
 816         if (info->port.flags & ASYNC_INITIALIZED)
 817                 wait_until_sent(tty, info->timeout);
 818
 819         flush_buffer(tty);
 820         tty_ldisc_flush(tty);
 821         shutdown(info);
 822
 823         tty_port_close_end(&info->port, tty);
 824         info->port.tty = NULL;
 825 cleanup:
 826         if (debug_level >= DEBUG_LEVEL_INFO)
 827                 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
 828                         tty->driver->name, info->port.count);
 829 }
 830
 831 /* Called by tty_hangup() when a hangup is signaled.
 832  * This is the same as closing all open descriptors for the port.
 833  */
 834 static void hangup(struct tty_struct *tty)
 835 {
 836         SLMP_INFO *info = tty->driver_data;
 837
 838         if (debug_level >= DEBUG_LEVEL_INFO)
 839                 printk("%s(%d):%s hangup()\n",
 840                          __FILE__,__LINE__, info->device_name );
 841
 842         if (sanity_check(info, tty->name, "hangup"))
 843                 return;
 844
 845         flush_buffer(tty);
 846         shutdown(info);
 847
 848         info->port.count = 0;
 849         info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
 850         info->port.tty = NULL;
 851
 852         wake_up_interruptible(&info->port.open_wait);
 853 }
 854
 855 /* Set new termios settings
 856  */
 857 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 858 {
 859         SLMP_INFO *info = tty->driver_data;
 860         unsigned long flags;
 861
 862         if (debug_level >= DEBUG_LEVEL_INFO)
 863                 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
 864                         tty->driver->name );
 865
 866         change_params(info);
 867
 868         /* Handle transition to B0 status */
 869         if (old_termios->c_cflag & CBAUD &&
 870             !(tty->termios->c_cflag & CBAUD)) {
 871                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 872                 spin_lock_irqsave(&info->lock,flags);
 873                 set_signals(info);
 874                 spin_unlock_irqrestore(&info->lock,flags);
 875         }
 876
 877         /* Handle transition away from B0 status */
 878         if (!(old_termios->c_cflag & CBAUD) &&
 879             tty->termios->c_cflag & CBAUD) {
 880                 info->serial_signals |= SerialSignal_DTR;
 881                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 882                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 883                         info->serial_signals |= SerialSignal_RTS;
 884                 }
 885                 spin_lock_irqsave(&info->lock,flags);
 886                 set_signals(info);
 887                 spin_unlock_irqrestore(&info->lock,flags);
 888         }
 889
 890         /* Handle turning off CRTSCTS */
 891         if (old_termios->c_cflag & CRTSCTS &&
 892             !(tty->termios->c_cflag & CRTSCTS)) {
 893                 tty->hw_stopped = 0;
 894                 tx_release(tty);
 895         }
 896 }
 897
 898 /* Send a block of data
 899  *
 900  * Arguments:
 901  *
 902  *      tty             pointer to tty information structure
 903  *      buf             pointer to buffer containing send data
 904  *      count           size of send data in bytes
 905  *
 906  * Return Value:        number of characters written
 907  */
 908 static int write(struct tty_struct *tty,
 909                  const unsigned char *buf, int count)
 910 {
 911         int     c, ret = 0;
 912         SLMP_INFO *info = tty->driver_data;
 913         unsigned long flags;
 914
 915         if (debug_level >= DEBUG_LEVEL_INFO)
 916                 printk("%s(%d):%s write() count=%d\n",
 917                        __FILE__,__LINE__,info->device_name,count);
 918
 919         if (sanity_check(info, tty->name, "write"))
 920                 goto cleanup;
 921
 922         if (!info->tx_buf)
 923                 goto cleanup;
 924
 925         if (info->params.mode == MGSL_MODE_HDLC) {
 926                 if (count > info->max_frame_size) {
 927                         ret = -EIO;
 928                         goto cleanup;
 929                 }
 930                 if (info->tx_active)
 931                         goto cleanup;
 932                 if (info->tx_count) {
 933                         /* send accumulated data from send_char() calls */
 934                         /* as frame and wait before accepting more data. */
 935                         tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
 936                         goto start;
 937                 }
 938                 ret = info->tx_count = count;
 939                 tx_load_dma_buffer(info, buf, count);
 940                 goto start;
 941         }
 942
 943         for (;;) {
 944                 c = min_t(int, count,
 945                         min(info->max_frame_size - info->tx_count - 1,
 946                             info->max_frame_size - info->tx_put));
 947                 if (c <= 0)
 948                         break;
 949
 950                 memcpy(info->tx_buf + info->tx_put, buf, c);
 951
 952                 spin_lock_irqsave(&info->lock,flags);
 953                 info->tx_put += c;
 954                 if (info->tx_put >= info->max_frame_size)
 955                         info->tx_put -= info->max_frame_size;
 956                 info->tx_count += c;
 957                 spin_unlock_irqrestore(&info->lock,flags);
 958
 959                 buf += c;
 960                 count -= c;
 961                 ret += c;
 962         }
 963
 964         if (info->params.mode == MGSL_MODE_HDLC) {
 965                 if (count) {
 966                         ret = info->tx_count = 0;
 967                         goto cleanup;
 968                 }
 969                 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
 970         }
 971 start:
 972         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
 973                 spin_lock_irqsave(&info->lock,flags);
 974                 if (!info->tx_active)
 975                         tx_start(info);
 976                 spin_unlock_irqrestore(&info->lock,flags);
 977         }
 978
 979 cleanup:
 980         if (debug_level >= DEBUG_LEVEL_INFO)
 981                 printk( "%s(%d):%s write() returning=%d\n",
 982                         __FILE__,__LINE__,info->device_name,ret);
 983         return ret;
 984 }
 985
 986 /* Add a character to the transmit buffer.
 987  */
 988 static int put_char(struct tty_struct *tty, unsigned char ch)
 989 {
 990         SLMP_INFO *info = tty->driver_data;
 991         unsigned long flags;
 992         int ret = 0;
 993
 994         if ( debug_level >= DEBUG_LEVEL_INFO ) {
 995                 printk( "%s(%d):%s put_char(%d)\n",
 996                         __FILE__,__LINE__,info->device_name,ch);
 997         }
 998
 999         if (sanity_check(info, tty->name, "put_char"))
1000                 return 0;
1001
1002         if (!info->tx_buf)
1003                 return 0;
1004
1005         spin_lock_irqsave(&info->lock,flags);
1006
1007         if ( (info->params.mode != MGSL_MODE_HDLC) ||
1008              !info->tx_active ) {
1009
1010                 if (info->tx_count < info->max_frame_size - 1) {
1011                         info->tx_buf[info->tx_put++] = ch;
1012                         if (info->tx_put >= info->max_frame_size)
1013                                 info->tx_put -= info->max_frame_size;
1014                         info->tx_count++;
1015                         ret = 1;
1016                 }
1017         }
1018
1019         spin_unlock_irqrestore(&info->lock,flags);
1020         return ret;
1021 }
1022
1023 /* Send a high-priority XON/XOFF character
1024  */
1025 static void send_xchar(struct tty_struct *tty, char ch)
1026 {
1027         SLMP_INFO *info = tty->driver_data;
1028         unsigned long flags;
1029
1030         if (debug_level >= DEBUG_LEVEL_INFO)
1031                 printk("%s(%d):%s send_xchar(%d)\n",
1032                          __FILE__,__LINE__, info->device_name, ch );
1033
1034         if (sanity_check(info, tty->name, "send_xchar"))
1035                 return;
1036
1037         info->x_char = ch;
1038         if (ch) {
1039                 /* Make sure transmit interrupts are on */
1040                 spin_lock_irqsave(&info->lock,flags);
1041                 if (!info->tx_enabled)
1042                         tx_start(info);
1043                 spin_unlock_irqrestore(&info->lock,flags);
1044         }
1045 }
1046
1047 /* Wait until the transmitter is empty.
1048  */
1049 static void wait_until_sent(struct tty_struct *tty, int timeout)
1050 {
1051         SLMP_INFO * info = tty->driver_data;
1052         unsigned long orig_jiffies, char_time;
1053
1054         if (!info )
1055                 return;
1056
1057         if (debug_level >= DEBUG_LEVEL_INFO)
1058                 printk("%s(%d):%s wait_until_sent() entry\n",
1059                          __FILE__,__LINE__, info->device_name );
1060
1061         if (sanity_check(info, tty->name, "wait_until_sent"))
1062                 return;
1063
1064         lock_kernel();
1065
1066         if (!(info->port.flags & ASYNC_INITIALIZED))
1067                 goto exit;
1068
1069         orig_jiffies = jiffies;
1070
1071         /* Set check interval to 1/5 of estimated time to
1072          * send a character, and make it at least 1. The check
1073          * interval should also be less than the timeout.
1074          * Note: use tight timings here to satisfy the NIST-PCTS.
1075          */
1076
1077         if ( info->params.data_rate ) {
1078                 char_time = info->timeout/(32 * 5);
1079                 if (!char_time)
1080                         char_time++;
1081         } else
1082                 char_time = 1;
1083
1084         if (timeout)
1085                 char_time = min_t(unsigned long, char_time, timeout);
1086
1087         if ( info->params.mode == MGSL_MODE_HDLC ) {
1088                 while (info->tx_active) {
1089                         msleep_interruptible(jiffies_to_msecs(char_time));
1090                         if (signal_pending(current))
1091                                 break;
1092                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1093                                 break;
1094                 }
1095         } else {
1096                 //TODO: determine if there is something similar to USC16C32
1097                 //      TXSTATUS_ALL_SENT status
1098                 while ( info->tx_active && info->tx_enabled) {
1099                         msleep_interruptible(jiffies_to_msecs(char_time));
1100                         if (signal_pending(current))
1101                                 break;
1102                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1103                                 break;
1104                 }
1105         }
1106
1107 exit:
1108         unlock_kernel();
1109         if (debug_level >= DEBUG_LEVEL_INFO)
1110                 printk("%s(%d):%s wait_until_sent() exit\n",
1111                          __FILE__,__LINE__, info->device_name );
1112 }
1113
1114 /* Return the count of free bytes in transmit buffer
1115  */
1116 static int write_room(struct tty_struct *tty)
1117 {
1118         SLMP_INFO *info = tty->driver_data;
1119         int ret;
1120
1121         if (sanity_check(info, tty->name, "write_room"))
1122                 return 0;
1123
1124         lock_kernel();
1125         if (info->params.mode == MGSL_MODE_HDLC) {
1126                 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1127         } else {
1128                 ret = info->max_frame_size - info->tx_count - 1;
1129                 if (ret < 0)
1130                         ret = 0;
1131         }
1132         unlock_kernel();
1133
1134         if (debug_level >= DEBUG_LEVEL_INFO)
1135                 printk("%s(%d):%s write_room()=%d\n",
1136                        __FILE__, __LINE__, info->device_name, ret);
1137
1138         return ret;
1139 }
1140
1141 /* enable transmitter and send remaining buffered characters
1142  */
1143 static void flush_chars(struct tty_struct *tty)
1144 {
1145         SLMP_INFO *info = tty->driver_data;
1146         unsigned long flags;
1147
1148         if ( debug_level >= DEBUG_LEVEL_INFO )
1149                 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1150                         __FILE__,__LINE__,info->device_name,info->tx_count);
1151
1152         if (sanity_check(info, tty->name, "flush_chars"))
1153                 return;
1154
1155         if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1156             !info->tx_buf)
1157                 return;
1158
1159         if ( debug_level >= DEBUG_LEVEL_INFO )
1160                 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1161                         __FILE__,__LINE__,info->device_name );
1162
1163         spin_lock_irqsave(&info->lock,flags);
1164
1165         if (!info->tx_active) {
1166                 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1167                         info->tx_count ) {
1168                         /* operating in synchronous (frame oriented) mode */
1169                         /* copy data from circular tx_buf to */
1170                         /* transmit DMA buffer. */
1171                         tx_load_dma_buffer(info,
1172                                  info->tx_buf,info->tx_count);
1173                 }
1174                 tx_start(info);
1175         }
1176
1177         spin_unlock_irqrestore(&info->lock,flags);
1178 }
1179
1180 /* Discard all data in the send buffer
1181  */
1182 static void flush_buffer(struct tty_struct *tty)
1183 {
1184         SLMP_INFO *info = tty->driver_data;
1185         unsigned long flags;
1186
1187         if (debug_level >= DEBUG_LEVEL_INFO)
1188                 printk("%s(%d):%s flush_buffer() entry\n",
1189                          __FILE__,__LINE__, info->device_name );
1190
1191         if (sanity_check(info, tty->name, "flush_buffer"))
1192                 return;
1193
1194         spin_lock_irqsave(&info->lock,flags);
1195         info->tx_count = info->tx_put = info->tx_get = 0;
1196         del_timer(&info->tx_timer);
1197         spin_unlock_irqrestore(&info->lock,flags);
1198
1199         tty_wakeup(tty);
1200 }
1201
1202 /* throttle (stop) transmitter
1203  */
1204 static void tx_hold(struct tty_struct *tty)
1205 {
1206         SLMP_INFO *info = tty->driver_data;
1207         unsigned long flags;
1208
1209         if (sanity_check(info, tty->name, "tx_hold"))
1210                 return;
1211
1212         if ( debug_level >= DEBUG_LEVEL_INFO )
1213                 printk("%s(%d):%s tx_hold()\n",
1214                         __FILE__,__LINE__,info->device_name);
1215
1216         spin_lock_irqsave(&info->lock,flags);
1217         if (info->tx_enabled)
1218                 tx_stop(info);
1219         spin_unlock_irqrestore(&info->lock,flags);
1220 }
1221
1222 /* release (start) transmitter
1223  */
1224 static void tx_release(struct tty_struct *tty)
1225 {
1226         SLMP_INFO *info = tty->driver_data;
1227         unsigned long flags;
1228
1229         if (sanity_check(info, tty->name, "tx_release"))
1230                 return;
1231
1232         if ( debug_level >= DEBUG_LEVEL_INFO )
1233                 printk("%s(%d):%s tx_release()\n",
1234                         __FILE__,__LINE__,info->device_name);
1235
1236         spin_lock_irqsave(&info->lock,flags);
1237         if (!info->tx_enabled)
1238                 tx_start(info);
1239         spin_unlock_irqrestore(&info->lock,flags);
1240 }
1241
1242 /* Service an IOCTL request
1243  *
1244  * Arguments:
1245  *
1246  *      tty     pointer to tty instance data
1247  *      file    pointer to associated file object for device
1248  *      cmd     IOCTL command code
1249  *      arg     command argument/context
1250  *
1251  * Return Value:        0 if success, otherwise error code
1252  */
1253 static int do_ioctl(struct tty_struct *tty, struct file *file,
1254                  unsigned int cmd, unsigned long arg)
1255 {
1256         SLMP_INFO *info = tty->driver_data;
1257         int error;
1258         struct mgsl_icount cnow;        /* kernel counter temps */
1259         struct serial_icounter_struct __user *p_cuser;  /* user space */
1260         unsigned long flags;
1261         void __user *argp = (void __user *)arg;
1262
1263         if (debug_level >= DEBUG_LEVEL_INFO)
1264                 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1265                         info->device_name, cmd );
1266
1267         if (sanity_check(info, tty->name, "ioctl"))
1268                 return -ENODEV;
1269
1270         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1271             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1272                 if (tty->flags & (1 << TTY_IO_ERROR))
1273                     return -EIO;
1274         }
1275
1276         switch (cmd) {
1277         case MGSL_IOCGPARAMS:
1278                 return get_params(info, argp);
1279         case MGSL_IOCSPARAMS:
1280                 return set_params(info, argp);
1281         case MGSL_IOCGTXIDLE:
1282                 return get_txidle(info, argp);
1283         case MGSL_IOCSTXIDLE:
1284                 return set_txidle(info, (int)arg);
1285         case MGSL_IOCTXENABLE:
1286                 return tx_enable(info, (int)arg);
1287         case MGSL_IOCRXENABLE:
1288                 return rx_enable(info, (int)arg);
1289         case MGSL_IOCTXABORT:
1290                 return tx_abort(info);
1291         case MGSL_IOCGSTATS:
1292                 return get_stats(info, argp);
1293         case MGSL_IOCWAITEVENT:
1294                 return wait_mgsl_event(info, argp);
1295         case MGSL_IOCLOOPTXDONE:
1296                 return 0; // TODO: Not supported, need to document
1297                 /* Wait for modem input (DCD,RI,DSR,CTS) change
1298                  * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1299                  */
1300         case TIOCMIWAIT:
1301                 return modem_input_wait(info,(int)arg);
1302
1303                 /*
1304                  * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1305                  * Return: write counters to the user passed counter struct
1306                  * NB: both 1->0 and 0->1 transitions are counted except for
1307                  *     RI where only 0->1 is counted.
1308                  */
1309         case TIOCGICOUNT:
1310                 spin_lock_irqsave(&info->lock,flags);
1311                 cnow = info->icount;
1312                 spin_unlock_irqrestore(&info->lock,flags);
1313                 p_cuser = argp;
1314                 PUT_USER(error,cnow.cts, &p_cuser->cts);
1315                 if (error) return error;
1316                 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1317                 if (error) return error;
1318                 PUT_USER(error,cnow.rng, &p_cuser->rng);
1319                 if (error) return error;
1320                 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1321                 if (error) return error;
1322                 PUT_USER(error,cnow.rx, &p_cuser->rx);
1323                 if (error) return error;
1324                 PUT_USER(error,cnow.tx, &p_cuser->tx);
1325                 if (error) return error;
1326                 PUT_USER(error,cnow.frame, &p_cuser->frame);
1327                 if (error) return error;
1328                 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1329                 if (error) return error;
1330                 PUT_USER(error,cnow.parity, &p_cuser->parity);
1331                 if (error) return error;
1332                 PUT_USER(error,cnow.brk, &p_cuser->brk);
1333                 if (error) return error;
1334                 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1335                 if (error) return error;
1336                 return 0;
1337         default:
1338                 return -ENOIOCTLCMD;
1339         }
1340         return 0;
1341 }
1342
1343 static int ioctl(struct tty_struct *tty, struct file *file,
1344                  unsigned int cmd, unsigned long arg)
1345 {
1346         int ret;
1347         lock_kernel();
1348         ret = do_ioctl(tty, file, cmd, arg);
1349         unlock_kernel();
1350         return ret;
1351 }
1352
1353 /*
1354  * /proc fs routines....
1355  */
1356
1357 static inline void line_info(struct seq_file *m, SLMP_INFO *info)
1358 {
1359         char    stat_buf[30];
1360         unsigned long flags;
1361
1362         seq_printf(m, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1363                        "\tIRQ=%d MaxFrameSize=%u\n",
1364                 info->device_name,
1365                 info->phys_sca_base,
1366                 info->phys_memory_base,
1367                 info->phys_statctrl_base,
1368                 info->phys_lcr_base,
1369                 info->irq_level,
1370                 info->max_frame_size );
1371
1372         /* output current serial signal states */
1373         spin_lock_irqsave(&info->lock,flags);
1374         get_signals(info);
1375         spin_unlock_irqrestore(&info->lock,flags);
1376
1377         stat_buf[0] = 0;
1378         stat_buf[1] = 0;
1379         if (info->serial_signals & SerialSignal_RTS)
1380                 strcat(stat_buf, "|RTS");
1381         if (info->serial_signals & SerialSignal_CTS)
1382                 strcat(stat_buf, "|CTS");
1383         if (info->serial_signals & SerialSignal_DTR)
1384                 strcat(stat_buf, "|DTR");
1385         if (info->serial_signals & SerialSignal_DSR)
1386                 strcat(stat_buf, "|DSR");
1387         if (info->serial_signals & SerialSignal_DCD)
1388                 strcat(stat_buf, "|CD");
1389         if (info->serial_signals & SerialSignal_RI)
1390                 strcat(stat_buf, "|RI");
1391
1392         if (info->params.mode == MGSL_MODE_HDLC) {
1393                 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1394                               info->icount.txok, info->icount.rxok);
1395                 if (info->icount.txunder)
1396                         seq_printf(m, " txunder:%d", info->icount.txunder);
1397                 if (info->icount.txabort)
1398                         seq_printf(m, " txabort:%d", info->icount.txabort);
1399                 if (info->icount.rxshort)
1400                         seq_printf(m, " rxshort:%d", info->icount.rxshort);
1401                 if (info->icount.rxlong)
1402                         seq_printf(m, " rxlong:%d", info->icount.rxlong);
1403                 if (info->icount.rxover)
1404                         seq_printf(m, " rxover:%d", info->icount.rxover);
1405                 if (info->icount.rxcrc)
1406                         seq_printf(m, " rxlong:%d", info->icount.rxcrc);
1407         } else {
1408                 seq_printf(m, "\tASYNC tx:%d rx:%d",
1409                               info->icount.tx, info->icount.rx);
1410                 if (info->icount.frame)
1411                         seq_printf(m, " fe:%d", info->icount.frame);
1412                 if (info->icount.parity)
1413                         seq_printf(m, " pe:%d", info->icount.parity);
1414                 if (info->icount.brk)
1415                         seq_printf(m, " brk:%d", info->icount.brk);
1416                 if (info->icount.overrun)
1417                         seq_printf(m, " oe:%d", info->icount.overrun);
1418         }
1419
1420         /* Append serial signal status to end */
1421         seq_printf(m, " %s\n", stat_buf+1);
1422
1423         seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1424          info->tx_active,info->bh_requested,info->bh_running,
1425          info->pending_bh);
1426 }
1427
1428 /* Called to print information about devices
1429  */
1430 static int synclinkmp_proc_show(struct seq_file *m, void *v)
1431 {
1432         SLMP_INFO *info;
1433
1434         seq_printf(m, "synclinkmp driver:%s\n", driver_version);
1435
1436         info = synclinkmp_device_list;
1437         while( info ) {
1438                 line_info(m, info);
1439                 info = info->next_device;
1440         }
1441         return 0;
1442 }
1443
1444 static int synclinkmp_proc_open(struct inode *inode, struct file *file)
1445 {
1446         return single_open(file, synclinkmp_proc_show, NULL);
1447 }
1448
1449 static const struct file_operations synclinkmp_proc_fops = {
1450         .owner          = THIS_MODULE,
1451         .open           = synclinkmp_proc_open,
1452         .read           = seq_read,
1453         .llseek         = seq_lseek,
1454         .release        = single_release,
1455 };
1456
1457 /* Return the count of bytes in transmit buffer
1458  */
1459 static int chars_in_buffer(struct tty_struct *tty)
1460 {
1461         SLMP_INFO *info = tty->driver_data;
1462
1463         if (sanity_check(info, tty->name, "chars_in_buffer"))
1464                 return 0;
1465
1466         if (debug_level >= DEBUG_LEVEL_INFO)
1467                 printk("%s(%d):%s chars_in_buffer()=%d\n",
1468                        __FILE__, __LINE__, info->device_name, info->tx_count);
1469
1470         return info->tx_count;
1471 }
1472
1473 /* Signal remote device to throttle send data (our receive data)
1474  */
1475 static void throttle(struct tty_struct * tty)
1476 {
1477         SLMP_INFO *info = tty->driver_data;
1478         unsigned long flags;
1479
1480         if (debug_level >= DEBUG_LEVEL_INFO)
1481                 printk("%s(%d):%s throttle() entry\n",
1482                          __FILE__,__LINE__, info->device_name );
1483
1484         if (sanity_check(info, tty->name, "throttle"))
1485                 return;
1486
1487         if (I_IXOFF(tty))
1488                 send_xchar(tty, STOP_CHAR(tty));
1489
1490         if (tty->termios->c_cflag & CRTSCTS) {
1491                 spin_lock_irqsave(&info->lock,flags);
1492                 info->serial_signals &= ~SerialSignal_RTS;
1493                 set_signals(info);
1494                 spin_unlock_irqrestore(&info->lock,flags);
1495         }
1496 }
1497
1498 /* Signal remote device to stop throttling send data (our receive data)
1499  */
1500 static void unthrottle(struct tty_struct * tty)
1501 {
1502         SLMP_INFO *info = tty->driver_data;
1503         unsigned long flags;
1504
1505         if (debug_level >= DEBUG_LEVEL_INFO)
1506                 printk("%s(%d):%s unthrottle() entry\n",
1507                          __FILE__,__LINE__, info->device_name );
1508
1509         if (sanity_check(info, tty->name, "unthrottle"))
1510                 return;
1511
1512         if (I_IXOFF(tty)) {
1513                 if (info->x_char)
1514                         info->x_char = 0;
1515                 else
1516                         send_xchar(tty, START_CHAR(tty));
1517         }
1518
1519         if (tty->termios->c_cflag & CRTSCTS) {
1520                 spin_lock_irqsave(&info->lock,flags);
1521                 info->serial_signals |= SerialSignal_RTS;
1522                 set_signals(info);
1523                 spin_unlock_irqrestore(&info->lock,flags);
1524         }
1525 }
1526
1527 /* set or clear transmit break condition
1528  * break_state  -1=set break condition, 0=clear
1529  */
1530 static int set_break(struct tty_struct *tty, int break_state)
1531 {
1532         unsigned char RegValue;
1533         SLMP_INFO * info = tty->driver_data;
1534         unsigned long flags;
1535
1536         if (debug_level >= DEBUG_LEVEL_INFO)
1537                 printk("%s(%d):%s set_break(%d)\n",
1538                          __FILE__,__LINE__, info->device_name, break_state);
1539
1540         if (sanity_check(info, tty->name, "set_break"))
1541                 return -EINVAL;
1542
1543         spin_lock_irqsave(&info->lock,flags);
1544         RegValue = read_reg(info, CTL);
1545         if (break_state == -1)
1546                 RegValue |= BIT3;
1547         else
1548                 RegValue &= ~BIT3;
1549         write_reg(info, CTL, RegValue);
1550         spin_unlock_irqrestore(&info->lock,flags);
1551         return 0;
1552 }
1553
1554 #if SYNCLINK_GENERIC_HDLC
1555
1556 /**
1557  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1558  * set encoding and frame check sequence (FCS) options
1559  *
1560  * dev       pointer to network device structure
1561  * encoding  serial encoding setting
1562  * parity    FCS setting
1563  *
1564  * returns 0 if success, otherwise error code
1565  */
1566 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1567                           unsigned short parity)
1568 {
1569         SLMP_INFO *info = dev_to_port(dev);
1570         unsigned char  new_encoding;
1571         unsigned short new_crctype;
1572
1573         /* return error if TTY interface open */
1574         if (info->port.count)
1575                 return -EBUSY;
1576
1577         switch (encoding)
1578         {
1579         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1580         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1581         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1582         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1583         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1584         default: return -EINVAL;
1585         }
1586
1587         switch (parity)
1588         {
1589         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1590         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1591         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1592         default: return -EINVAL;
1593         }
1594
1595         info->params.encoding = new_encoding;
1596         info->params.crc_type = new_crctype;
1597
1598         /* if network interface up, reprogram hardware */
1599         if (info->netcount)
1600                 program_hw(info);
1601
1602         return 0;
1603 }
1604
1605 /**
1606  * called by generic HDLC layer to send frame
1607  *
1608  * skb  socket buffer containing HDLC frame
1609  * dev  pointer to network device structure
1610  *
1611  * returns 0 if success, otherwise error code
1612  */
1613 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1614 {
1615         SLMP_INFO *info = dev_to_port(dev);
1616         unsigned long flags;
1617
1618         if (debug_level >= DEBUG_LEVEL_INFO)
1619                 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1620
1621         /* stop sending until this frame completes */
1622         netif_stop_queue(dev);
1623
1624         /* copy data to device buffers */
1625         info->tx_count = skb->len;
1626         tx_load_dma_buffer(info, skb->data, skb->len);
1627
1628         /* update network statistics */
1629         dev->stats.tx_packets++;
1630         dev->stats.tx_bytes += skb->len;
1631
1632         /* done with socket buffer, so free it */
1633         dev_kfree_skb(skb);
1634
1635         /* save start time for transmit timeout detection */
1636         dev->trans_start = jiffies;
1637
1638         /* start hardware transmitter if necessary */
1639         spin_lock_irqsave(&info->lock,flags);
1640         if (!info->tx_active)
1641                 tx_start(info);
1642         spin_unlock_irqrestore(&info->lock,flags);
1643
1644         return 0;
1645 }
1646
1647 /**
1648  * called by network layer when interface enabled
1649  * claim resources and initialize hardware
1650  *
1651  * dev  pointer to network device structure
1652  *
1653  * returns 0 if success, otherwise error code
1654  */
1655 static int hdlcdev_open(struct net_device *dev)
1656 {
1657         SLMP_INFO *info = dev_to_port(dev);
1658         int rc;
1659         unsigned long flags;
1660
1661         if (debug_level >= DEBUG_LEVEL_INFO)
1662                 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1663
1664         /* generic HDLC layer open processing */
1665         if ((rc = hdlc_open(dev)))
1666                 return rc;
1667
1668         /* arbitrate between network and tty opens */
1669         spin_lock_irqsave(&info->netlock, flags);
1670         if (info->port.count != 0 || info->netcount != 0) {
1671                 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1672                 spin_unlock_irqrestore(&info->netlock, flags);
1673                 return -EBUSY;
1674         }
1675         info->netcount=1;
1676         spin_unlock_irqrestore(&info->netlock, flags);
1677
1678         /* claim resources and init adapter */
1679         if ((rc = startup(info)) != 0) {
1680                 spin_lock_irqsave(&info->netlock, flags);
1681                 info->netcount=0;
1682                 spin_unlock_irqrestore(&info->netlock, flags);
1683                 return rc;
1684         }
1685
1686         /* assert DTR and RTS, apply hardware settings */
1687         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1688         program_hw(info);
1689
1690         /* enable network layer transmit */
1691         dev->trans_start = jiffies;
1692         netif_start_queue(dev);
1693
1694         /* inform generic HDLC layer of current DCD status */
1695         spin_lock_irqsave(&info->lock, flags);
1696         get_signals(info);
1697         spin_unlock_irqrestore(&info->lock, flags);
1698         if (info->serial_signals & SerialSignal_DCD)
1699                 netif_carrier_on(dev);
1700         else
1701                 netif_carrier_off(dev);
1702         return 0;
1703 }
1704
1705 /**
1706  * called by network layer when interface is disabled
1707  * shutdown hardware and release resources
1708  *
1709  * dev  pointer to network device structure
1710  *
1711  * returns 0 if success, otherwise error code
1712  */
1713 static int hdlcdev_close(struct net_device *dev)
1714 {
1715         SLMP_INFO *info = dev_to_port(dev);
1716         unsigned long flags;
1717
1718         if (debug_level >= DEBUG_LEVEL_INFO)
1719                 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1720
1721         netif_stop_queue(dev);
1722
1723         /* shutdown adapter and release resources */
1724         shutdown(info);
1725
1726         hdlc_close(dev);
1727
1728         spin_lock_irqsave(&info->netlock, flags);
1729         info->netcount=0;
1730         spin_unlock_irqrestore(&info->netlock, flags);
1731
1732         return 0;
1733 }
1734
1735 /**
1736  * called by network layer to process IOCTL call to network device
1737  *
1738  * dev  pointer to network device structure
1739  * ifr  pointer to network interface request structure
1740  * cmd  IOCTL command code
1741  *
1742  * returns 0 if success, otherwise error code
1743  */
1744 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1745 {
1746         const size_t size = sizeof(sync_serial_settings);
1747         sync_serial_settings new_line;
1748         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1749         SLMP_INFO *info = dev_to_port(dev);
1750         unsigned int flags;
1751
1752         if (debug_level >= DEBUG_LEVEL_INFO)
1753                 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1754
1755         /* return error if TTY interface open */
1756         if (info->port.count)
1757                 return -EBUSY;
1758
1759         if (cmd != SIOCWANDEV)
1760                 return hdlc_ioctl(dev, ifr, cmd);
1761
1762         switch(ifr->ifr_settings.type) {
1763         case IF_GET_IFACE: /* return current sync_serial_settings */
1764
1765                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1766                 if (ifr->ifr_settings.size < size) {
1767                         ifr->ifr_settings.size = size; /* data size wanted */
1768                         return -ENOBUFS;
1769                 }
1770
1771                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1772                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1773                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1774                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1775
1776                 switch (flags){
1777                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1778                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1779                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1780                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1781                 default: new_line.clock_type = CLOCK_DEFAULT;
1782                 }
1783
1784                 new_line.clock_rate = info->params.clock_speed;
1785                 new_line.loopback   = info->params.loopback ? 1:0;
1786
1787                 if (copy_to_user(line, &new_line, size))
1788                         return -EFAULT;
1789                 return 0;
1790
1791         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1792
1793                 if(!capable(CAP_NET_ADMIN))
1794                         return -EPERM;
1795                 if (copy_from_user(&new_line, line, size))
1796                         return -EFAULT;
1797
1798                 switch (new_line.clock_type)
1799                 {
1800                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1801                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1802                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1803                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1804                 case CLOCK_DEFAULT:  flags = info->params.flags &
1805                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1806                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1807                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1808                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1809                 default: return -EINVAL;
1810                 }
1811
1812                 if (new_line.loopback != 0 && new_line.loopback != 1)
1813                         return -EINVAL;
1814
1815                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1816                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1817                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1818                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1819                 info->params.flags |= flags;
1820
1821                 info->params.loopback = new_line.loopback;
1822
1823                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1824                         info->params.clock_speed = new_line.clock_rate;
1825                 else
1826                         info->params.clock_speed = 0;
1827
1828                 /* if network interface up, reprogram hardware */
1829                 if (info->netcount)
1830                         program_hw(info);
1831                 return 0;
1832
1833         default:
1834                 return hdlc_ioctl(dev, ifr, cmd);
1835         }
1836 }
1837
1838 /**
1839  * called by network layer when transmit timeout is detected
1840  *
1841  * dev  pointer to network device structure
1842  */
1843 static void hdlcdev_tx_timeout(struct net_device *dev)
1844 {
1845         SLMP_INFO *info = dev_to_port(dev);
1846         unsigned long flags;
1847
1848         if (debug_level >= DEBUG_LEVEL_INFO)
1849                 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1850
1851         dev->stats.tx_errors++;
1852         dev->stats.tx_aborted_errors++;
1853
1854         spin_lock_irqsave(&info->lock,flags);
1855         tx_stop(info);
1856         spin_unlock_irqrestore(&info->lock,flags);
1857
1858         netif_wake_queue(dev);
1859 }
1860
1861 /**
1862  * called by device driver when transmit completes
1863  * reenable network layer transmit if stopped
1864  *
1865  * info  pointer to device instance information
1866  */
1867 static void hdlcdev_tx_done(SLMP_INFO *info)
1868 {
1869         if (netif_queue_stopped(info->netdev))
1870                 netif_wake_queue(info->netdev);
1871 }
1872
1873 /**
1874  * called by device driver when frame received
1875  * pass frame to network layer
1876  *
1877  * info  pointer to device instance information
1878  * buf   pointer to buffer contianing frame data
1879  * size  count of data bytes in buf
1880  */
1881 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1882 {
1883         struct sk_buff *skb = dev_alloc_skb(size);
1884         struct net_device *dev = info->netdev;
1885
1886         if (debug_level >= DEBUG_LEVEL_INFO)
1887                 printk("hdlcdev_rx(%s)\n",dev->name);
1888
1889         if (skb == NULL) {
1890                 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1891                        dev->name);
1892                 dev->stats.rx_dropped++;
1893                 return;
1894         }
1895
1896         memcpy(skb_put(skb, size), buf, size);
1897
1898         skb->protocol = hdlc_type_trans(skb, dev);
1899
1900         dev->stats.rx_packets++;
1901         dev->stats.rx_bytes += size;
1902
1903         netif_rx(skb);
1904 }
1905
1906 static const struct net_device_ops hdlcdev_ops = {
1907         .ndo_open       = hdlcdev_open,
1908         .ndo_stop       = hdlcdev_close,
1909         .ndo_change_mtu = hdlc_change_mtu,
1910         .ndo_start_xmit = hdlc_start_xmit,
1911         .ndo_do_ioctl   = hdlcdev_ioctl,
1912         .ndo_tx_timeout = hdlcdev_tx_timeout,
1913 };
1914
1915 /**
1916  * called by device driver when adding device instance
1917  * do generic HDLC initialization
1918  *
1919  * info  pointer to device instance information
1920  *
1921  * returns 0 if success, otherwise error code
1922  */
1923 static int hdlcdev_init(SLMP_INFO *info)
1924 {
1925         int rc;
1926         struct net_device *dev;
1927         hdlc_device *hdlc;
1928
1929         /* allocate and initialize network and HDLC layer objects */
1930
1931         if (!(dev = alloc_hdlcdev(info))) {
1932                 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1933                 return -ENOMEM;
1934         }
1935
1936         /* for network layer reporting purposes only */
1937         dev->mem_start = info->phys_sca_base;
1938         dev->mem_end   = info->phys_sca_base + SCA_BASE_SIZE - 1;
1939         dev->irq       = info->irq_level;
1940
1941         /* network layer callbacks and settings */
1942         dev->netdev_ops     = &hdlcdev_ops;
1943         dev->watchdog_timeo = 10 * HZ;
1944         dev->tx_queue_len   = 50;
1945
1946         /* generic HDLC layer callbacks and settings */
1947         hdlc         = dev_to_hdlc(dev);
1948         hdlc->attach = hdlcdev_attach;
1949         hdlc->xmit   = hdlcdev_xmit;
1950
1951         /* register objects with HDLC layer */
1952         if ((rc = register_hdlc_device(dev))) {
1953                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1954                 free_netdev(dev);
1955                 return rc;
1956         }
1957
1958         info->netdev = dev;
1959         return 0;
1960 }
1961
1962 /**
1963  * called by device driver when removing device instance
1964  * do generic HDLC cleanup
1965  *
1966  * info  pointer to device instance information
1967  */
1968 static void hdlcdev_exit(SLMP_INFO *info)
1969 {
1970         unregister_hdlc_device(info->netdev);
1971         free_netdev(info->netdev);
1972         info->netdev = NULL;
1973 }
1974
1975 #endif /* CONFIG_HDLC */
1976
1977
1978 /* Return next bottom half action to perform.
1979  * Return Value:        BH action code or 0 if nothing to do.
1980  */
1981 static int bh_action(SLMP_INFO *info)
1982 {
1983         unsigned long flags;
1984         int rc = 0;
1985
1986         spin_lock_irqsave(&info->lock,flags);
1987
1988         if (info->pending_bh & BH_RECEIVE) {
1989                 info->pending_bh &= ~BH_RECEIVE;
1990                 rc = BH_RECEIVE;
1991         } else if (info->pending_bh & BH_TRANSMIT) {
1992                 info->pending_bh &= ~BH_TRANSMIT;
1993                 rc = BH_TRANSMIT;
1994         } else if (info->pending_bh & BH_STATUS) {
1995                 info->pending_bh &= ~BH_STATUS;
1996                 rc = BH_STATUS;
1997         }
1998
1999         if (!rc) {
2000                 /* Mark BH routine as complete */
2001                 info->bh_running = false;
2002                 info->bh_requested = false;
2003         }
2004
2005         spin_unlock_irqrestore(&info->lock,flags);
2006
2007         return rc;
2008 }
2009
2010 /* Perform bottom half processing of work items queued by ISR.
2011  */
2012 static void bh_handler(struct work_struct *work)
2013 {
2014         SLMP_INFO *info = container_of(work, SLMP_INFO, task);
2015         int action;
2016
2017         if (!info)
2018                 return;
2019
2020         if ( debug_level >= DEBUG_LEVEL_BH )
2021                 printk( "%s(%d):%s bh_handler() entry\n",
2022                         __FILE__,__LINE__,info->device_name);
2023
2024         info->bh_running = true;
2025
2026         while((action = bh_action(info)) != 0) {
2027
2028                 /* Process work item */
2029                 if ( debug_level >= DEBUG_LEVEL_BH )
2030                         printk( "%s(%d):%s bh_handler() work item action=%d\n",
2031                                 __FILE__,__LINE__,info->device_name, action);
2032
2033                 switch (action) {
2034
2035                 case BH_RECEIVE:
2036                         bh_receive(info);
2037                         break;
2038                 case BH_TRANSMIT:
2039                         bh_transmit(info);
2040                         break;
2041                 case BH_STATUS:
2042                         bh_status(info);
2043                         break;
2044                 default:
2045                         /* unknown work item ID */
2046                         printk("%s(%d):%s Unknown work item ID=%08X!\n",
2047                                 __FILE__,__LINE__,info->device_name,action);
2048                         break;
2049                 }
2050         }
2051
2052         if ( debug_level >= DEBUG_LEVEL_BH )
2053                 printk( "%s(%d):%s bh_handler() exit\n",
2054                         __FILE__,__LINE__,info->device_name);
2055 }
2056
2057 static void bh_receive(SLMP_INFO *info)
2058 {
2059         if ( debug_level >= DEBUG_LEVEL_BH )
2060                 printk( "%s(%d):%s bh_receive()\n",
2061                         __FILE__,__LINE__,info->device_name);
2062
2063         while( rx_get_frame(info) );
2064 }
2065
2066 static void bh_transmit(SLMP_INFO *info)
2067 {
2068         struct tty_struct *tty = info->port.tty;
2069
2070         if ( debug_level >= DEBUG_LEVEL_BH )
2071                 printk( "%s(%d):%s bh_transmit() entry\n",
2072                         __FILE__,__LINE__,info->device_name);
2073
2074         if (tty)
2075                 tty_wakeup(tty);
2076 }
2077
2078 static void bh_status(SLMP_INFO *info)
2079 {
2080         if ( debug_level >= DEBUG_LEVEL_BH )
2081                 printk( "%s(%d):%s bh_status() entry\n",
2082                         __FILE__,__LINE__,info->device_name);
2083
2084         info->ri_chkcount = 0;
2085         info->dsr_chkcount = 0;
2086         info->dcd_chkcount = 0;
2087         info->cts_chkcount = 0;
2088 }
2089
2090 static void isr_timer(SLMP_INFO * info)
2091 {
2092         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2093
2094         /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2095         write_reg(info, IER2, 0);
2096
2097         /* TMCS, Timer Control/Status Register
2098          *
2099          * 07      CMF, Compare match flag (read only) 1=match
2100          * 06      ECMI, CMF Interrupt Enable: 0=disabled
2101          * 05      Reserved, must be 0
2102          * 04      TME, Timer Enable
2103          * 03..00  Reserved, must be 0
2104          *
2105          * 0000 0000
2106          */
2107         write_reg(info, (unsigned char)(timer + TMCS), 0);
2108
2109         info->irq_occurred = true;
2110
2111         if ( debug_level >= DEBUG_LEVEL_ISR )
2112                 printk("%s(%d):%s isr_timer()\n",
2113                         __FILE__,__LINE__,info->device_name);
2114 }
2115
2116 static void isr_rxint(SLMP_INFO * info)
2117 {
2118         struct tty_struct *tty = info->port.tty;
2119         struct  mgsl_icount *icount = &info->icount;
2120         unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2121         unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2122
2123         /* clear status bits */
2124         if (status)
2125                 write_reg(info, SR1, status);
2126
2127         if (status2)
2128                 write_reg(info, SR2, status2);
2129
2130         if ( debug_level >= DEBUG_LEVEL_ISR )
2131                 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2132                         __FILE__,__LINE__,info->device_name,status,status2);
2133
2134         if (info->params.mode == MGSL_MODE_ASYNC) {
2135                 if (status & BRKD) {
2136                         icount->brk++;
2137
2138                         /* process break detection if tty control
2139                          * is not set to ignore it
2140                          */
2141                         if ( tty ) {
2142                                 if (!(status & info->ignore_status_mask1)) {
2143                                         if (info->read_status_mask1 & BRKD) {
2144                                                 tty_insert_flip_char(tty, 0, TTY_BREAK);
2145                                                 if (info->port.flags & ASYNC_SAK)
2146                                                         do_SAK(tty);
2147                                         }
2148                                 }
2149                         }
2150                 }
2151         }
2152         else {
2153                 if (status & (FLGD|IDLD)) {
2154                         if (status & FLGD)
2155                                 info->icount.exithunt++;
2156                         else if (status & IDLD)
2157                                 info->icount.rxidle++;
2158                         wake_up_interruptible(&info->event_wait_q);
2159                 }
2160         }
2161
2162         if (status & CDCD) {
2163                 /* simulate a common modem status change interrupt
2164                  * for our handler
2165                  */
2166                 get_signals( info );
2167                 isr_io_pin(info,
2168                         MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2169         }
2170 }
2171
2172 /*
2173  * handle async rx data interrupts
2174  */
2175 static void isr_rxrdy(SLMP_INFO * info)
2176 {
2177         u16 status;
2178         unsigned char DataByte;
2179         struct tty_struct *tty = info->port.tty;
2180         struct  mgsl_icount *icount = &info->icount;
2181
2182         if ( debug_level >= DEBUG_LEVEL_ISR )
2183                 printk("%s(%d):%s isr_rxrdy\n",
2184                         __FILE__,__LINE__,info->device_name);
2185
2186         while((status = read_reg(info,CST0)) & BIT0)
2187         {
2188                 int flag = 0;
2189                 bool over = false;
2190                 DataByte = read_reg(info,TRB);
2191
2192                 icount->rx++;
2193
2194                 if ( status & (PE + FRME + OVRN) ) {
2195                         printk("%s(%d):%s rxerr=%04X\n",
2196                                 __FILE__,__LINE__,info->device_name,status);
2197
2198                         /* update error statistics */
2199                         if (status & PE)
2200                                 icount->parity++;
2201                         else if (status & FRME)
2202                                 icount->frame++;
2203                         else if (status & OVRN)
2204                                 icount->overrun++;
2205
2206                         /* discard char if tty control flags say so */
2207                         if (status & info->ignore_status_mask2)
2208                                 continue;
2209
2210                         status &= info->read_status_mask2;
2211
2212                         if ( tty ) {
2213                                 if (status & PE)
2214                                         flag = TTY_PARITY;
2215                                 else if (status & FRME)
2216                                         flag = TTY_FRAME;
2217                                 if (status & OVRN) {
2218                                         /* Overrun is special, since it's
2219                                          * reported immediately, and doesn't
2220                                          * affect the current character
2221                                          */
2222                                         over = true;
2223                                 }
2224                         }
2225                 }       /* end of if (error) */
2226
2227                 if ( tty ) {
2228                         tty_insert_flip_char(tty, DataByte, flag);
2229                         if (over)
2230                                 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
2231                 }
2232         }
2233
2234         if ( debug_level >= DEBUG_LEVEL_ISR ) {
2235                 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2236                         __FILE__,__LINE__,info->device_name,
2237                         icount->rx,icount->brk,icount->parity,
2238                         icount->frame,icount->overrun);
2239         }
2240
2241         if ( tty )
2242                 tty_flip_buffer_push(tty);
2243 }
2244
2245 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2246 {
2247         if ( debug_level >= DEBUG_LEVEL_ISR )
2248                 printk("%s(%d):%s isr_txeom status=%02x\n",
2249                         __FILE__,__LINE__,info->device_name,status);
2250
2251         write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2252         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2253         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2254
2255         if (status & UDRN) {
2256                 write_reg(info, CMD, TXRESET);
2257                 write_reg(info, CMD, TXENABLE);
2258         } else
2259                 write_reg(info, CMD, TXBUFCLR);
2260
2261         /* disable and clear tx interrupts */
2262         info->ie0_value &= ~TXRDYE;
2263         info->ie1_value &= ~(IDLE + UDRN);
2264         write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2265         write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2266
2267         if ( info->tx_active ) {
2268                 if (info->params.mode != MGSL_MODE_ASYNC) {
2269                         if (status & UDRN)
2270                                 info->icount.txunder++;
2271                         else if (status & IDLE)
2272                                 info->icount.txok++;
2273                 }
2274
2275                 info->tx_active = false;
2276                 info->tx_count = info->tx_put = info->tx_get = 0;
2277
2278                 del_timer(&info->tx_timer);
2279
2280                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2281                         info->serial_signals &= ~SerialSignal_RTS;
2282                         info->drop_rts_on_tx_done = false;
2283                         set_signals(info);
2284                 }
2285
2286 #if SYNCLINK_GENERIC_HDLC
2287                 if (info->netcount)
2288                         hdlcdev_tx_done(info);
2289                 else
2290 #endif
2291                 {
2292                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2293                                 tx_stop(info);
2294                                 return;
2295                         }
2296                         info->pending_bh |= BH_TRANSMIT;
2297                 }
2298         }
2299 }
2300
2301
2302 /*
2303  * handle tx status interrupts
2304  */
2305 static void isr_txint(SLMP_INFO * info)
2306 {
2307         unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2308
2309         /* clear status bits */
2310         write_reg(info, SR1, status);
2311
2312         if ( debug_level >= DEBUG_LEVEL_ISR )
2313                 printk("%s(%d):%s isr_txint status=%02x\n",
2314                         __FILE__,__LINE__,info->device_name,status);
2315
2316         if (status & (UDRN + IDLE))
2317                 isr_txeom(info, status);
2318
2319         if (status & CCTS) {
2320                 /* simulate a common modem status change interrupt
2321                  * for our handler
2322                  */
2323                 get_signals( info );
2324                 isr_io_pin(info,
2325                         MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2326
2327         }
2328 }
2329
2330 /*
2331  * handle async tx data interrupts
2332  */
2333 static void isr_txrdy(SLMP_INFO * info)
2334 {
2335         if ( debug_level >= DEBUG_LEVEL_ISR )
2336                 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2337                         __FILE__,__LINE__,info->device_name,info->tx_count);
2338
2339         if (info->params.mode != MGSL_MODE_ASYNC) {
2340                 /* disable TXRDY IRQ, enable IDLE IRQ */
2341                 info->ie0_value &= ~TXRDYE;
2342                 info->ie1_value |= IDLE;
2343                 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2344                 return;
2345         }
2346
2347         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2348                 tx_stop(info);
2349                 return;
2350         }
2351
2352         if ( info->tx_count )
2353                 tx_load_fifo( info );
2354         else {
2355                 info->tx_active = false;
2356                 info->ie0_value &= ~TXRDYE;
2357                 write_reg(info, IE0, info->ie0_value);
2358         }
2359
2360         if (info->tx_count < WAKEUP_CHARS)
2361                 info->pending_bh |= BH_TRANSMIT;
2362 }
2363
2364 static void isr_rxdmaok(SLMP_INFO * info)
2365 {
2366         /* BIT7 = EOT (end of transfer)
2367          * BIT6 = EOM (end of message/frame)
2368          */
2369         unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2370
2371         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2372         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2373
2374         if ( debug_level >= DEBUG_LEVEL_ISR )
2375                 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2376                         __FILE__,__LINE__,info->device_name,status);
2377
2378         info->pending_bh |= BH_RECEIVE;
2379 }
2380
2381 static void isr_rxdmaerror(SLMP_INFO * info)
2382 {
2383         /* BIT5 = BOF (buffer overflow)
2384          * BIT4 = COF (counter overflow)
2385          */
2386         unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2387
2388         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2389         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2390
2391         if ( debug_level >= DEBUG_LEVEL_ISR )
2392                 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2393                         __FILE__,__LINE__,info->device_name,status);
2394
2395         info->rx_overflow = true;
2396         info->pending_bh |= BH_RECEIVE;
2397 }
2398
2399 static void isr_txdmaok(SLMP_INFO * info)
2400 {
2401         unsigned char status_reg1 = read_reg(info, SR1);
2402
2403         write_reg(info, TXDMA + DIR, 0x00);     /* disable Tx DMA IRQs */
2404         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2405         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2406
2407         if ( debug_level >= DEBUG_LEVEL_ISR )
2408                 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2409                         __FILE__,__LINE__,info->device_name,status_reg1);
2410
2411         /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2412         write_reg16(info, TRC0, 0);
2413         info->ie0_value |= TXRDYE;
2414         write_reg(info, IE0, info->ie0_value);
2415 }
2416
2417 static void isr_txdmaerror(SLMP_INFO * info)
2418 {
2419         /* BIT5 = BOF (buffer overflow)
2420          * BIT4 = COF (counter overflow)
2421          */
2422         unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2423
2424         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2425         write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2426
2427         if ( debug_level >= DEBUG_LEVEL_ISR )
2428                 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2429                         __FILE__,__LINE__,info->device_name,status);
2430 }
2431
2432 /* handle input serial signal changes
2433  */
2434 static void isr_io_pin( SLMP_INFO *info, u16 status )
2435 {
2436         struct  mgsl_icount *icount;
2437
2438         if ( debug_level >= DEBUG_LEVEL_ISR )
2439                 printk("%s(%d):isr_io_pin status=%04X\n",
2440                         __FILE__,__LINE__,status);
2441
2442         if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2443                       MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2444                 icount = &info->icount;
2445                 /* update input line counters */
2446                 if (status & MISCSTATUS_RI_LATCHED) {
2447                         icount->rng++;
2448                         if ( status & SerialSignal_RI )
2449                                 info->input_signal_events.ri_up++;
2450                         else
2451                                 info->input_signal_events.ri_down++;
2452                 }
2453                 if (status & MISCSTATUS_DSR_LATCHED) {
2454                         icount->dsr++;
2455                         if ( status & SerialSignal_DSR )
2456                                 info->input_signal_events.dsr_up++;
2457                         else
2458                                 info->input_signal_events.dsr_down++;
2459                 }
2460                 if (status & MISCSTATUS_DCD_LATCHED) {
2461                         if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2462                                 info->ie1_value &= ~CDCD;
2463                                 write_reg(info, IE1, info->ie1_value);
2464                         }
2465                         icount->dcd++;
2466                         if (status & SerialSignal_DCD) {
2467                                 info->input_signal_events.dcd_up++;
2468                         } else
2469                                 info->input_signal_events.dcd_down++;
2470 #if SYNCLINK_GENERIC_HDLC
2471                         if (info->netcount) {
2472                                 if (status & SerialSignal_DCD)
2473                                         netif_carrier_on(info->netdev);
2474                                 else
2475                                         netif_carrier_off(info->netdev);
2476                         }
2477 #endif
2478                 }
2479                 if (status & MISCSTATUS_CTS_LATCHED)
2480                 {
2481                         if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2482                                 info->ie1_value &= ~CCTS;
2483                                 write_reg(info, IE1, info->ie1_value);
2484                         }
2485                         icount->cts++;
2486                         if ( status & SerialSignal_CTS )
2487                                 info->input_signal_events.cts_up++;
2488                         else
2489                                 info->input_signal_events.cts_down++;
2490                 }
2491                 wake_up_interruptible(&info->status_event_wait_q);
2492                 wake_up_interruptible(&info->event_wait_q);
2493
2494                 if ( (info->port.flags & ASYNC_CHECK_CD) &&
2495                      (status & MISCSTATUS_DCD_LATCHED) ) {
2496                         if ( debug_level >= DEBUG_LEVEL_ISR )
2497                                 printk("%s CD now %s...", info->device_name,
2498                                        (status & SerialSignal_DCD) ? "on" : "off");
2499                         if (status & SerialSignal_DCD)
2500                                 wake_up_interruptible(&info->port.open_wait);
2501                         else {
2502                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2503                                         printk("doing serial hangup...");
2504                                 if (info->port.tty)
2505                                         tty_hangup(info->port.tty);
2506                         }
2507                 }
2508
2509                 if ( (info->port.flags & ASYNC_CTS_FLOW) &&
2510                      (status & MISCSTATUS_CTS_LATCHED) ) {
2511                         if ( info->port.tty ) {
2512                                 if (info->port.tty->hw_stopped) {
2513                                         if (status & SerialSignal_CTS) {
2514                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2515                                                         printk("CTS tx start...");
2516                                                 info->port.tty->hw_stopped = 0;
2517                                                 tx_start(info);
2518                                                 info->pending_bh |= BH_TRANSMIT;
2519                                                 return;
2520                                         }
2521                                 } else {
2522                                         if (!(status & SerialSignal_CTS)) {
2523                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2524                                                         printk("CTS tx stop...");
2525                                                 info->port.tty->hw_stopped = 1;
2526                                                 tx_stop(info);
2527                                         }
2528                                 }
2529                         }
2530                 }
2531         }
2532
2533         info->pending_bh |= BH_STATUS;
2534 }
2535
2536 /* Interrupt service routine entry point.
2537  *
2538  * Arguments:
2539  *      irq             interrupt number that caused interrupt
2540  *      dev_id          device ID supplied during interrupt registration
2541  *      regs            interrupted processor context
2542  */
2543 static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2544 {
2545         SLMP_INFO *info = dev_id;
2546         unsigned char status, status0, status1=0;
2547         unsigned char dmastatus, dmastatus0, dmastatus1=0;
2548         unsigned char timerstatus0, timerstatus1=0;
2549         unsigned char shift;
2550         unsigned int i;
2551         unsigned short tmp;
2552
2553         if ( debug_level >= DEBUG_LEVEL_ISR )
2554                 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2555                         __FILE__, __LINE__, info->irq_level);
2556
2557         spin_lock(&info->lock);
2558
2559         for(;;) {
2560
2561                 /* get status for SCA0 (ports 0-1) */
2562                 tmp = read_reg16(info, ISR0);   /* get ISR0 and ISR1 in one read */
2563                 status0 = (unsigned char)tmp;
2564                 dmastatus0 = (unsigned char)(tmp>>8);
2565                 timerstatus0 = read_reg(info, ISR2);
2566
2567                 if ( debug_level >= DEBUG_LEVEL_ISR )
2568                         printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2569                                 __FILE__, __LINE__, info->device_name,
2570                                 status0, dmastatus0, timerstatus0);
2571
2572                 if (info->port_count == 4) {
2573                         /* get status for SCA1 (ports 2-3) */
2574                         tmp = read_reg16(info->port_array[2], ISR0);
2575                         status1 = (unsigned char)tmp;
2576                         dmastatus1 = (unsigned char)(tmp>>8);
2577                         timerstatus1 = read_reg(info->port_array[2], ISR2);
2578
2579                         if ( debug_level >= DEBUG_LEVEL_ISR )
2580                                 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2581                                         __FILE__,__LINE__,info->device_name,
2582                                         status1,dmastatus1,timerstatus1);
2583                 }
2584
2585                 if (!status0 && !dmastatus0 && !timerstatus0 &&
2586                          !status1 && !dmastatus1 && !timerstatus1)
2587                         break;
2588
2589                 for(i=0; i < info->port_count ; i++) {
2590                         if (info->port_array[i] == NULL)
2591                                 continue;
2592                         if (i < 2) {
2593                                 status = status0;
2594                                 dmastatus = dmastatus0;
2595                         } else {
2596                                 status = status1;
2597                                 dmastatus = dmastatus1;
2598                         }
2599
2600                         shift = i & 1 ? 4 :0;
2601
2602                         if (status & BIT0 << shift)
2603                                 isr_rxrdy(info->port_array[i]);
2604                         if (status & BIT1 << shift)
2605                                 isr_txrdy(info->port_array[i]);
2606                         if (status & BIT2 << shift)
2607                                 isr_rxint(info->port_array[i]);
2608                         if (status & BIT3 << shift)
2609                                 isr_txint(info->port_array[i]);
2610
2611                         if (dmastatus & BIT0 << shift)
2612                                 isr_rxdmaerror(info->port_array[i]);
2613                         if (dmastatus & BIT1 << shift)
2614                                 isr_rxdmaok(info->port_array[i]);
2615                         if (dmastatus & BIT2 << shift)
2616                                 isr_txdmaerror(info->port_array[i]);
2617                         if (dmastatus & BIT3 << shift)
2618                                 isr_txdmaok(info->port_array[i]);
2619                 }
2620
2621                 if (timerstatus0 & (BIT5 | BIT4))
2622                         isr_timer(info->port_array[0]);
2623                 if (timerstatus0 & (BIT7 | BIT6))
2624                         isr_timer(info->port_array[1]);
2625                 if (timerstatus1 & (BIT5 | BIT4))
2626                         isr_timer(info->port_array[2]);
2627                 if (timerstatus1 & (BIT7 | BIT6))
2628                         isr_timer(info->port_array[3]);
2629         }
2630
2631         for(i=0; i < info->port_count ; i++) {
2632                 SLMP_INFO * port = info->port_array[i];
2633
2634                 /* Request bottom half processing if there's something
2635                  * for it to do and the bh is not already running.
2636                  *
2637                  * Note: startup adapter diags require interrupts.
2638                  * do not request bottom half processing if the
2639                  * device is not open in a normal mode.
2640                  */
2641                 if ( port && (port->port.count || port->netcount) &&
2642                      port->pending_bh && !port->bh_running &&
2643                      !port->bh_requested ) {
2644                         if ( debug_level >= DEBUG_LEVEL_ISR )
2645                                 printk("%s(%d):%s queueing bh task.\n",
2646                                         __FILE__,__LINE__,port->device_name);
2647                         schedule_work(&port->task);
2648                         port->bh_requested = true;
2649                 }
2650         }
2651
2652         spin_unlock(&info->lock);
2653
2654         if ( debug_level >= DEBUG_LEVEL_ISR )
2655                 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2656                         __FILE__, __LINE__, info->irq_level);
2657         return IRQ_HANDLED;
2658 }
2659
2660 /* Initialize and start device.
2661  */
2662 static int startup(SLMP_INFO * info)
2663 {
2664         if ( debug_level >= DEBUG_LEVEL_INFO )
2665                 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2666
2667         if (info->port.flags & ASYNC_INITIALIZED)
2668                 return 0;
2669
2670         if (!info->tx_buf) {
2671                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2672                 if (!info->tx_buf) {
2673                         printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2674                                 __FILE__,__LINE__,info->device_name);
2675                         return -ENOMEM;
2676                 }
2677         }
2678
2679         info->pending_bh = 0;
2680
2681         memset(&info->icount, 0, sizeof(info->icount));
2682
2683         /* program hardware for current parameters */
2684         reset_port(info);
2685
2686         change_params(info);
2687
2688         mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2689
2690         if (info->port.tty)
2691                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2692
2693         info->port.flags |= ASYNC_INITIALIZED;
2694
2695         return 0;
2696 }
2697
2698 /* Called by close() and hangup() to shutdown hardware
2699  */
2700 static void shutdown(SLMP_INFO * info)
2701 {
2702         unsigned long flags;
2703
2704         if (!(info->port.flags & ASYNC_INITIALIZED))
2705                 return;
2706
2707         if (debug_level >= DEBUG_LEVEL_INFO)
2708                 printk("%s(%d):%s synclinkmp_shutdown()\n",
2709                          __FILE__,__LINE__, info->device_name );
2710
2711         /* clear status wait queue because status changes */
2712         /* can't happen after shutting down the hardware */
2713         wake_up_interruptible(&info->status_event_wait_q);
2714         wake_up_interruptible(&info->event_wait_q);
2715
2716         del_timer(&info->tx_timer);
2717         del_timer(&info->status_timer);
2718
2719         kfree(info->tx_buf);
2720         info->tx_buf = NULL;
2721
2722         spin_lock_irqsave(&info->lock,flags);
2723
2724         reset_port(info);
2725
2726         if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2727                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2728                 set_signals(info);
2729         }
2730
2731         spin_unlock_irqrestore(&info->lock,flags);
2732
2733         if (info->port.tty)
2734                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2735
2736         info->port.flags &= ~ASYNC_INITIALIZED;
2737 }
2738
2739 static void program_hw(SLMP_INFO *info)
2740 {
2741         unsigned long flags;
2742
2743         spin_lock_irqsave(&info->lock,flags);
2744
2745         rx_stop(info);
2746         tx_stop(info);
2747
2748         info->tx_count = info->tx_put = info->tx_get = 0;
2749
2750         if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2751                 hdlc_mode(info);
2752         else
2753                 async_mode(info);
2754
2755         set_signals(info);
2756
2757         info->dcd_chkcount = 0;
2758         info->cts_chkcount = 0;
2759         info->ri_chkcount = 0;
2760         info->dsr_chkcount = 0;
2761
2762         info->ie1_value |= (CDCD|CCTS);
2763         write_reg(info, IE1, info->ie1_value);
2764
2765         get_signals(info);
2766
2767         if (info->netcount || (info->port.tty && info->port.tty->termios->c_cflag & CREAD) )
2768                 rx_start(info);
2769
2770         spin_unlock_irqrestore(&info->lock,flags);
2771 }
2772
2773 /* Reconfigure adapter based on new parameters
2774  */
2775 static void change_params(SLMP_INFO *info)
2776 {
2777         unsigned cflag;
2778         int bits_per_char;
2779
2780         if (!info->port.tty || !info->port.tty->termios)
2781                 return;
2782
2783         if (debug_level >= DEBUG_LEVEL_INFO)
2784                 printk("%s(%d):%s change_params()\n",
2785                          __FILE__,__LINE__, info->device_name );
2786
2787         cflag = info->port.tty->termios->c_cflag;
2788
2789         /* if B0 rate (hangup) specified then negate DTR and RTS */
2790         /* otherwise assert DTR and RTS */
2791         if (cflag & CBAUD)
2792                 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2793         else
2794                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2795
2796         /* byte size and parity */
2797
2798         switch (cflag & CSIZE) {
2799               case CS5: info->params.data_bits = 5; break;
2800               case CS6: info->params.data_bits = 6; break;
2801               case CS7: info->params.data_bits = 7; break;
2802               case CS8: info->params.data_bits = 8; break;
2803               /* Never happens, but GCC is too dumb to figure it out */
2804               default:  info->params.data_bits = 7; break;
2805               }
2806
2807         if (cflag & CSTOPB)
2808                 info->params.stop_bits = 2;
2809         else
2810                 info->params.stop_bits = 1;
2811
2812         info->params.parity = ASYNC_PARITY_NONE;
2813         if (cflag & PARENB) {
2814                 if (cflag & PARODD)
2815                         info->params.parity = ASYNC_PARITY_ODD;
2816                 else
2817                         info->params.parity = ASYNC_PARITY_EVEN;
2818 #ifdef CMSPAR
2819                 if (cflag & CMSPAR)
2820                         info->params.parity = ASYNC_PARITY_SPACE;
2821 #endif
2822         }
2823
2824         /* calculate number of jiffies to transmit a full
2825          * FIFO (32 bytes) at specified data rate
2826          */
2827         bits_per_char = info->params.data_bits +
2828                         info->params.stop_bits + 1;
2829
2830         /* if port data rate is set to 460800 or less then
2831          * allow tty settings to override, otherwise keep the
2832          * current data rate.
2833          */
2834         if (info->params.data_rate <= 460800) {
2835                 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2836         }
2837
2838         if ( info->params.data_rate ) {
2839                 info->timeout = (32*HZ*bits_per_char) /
2840                                 info->params.data_rate;
2841         }
2842         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2843
2844         if (cflag & CRTSCTS)
2845                 info->port.flags |= ASYNC_CTS_FLOW;
2846         else
2847                 info->port.flags &= ~ASYNC_CTS_FLOW;
2848
2849         if (cflag & CLOCAL)
2850                 info->port.flags &= ~ASYNC_CHECK_CD;
2851         else
2852                 info->port.flags |= ASYNC_CHECK_CD;
2853
2854         /* process tty input control flags */
2855
2856         info->read_status_mask2 = OVRN;
2857         if (I_INPCK(info->port.tty))
2858                 info->read_status_mask2 |= PE | FRME;
2859         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2860                 info->read_status_mask1 |= BRKD;
2861         if (I_IGNPAR(info->port.tty))
2862                 info->ignore_status_mask2 |= PE | FRME;
2863         if (I_IGNBRK(info->port.tty)) {
2864                 info->ignore_status_mask1 |= BRKD;
2865                 /* If ignoring parity and break indicators, ignore
2866                  * overruns too.  (For real raw support).
2867                  */
2868                 if (I_IGNPAR(info->port.tty))
2869                         info->ignore_status_mask2 |= OVRN;
2870         }
2871
2872         program_hw(info);
2873 }
2874
2875 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2876 {
2877         int err;
2878
2879         if (debug_level >= DEBUG_LEVEL_INFO)
2880                 printk("%s(%d):%s get_params()\n",
2881                          __FILE__,__LINE__, info->device_name);
2882
2883         if (!user_icount) {
2884                 memset(&info->icount, 0, sizeof(info->icount));
2885         } else {
2886                 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2887                 if (err)
2888                         return -EFAULT;
2889         }
2890
2891         return 0;
2892 }
2893
2894 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2895 {
2896         int err;
2897         if (debug_level >= DEBUG_LEVEL_INFO)
2898                 printk("%s(%d):%s get_params()\n",
2899                          __FILE__,__LINE__, info->device_name);
2900
2901         COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2902         if (err) {
2903                 if ( debug_level >= DEBUG_LEVEL_INFO )
2904                         printk( "%s(%d):%s get_params() user buffer copy failed\n",
2905                                 __FILE__,__LINE__,info->device_name);
2906                 return -EFAULT;
2907         }
2908
2909         return 0;
2910 }
2911
2912 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2913 {
2914         unsigned long flags;
2915         MGSL_PARAMS tmp_params;
2916         int err;
2917
2918         if (debug_level >= DEBUG_LEVEL_INFO)
2919                 printk("%s(%d):%s set_params\n",
2920                         __FILE__,__LINE__,info->device_name );
2921         COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2922         if (err) {
2923                 if ( debug_level >= DEBUG_LEVEL_INFO )
2924                         printk( "%s(%d):%s set_params() user buffer copy failed\n",
2925                                 __FILE__,__LINE__,info->device_name);
2926                 return -EFAULT;
2927         }
2928
2929         spin_lock_irqsave(&info->lock,flags);
2930         memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2931         spin_unlock_irqrestore(&info->lock,flags);
2932
2933         change_params(info);
2934
2935         return 0;
2936 }
2937
2938 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2939 {
2940         int err;
2941
2942         if (debug_level >= DEBUG_LEVEL_INFO)
2943                 printk("%s(%d):%s get_txidle()=%d\n",
2944                          __FILE__,__LINE__, info->device_name, info->idle_mode);
2945
2946         COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2947         if (err) {
2948                 if ( debug_level >= DEBUG_LEVEL_INFO )
2949                         printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2950                                 __FILE__,__LINE__,info->device_name);
2951                 return -EFAULT;
2952         }
2953
2954         return 0;
2955 }
2956
2957 static int set_txidle(SLMP_INFO * info, int idle_mode)
2958 {
2959         unsigned long flags;
2960
2961         if (debug_level >= DEBUG_LEVEL_INFO)
2962                 printk("%s(%d):%s set_txidle(%d)\n",
2963                         __FILE__,__LINE__,info->device_name, idle_mode );
2964
2965         spin_lock_irqsave(&info->lock,flags);
2966         info->idle_mode = idle_mode;
2967         tx_set_idle( info );
2968         spin_unlock_irqrestore(&info->lock,flags);
2969         return 0;
2970 }
2971
2972 static int tx_enable(SLMP_INFO * info, int enable)
2973 {
2974         unsigned long flags;
2975
2976         if (debug_level >= DEBUG_LEVEL_INFO)
2977                 printk("%s(%d):%s tx_enable(%d)\n",
2978                         __FILE__,__LINE__,info->device_name, enable);
2979
2980         spin_lock_irqsave(&info->lock,flags);
2981         if ( enable ) {
2982                 if ( !info->tx_enabled ) {
2983                         tx_start(info);
2984                 }
2985         } else {
2986                 if ( info->tx_enabled )
2987                         tx_stop(info);
2988         }
2989         spin_unlock_irqrestore(&info->lock,flags);
2990         return 0;
2991 }
2992
2993 /* abort send HDLC frame
2994  */
2995 static int tx_abort(SLMP_INFO * info)
2996 {
2997         unsigned long flags;
2998
2999         if (debug_level >= DEBUG_LEVEL_INFO)
3000                 printk("%s(%d):%s tx_abort()\n",
3001                         __FILE__,__LINE__,info->device_name);
3002
3003         spin_lock_irqsave(&info->lock,flags);
3004         if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
3005                 info->ie1_value &= ~UDRN;
3006                 info->ie1_value |= IDLE;
3007                 write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
3008                 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
3009
3010                 write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
3011                 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3012
3013                 write_reg(info, CMD, TXABORT);
3014         }
3015         spin_unlock_irqrestore(&info->lock,flags);
3016         return 0;
3017 }
3018
3019 static int rx_enable(SLMP_INFO * info, int enable)
3020 {
3021         unsigned long flags;
3022
3023         if (debug_level >= DEBUG_LEVEL_INFO)
3024                 printk("%s(%d):%s rx_enable(%d)\n",
3025                         __FILE__,__LINE__,info->device_name,enable);
3026
3027         spin_lock_irqsave(&info->lock,flags);
3028         if ( enable ) {
3029                 if ( !info->rx_enabled )
3030                         rx_start(info);
3031         } else {
3032                 if ( info->rx_enabled )
3033                         rx_stop(info);
3034         }
3035         spin_unlock_irqrestore(&info->lock,flags);
3036         return 0;
3037 }
3038
3039 /* wait for specified event to occur
3040  */
3041 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3042 {
3043         unsigned long flags;
3044         int s;
3045         int rc=0;
3046         struct mgsl_icount cprev, cnow;
3047         int events;
3048         int mask;
3049         struct  _input_signal_events oldsigs, newsigs;
3050         DECLARE_WAITQUEUE(wait, current);
3051
3052         COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3053         if (rc) {
3054                 return  -EFAULT;
3055         }
3056
3057         if (debug_level >= DEBUG_LEVEL_INFO)
3058                 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3059                         __FILE__,__LINE__,info->device_name,mask);
3060
3061         spin_lock_irqsave(&info->lock,flags);
3062
3063         /* return immediately if state matches requested events */
3064         get_signals(info);
3065         s = info->serial_signals;
3066
3067         events = mask &
3068                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3069                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3070                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3071                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3072         if (events) {
3073                 spin_unlock_irqrestore(&info->lock,flags);
3074                 goto exit;
3075         }
3076
3077         /* save current irq counts */
3078         cprev = info->icount;
3079         oldsigs = info->input_signal_events;
3080
3081         /* enable hunt and idle irqs if needed */
3082         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3083                 unsigned char oldval = info->ie1_value;
3084                 unsigned char newval = oldval +
3085                          (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3086                          (mask & MgslEvent_IdleReceived ? IDLD:0);
3087                 if ( oldval != newval ) {
3088                         info->ie1_value = newval;
3089                         write_reg(info, IE1, info->ie1_value);
3090                 }
3091         }
3092
3093         set_current_state(TASK_INTERRUPTIBLE);
3094         add_wait_queue(&info->event_wait_q, &wait);
3095
3096         spin_unlock_irqrestore(&info->lock,flags);
3097
3098         for(;;) {
3099                 schedule();
3100                 if (signal_pending(current)) {
3101                         rc = -ERESTARTSYS;
3102                         break;
3103                 }
3104
3105                 /* get current irq counts */
3106                 spin_lock_irqsave(&info->lock,flags);
3107                 cnow = info->icount;
3108                 newsigs = info->input_signal_events;
3109                 set_current_state(TASK_INTERRUPTIBLE);
3110                 spin_unlock_irqrestore(&info->lock,flags);
3111
3112                 /* if no change, wait aborted for some reason */
3113                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
3114                     newsigs.dsr_down == oldsigs.dsr_down &&
3115                     newsigs.dcd_up   == oldsigs.dcd_up   &&
3116                     newsigs.dcd_down == oldsigs.dcd_down &&
3117                     newsigs.cts_up   == oldsigs.cts_up   &&
3118                     newsigs.cts_down == oldsigs.cts_down &&
3119                     newsigs.ri_up    == oldsigs.ri_up    &&
3120                     newsigs.ri_down  == oldsigs.ri_down  &&
3121                     cnow.exithunt    == cprev.exithunt   &&
3122                     cnow.rxidle      == cprev.rxidle) {
3123                         rc = -EIO;
3124                         break;
3125                 }
3126
3127                 events = mask &
3128                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
3129                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3130                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
3131                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3132                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
3133                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3134                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
3135                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
3136                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
3137                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
3138                 if (events)
3139                         break;
3140
3141                 cprev = cnow;
3142                 oldsigs = newsigs;
3143         }
3144
3145         remove_wait_queue(&info->event_wait_q, &wait);
3146         set_current_state(TASK_RUNNING);
3147
3148
3149         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3150                 spin_lock_irqsave(&info->lock,flags);
3151                 if (!waitqueue_active(&info->event_wait_q)) {
3152                         /* disable enable exit hunt mode/idle rcvd IRQs */
3153                         info->ie1_value &= ~(FLGD|IDLD);
3154                         write_reg(info, IE1, info->ie1_value);
3155                 }
3156                 spin_unlock_irqrestore(&info->lock,flags);
3157         }
3158 exit:
3159         if ( rc == 0 )
3160                 PUT_USER(rc, events, mask_ptr);
3161
3162         return rc;
3163 }
3164
3165 static int modem_input_wait(SLMP_INFO *info,int arg)
3166 {
3167         unsigned long flags;
3168         int rc;
3169         struct mgsl_icount cprev, cnow;
3170         DECLARE_WAITQUEUE(wait, current);
3171
3172         /* save current irq counts */
3173         spin_lock_irqsave(&info->lock,flags);
3174         cprev = info->icount;
3175         add_wait_queue(&info->status_event_wait_q, &wait);
3176         set_current_state(TASK_INTERRUPTIBLE);
3177         spin_unlock_irqrestore(&info->lock,flags);
3178
3179         for(;;) {
3180                 schedule();
3181                 if (signal_pending(current)) {
3182                         rc = -ERESTARTSYS;
3183                         break;
3184                 }
3185
3186                 /* get new irq counts */
3187                 spin_lock_irqsave(&info->lock,flags);
3188                 cnow = info->icount;
3189                 set_current_state(TASK_INTERRUPTIBLE);
3190                 spin_unlock_irqrestore(&info->lock,flags);
3191
3192                 /* if no change, wait aborted for some reason */
3193                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3194                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3195                         rc = -EIO;
3196                         break;
3197                 }
3198
3199                 /* check for change in caller specified modem input */
3200                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3201                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3202                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3203                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3204                         rc = 0;
3205                         break;
3206                 }
3207
3208                 cprev = cnow;
3209         }
3210         remove_wait_queue(&info->status_event_wait_q, &wait);
3211         set_current_state(TASK_RUNNING);
3212         return rc;
3213 }
3214
3215 /* return the state of the serial control and status signals
3216  */
3217 static int tiocmget(struct tty_struct *tty, struct file *file)
3218 {
3219         SLMP_INFO *info = tty->driver_data;
3220         unsigned int result;
3221         unsigned long flags;
3222
3223         spin_lock_irqsave(&info->lock,flags);
3224         get_signals(info);
3225         spin_unlock_irqrestore(&info->lock,flags);
3226
3227         result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3228                 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3229                 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3230                 ((info->serial_signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3231                 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3232                 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3233
3234         if (debug_level >= DEBUG_LEVEL_INFO)
3235                 printk("%s(%d):%s tiocmget() value=%08X\n",
3236                          __FILE__,__LINE__, info->device_name, result );
3237         return result;
3238 }
3239
3240 /* set modem control signals (DTR/RTS)
3241  */
3242 static int tiocmset(struct tty_struct *tty, struct file *file,
3243                     unsigned int set, unsigned int clear)
3244 {
3245         SLMP_INFO *info = tty->driver_data;
3246         unsigned long flags;
3247
3248         if (debug_level >= DEBUG_LEVEL_INFO)
3249                 printk("%s(%d):%s tiocmset(%x,%x)\n",
3250                         __FILE__,__LINE__,info->device_name, set, clear);
3251
3252         if (set & TIOCM_RTS)
3253                 info->serial_signals |= SerialSignal_RTS;
3254         if (set & TIOCM_DTR)
3255                 info->serial_signals |= SerialSignal_DTR;
3256         if (clear & TIOCM_RTS)
3257                 info->serial_signals &= ~SerialSignal_RTS;
3258         if (clear & TIOCM_DTR)
3259                 info->serial_signals &= ~SerialSignal_DTR;
3260
3261         spin_lock_irqsave(&info->lock,flags);
3262         set_signals(info);
3263         spin_unlock_irqrestore(&info->lock,flags);
3264
3265         return 0;
3266 }
3267
3268 static int carrier_raised(struct tty_port *port)
3269 {
3270         SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3271         unsigned long flags;
3272
3273         spin_lock_irqsave(&info->lock,flags);
3274         get_signals(info);
3275         spin_unlock_irqrestore(&info->lock,flags);
3276
3277         return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3278 }
3279
3280 static void raise_dtr_rts(struct tty_port *port)
3281 {
3282         SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3283         unsigned long flags;
3284
3285         spin_lock_irqsave(&info->lock,flags);
3286         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3287         set_signals(info);
3288         spin_unlock_irqrestore(&info->lock,flags);
3289 }
3290
3291 /* Block the current process until the specified port is ready to open.
3292  */
3293 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3294                            SLMP_INFO *info)
3295 {
3296         DECLARE_WAITQUEUE(wait, current);
3297         int             retval;
3298         bool            do_clocal = false;
3299         bool            extra_count = false;
3300         unsigned long   flags;
3301         int             cd;
3302         struct tty_port *port = &info->port;
3303
3304         if (debug_level >= DEBUG_LEVEL_INFO)
3305                 printk("%s(%d):%s block_til_ready()\n",
3306                          __FILE__,__LINE__, tty->driver->name );
3307
3308         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3309                 /* nonblock mode is set or port is not enabled */
3310                 /* just verify that callout device is not active */
3311                 port->flags |= ASYNC_NORMAL_ACTIVE;
3312                 return 0;
3313         }
3314
3315         if (tty->termios->c_cflag & CLOCAL)
3316                 do_clocal = true;
3317
3318         /* Wait for carrier detect and the line to become
3319          * free (i.e., not in use by the callout).  While we are in
3320          * this loop, port->count is dropped by one, so that
3321          * close() knows when to free things.  We restore it upon
3322          * exit, either normal or abnormal.
3323          */
3324
3325         retval = 0;
3326         add_wait_queue(&port->open_wait, &wait);
3327
3328         if (debug_level >= DEBUG_LEVEL_INFO)
3329                 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3330                          __FILE__,__LINE__, tty->driver->name, port->count );
3331
3332         spin_lock_irqsave(&info->lock, flags);
3333         if (!tty_hung_up_p(filp)) {
3334                 extra_count = true;
3335                 port->count--;
3336         }
3337         spin_unlock_irqrestore(&info->lock, flags);
3338         port->blocked_open++;
3339
3340         while (1) {
3341                 if (tty->termios->c_cflag & CBAUD)
3342                         tty_port_raise_dtr_rts(port);
3343
3344                 set_current_state(TASK_INTERRUPTIBLE);
3345
3346                 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3347                         retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3348                                         -EAGAIN : -ERESTARTSYS;
3349                         break;
3350                 }
3351
3352                 cd = tty_port_carrier_raised(port);
3353
3354                 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd))
3355                         break;
3356
3357                 if (signal_pending(current)) {
3358                         retval = -ERESTARTSYS;
3359                         break;
3360                 }
3361
3362                 if (debug_level >= DEBUG_LEVEL_INFO)
3363                         printk("%s(%d):%s block_til_ready() count=%d\n",
3364                                  __FILE__,__LINE__, tty->driver->name, port->count );
3365
3366                 schedule();
3367         }
3368
3369         set_current_state(TASK_RUNNING);
3370         remove_wait_queue(&port->open_wait, &wait);
3371
3372         if (extra_count)
3373                 port->count++;
3374         port->blocked_open--;
3375
3376         if (debug_level >= DEBUG_LEVEL_INFO)
3377                 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3378                          __FILE__,__LINE__, tty->driver->name, port->count );
3379
3380         if (!retval)
3381                 port->flags |= ASYNC_NORMAL_ACTIVE;
3382
3383         return retval;
3384 }
3385
3386 static int alloc_dma_bufs(SLMP_INFO *info)
3387 {
3388         unsigned short BuffersPerFrame;
3389         unsigned short BufferCount;
3390
3391         // Force allocation to start at 64K boundary for each port.
3392         // This is necessary because *all* buffer descriptors for a port
3393         // *must* be in the same 64K block. All descriptors on a port
3394         // share a common 'base' address (upper 8 bits of 24 bits) programmed
3395         // into the CBP register.
3396         info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3397
3398         /* Calculate the number of DMA buffers necessary to hold the */
3399         /* largest allowable frame size. Note: If the max frame size is */
3400         /* not an even multiple of the DMA buffer size then we need to */
3401         /* round the buffer count per frame up one. */
3402
3403         BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3404         if ( info->max_frame_size % SCABUFSIZE )
3405                 BuffersPerFrame++;
3406
3407         /* calculate total number of data buffers (SCABUFSIZE) possible
3408          * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3409          * for the descriptor list (BUFFERLISTSIZE).
3410          */
3411         BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3412
3413         /* limit number of buffers to maximum amount of descriptors */
3414         if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3415                 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3416
3417         /* use enough buffers to transmit one max size frame */
3418         info->tx_buf_count = BuffersPerFrame + 1;
3419
3420         /* never use more than half the available buffers for transmit */
3421         if (info->tx_buf_count > (BufferCount/2))
3422                 info->tx_buf_count = BufferCount/2;
3423
3424         if (info->tx_buf_count > SCAMAXDESC)
3425                 info->tx_buf_count = SCAMAXDESC;
3426
3427         /* use remaining buffers for receive */
3428         info->rx_buf_count = BufferCount - info->tx_buf_count;
3429
3430         if (info->rx_buf_count > SCAMAXDESC)
3431                 info->rx_buf_count = SCAMAXDESC;
3432
3433         if ( debug_level >= DEBUG_LEVEL_INFO )
3434                 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3435                         __FILE__,__LINE__, info->device_name,
3436                         info->tx_buf_count,info->rx_buf_count);
3437
3438         if ( alloc_buf_list( info ) < 0 ||
3439                 alloc_frame_bufs(info,
3440                                         info->rx_buf_list,
3441                                         info->rx_buf_list_ex,
3442                                         info->rx_buf_count) < 0 ||
3443                 alloc_frame_bufs(info,
3444                                         info->tx_buf_list,
3445                                         info->tx_buf_list_ex,
3446                                         info->tx_buf_count) < 0 ||
3447                 alloc_tmp_rx_buf(info) < 0 ) {
3448                 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3449                         __FILE__,__LINE__, info->device_name);
3450                 return -ENOMEM;
3451         }
3452
3453         rx_reset_buffers( info );
3454
3455         return 0;
3456 }
3457
3458 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3459  */
3460 static int alloc_buf_list(SLMP_INFO *info)
3461 {
3462         unsigned int i;
3463
3464         /* build list in adapter shared memory */
3465         info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3466         info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3467         info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3468
3469         memset(info->buffer_list, 0, BUFFERLISTSIZE);
3470
3471         /* Save virtual address pointers to the receive and */
3472         /* transmit buffer lists. (Receive 1st). These pointers will */
3473         /* be used by the processor to access the lists. */
3474         info->rx_buf_list = (SCADESC *)info->buffer_list;
3475
3476         info->tx_buf_list = (SCADESC *)info->buffer_list;
3477         info->tx_buf_list += info->rx_buf_count;
3478
3479         /* Build links for circular buffer entry lists (tx and rx)
3480          *
3481          * Note: links are physical addresses read by the SCA device
3482          * to determine the next buffer entry to use.
3483          */
3484
3485         for ( i = 0; i < info->rx_buf_count; i++ ) {
3486                 /* calculate and store physical address of this buffer entry */
3487                 info->rx_buf_list_ex[i].phys_entry =
3488                         info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3489
3490                 /* calculate and store physical address of */
3491                 /* next entry in cirular list of entries */
3492                 info->rx_buf_list[i].next = info->buffer_list_phys;
3493                 if ( i < info->rx_buf_count - 1 )
3494                         info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3495
3496                 info->rx_buf_list[i].length = SCABUFSIZE;
3497         }
3498
3499         for ( i = 0; i < info->tx_buf_count; i++ ) {
3500                 /* calculate and store physical address of this buffer entry */
3501                 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3502                         ((info->rx_buf_count + i) * sizeof(SCADESC));
3503
3504                 /* calculate and store physical address of */
3505                 /* next entry in cirular list of entries */
3506
3507                 info->tx_buf_list[i].next = info->buffer_list_phys +
3508                         info->rx_buf_count * sizeof(SCADESC);
3509
3510                 if ( i < info->tx_buf_count - 1 )
3511                         info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3512         }
3513
3514         return 0;
3515 }
3516
3517 /* Allocate the frame DMA buffers used by the specified buffer list.
3518  */
3519 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3520 {
3521         int i;
3522         unsigned long phys_addr;
3523
3524         for ( i = 0; i < count; i++ ) {
3525                 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3526                 phys_addr = info->port_array[0]->last_mem_alloc;
3527                 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3528
3529                 buf_list[i].buf_ptr  = (unsigned short)phys_addr;
3530                 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3531         }
3532
3533         return 0;
3534 }
3535
3536 static void free_dma_bufs(SLMP_INFO *info)
3537 {
3538         info->buffer_list = NULL;
3539         info->rx_buf_list = NULL;
3540         info->tx_buf_list = NULL;
3541 }
3542
3543 /* allocate buffer large enough to hold max_frame_size.
3544  * This buffer is used to pass an assembled frame to the line discipline.
3545  */
3546 static int alloc_tmp_rx_buf(SLMP_INFO *info)
3547 {
3548         info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3549         if (info->tmp_rx_buf == NULL)
3550                 return -ENOMEM;
3551         return 0;
3552 }
3553
3554 static void free_tmp_rx_buf(SLMP_INFO *info)
3555 {
3556         kfree(info->tmp_rx_buf);
3557         info->tmp_rx_buf = NULL;
3558 }
3559
3560 static int claim_resources(SLMP_INFO *info)
3561 {
3562         if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3563                 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3564                         __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3565                 info->init_error = DiagStatus_AddressConflict;
3566                 goto errout;
3567         }
3568         else
3569                 info->shared_mem_requested = true;
3570
3571         if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3572                 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3573                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3574                 info->init_error = DiagStatus_AddressConflict;
3575                 goto errout;
3576         }
3577         else
3578                 info->lcr_mem_requested = true;
3579
3580         if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3581                 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3582                         __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3583                 info->init_error = DiagStatus_AddressConflict;
3584                 goto errout;
3585         }
3586         else
3587                 info->sca_base_requested = true;
3588
3589         if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3590                 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3591                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3592                 info->init_error = DiagStatus_AddressConflict;
3593                 goto errout;
3594         }
3595         else
3596                 info->sca_statctrl_requested = true;
3597
3598         info->memory_base = ioremap_nocache(info->phys_memory_base,
3599                                                                 SCA_MEM_SIZE);
3600         if (!info->memory_base) {
3601                 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3602                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3603                 info->init_error = DiagStatus_CantAssignPciResources;
3604                 goto errout;
3605         }
3606
3607         info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE);
3608         if (!info->lcr_base) {
3609                 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3610                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3611                 info->init_error = DiagStatus_CantAssignPciResources;
3612                 goto errout;
3613         }
3614         info->lcr_base += info->lcr_offset;
3615
3616         info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE);
3617         if (!info->sca_base) {
3618                 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3619                         __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3620                 info->init_error = DiagStatus_CantAssignPciResources;
3621                 goto errout;
3622         }
3623         info->sca_base += info->sca_offset;
3624
3625         info->statctrl_base = ioremap_nocache(info->phys_statctrl_base,
3626                                                                 PAGE_SIZE);
3627         if (!info->statctrl_base) {
3628                 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3629                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3630                 info->init_error = DiagStatus_CantAssignPciResources;
3631                 goto errout;
3632         }
3633         info->statctrl_base += info->statctrl_offset;
3634
3635         if ( !memory_test(info) ) {
3636                 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3637                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3638                 info->init_error = DiagStatus_MemoryError;
3639                 goto errout;
3640         }
3641
3642         return 0;
3643
3644 errout:
3645         release_resources( info );
3646         return -ENODEV;
3647 }
3648
3649 static void release_resources(SLMP_INFO *info)
3650 {
3651         if ( debug_level >= DEBUG_LEVEL_INFO )
3652                 printk( "%s(%d):%s release_resources() entry\n",
3653                         __FILE__,__LINE__,info->device_name );
3654
3655         if ( info->irq_requested ) {
3656                 free_irq(info->irq_level, info);
3657                 info->irq_requested = false;
3658         }
3659
3660         if ( info->shared_mem_requested ) {
3661                 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3662                 info->shared_mem_requested = false;
3663         }
3664         if ( info->lcr_mem_requested ) {
3665                 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3666                 info->lcr_mem_requested = false;
3667         }
3668         if ( info->sca_base_requested ) {
3669                 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3670                 info->sca_base_requested = false;
3671         }
3672         if ( info->sca_statctrl_requested ) {
3673                 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3674                 info->sca_statctrl_requested = false;
3675         }
3676
3677         if (info->memory_base){
3678                 iounmap(info->memory_base);
3679                 info->memory_base = NULL;
3680         }
3681
3682         if (info->sca_base) {
3683                 iounmap(info->sca_base - info->sca_offset);
3684                 info->sca_base=NULL;
3685         }
3686
3687         if (info->statctrl_base) {
3688                 iounmap(info->statctrl_base - info->statctrl_offset);
3689                 info->statctrl_base=NULL;
3690         }
3691
3692         if (info->lcr_base){
3693                 iounmap(info->lcr_base - info->lcr_offset);
3694                 info->lcr_base = NULL;
3695         }
3696
3697         if ( debug_level >= DEBUG_LEVEL_INFO )
3698                 printk( "%s(%d):%s release_resources() exit\n",
3699                         __FILE__,__LINE__,info->device_name );
3700 }
3701
3702 /* Add the specified device instance data structure to the
3703  * global linked list of devices and increment the device count.
3704  */
3705 static void add_device(SLMP_INFO *info)
3706 {
3707         info->next_device = NULL;
3708         info->line = synclinkmp_device_count;
3709         sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3710
3711         if (info->line < MAX_DEVICES) {
3712                 if (maxframe[info->line])
3713                         info->max_frame_size = maxframe[info->line];
3714         }
3715
3716         synclinkmp_device_count++;
3717
3718         if ( !synclinkmp_device_list )
3719                 synclinkmp_device_list = info;
3720         else {
3721                 SLMP_INFO *current_dev = synclinkmp_device_list;
3722                 while( current_dev->next_device )
3723                         current_dev = current_dev->next_device;
3724                 current_dev->next_device = info;
3725         }
3726
3727         if ( info->max_frame_size < 4096 )
3728                 info->max_frame_size = 4096;
3729         else if ( info->max_frame_size > 65535 )
3730                 info->max_frame_size = 65535;
3731
3732         printk( "SyncLink MultiPort %s: "
3733                 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3734                 info->device_name,
3735                 info->phys_sca_base,
3736                 info->phys_memory_base,
3737                 info->phys_statctrl_base,
3738                 info->phys_lcr_base,
3739                 info->irq_level,
3740                 info->max_frame_size );
3741
3742 #if SYNCLINK_GENERIC_HDLC
3743         hdlcdev_init(info);
3744 #endif
3745 }
3746
3747 static const struct tty_port_operations port_ops = {
3748         .carrier_raised = carrier_raised,
3749         .raise_dtr_rts = raise_dtr_rts,
3750 };
3751
3752 /* Allocate and initialize a device instance structure
3753  *
3754  * Return Value:        pointer to SLMP_INFO if success, otherwise NULL
3755  */
3756 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3757 {
3758         SLMP_INFO *info;
3759
3760         info = kzalloc(sizeof(SLMP_INFO),
3761                  GFP_KERNEL);
3762
3763         if (!info) {
3764                 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3765                         __FILE__,__LINE__, adapter_num, port_num);
3766         } else {
3767                 tty_port_init(&info->port);
3768                 info->port.ops = &port_ops;
3769                 info->magic = MGSL_MAGIC;
3770                 INIT_WORK(&info->task, bh_handler);
3771                 info->max_frame_size = 4096;
3772                 info->port.close_delay = 5*HZ/10;
3773                 info->port.closing_wait = 30*HZ;
3774                 init_waitqueue_head(&info->status_event_wait_q);
3775                 init_waitqueue_head(&info->event_wait_q);
3776                 spin_lock_init(&info->netlock);
3777                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3778                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3779                 info->adapter_num = adapter_num;
3780                 info->port_num = port_num;
3781
3782                 /* Copy configuration info to device instance data */
3783                 info->irq_level = pdev->irq;
3784                 info->phys_lcr_base = pci_resource_start(pdev,0);
3785                 info->phys_sca_base = pci_resource_start(pdev,2);
3786                 info->phys_memory_base = pci_resource_start(pdev,3);
3787                 info->phys_statctrl_base = pci_resource_start(pdev,4);
3788
3789                 /* Because veremap only works on page boundaries we must map
3790                  * a larger area than is actually implemented for the LCR
3791                  * memory range. We map a full page starting at the page boundary.
3792                  */
3793                 info->lcr_offset    = info->phys_lcr_base & (PAGE_SIZE-1);
3794                 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3795
3796                 info->sca_offset    = info->phys_sca_base & (PAGE_SIZE-1);
3797                 info->phys_sca_base &= ~(PAGE_SIZE-1);
3798
3799                 info->statctrl_offset    = info->phys_statctrl_base & (PAGE_SIZE-1);
3800                 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3801
3802                 info->bus_type = MGSL_BUS_TYPE_PCI;
3803                 info->irq_flags = IRQF_SHARED;
3804
3805                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3806                 setup_timer(&info->status_timer, status_timeout,
3807                                 (unsigned long)info);
3808
3809                 /* Store the PCI9050 misc control register value because a flaw
3810                  * in the PCI9050 prevents LCR registers from being read if
3811                  * BIOS assigns an LCR base address with bit 7 set.
3812                  *
3813                  * Only the misc control register is accessed for which only
3814                  * write access is needed, so set an initial value and change
3815                  * bits to the device instance data as we write the value
3816                  * to the actual misc control register.
3817                  */
3818                 info->misc_ctrl_value = 0x087e4546;
3819
3820                 /* initial port state is unknown - if startup errors
3821                  * occur, init_error will be set to indicate the
3822                  * problem. Once the port is fully initialized,
3823                  * this value will be set to 0 to indicate the
3824                  * port is available.
3825                  */
3826                 info->init_error = -1;
3827         }
3828
3829         return info;
3830 }
3831
3832 static void device_init(int adapter_num, struct pci_dev *pdev)
3833 {
3834         SLMP_INFO *port_array[SCA_MAX_PORTS];
3835         int port;
3836
3837         /* allocate device instances for up to SCA_MAX_PORTS devices */
3838         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3839                 port_array[port] = alloc_dev(adapter_num,port,pdev);
3840                 if( port_array[port] == NULL ) {
3841                         for ( --port; port >= 0; --port )
3842                                 kfree(port_array[port]);
3843                         return;
3844                 }
3845         }
3846
3847         /* give copy of port_array to all ports and add to device list  */
3848         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3849                 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3850                 add_device( port_array[port] );
3851                 spin_lock_init(&port_array[port]->lock);
3852         }
3853
3854         /* Allocate and claim adapter resources */
3855         if ( !claim_resources(port_array[0]) ) {
3856
3857                 alloc_dma_bufs(port_array[0]);
3858
3859                 /* copy resource information from first port to others */
3860                 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3861                         port_array[port]->lock  = port_array[0]->lock;
3862                         port_array[port]->irq_level     = port_array[0]->irq_level;
3863                         port_array[port]->memory_base   = port_array[0]->memory_base;
3864                         port_array[port]->sca_base      = port_array[0]->sca_base;
3865                         port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3866                         port_array[port]->lcr_base      = port_array[0]->lcr_base;
3867                         alloc_dma_bufs(port_array[port]);
3868                 }
3869
3870                 if ( request_irq(port_array[0]->irq_level,
3871                                         synclinkmp_interrupt,
3872                                         port_array[0]->irq_flags,
3873                                         port_array[0]->device_name,
3874                                         port_array[0]) < 0 ) {
3875                         printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3876                                 __FILE__,__LINE__,
3877                                 port_array[0]->device_name,
3878                                 port_array[0]->irq_level );
3879                 }
3880                 else {
3881                         port_array[0]->irq_requested = true;
3882                         adapter_test(port_array[0]);
3883                 }
3884         }
3885 }
3886
3887 static const struct tty_operations ops = {
3888         .open = open,
3889         .close = close,
3890         .write = write,
3891         .put_char = put_char,
3892         .flush_chars = flush_chars,
3893         .write_room = write_room,
3894         .chars_in_buffer = chars_in_buffer,
3895         .flush_buffer = flush_buffer,
3896         .ioctl = ioctl,
3897         .throttle = throttle,
3898         .unthrottle = unthrottle,
3899         .send_xchar = send_xchar,
3900         .break_ctl = set_break,
3901         .wait_until_sent = wait_until_sent,
3902         .set_termios = set_termios,
3903         .stop = tx_hold,
3904         .start = tx_release,
3905         .hangup = hangup,
3906         .tiocmget = tiocmget,
3907         .tiocmset = tiocmset,
3908         .proc_fops = &synclinkmp_proc_fops,
3909 };
3910
3911
3912 static void synclinkmp_cleanup(void)
3913 {
3914         int rc;
3915         SLMP_INFO *info;
3916         SLMP_INFO *tmp;
3917
3918         printk("Unloading %s %s\n", driver_name, driver_version);
3919
3920         if (serial_driver) {
3921                 if ((rc = tty_unregister_driver(serial_driver)))
3922                         printk("%s(%d) failed to unregister tty driver err=%d\n",
3923                                __FILE__,__LINE__,rc);
3924                 put_tty_driver(serial_driver);
3925         }
3926
3927         /* reset devices */
3928         info = synclinkmp_device_list;
3929         while(info) {
3930                 reset_port(info);
3931                 info = info->next_device;
3932         }
3933
3934         /* release devices */
3935         info = synclinkmp_device_list;
3936         while(info) {
3937 #if SYNCLINK_GENERIC_HDLC
3938                 hdlcdev_exit(info);
3939 #endif
3940                 free_dma_bufs(info);
3941                 free_tmp_rx_buf(info);
3942                 if ( info->port_num == 0 ) {
3943                         if (info->sca_base)
3944                                 write_reg(info, LPR, 1); /* set low power mode */
3945                         release_resources(info);
3946                 }
3947                 tmp = info;
3948                 info = info->next_device;
3949                 kfree(tmp);
3950         }
3951
3952         pci_unregister_driver(&synclinkmp_pci_driver);
3953 }
3954
3955 /* Driver initialization entry point.
3956  */
3957
3958 static int __init synclinkmp_init(void)
3959 {
3960         int rc;
3961
3962         if (break_on_load) {
3963                 synclinkmp_get_text_ptr();
3964                 BREAKPOINT();
3965         }
3966
3967         printk("%s %s\n", driver_name, driver_version);
3968
3969         if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
3970                 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
3971                 return rc;
3972         }
3973
3974         serial_driver = alloc_tty_driver(128);
3975         if (!serial_driver) {
3976                 rc = -ENOMEM;
3977                 goto error;
3978         }
3979
3980         /* Initialize the tty_driver structure */
3981
3982         serial_driver->owner = THIS_MODULE;
3983         serial_driver->driver_name = "synclinkmp";
3984         serial_driver->name = "ttySLM";
3985         serial_driver->major = ttymajor;
3986         serial_driver->minor_start = 64;
3987         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3988         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3989         serial_driver->init_termios = tty_std_termios;
3990         serial_driver->init_termios.c_cflag =
3991                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3992         serial_driver->init_termios.c_ispeed = 9600;
3993         serial_driver->init_termios.c_ospeed = 9600;
3994         serial_driver->flags = TTY_DRIVER_REAL_RAW;
3995         tty_set_operations(serial_driver, &ops);
3996         if ((rc = tty_register_driver(serial_driver)) < 0) {
3997                 printk("%s(%d):Couldn't register serial driver\n",
3998                         __FILE__,__LINE__);
3999                 put_tty_driver(serial_driver);
4000                 serial_driver = NULL;
4001                 goto error;
4002         }
4003
4004         printk("%s %s, tty major#%d\n",
4005                 driver_name, driver_version,
4006                 serial_driver->major);
4007
4008         return 0;
4009
4010 error:
4011         synclinkmp_cleanup();
4012         return rc;
4013 }
4014
4015 static void __exit synclinkmp_exit(void)
4016 {
4017         synclinkmp_cleanup();
4018 }
4019
4020 module_init(synclinkmp_init);
4021 module_exit(synclinkmp_exit);
4022
4023 /* Set the port for internal loopback mode.
4024  * The TxCLK and RxCLK signals are generated from the BRG and
4025  * the TxD is looped back to the RxD internally.
4026  */
4027 static void enable_loopback(SLMP_INFO *info, int enable)
4028 {
4029         if (enable) {
4030                 /* MD2 (Mode Register 2)
4031                  * 01..00  CNCT<1..0> Channel Connection 11=Local Loopback
4032                  */
4033                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4034
4035                 /* degate external TxC clock source */
4036                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4037                 write_control_reg(info);
4038
4039                 /* RXS/TXS (Rx/Tx clock source)
4040                  * 07      Reserved, must be 0
4041                  * 06..04  Clock Source, 100=BRG
4042                  * 03..00  Clock Divisor, 0000=1
4043                  */
4044                 write_reg(info, RXS, 0x40);
4045                 write_reg(info, TXS, 0x40);
4046
4047         } else {
4048                 /* MD2 (Mode Register 2)
4049                  * 01..00  CNCT<1..0> Channel connection, 0=normal
4050                  */
4051                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4052
4053                 /* RXS/TXS (Rx/Tx clock source)
4054                  * 07      Reserved, must be 0
4055                  * 06..04  Clock Source, 000=RxC/TxC Pin
4056                  * 03..00  Clock Divisor, 0000=1
4057                  */
4058                 write_reg(info, RXS, 0x00);
4059                 write_reg(info, TXS, 0x00);
4060         }
4061
4062         /* set LinkSpeed if available, otherwise default to 2Mbps */
4063         if (info->params.clock_speed)
4064                 set_rate(info, info->params.clock_speed);
4065         else
4066                 set_rate(info, 3686400);
4067 }
4068
4069 /* Set the baud rate register to the desired speed
4070  *
4071  *      data_rate       data rate of clock in bits per second
4072  *                      A data rate of 0 disables the AUX clock.
4073  */
4074 static void set_rate( SLMP_INFO *info, u32 data_rate )
4075 {
4076         u32 TMCValue;
4077         unsigned char BRValue;
4078         u32 Divisor=0;
4079
4080         /* fBRG = fCLK/(TMC * 2^BR)
4081          */
4082         if (data_rate != 0) {
4083                 Divisor = 14745600/data_rate;
4084                 if (!Divisor)
4085                         Divisor = 1;
4086
4087                 TMCValue = Divisor;
4088
4089                 BRValue = 0;
4090                 if (TMCValue != 1 && TMCValue != 2) {
4091                         /* BRValue of 0 provides 50/50 duty cycle *only* when
4092                          * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4093                          * 50/50 duty cycle.
4094                          */
4095                         BRValue = 1;
4096                         TMCValue >>= 1;
4097                 }
4098
4099                 /* while TMCValue is too big for TMC register, divide
4100                  * by 2 and increment BR exponent.
4101                  */
4102                 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4103                         TMCValue >>= 1;
4104
4105                 write_reg(info, TXS,
4106                         (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4107                 write_reg(info, RXS,
4108                         (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4109                 write_reg(info, TMC, (unsigned char)TMCValue);
4110         }
4111         else {
4112                 write_reg(info, TXS,0);
4113                 write_reg(info, RXS,0);
4114                 write_reg(info, TMC, 0);
4115         }
4116 }
4117
4118 /* Disable receiver
4119  */
4120 static void rx_stop(SLMP_INFO *info)
4121 {
4122         if (debug_level >= DEBUG_LEVEL_ISR)
4123                 printk("%s(%d):%s rx_stop()\n",
4124                          __FILE__,__LINE__, info->device_name );
4125
4126         write_reg(info, CMD, RXRESET);
4127
4128         info->ie0_value &= ~RXRDYE;
4129         write_reg(info, IE0, info->ie0_value);  /* disable Rx data interrupts */
4130
4131         write_reg(info, RXDMA + DSR, 0);        /* disable Rx DMA */
4132         write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4133         write_reg(info, RXDMA + DIR, 0);        /* disable Rx DMA interrupts */
4134
4135         info->rx_enabled = false;
4136         info->rx_overflow = false;
4137 }
4138
4139 /* enable the receiver
4140  */
4141 static void rx_start(SLMP_INFO *info)
4142 {
4143         int i;
4144
4145         if (debug_level >= DEBUG_LEVEL_ISR)
4146                 printk("%s(%d):%s rx_start()\n",
4147                          __FILE__,__LINE__, info->device_name );
4148
4149         write_reg(info, CMD, RXRESET);
4150
4151         if ( info->params.mode == MGSL_MODE_HDLC ) {
4152                 /* HDLC, disabe IRQ on rxdata */
4153                 info->ie0_value &= ~RXRDYE;
4154                 write_reg(info, IE0, info->ie0_value);
4155
4156                 /* Reset all Rx DMA buffers and program rx dma */
4157                 write_reg(info, RXDMA + DSR, 0);                /* disable Rx DMA */
4158                 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4159
4160                 for (i = 0; i < info->rx_buf_count; i++) {
4161                         info->rx_buf_list[i].status = 0xff;
4162
4163                         // throttle to 4 shared memory writes at a time to prevent
4164                         // hogging local bus (keep latency time for DMA requests low).
4165                         if (!(i % 4))
4166                                 read_status_reg(info);
4167                 }
4168                 info->current_rx_buf = 0;
4169
4170                 /* set current/1st descriptor address */
4171                 write_reg16(info, RXDMA + CDA,
4172                         info->rx_buf_list_ex[0].phys_entry);
4173
4174                 /* set new last rx descriptor address */
4175                 write_reg16(info, RXDMA + EDA,
4176                         info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4177
4178                 /* set buffer length (shared by all rx dma data buffers) */
4179                 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4180
4181                 write_reg(info, RXDMA + DIR, 0x60);     /* enable Rx DMA interrupts (EOM/BOF) */
4182                 write_reg(info, RXDMA + DSR, 0xf2);     /* clear Rx DMA IRQs, enable Rx DMA */
4183         } else {
4184                 /* async, enable IRQ on rxdata */
4185                 info->ie0_value |= RXRDYE;
4186                 write_reg(info, IE0, info->ie0_value);
4187         }
4188
4189         write_reg(info, CMD, RXENABLE);
4190
4191         info->rx_overflow = false;
4192         info->rx_enabled = true;
4193 }
4194
4195 /* Enable the transmitter and send a transmit frame if
4196  * one is loaded in the DMA buffers.
4197  */
4198 static void tx_start(SLMP_INFO *info)
4199 {
4200         if (debug_level >= DEBUG_LEVEL_ISR)
4201                 printk("%s(%d):%s tx_start() tx_count=%d\n",
4202                          __FILE__,__LINE__, info->device_name,info->tx_count );
4203
4204         if (!info->tx_enabled ) {
4205                 write_reg(info, CMD, TXRESET);
4206                 write_reg(info, CMD, TXENABLE);
4207                 info->tx_enabled = true;
4208         }
4209
4210         if ( info->tx_count ) {
4211
4212                 /* If auto RTS enabled and RTS is inactive, then assert */
4213                 /* RTS and set a flag indicating that the driver should */
4214                 /* negate RTS when the transmission completes. */
4215
4216                 info->drop_rts_on_tx_done = false;
4217
4218                 if (info->params.mode != MGSL_MODE_ASYNC) {
4219
4220                         if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4221                                 get_signals( info );
4222                                 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4223                                         info->serial_signals |= SerialSignal_RTS;
4224                                         set_signals( info );
4225                                         info->drop_rts_on_tx_done = true;
4226                                 }
4227                         }
4228
4229                         write_reg16(info, TRC0,
4230                                 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4231
4232                         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4233                         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4234
4235                         /* set TX CDA (current descriptor address) */
4236                         write_reg16(info, TXDMA + CDA,
4237                                 info->tx_buf_list_ex[0].phys_entry);
4238
4239                         /* set TX EDA (last descriptor address) */
4240                         write_reg16(info, TXDMA + EDA,
4241                                 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4242
4243                         /* enable underrun IRQ */
4244                         info->ie1_value &= ~IDLE;
4245                         info->ie1_value |= UDRN;
4246                         write_reg(info, IE1, info->ie1_value);
4247                         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4248
4249                         write_reg(info, TXDMA + DIR, 0x40);             /* enable Tx DMA interrupts (EOM) */
4250                         write_reg(info, TXDMA + DSR, 0xf2);             /* clear Tx DMA IRQs, enable Tx DMA */
4251
4252                         mod_timer(&info->tx_timer, jiffies +
4253                                         msecs_to_jiffies(5000));
4254                 }
4255                 else {
4256                         tx_load_fifo(info);
4257                         /* async, enable IRQ on txdata */
4258                         info->ie0_value |= TXRDYE;
4259                         write_reg(info, IE0, info->ie0_value);
4260                 }
4261
4262                 info->tx_active = true;
4263         }
4264 }
4265
4266 /* stop the transmitter and DMA
4267  */
4268 static void tx_stop( SLMP_INFO *info )
4269 {
4270         if (debug_level >= DEBUG_LEVEL_ISR)
4271                 printk("%s(%d):%s tx_stop()\n",
4272                          __FILE__,__LINE__, info->device_name );
4273
4274         del_timer(&info->tx_timer);
4275
4276         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4277         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4278
4279         write_reg(info, CMD, TXRESET);
4280
4281         info->ie1_value &= ~(UDRN + IDLE);
4282         write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
4283         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
4284
4285         info->ie0_value &= ~TXRDYE;
4286         write_reg(info, IE0, info->ie0_value);  /* disable tx data interrupts */
4287
4288         info->tx_enabled = false;
4289         info->tx_active = false;
4290 }
4291
4292 /* Fill the transmit FIFO until the FIFO is full or
4293  * there is no more data to load.
4294  */
4295 static void tx_load_fifo(SLMP_INFO *info)
4296 {
4297         u8 TwoBytes[2];
4298
4299         /* do nothing is now tx data available and no XON/XOFF pending */
4300
4301         if ( !info->tx_count && !info->x_char )
4302                 return;
4303
4304         /* load the Transmit FIFO until FIFOs full or all data sent */
4305
4306         while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4307
4308                 /* there is more space in the transmit FIFO and */
4309                 /* there is more data in transmit buffer */
4310
4311                 if ( (info->tx_count > 1) && !info->x_char ) {
4312                         /* write 16-bits */
4313                         TwoBytes[0] = info->tx_buf[info->tx_get++];
4314                         if (info->tx_get >= info->max_frame_size)
4315                                 info->tx_get -= info->max_frame_size;
4316                         TwoBytes[1] = info->tx_buf[info->tx_get++];
4317                         if (info->tx_get >= info->max_frame_size)
4318                                 info->tx_get -= info->max_frame_size;
4319
4320                         write_reg16(info, TRB, *((u16 *)TwoBytes));
4321
4322                         info->tx_count -= 2;
4323                         info->icount.tx += 2;
4324                 } else {
4325                         /* only 1 byte left to transmit or 1 FIFO slot left */
4326
4327                         if (info->x_char) {
4328                                 /* transmit pending high priority char */
4329                                 write_reg(info, TRB, info->x_char);
4330                                 info->x_char = 0;
4331                         } else {
4332                                 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4333                                 if (info->tx_get >= info->max_frame_size)
4334                                         info->tx_get -= info->max_frame_size;
4335                                 info->tx_count--;
4336                         }
4337                         info->icount.tx++;
4338                 }
4339         }
4340 }
4341
4342 /* Reset a port to a known state
4343  */
4344 static void reset_port(SLMP_INFO *info)
4345 {
4346         if (info->sca_base) {
4347
4348                 tx_stop(info);
4349                 rx_stop(info);
4350
4351                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4352                 set_signals(info);
4353
4354                 /* disable all port interrupts */
4355                 info->ie0_value = 0;
4356                 info->ie1_value = 0;
4357                 info->ie2_value = 0;
4358                 write_reg(info, IE0, info->ie0_value);
4359                 write_reg(info, IE1, info->ie1_value);
4360                 write_reg(info, IE2, info->ie2_value);
4361
4362                 write_reg(info, CMD, CHRESET);
4363         }
4364 }
4365
4366 /* Reset all the ports to a known state.
4367  */
4368 static void reset_adapter(SLMP_INFO *info)
4369 {
4370         int i;
4371
4372         for ( i=0; i < SCA_MAX_PORTS; ++i) {
4373                 if (info->port_array[i])
4374                         reset_port(info->port_array[i]);
4375         }
4376 }
4377
4378 /* Program port for asynchronous communications.
4379  */
4380 static void async_mode(SLMP_INFO *info)
4381 {
4382
4383         unsigned char RegValue;
4384
4385         tx_stop(info);
4386         rx_stop(info);
4387
4388         /* MD0, Mode Register 0
4389          *
4390          * 07..05  PRCTL<2..0>, Protocol Mode, 000=async
4391          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4392          * 03      Reserved, must be 0
4393          * 02      CRCCC, CRC Calculation, 0=disabled
4394          * 01..00  STOP<1..0> Stop bits (00=1,10=2)
4395          *
4396          * 0000 0000
4397          */
4398         RegValue = 0x00;
4399         if (info->params.stop_bits != 1)
4400                 RegValue |= BIT1;
4401         write_reg(info, MD0, RegValue);
4402
4403         /* MD1, Mode Register 1
4404          *
4405          * 07..06  BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4406          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4407          * 03..02  RXCHR<1..0>, rx char size
4408          * 01..00  PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4409          *
4410          * 0100 0000
4411          */
4412         RegValue = 0x40;
4413         switch (info->params.data_bits) {
4414         case 7: RegValue |= BIT4 + BIT2; break;
4415         case 6: RegValue |= BIT5 + BIT3; break;
4416         case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4417         }
4418         if (info->params.parity != ASYNC_PARITY_NONE) {
4419                 RegValue |= BIT1;
4420                 if (info->params.parity == ASYNC_PARITY_ODD)
4421                         RegValue |= BIT0;
4422         }
4423         write_reg(info, MD1, RegValue);
4424
4425         /* MD2, Mode Register 2
4426          *
4427          * 07..02  Reserved, must be 0
4428          * 01..00  CNCT<1..0> Channel connection, 00=normal 11=local loopback
4429          *
4430          * 0000 0000
4431          */
4432         RegValue = 0x00;
4433         if (info->params.loopback)
4434                 RegValue |= (BIT1 + BIT0);
4435         write_reg(info, MD2, RegValue);
4436
4437         /* RXS, Receive clock source
4438          *
4439          * 07      Reserved, must be 0
4440          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4441          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4442          */
4443         RegValue=BIT6;
4444         write_reg(info, RXS, RegValue);
4445
4446         /* TXS, Transmit clock source
4447          *
4448          * 07      Reserved, must be 0
4449          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4450          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4451          */
4452         RegValue=BIT6;
4453         write_reg(info, TXS, RegValue);
4454
4455         /* Control Register
4456          *
4457          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4458          */
4459         info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4460         write_control_reg(info);
4461
4462         tx_set_idle(info);
4463
4464         /* RRC Receive Ready Control 0
4465          *
4466          * 07..05  Reserved, must be 0
4467          * 04..00  RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4468          */
4469         write_reg(info, RRC, 0x00);
4470
4471         /* TRC0 Transmit Ready Control 0
4472          *
4473          * 07..05  Reserved, must be 0
4474          * 04..00  TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4475          */
4476         write_reg(info, TRC0, 0x10);
4477
4478         /* TRC1 Transmit Ready Control 1
4479          *
4480          * 07..05  Reserved, must be 0
4481          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4482          */
4483         write_reg(info, TRC1, 0x1e);
4484
4485         /* CTL, MSCI control register
4486          *
4487          * 07..06  Reserved, set to 0
4488          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4489          * 04      IDLC, idle control, 0=mark 1=idle register
4490          * 03      BRK, break, 0=off 1 =on (async)
4491          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4492          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4493          * 00      RTS, RTS output control, 0=active 1=inactive
4494          *
4495          * 0001 0001
4496          */
4497         RegValue = 0x10;
4498         if (!(info->serial_signals & SerialSignal_RTS))
4499                 RegValue |= 0x01;
4500         write_reg(info, CTL, RegValue);
4501
4502         /* enable status interrupts */
4503         info->ie0_value |= TXINTE + RXINTE;
4504         write_reg(info, IE0, info->ie0_value);
4505
4506         /* enable break detect interrupt */
4507         info->ie1_value = BRKD;
4508         write_reg(info, IE1, info->ie1_value);
4509
4510         /* enable rx overrun interrupt */
4511         info->ie2_value = OVRN;
4512         write_reg(info, IE2, info->ie2_value);
4513
4514         set_rate( info, info->params.data_rate * 16 );
4515 }
4516
4517 /* Program the SCA for HDLC communications.
4518  */
4519 static void hdlc_mode(SLMP_INFO *info)
4520 {
4521         unsigned char RegValue;
4522         u32 DpllDivisor;
4523
4524         // Can't use DPLL because SCA outputs recovered clock on RxC when
4525         // DPLL mode selected. This causes output contention with RxC receiver.
4526         // Use of DPLL would require external hardware to disable RxC receiver
4527         // when DPLL mode selected.
4528         info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4529
4530         /* disable DMA interrupts */
4531         write_reg(info, TXDMA + DIR, 0);
4532         write_reg(info, RXDMA + DIR, 0);
4533
4534         /* MD0, Mode Register 0
4535          *
4536          * 07..05  PRCTL<2..0>, Protocol Mode, 100=HDLC
4537          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4538          * 03      Reserved, must be 0
4539          * 02      CRCCC, CRC Calculation, 1=enabled
4540          * 01      CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4541          * 00      CRC0, CRC initial value, 1 = all 1s
4542          *
4543          * 1000 0001
4544          */
4545         RegValue = 0x81;
4546         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4547                 RegValue |= BIT4;
4548         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4549                 RegValue |= BIT4;
4550         if (info->params.crc_type == HDLC_CRC_16_CCITT)
4551                 RegValue |= BIT2 + BIT1;
4552         write_reg(info, MD0, RegValue);
4553
4554         /* MD1, Mode Register 1
4555          *
4556          * 07..06  ADDRS<1..0>, Address detect, 00=no addr check
4557          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits
4558          * 03..02  RXCHR<1..0>, rx char size, 00=8 bits
4559          * 01..00  PMPM<1..0>, Parity mode, 00=no parity
4560          *
4561          * 0000 0000
4562          */
4563         RegValue = 0x00;
4564         write_reg(info, MD1, RegValue);
4565
4566         /* MD2, Mode Register 2
4567          *
4568          * 07      NRZFM, 0=NRZ, 1=FM
4569          * 06..05  CODE<1..0> Encoding, 00=NRZ
4570          * 04..03  DRATE<1..0> DPLL Divisor, 00=8
4571          * 02      Reserved, must be 0
4572          * 01..00  CNCT<1..0> Channel connection, 0=normal
4573          *
4574          * 0000 0000
4575          */
4576         RegValue = 0x00;
4577         switch(info->params.encoding) {
4578         case HDLC_ENCODING_NRZI:          RegValue |= BIT5; break;
4579         case HDLC_ENCODING_BIPHASE_MARK:  RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4580         case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4581         case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break;      /* aka Manchester */
4582 #if 0
4583         case HDLC_ENCODING_NRZB:                                        /* not supported */
4584         case HDLC_ENCODING_NRZI_MARK:                                   /* not supported */
4585         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:                          /* not supported */
4586 #endif
4587         }
4588         if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4589                 DpllDivisor = 16;
4590                 RegValue |= BIT3;
4591         } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4592                 DpllDivisor = 8;
4593         } else {
4594                 DpllDivisor = 32;
4595                 RegValue |= BIT4;
4596         }
4597         write_reg(info, MD2, RegValue);
4598
4599
4600         /* RXS, Receive clock source
4601          *
4602          * 07      Reserved, must be 0
4603          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4604          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4605          */
4606         RegValue=0;
4607         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4608                 RegValue |= BIT6;
4609         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4610                 RegValue |= BIT6 + BIT5;
4611         write_reg(info, RXS, RegValue);
4612
4613         /* TXS, Transmit clock source
4614          *
4615          * 07      Reserved, must be 0
4616          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4617          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4618          */
4619         RegValue=0;
4620         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4621                 RegValue |= BIT6;
4622         if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4623                 RegValue |= BIT6 + BIT5;
4624         write_reg(info, TXS, RegValue);
4625
4626         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4627                 set_rate(info, info->params.clock_speed * DpllDivisor);
4628         else
4629                 set_rate(info, info->params.clock_speed);
4630
4631         /* GPDATA (General Purpose I/O Data Register)
4632          *
4633          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4634          */
4635         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4636                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4637         else
4638                 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4639         write_control_reg(info);
4640
4641         /* RRC Receive Ready Control 0
4642          *
4643          * 07..05  Reserved, must be 0
4644          * 04..00  RRC<4..0> Rx FIFO trigger active
4645          */
4646         write_reg(info, RRC, rx_active_fifo_level);
4647
4648         /* TRC0 Transmit Ready Control 0
4649          *
4650          * 07..05  Reserved, must be 0
4651          * 04..00  TRC<4..0> Tx FIFO trigger active
4652          */
4653         write_reg(info, TRC0, tx_active_fifo_level);
4654
4655         /* TRC1 Transmit Ready Control 1
4656          *
4657          * 07..05  Reserved, must be 0
4658          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4659          */
4660         write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4661
4662         /* DMR, DMA Mode Register
4663          *
4664          * 07..05  Reserved, must be 0
4665          * 04      TMOD, Transfer Mode: 1=chained-block
4666          * 03      Reserved, must be 0
4667          * 02      NF, Number of Frames: 1=multi-frame
4668          * 01      CNTE, Frame End IRQ Counter enable: 0=disabled
4669          * 00      Reserved, must be 0
4670          *
4671          * 0001 0100
4672          */
4673         write_reg(info, TXDMA + DMR, 0x14);
4674         write_reg(info, RXDMA + DMR, 0x14);
4675
4676         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4677         write_reg(info, RXDMA + CPB,
4678                 (unsigned char)(info->buffer_list_phys >> 16));
4679
4680         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4681         write_reg(info, TXDMA + CPB,
4682                 (unsigned char)(info->buffer_list_phys >> 16));
4683
4684         /* enable status interrupts. other code enables/disables
4685          * the individual sources for these two interrupt classes.
4686          */
4687         info->ie0_value |= TXINTE + RXINTE;
4688         write_reg(info, IE0, info->ie0_value);
4689
4690         /* CTL, MSCI control register
4691          *
4692          * 07..06  Reserved, set to 0
4693          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4694          * 04      IDLC, idle control, 0=mark 1=idle register
4695          * 03      BRK, break, 0=off 1 =on (async)
4696          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4697          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4698          * 00      RTS, RTS output control, 0=active 1=inactive
4699          *
4700          * 0001 0001
4701          */
4702         RegValue = 0x10;
4703         if (!(info->serial_signals & SerialSignal_RTS))
4704                 RegValue |= 0x01;
4705         write_reg(info, CTL, RegValue);
4706
4707         /* preamble not supported ! */
4708
4709         tx_set_idle(info);
4710         tx_stop(info);
4711         rx_stop(info);
4712
4713         set_rate(info, info->params.clock_speed);
4714
4715         if (info->params.loopback)
4716                 enable_loopback(info,1);
4717 }
4718
4719 /* Set the transmit HDLC idle mode
4720  */
4721 static void tx_set_idle(SLMP_INFO *info)
4722 {
4723         unsigned char RegValue = 0xff;
4724
4725         /* Map API idle mode to SCA register bits */
4726         switch(info->idle_mode) {
4727         case HDLC_TXIDLE_FLAGS:                 RegValue = 0x7e; break;
4728         case HDLC_TXIDLE_ALT_ZEROS_ONES:        RegValue = 0xaa; break;
4729         case HDLC_TXIDLE_ZEROS:                 RegValue = 0x00; break;
4730         case HDLC_TXIDLE_ONES:                  RegValue = 0xff; break;
4731         case HDLC_TXIDLE_ALT_MARK_SPACE:        RegValue = 0xaa; break;
4732         case HDLC_TXIDLE_SPACE:                 RegValue = 0x00; break;
4733         case HDLC_TXIDLE_MARK:                  RegValue = 0xff; break;
4734         }
4735
4736         write_reg(info, IDL, RegValue);
4737 }
4738
4739 /* Query the adapter for the state of the V24 status (input) signals.
4740  */
4741 static void get_signals(SLMP_INFO *info)
4742 {
4743         u16 status = read_reg(info, SR3);
4744         u16 gpstatus = read_status_reg(info);
4745         u16 testbit;
4746
4747         /* clear all serial signals except DTR and RTS */
4748         info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4749
4750         /* set serial signal bits to reflect MISR */
4751
4752         if (!(status & BIT3))
4753                 info->serial_signals |= SerialSignal_CTS;
4754
4755         if ( !(status & BIT2))
4756                 info->serial_signals |= SerialSignal_DCD;
4757
4758         testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4759         if (!(gpstatus & testbit))
4760                 info->serial_signals |= SerialSignal_RI;
4761
4762         testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4763         if (!(gpstatus & testbit))
4764                 info->serial_signals |= SerialSignal_DSR;
4765 }
4766
4767 /* Set the state of DTR and RTS based on contents of
4768  * serial_signals member of device context.
4769  */
4770 static void set_signals(SLMP_INFO *info)
4771 {
4772         unsigned char RegValue;
4773         u16 EnableBit;
4774
4775         RegValue = read_reg(info, CTL);
4776         if (info->serial_signals & SerialSignal_RTS)
4777                 RegValue &= ~BIT0;
4778         else
4779                 RegValue |= BIT0;
4780         write_reg(info, CTL, RegValue);
4781
4782         // Port 0..3 DTR is ctrl reg <1,3,5,7>
4783         EnableBit = BIT1 << (info->port_num*2);
4784         if (info->serial_signals & SerialSignal_DTR)
4785                 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4786         else
4787                 info->port_array[0]->ctrlreg_value |= EnableBit;
4788         write_control_reg(info);
4789 }
4790
4791 /*******************/
4792 /* DMA Buffer Code */
4793 /*******************/
4794
4795 /* Set the count for all receive buffers to SCABUFSIZE
4796  * and set the current buffer to the first buffer. This effectively
4797  * makes all buffers free and discards any data in buffers.
4798  */
4799 static void rx_reset_buffers(SLMP_INFO *info)
4800 {
4801         rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4802 }
4803
4804 /* Free the buffers used by a received frame
4805  *
4806  * info   pointer to device instance data
4807  * first  index of 1st receive buffer of frame
4808  * last   index of last receive buffer of frame
4809  */
4810 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4811 {
4812         bool done = false;
4813
4814         while(!done) {
4815                 /* reset current buffer for reuse */
4816                 info->rx_buf_list[first].status = 0xff;
4817
4818                 if (first == last) {
4819                         done = true;
4820                         /* set new last rx descriptor address */
4821                         write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4822                 }
4823
4824                 first++;
4825                 if (first == info->rx_buf_count)
4826                         first = 0;
4827         }
4828
4829         /* set current buffer to next buffer after last buffer of frame */
4830         info->current_rx_buf = first;
4831 }
4832
4833 /* Return a received frame from the receive DMA buffers.
4834  * Only frames received without errors are returned.
4835  *
4836  * Return Value:        true if frame returned, otherwise false
4837  */
4838 static bool rx_get_frame(SLMP_INFO *info)
4839 {
4840         unsigned int StartIndex, EndIndex;      /* index of 1st and last buffers of Rx frame */
4841         unsigned short status;
4842         unsigned int framesize = 0;
4843         bool ReturnCode = false;
4844         unsigned long flags;
4845         struct tty_struct *tty = info->port.tty;
4846         unsigned char addr_field = 0xff;
4847         SCADESC *desc;
4848         SCADESC_EX *desc_ex;
4849
4850 CheckAgain:
4851         /* assume no frame returned, set zero length */
4852         framesize = 0;
4853         addr_field = 0xff;
4854
4855         /*
4856          * current_rx_buf points to the 1st buffer of the next available
4857          * receive frame. To find the last buffer of the frame look for
4858          * a non-zero status field in the buffer entries. (The status
4859          * field is set by the 16C32 after completing a receive frame.
4860          */
4861         StartIndex = EndIndex = info->current_rx_buf;
4862
4863         for ( ;; ) {
4864                 desc = &info->rx_buf_list[EndIndex];
4865                 desc_ex = &info->rx_buf_list_ex[EndIndex];
4866
4867                 if (desc->status == 0xff)
4868                         goto Cleanup;   /* current desc still in use, no frames available */
4869
4870                 if (framesize == 0 && info->params.addr_filter != 0xff)
4871                         addr_field = desc_ex->virt_addr[0];
4872
4873                 framesize += desc->length;
4874
4875                 /* Status != 0 means last buffer of frame */
4876                 if (desc->status)
4877                         break;
4878
4879                 EndIndex++;
4880                 if (EndIndex == info->rx_buf_count)
4881                         EndIndex = 0;
4882
4883                 if (EndIndex == info->current_rx_buf) {
4884                         /* all buffers have been 'used' but none mark      */
4885                         /* the end of a frame. Reset buffers and receiver. */
4886                         if ( info->rx_enabled ){
4887                                 spin_lock_irqsave(&info->lock,flags);
4888                                 rx_start(info);
4889                                 spin_unlock_irqrestore(&info->lock,flags);
4890                         }
4891                         goto Cleanup;
4892                 }
4893
4894         }
4895
4896         /* check status of receive frame */
4897
4898         /* frame status is byte stored after frame data
4899          *
4900          * 7 EOM (end of msg), 1 = last buffer of frame
4901          * 6 Short Frame, 1 = short frame
4902          * 5 Abort, 1 = frame aborted
4903          * 4 Residue, 1 = last byte is partial
4904          * 3 Overrun, 1 = overrun occurred during frame reception
4905          * 2 CRC,     1 = CRC error detected
4906          *
4907          */
4908         status = desc->status;
4909
4910         /* ignore CRC bit if not using CRC (bit is undefined) */
4911         /* Note:CRC is not save to data buffer */
4912         if (info->params.crc_type == HDLC_CRC_NONE)
4913                 status &= ~BIT2;
4914
4915         if (framesize == 0 ||
4916                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4917                 /* discard 0 byte frames, this seems to occur sometime
4918                  * when remote is idling flags.
4919                  */
4920                 rx_free_frame_buffers(info, StartIndex, EndIndex);
4921                 goto CheckAgain;
4922         }
4923
4924         if (framesize < 2)
4925                 status |= BIT6;
4926
4927         if (status & (BIT6+BIT5+BIT3+BIT2)) {
4928                 /* received frame has errors,
4929                  * update counts and mark frame size as 0
4930                  */
4931                 if (status & BIT6)
4932                         info->icount.rxshort++;
4933                 else if (status & BIT5)
4934                         info->icount.rxabort++;
4935                 else if (status & BIT3)
4936                         info->icount.rxover++;
4937                 else
4938                         info->icount.rxcrc++;
4939
4940                 framesize = 0;
4941 #if SYNCLINK_GENERIC_HDLC
4942                 {
4943                         info->netdev->stats.rx_errors++;
4944                         info->netdev->stats.rx_frame_errors++;
4945                 }
4946 #endif
4947         }
4948
4949         if ( debug_level >= DEBUG_LEVEL_BH )
4950                 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4951                         __FILE__,__LINE__,info->device_name,status,framesize);
4952
4953         if ( debug_level >= DEBUG_LEVEL_DATA )
4954                 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4955                         min_t(int, framesize,SCABUFSIZE),0);
4956
4957         if (framesize) {
4958                 if (framesize > info->max_frame_size)
4959                         info->icount.rxlong++;
4960                 else {
4961                         /* copy dma buffer(s) to contiguous intermediate buffer */
4962                         int copy_count = framesize;
4963                         int index = StartIndex;
4964                         unsigned char *ptmp = info->tmp_rx_buf;
4965                         info->tmp_rx_buf_count = framesize;
4966
4967                         info->icount.rxok++;
4968
4969                         while(copy_count) {
4970                                 int partial_count = min(copy_count,SCABUFSIZE);
4971                                 memcpy( ptmp,
4972                                         info->rx_buf_list_ex[index].virt_addr,
4973                                         partial_count );
4974                                 ptmp += partial_count;
4975                                 copy_count -= partial_count;
4976
4977                                 if ( ++index == info->rx_buf_count )
4978                                         index = 0;
4979                         }
4980
4981 #if SYNCLINK_GENERIC_HDLC
4982                         if (info->netcount)
4983                                 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
4984                         else
4985 #endif
4986                                 ldisc_receive_buf(tty,info->tmp_rx_buf,
4987                                                   info->flag_buf, framesize);
4988                 }
4989         }
4990         /* Free the buffers used by this frame. */
4991         rx_free_frame_buffers( info, StartIndex, EndIndex );
4992
4993         ReturnCode = true;
4994
4995 Cleanup:
4996         if ( info->rx_enabled && info->rx_overflow ) {
4997                 /* Receiver is enabled, but needs to restarted due to
4998                  * rx buffer overflow. If buffers are empty, restart receiver.
4999                  */
5000                 if (info->rx_buf_list[EndIndex].status == 0xff) {
5001                         spin_lock_irqsave(&info->lock,flags);
5002                         rx_start(info);
5003                         spin_unlock_irqrestore(&info->lock,flags);
5004                 }
5005         }
5006
5007         return ReturnCode;
5008 }
5009
5010 /* load the transmit DMA buffer with data
5011  */
5012 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5013 {
5014         unsigned short copy_count;
5015         unsigned int i = 0;
5016         SCADESC *desc;
5017         SCADESC_EX *desc_ex;
5018
5019         if ( debug_level >= DEBUG_LEVEL_DATA )
5020                 trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
5021
5022         /* Copy source buffer to one or more DMA buffers, starting with
5023          * the first transmit dma buffer.
5024          */
5025         for(i=0;;)
5026         {
5027                 copy_count = min_t(unsigned short,count,SCABUFSIZE);
5028
5029                 desc = &info->tx_buf_list[i];
5030                 desc_ex = &info->tx_buf_list_ex[i];
5031
5032                 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5033
5034                 desc->length = copy_count;
5035                 desc->status = 0;
5036
5037                 buf += copy_count;
5038                 count -= copy_count;
5039
5040                 if (!count)
5041                         break;
5042
5043                 i++;
5044                 if (i >= info->tx_buf_count)
5045                         i = 0;
5046         }
5047
5048         info->tx_buf_list[i].status = 0x81;     /* set EOM and EOT status */
5049         info->last_tx_buf = ++i;
5050 }
5051
5052 static bool register_test(SLMP_INFO *info)
5053 {
5054         static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5055         static unsigned int count = ARRAY_SIZE(testval);
5056         unsigned int i;
5057         bool rc = true;
5058         unsigned long flags;
5059
5060         spin_lock_irqsave(&info->lock,flags);
5061         reset_port(info);
5062
5063         /* assume failure */
5064         info->init_error = DiagStatus_AddressFailure;
5065
5066         /* Write bit patterns to various registers but do it out of */
5067         /* sync, then read back and verify values. */
5068
5069         for (i = 0 ; i < count ; i++) {
5070                 write_reg(info, TMC, testval[i]);
5071                 write_reg(info, IDL, testval[(i+1)%count]);
5072                 write_reg(info, SA0, testval[(i+2)%count]);
5073                 write_reg(info, SA1, testval[(i+3)%count]);
5074
5075                 if ( (read_reg(info, TMC) != testval[i]) ||
5076                           (read_reg(info, IDL) != testval[(i+1)%count]) ||
5077                           (read_reg(info, SA0) != testval[(i+2)%count]) ||
5078                           (read_reg(info, SA1) != testval[(i+3)%count]) )
5079                 {
5080                         rc = false;
5081                         break;
5082                 }
5083         }
5084
5085         reset_port(info);
5086         spin_unlock_irqrestore(&info->lock,flags);
5087
5088         return rc;
5089 }
5090
5091 static bool irq_test(SLMP_INFO *info)
5092 {
5093         unsigned long timeout;
5094         unsigned long flags;
5095
5096         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5097
5098         spin_lock_irqsave(&info->lock,flags);
5099         reset_port(info);
5100
5101         /* assume failure */
5102         info->init_error = DiagStatus_IrqFailure;
5103         info->irq_occurred = false;
5104
5105         /* setup timer0 on SCA0 to interrupt */
5106
5107         /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5108         write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5109
5110         write_reg(info, (unsigned char)(timer + TEPR), 0);      /* timer expand prescale */
5111         write_reg16(info, (unsigned char)(timer + TCONR), 1);   /* timer constant */
5112
5113
5114         /* TMCS, Timer Control/Status Register
5115          *
5116          * 07      CMF, Compare match flag (read only) 1=match
5117          * 06      ECMI, CMF Interrupt Enable: 1=enabled
5118          * 05      Reserved, must be 0
5119          * 04      TME, Timer Enable
5120          * 03..00  Reserved, must be 0
5121          *
5122          * 0101 0000
5123          */
5124         write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5125
5126         spin_unlock_irqrestore(&info->lock,flags);
5127
5128         timeout=100;
5129         while( timeout-- && !info->irq_occurred ) {
5130                 msleep_interruptible(10);
5131         }
5132
5133         spin_lock_irqsave(&info->lock,flags);
5134         reset_port(info);
5135         spin_unlock_irqrestore(&info->lock,flags);
5136
5137         return info->irq_occurred;
5138 }
5139
5140 /* initialize individual SCA device (2 ports)
5141  */
5142 static bool sca_init(SLMP_INFO *info)
5143 {
5144         /* set wait controller to single mem partition (low), no wait states */
5145         write_reg(info, PABR0, 0);      /* wait controller addr boundary 0 */
5146         write_reg(info, PABR1, 0);      /* wait controller addr boundary 1 */
5147         write_reg(info, WCRL, 0);       /* wait controller low range */
5148         write_reg(info, WCRM, 0);       /* wait controller mid range */
5149         write_reg(info, WCRH, 0);       /* wait controller high range */
5150
5151         /* DPCR, DMA Priority Control
5152          *
5153          * 07..05  Not used, must be 0
5154          * 04      BRC, bus release condition: 0=all transfers complete
5155          * 03      CCC, channel change condition: 0=every cycle
5156          * 02..00  PR<2..0>, priority 100=round robin
5157          *
5158          * 00000100 = 0x04
5159          */
5160         write_reg(info, DPCR, dma_priority);
5161
5162         /* DMA Master Enable, BIT7: 1=enable all channels */
5163         write_reg(info, DMER, 0x80);
5164
5165         /* enable all interrupt classes */
5166         write_reg(info, IER0, 0xff);    /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5167         write_reg(info, IER1, 0xff);    /* DMIB,DMIA (channels 0-3) */
5168         write_reg(info, IER2, 0xf0);    /* TIRQ (timers 0-3) */
5169
5170         /* ITCR, interrupt control register
5171          * 07      IPC, interrupt priority, 0=MSCI->DMA
5172          * 06..05  IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5173          * 04      VOS, Vector Output, 0=unmodified vector
5174          * 03..00  Reserved, must be 0
5175          */
5176         write_reg(info, ITCR, 0);
5177
5178         return true;
5179 }
5180
5181 /* initialize adapter hardware
5182  */
5183 static bool init_adapter(SLMP_INFO *info)
5184 {
5185         int i;
5186
5187         /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5188         volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5189         u32 readval;
5190
5191         info->misc_ctrl_value |= BIT30;
5192         *MiscCtrl = info->misc_ctrl_value;
5193
5194         /*
5195          * Force at least 170ns delay before clearing
5196          * reset bit. Each read from LCR takes at least
5197          * 30ns so 10 times for 300ns to be safe.
5198          */
5199         for(i=0;i<10;i++)
5200                 readval = *MiscCtrl;
5201
5202         info->misc_ctrl_value &= ~BIT30;
5203         *MiscCtrl = info->misc_ctrl_value;
5204
5205         /* init control reg (all DTRs off, all clksel=input) */
5206         info->ctrlreg_value = 0xaa;
5207         write_control_reg(info);
5208
5209         {
5210                 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5211                 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5212
5213                 switch(read_ahead_count)
5214                 {
5215                 case 16:
5216                         lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5217                         break;
5218                 case 8:
5219                         lcr1_brdr_value |= BIT5 + BIT4;
5220                         break;
5221                 case 4:
5222                         lcr1_brdr_value |= BIT5 + BIT3;
5223                         break;
5224                 case 0:
5225                         lcr1_brdr_value |= BIT5;
5226                         break;
5227                 }
5228
5229                 *LCR1BRDR = lcr1_brdr_value;
5230                 *MiscCtrl = misc_ctrl_value;
5231         }
5232
5233         sca_init(info->port_array[0]);
5234         sca_init(info->port_array[2]);
5235
5236         return true;
5237 }
5238
5239 /* Loopback an HDLC frame to test the hardware
5240  * interrupt and DMA functions.
5241  */
5242 static bool loopback_test(SLMP_INFO *info)
5243 {
5244 #define TESTFRAMESIZE 20
5245
5246         unsigned long timeout;
5247         u16 count = TESTFRAMESIZE;
5248         unsigned char buf[TESTFRAMESIZE];
5249         bool rc = false;
5250         unsigned long flags;
5251
5252         struct tty_struct *oldtty = info->port.tty;
5253         u32 speed = info->params.clock_speed;
5254
5255         info->params.clock_speed = 3686400;
5256         info->port.tty = NULL;
5257
5258         /* assume failure */
5259         info->init_error = DiagStatus_DmaFailure;
5260
5261         /* build and send transmit frame */
5262         for (count = 0; count < TESTFRAMESIZE;++count)
5263                 buf[count] = (unsigned char)count;
5264
5265         memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5266
5267         /* program hardware for HDLC and enabled receiver */
5268         spin_lock_irqsave(&info->lock,flags);
5269         hdlc_mode(info);
5270         enable_loopback(info,1);
5271         rx_start(info);
5272         info->tx_count = count;
5273         tx_load_dma_buffer(info,buf,count);
5274         tx_start(info);
5275         spin_unlock_irqrestore(&info->lock,flags);
5276
5277         /* wait for receive complete */
5278         /* Set a timeout for waiting for interrupt. */
5279         for ( timeout = 100; timeout; --timeout ) {
5280                 msleep_interruptible(10);
5281
5282                 if (rx_get_frame(info)) {
5283                         rc = true;
5284                         break;
5285                 }
5286         }
5287
5288         /* verify received frame length and contents */
5289         if (rc &&
5290             ( info->tmp_rx_buf_count != count ||
5291               memcmp(buf, info->tmp_rx_buf,count))) {
5292                 rc = false;
5293         }
5294
5295         spin_lock_irqsave(&info->lock,flags);
5296         reset_adapter(info);
5297         spin_unlock_irqrestore(&info->lock,flags);
5298
5299         info->params.clock_speed = speed;
5300         info->port.tty = oldtty;
5301
5302         return rc;
5303 }
5304
5305 /* Perform diagnostics on hardware
5306  */
5307 static int adapter_test( SLMP_INFO *info )
5308 {
5309         unsigned long flags;
5310         if ( debug_level >= DEBUG_LEVEL_INFO )
5311                 printk( "%s(%d):Testing device %s\n",
5312                         __FILE__,__LINE__,info->device_name );
5313
5314         spin_lock_irqsave(&info->lock,flags);
5315         init_adapter(info);
5316         spin_unlock_irqrestore(&info->lock,flags);
5317
5318         info->port_array[0]->port_count = 0;
5319
5320         if ( register_test(info->port_array[0]) &&
5321                 register_test(info->port_array[1])) {
5322
5323                 info->port_array[0]->port_count = 2;
5324
5325                 if ( register_test(info->port_array[2]) &&
5326                         register_test(info->port_array[3]) )
5327                         info->port_array[0]->port_count += 2;
5328         }
5329         else {
5330                 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5331                         __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5332                 return -ENODEV;
5333         }
5334
5335         if ( !irq_test(info->port_array[0]) ||
5336                 !irq_test(info->port_array[1]) ||
5337                  (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5338                  (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5339                 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5340                         __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5341                 return -ENODEV;
5342         }
5343
5344         if (!loopback_test(info->port_array[0]) ||
5345                 !loopback_test(info->port_array[1]) ||
5346                  (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5347                  (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5348                 printk( "%s(%d):DMA test failure for device %s\n",
5349                         __FILE__,__LINE__,info->device_name);
5350                 return -ENODEV;
5351         }
5352
5353         if ( debug_level >= DEBUG_LEVEL_INFO )
5354                 printk( "%s(%d):device %s passed diagnostics\n",
5355                         __FILE__,__LINE__,info->device_name );
5356
5357         info->port_array[0]->init_error = 0;
5358         info->port_array[1]->init_error = 0;
5359         if ( info->port_count > 2 ) {
5360                 info->port_array[2]->init_error = 0;
5361                 info->port_array[3]->init_error = 0;
5362         }
5363
5364         return 0;
5365 }
5366
5367 /* Test the shared memory on a PCI adapter.
5368  */
5369 static bool memory_test(SLMP_INFO *info)
5370 {
5371         static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5372                 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5373         unsigned long count = ARRAY_SIZE(testval);
5374         unsigned long i;
5375         unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5376         unsigned long * addr = (unsigned long *)info->memory_base;
5377
5378         /* Test data lines with test pattern at one location. */
5379
5380         for ( i = 0 ; i < count ; i++ ) {
5381                 *addr = testval[i];
5382                 if ( *addr != testval[i] )
5383                         return false;
5384         }
5385
5386         /* Test address lines with incrementing pattern over */
5387         /* entire address range. */
5388
5389         for ( i = 0 ; i < limit ; i++ ) {
5390                 *addr = i * 4;
5391                 addr++;
5392         }
5393
5394         addr = (unsigned long *)info->memory_base;
5395
5396         for ( i = 0 ; i < limit ; i++ ) {
5397                 if ( *addr != i * 4 )
5398                         return false;
5399                 addr++;
5400         }
5401
5402         memset( info->memory_base, 0, SCA_MEM_SIZE );
5403         return true;
5404 }
5405
5406 /* Load data into PCI adapter shared memory.
5407  *
5408  * The PCI9050 releases control of the local bus
5409  * after completing the current read or write operation.
5410  *
5411  * While the PCI9050 write FIFO not empty, the
5412  * PCI9050 treats all of the writes as a single transaction
5413  * and does not release the bus. This causes DMA latency problems
5414  * at high speeds when copying large data blocks to the shared memory.
5415  *
5416  * This function breaks a write into multiple transations by
5417  * interleaving a read which flushes the write FIFO and 'completes'
5418  * the write transation. This allows any pending DMA request to gain control
5419  * of the local bus in a timely fasion.
5420  */
5421 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5422 {
5423         /* A load interval of 16 allows for 4 32-bit writes at */
5424         /* 136ns each for a maximum latency of 542ns on the local bus.*/
5425
5426         unsigned short interval = count / sca_pci_load_interval;
5427         unsigned short i;
5428
5429         for ( i = 0 ; i < interval ; i++ )
5430         {
5431                 memcpy(dest, src, sca_pci_load_interval);
5432                 read_status_reg(info);
5433                 dest += sca_pci_load_interval;
5434                 src += sca_pci_load_interval;
5435         }
5436
5437         memcpy(dest, src, count % sca_pci_load_interval);
5438 }
5439
5440 static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5441 {
5442         int i;
5443         int linecount;
5444         if (xmit)
5445                 printk("%s tx data:\n",info->device_name);
5446         else
5447                 printk("%s rx data:\n",info->device_name);
5448
5449         while(count) {
5450                 if (count > 16)
5451                         linecount = 16;
5452                 else
5453                         linecount = count;
5454
5455                 for(i=0;i<linecount;i++)
5456                         printk("%02X ",(unsigned char)data[i]);
5457                 for(;i<17;i++)
5458                         printk("   ");
5459                 for(i=0;i<linecount;i++) {
5460                         if (data[i]>=040 && data[i]<=0176)
5461                                 printk("%c",data[i]);
5462                         else
5463                                 printk(".");
5464                 }
5465                 printk("\n");
5466
5467                 data  += linecount;
5468                 count -= linecount;
5469         }
5470 }       /* end of trace_block() */
5471
5472 /* called when HDLC frame times out
5473  * update stats and do tx completion processing
5474  */
5475 static void tx_timeout(unsigned long context)
5476 {
5477         SLMP_INFO *info = (SLMP_INFO*)context;
5478         unsigned long flags;
5479
5480         if ( debug_level >= DEBUG_LEVEL_INFO )
5481                 printk( "%s(%d):%s tx_timeout()\n",
5482                         __FILE__,__LINE__,info->device_name);
5483         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5484                 info->icount.txtimeout++;
5485         }
5486         spin_lock_irqsave(&info->lock,flags);
5487         info->tx_active = false;
5488         info->tx_count = info->tx_put = info->tx_get = 0;
5489
5490         spin_unlock_irqrestore(&info->lock,flags);
5491
5492 #if SYNCLINK_GENERIC_HDLC
5493         if (info->netcount)
5494                 hdlcdev_tx_done(info);
5495         else
5496 #endif
5497                 bh_transmit(info);
5498 }
5499
5500 /* called to periodically check the DSR/RI modem signal input status
5501  */
5502 static void status_timeout(unsigned long context)
5503 {
5504         u16 status = 0;
5505         SLMP_INFO *info = (SLMP_INFO*)context;
5506         unsigned long flags;
5507         unsigned char delta;
5508
5509
5510         spin_lock_irqsave(&info->lock,flags);
5511         get_signals(info);
5512         spin_unlock_irqrestore(&info->lock,flags);
5513
5514         /* check for DSR/RI state change */
5515
5516         delta = info->old_signals ^ info->serial_signals;
5517         info->old_signals = info->serial_signals;
5518
5519         if (delta & SerialSignal_DSR)
5520                 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5521
5522         if (delta & SerialSignal_RI)
5523                 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5524
5525         if (delta & SerialSignal_DCD)
5526                 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5527
5528         if (delta & SerialSignal_CTS)
5529                 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5530
5531         if (status)
5532                 isr_io_pin(info,status);
5533
5534         mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5535 }
5536
5537
5538 /* Register Access Routines -
5539  * All registers are memory mapped
5540  */
5541 #define CALC_REGADDR() \
5542         unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5543         if (info->port_num > 1) \
5544                 RegAddr += 256;                 /* port 0-1 SCA0, 2-3 SCA1 */ \
5545         if ( info->port_num & 1) { \
5546                 if (Addr > 0x7f) \
5547                         RegAddr += 0x40;        /* DMA access */ \
5548                 else if (Addr > 0x1f && Addr < 0x60) \
5549                         RegAddr += 0x20;        /* MSCI access */ \
5550         }
5551
5552
5553 static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5554 {
5555         CALC_REGADDR();
5556         return *RegAddr;
5557 }
5558 static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5559 {
5560         CALC_REGADDR();
5561         *RegAddr = Value;
5562 }
5563
5564 static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5565 {
5566         CALC_REGADDR();
5567         return *((u16 *)RegAddr);
5568 }
5569
5570 static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5571 {
5572         CALC_REGADDR();
5573         *((u16 *)RegAddr) = Value;
5574 }
5575
5576 static unsigned char read_status_reg(SLMP_INFO * info)
5577 {
5578         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5579         return *RegAddr;
5580 }
5581
5582 static void write_control_reg(SLMP_INFO * info)
5583 {
5584         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5585         *RegAddr = info->port_array[0]->ctrlreg_value;
5586 }
5587
5588
5589 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5590                                           const struct pci_device_id *ent)
5591 {
5592         if (pci_enable_device(dev)) {
5593                 printk("error enabling pci device %p\n", dev);
5594                 return -EIO;
5595         }
5596         device_init( ++synclinkmp_adapter_count, dev );
5597         return 0;
5598 }
5599
5600 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5601 {
5602 }