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   1 /* savage_bci.c -- BCI support for Savage
   2  *
   3  * Copyright 2004  Felix Kuehling
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sub license,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  20  * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
  22  * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25 #include "drmP.h"
  26 #include "savage_drm.h"
  27 #include "savage_drv.h"
  28
  29 /* Need a long timeout for shadow status updates can take a while
  30  * and so can waiting for events when the queue is full. */
  31 #define SAVAGE_DEFAULT_USEC_TIMEOUT     1000000 /* 1s */
  32 #define SAVAGE_EVENT_USEC_TIMEOUT       5000000 /* 5s */
  33 #define SAVAGE_FREELIST_DEBUG           0
  34
  35 static int
  36 savage_bci_wait_fifo_shadow(drm_savage_private_t *dev_priv, unsigned int n)
  37 {
  38         uint32_t mask = dev_priv->status_used_mask;
  39         uint32_t threshold = dev_priv->bci_threshold_hi;
  40         uint32_t status;
  41         int i;
  42
  43 #if SAVAGE_BCI_DEBUG
  44         if (n > dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - threshold)
  45                 DRM_ERROR("Trying to emit %d words "
  46                           "(more than guaranteed space in COB)\n", n);
  47 #endif
  48
  49         for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) {
  50                 DRM_MEMORYBARRIER();
  51                 status = dev_priv->status_ptr[0];
  52                 if ((status & mask) < threshold)
  53                         return 0;
  54                 DRM_UDELAY(1);
  55         }
  56
  57 #if SAVAGE_BCI_DEBUG
  58         DRM_ERROR("failed!\n");
  59         DRM_INFO("   status=0x%08x, threshold=0x%08x\n", status, threshold);
  60 #endif
  61         return DRM_ERR(EBUSY);
  62 }
  63
  64 static int
  65 savage_bci_wait_fifo_s3d(drm_savage_private_t *dev_priv, unsigned int n)
  66 {
  67         uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n;
  68         uint32_t status;
  69         int i;
  70
  71         for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) {
  72                 status = SAVAGE_READ(SAVAGE_STATUS_WORD0);
  73                 if ((status & SAVAGE_FIFO_USED_MASK_S3D) <= maxUsed)
  74                         return 0;
  75                 DRM_UDELAY(1);
  76         }
  77
  78 #if SAVAGE_BCI_DEBUG
  79         DRM_ERROR("failed!\n");
  80         DRM_INFO("   status=0x%08x\n", status);
  81 #endif
  82         return DRM_ERR(EBUSY);
  83 }
  84
  85 static int
  86 savage_bci_wait_fifo_s4(drm_savage_private_t *dev_priv, unsigned int n)
  87 {
  88         uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n;
  89         uint32_t status;
  90         int i;
  91
  92         for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) {
  93                 status = SAVAGE_READ(SAVAGE_ALT_STATUS_WORD0);
  94                 if ((status & SAVAGE_FIFO_USED_MASK_S4) <= maxUsed)
  95                         return 0;
  96                 DRM_UDELAY(1);
  97         }
  98
  99 #if SAVAGE_BCI_DEBUG
 100         DRM_ERROR("failed!\n");
 101         DRM_INFO("   status=0x%08x\n", status);
 102 #endif
 103         return DRM_ERR(EBUSY);
 104 }
 105
 106 /*
 107  * Waiting for events.
 108  *
 109  * The BIOSresets the event tag to 0 on mode changes. Therefore we
 110  * never emit 0 to the event tag. If we find a 0 event tag we know the
 111  * BIOS stomped on it and return success assuming that the BIOS waited
 112  * for engine idle.
 113  *
 114  * Note: if the Xserver uses the event tag it has to follow the same
 115  * rule. Otherwise there may be glitches every 2^16 events.
 116  */
 117 static int
 118 savage_bci_wait_event_shadow(drm_savage_private_t *dev_priv, uint16_t e)
 119 {
 120         uint32_t status;
 121         int i;
 122
 123         for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) {
 124                 DRM_MEMORYBARRIER();
 125                 status = dev_priv->status_ptr[1];
 126                 if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff ||
 127                     (status & 0xffff) == 0)
 128                         return 0;
 129                 DRM_UDELAY(1);
 130         }
 131
 132 #if SAVAGE_BCI_DEBUG
 133         DRM_ERROR("failed!\n");
 134         DRM_INFO("   status=0x%08x, e=0x%04x\n", status, e);
 135 #endif
 136
 137         return DRM_ERR(EBUSY);
 138 }
 139
 140 static int
 141 savage_bci_wait_event_reg(drm_savage_private_t *dev_priv, uint16_t e)
 142 {
 143         uint32_t status;
 144         int i;
 145
 146         for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) {
 147                 status = SAVAGE_READ(SAVAGE_STATUS_WORD1);
 148                 if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff ||
 149                     (status & 0xffff) == 0)
 150                         return 0;
 151                 DRM_UDELAY(1);
 152         }
 153
 154 #if SAVAGE_BCI_DEBUG
 155         DRM_ERROR("failed!\n");
 156         DRM_INFO("   status=0x%08x, e=0x%04x\n", status, e);
 157 #endif
 158
 159         return DRM_ERR(EBUSY);
 160 }
 161
 162 uint16_t savage_bci_emit_event(drm_savage_private_t *dev_priv,
 163                                unsigned int flags)
 164 {
 165         uint16_t count;
 166         BCI_LOCALS;
 167
 168         if (dev_priv->status_ptr) {
 169                 /* coordinate with Xserver */
 170                 count = dev_priv->status_ptr[1023];
 171                 if (count < dev_priv->event_counter)
 172                         dev_priv->event_wrap++;
 173         } else {
 174                 count = dev_priv->event_counter;
 175         }
 176         count = (count + 1) & 0xffff;
 177         if (count == 0) {
 178                 count++; /* See the comment above savage_wait_event_*. */
 179                 dev_priv->event_wrap++;
 180         }
 181         dev_priv->event_counter = count;
 182         if (dev_priv->status_ptr)
 183                 dev_priv->status_ptr[1023] = (uint32_t)count;
 184
 185         if ((flags & (SAVAGE_WAIT_2D | SAVAGE_WAIT_3D))) {
 186                 unsigned int wait_cmd = BCI_CMD_WAIT;
 187                 if ((flags & SAVAGE_WAIT_2D))
 188                         wait_cmd |= BCI_CMD_WAIT_2D;
 189                 if ((flags & SAVAGE_WAIT_3D))
 190                         wait_cmd |= BCI_CMD_WAIT_3D;
 191                 BEGIN_BCI(2);
 192                 BCI_WRITE(wait_cmd);
 193         } else {
 194                 BEGIN_BCI(1);
 195         }
 196         BCI_WRITE(BCI_CMD_UPDATE_EVENT_TAG | (uint32_t)count);
 197
 198         return count;
 199 }
 200
 201 /*
 202  * Freelist management
 203  */
 204 static int savage_freelist_init(drm_device_t *dev)
 205 {
 206         drm_savage_private_t *dev_priv = dev->dev_private;
 207         drm_device_dma_t *dma = dev->dma;
 208         drm_buf_t *buf;
 209         drm_savage_buf_priv_t *entry;
 210         int i;
 211         DRM_DEBUG("count=%d\n", dma->buf_count);
 212
 213         dev_priv->head.next = &dev_priv->tail;
 214         dev_priv->head.prev = NULL;
 215         dev_priv->head.buf = NULL;
 216
 217         dev_priv->tail.next = NULL;
 218         dev_priv->tail.prev = &dev_priv->head;
 219         dev_priv->tail.buf = NULL;
 220
 221         for (i = 0; i < dma->buf_count; i++) {
 222                 buf = dma->buflist[i];
 223                 entry = buf->dev_private;
 224
 225                 SET_AGE(&entry->age, 0, 0);
 226                 entry->buf = buf;
 227
 228                 entry->next = dev_priv->head.next;
 229                 entry->prev = &dev_priv->head;
 230                 dev_priv->head.next->prev = entry;
 231                 dev_priv->head.next = entry;
 232         }
 233
 234         return 0;
 235 }
 236
 237 static drm_buf_t *savage_freelist_get(drm_device_t *dev)
 238 {
 239         drm_savage_private_t *dev_priv = dev->dev_private;
 240         drm_savage_buf_priv_t *tail = dev_priv->tail.prev;
 241         uint16_t event;
 242         unsigned int wrap;
 243         DRM_DEBUG("\n");
 244
 245         UPDATE_EVENT_COUNTER();
 246         if (dev_priv->status_ptr)
 247                 event = dev_priv->status_ptr[1] & 0xffff;
 248         else
 249                 event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff;
 250         wrap = dev_priv->event_wrap;
 251         if (event > dev_priv->event_counter)
 252                 wrap--; /* hardware hasn't passed the last wrap yet */
 253
 254         DRM_DEBUG("   tail=0x%04x %d\n", tail->age.event, tail->age.wrap);
 255         DRM_DEBUG("   head=0x%04x %d\n", event, wrap);
 256
 257         if (tail->buf && (TEST_AGE(&tail->age, event, wrap) || event == 0)) {
 258                 drm_savage_buf_priv_t *next = tail->next;
 259                 drm_savage_buf_priv_t *prev = tail->prev;
 260                 prev->next = next;
 261                 next->prev = prev;
 262                 tail->next = tail->prev = NULL;
 263                 return tail->buf;
 264         }
 265
 266         DRM_DEBUG("returning NULL, tail->buf=%p!\n", tail->buf);
 267         return NULL;
 268 }
 269
 270 void savage_freelist_put(drm_device_t *dev, drm_buf_t *buf)
 271 {
 272         drm_savage_private_t *dev_priv = dev->dev_private;
 273         drm_savage_buf_priv_t *entry = buf->dev_private, *prev, *next;
 274
 275         DRM_DEBUG("age=0x%04x wrap=%d\n", entry->age.event, entry->age.wrap);
 276
 277         if (entry->next != NULL || entry->prev != NULL) {
 278                 DRM_ERROR("entry already on freelist.\n");
 279                 return;
 280         }
 281
 282         prev = &dev_priv->head;
 283         next = prev->next;
 284         prev->next = entry;
 285         next->prev = entry;
 286         entry->prev = prev;
 287         entry->next = next;
 288 }
 289
 290 /*
 291  * Command DMA
 292  */
 293 static int savage_dma_init(drm_savage_private_t *dev_priv)
 294 {
 295         unsigned int i;
 296
 297         dev_priv->nr_dma_pages = dev_priv->cmd_dma->size /
 298                 (SAVAGE_DMA_PAGE_SIZE*4);
 299         dev_priv->dma_pages = drm_alloc(sizeof(drm_savage_dma_page_t) *
 300                                         dev_priv->nr_dma_pages,
 301                                         DRM_MEM_DRIVER);
 302         if (dev_priv->dma_pages == NULL)
 303                 return DRM_ERR(ENOMEM);
 304
 305         for (i = 0; i < dev_priv->nr_dma_pages; ++i) {
 306                 SET_AGE(&dev_priv->dma_pages[i].age, 0, 0);
 307                 dev_priv->dma_pages[i].used = 0;
 308                 dev_priv->dma_pages[i].flushed = 0;
 309         }
 310         SET_AGE(&dev_priv->last_dma_age, 0, 0);
 311
 312         dev_priv->first_dma_page = 0;
 313         dev_priv->current_dma_page = 0;
 314
 315         return 0;
 316 }
 317
 318 void savage_dma_reset(drm_savage_private_t *dev_priv)
 319 {
 320         uint16_t event;
 321         unsigned int wrap, i;
 322         event = savage_bci_emit_event(dev_priv, 0);
 323         wrap = dev_priv->event_wrap;
 324         for (i = 0; i < dev_priv->nr_dma_pages; ++i) {
 325                 SET_AGE(&dev_priv->dma_pages[i].age, event, wrap);
 326                 dev_priv->dma_pages[i].used = 0;
 327                 dev_priv->dma_pages[i].flushed = 0;
 328         }
 329         SET_AGE(&dev_priv->last_dma_age, event, wrap);
 330         dev_priv->first_dma_page = dev_priv->current_dma_page = 0;
 331 }
 332
 333 void savage_dma_wait(drm_savage_private_t *dev_priv, unsigned int page)
 334 {
 335         uint16_t event;
 336         unsigned int wrap;
 337
 338         /* Faked DMA buffer pages don't age. */
 339         if (dev_priv->cmd_dma == &dev_priv->fake_dma)
 340                 return;
 341
 342         UPDATE_EVENT_COUNTER();
 343         if (dev_priv->status_ptr)
 344                 event = dev_priv->status_ptr[1] & 0xffff;
 345         else
 346                 event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff;
 347         wrap = dev_priv->event_wrap;
 348         if (event > dev_priv->event_counter)
 349                 wrap--; /* hardware hasn't passed the last wrap yet */
 350
 351         if (dev_priv->dma_pages[page].age.wrap > wrap ||
 352             (dev_priv->dma_pages[page].age.wrap == wrap &&
 353              dev_priv->dma_pages[page].age.event > event)) {
 354                 if (dev_priv->wait_evnt(dev_priv,
 355                                         dev_priv->dma_pages[page].age.event)
 356                     < 0)
 357                         DRM_ERROR("wait_evnt failed!\n");
 358         }
 359 }
 360
 361 uint32_t *savage_dma_alloc(drm_savage_private_t *dev_priv, unsigned int n)
 362 {
 363         unsigned int cur = dev_priv->current_dma_page;
 364         unsigned int rest = SAVAGE_DMA_PAGE_SIZE -
 365                 dev_priv->dma_pages[cur].used;
 366         unsigned int nr_pages = (n - rest + SAVAGE_DMA_PAGE_SIZE-1) /
 367                 SAVAGE_DMA_PAGE_SIZE;
 368         uint32_t *dma_ptr;
 369         unsigned int i;
 370
 371         DRM_DEBUG("cur=%u, cur->used=%u, n=%u, rest=%u, nr_pages=%u\n",
 372                   cur, dev_priv->dma_pages[cur].used, n, rest, nr_pages);
 373
 374         if (cur + nr_pages < dev_priv->nr_dma_pages) {
 375                 dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle +
 376                         cur*SAVAGE_DMA_PAGE_SIZE +
 377                         dev_priv->dma_pages[cur].used;
 378                 if (n < rest)
 379                         rest = n;
 380                 dev_priv->dma_pages[cur].used += rest;
 381                 n -= rest;
 382                 cur++;
 383         } else {
 384                 dev_priv->dma_flush(dev_priv);
 385                 nr_pages = (n + SAVAGE_DMA_PAGE_SIZE-1) / SAVAGE_DMA_PAGE_SIZE;
 386                 for (i = cur; i < dev_priv->nr_dma_pages; ++i) {
 387                         dev_priv->dma_pages[i].age = dev_priv->last_dma_age;
 388                         dev_priv->dma_pages[i].used = 0;
 389                         dev_priv->dma_pages[i].flushed = 0;
 390                 }
 391                 dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle;
 392                 dev_priv->first_dma_page = cur = 0;
 393         }
 394         for (i = cur; nr_pages > 0; ++i, --nr_pages) {
 395 #if SAVAGE_DMA_DEBUG
 396                 if (dev_priv->dma_pages[i].used) {
 397                         DRM_ERROR("unflushed page %u: used=%u\n",
 398                                   i, dev_priv->dma_pages[i].used);
 399                 }
 400 #endif
 401                 if (n > SAVAGE_DMA_PAGE_SIZE)
 402                         dev_priv->dma_pages[i].used = SAVAGE_DMA_PAGE_SIZE;
 403                 else
 404                         dev_priv->dma_pages[i].used = n;
 405                 n -= SAVAGE_DMA_PAGE_SIZE;
 406         }
 407         dev_priv->current_dma_page = --i;
 408
 409         DRM_DEBUG("cur=%u, cur->used=%u, n=%u\n",
 410                   i, dev_priv->dma_pages[i].used, n);
 411
 412         savage_dma_wait(dev_priv, dev_priv->current_dma_page);
 413
 414         return dma_ptr;
 415 }
 416
 417 static void savage_dma_flush(drm_savage_private_t *dev_priv)
 418 {
 419         unsigned int first = dev_priv->first_dma_page;
 420         unsigned int cur = dev_priv->current_dma_page;
 421         uint16_t event;
 422         unsigned int wrap, pad, align, len, i;
 423         unsigned long phys_addr;
 424         BCI_LOCALS;
 425
 426         if (first == cur &&
 427             dev_priv->dma_pages[cur].used == dev_priv->dma_pages[cur].flushed)
 428                 return;
 429
 430         /* pad length to multiples of 2 entries
 431          * align start of next DMA block to multiles of 8 entries */
 432         pad = -dev_priv->dma_pages[cur].used & 1;
 433         align = -(dev_priv->dma_pages[cur].used + pad) & 7;
 434
 435         DRM_DEBUG("first=%u, cur=%u, first->flushed=%u, cur->used=%u, "
 436                   "pad=%u, align=%u\n",
 437                   first, cur, dev_priv->dma_pages[first].flushed,
 438                   dev_priv->dma_pages[cur].used, pad, align);
 439
 440         /* pad with noops */
 441         if (pad) {
 442                 uint32_t *dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle +
 443                         cur * SAVAGE_DMA_PAGE_SIZE +
 444                         dev_priv->dma_pages[cur].used;
 445                 dev_priv->dma_pages[cur].used += pad;
 446                 while(pad != 0) {
 447                         *dma_ptr++ = BCI_CMD_WAIT;
 448                         pad--;
 449                 }
 450         }
 451
 452         DRM_MEMORYBARRIER();
 453
 454         /* do flush ... */
 455         phys_addr = dev_priv->cmd_dma->offset +
 456                 (first * SAVAGE_DMA_PAGE_SIZE +
 457                  dev_priv->dma_pages[first].flushed) * 4;
 458         len = (cur - first) * SAVAGE_DMA_PAGE_SIZE +
 459                 dev_priv->dma_pages[cur].used -
 460                 dev_priv->dma_pages[first].flushed;
 461
 462         DRM_DEBUG("phys_addr=%lx, len=%u\n",
 463                   phys_addr | dev_priv->dma_type, len);
 464
 465         BEGIN_BCI(3);
 466         BCI_SET_REGISTERS(SAVAGE_DMABUFADDR, 1);
 467         BCI_WRITE(phys_addr | dev_priv->dma_type);
 468         BCI_DMA(len);
 469
 470         /* fix alignment of the start of the next block */
 471         dev_priv->dma_pages[cur].used += align;
 472
 473         /* age DMA pages */
 474         event = savage_bci_emit_event(dev_priv, 0);
 475         wrap = dev_priv->event_wrap;
 476         for (i = first; i < cur; ++i) {
 477                 SET_AGE(&dev_priv->dma_pages[i].age, event, wrap);
 478                 dev_priv->dma_pages[i].used = 0;
 479                 dev_priv->dma_pages[i].flushed = 0;
 480         }
 481         /* age the current page only when it's full */
 482         if (dev_priv->dma_pages[cur].used == SAVAGE_DMA_PAGE_SIZE) {
 483                 SET_AGE(&dev_priv->dma_pages[cur].age, event, wrap);
 484                 dev_priv->dma_pages[cur].used = 0;
 485                 dev_priv->dma_pages[cur].flushed = 0;
 486                 /* advance to next page */
 487                 cur++;
 488                 if (cur == dev_priv->nr_dma_pages)
 489                         cur = 0;
 490                 dev_priv->first_dma_page = dev_priv->current_dma_page = cur;
 491         } else {
 492                 dev_priv->first_dma_page = cur;
 493                 dev_priv->dma_pages[cur].flushed = dev_priv->dma_pages[i].used;
 494         }
 495         SET_AGE(&dev_priv->last_dma_age, event, wrap);
 496
 497         DRM_DEBUG("first=cur=%u, cur->used=%u, cur->flushed=%u\n", cur,
 498                   dev_priv->dma_pages[cur].used,
 499                   dev_priv->dma_pages[cur].flushed);
 500 }
 501
 502 static void savage_fake_dma_flush(drm_savage_private_t *dev_priv)
 503 {
 504         unsigned int i, j;
 505         BCI_LOCALS;
 506
 507         if (dev_priv->first_dma_page == dev_priv->current_dma_page &&
 508             dev_priv->dma_pages[dev_priv->current_dma_page].used == 0)
 509                 return;
 510
 511         DRM_DEBUG("first=%u, cur=%u, cur->used=%u\n",
 512                   dev_priv->first_dma_page, dev_priv->current_dma_page,
 513                   dev_priv->dma_pages[dev_priv->current_dma_page].used);
 514
 515         for (i = dev_priv->first_dma_page;
 516              i <= dev_priv->current_dma_page && dev_priv->dma_pages[i].used;
 517              ++i) {
 518                 uint32_t *dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle +
 519                         i * SAVAGE_DMA_PAGE_SIZE;
 520 #if SAVAGE_DMA_DEBUG
 521                 /* Sanity check: all pages except the last one must be full. */
 522                 if (i < dev_priv->current_dma_page &&
 523                     dev_priv->dma_pages[i].used != SAVAGE_DMA_PAGE_SIZE) {
 524                         DRM_ERROR("partial DMA page %u: used=%u",
 525                                   i, dev_priv->dma_pages[i].used);
 526                 }
 527 #endif
 528                 BEGIN_BCI(dev_priv->dma_pages[i].used);
 529                 for (j = 0; j < dev_priv->dma_pages[i].used; ++j) {
 530                         BCI_WRITE(dma_ptr[j]);
 531                 }
 532                 dev_priv->dma_pages[i].used = 0;
 533         }
 534
 535         /* reset to first page */
 536         dev_priv->first_dma_page = dev_priv->current_dma_page = 0;
 537 }
 538
 539 /*
 540  * Initalize mappings. On Savage4 and SavageIX the alignment
 541  * and size of the aperture is not suitable for automatic MTRR setup
 542  * in drm_addmap. Therefore we do it manually before the maps are
 543  * initialized. We also need to take care of deleting the MTRRs in
 544  * postcleanup.
 545  */
 546 int savage_preinit(drm_device_t *dev, unsigned long chipset)
 547 {
 548         drm_savage_private_t *dev_priv;
 549         unsigned long mmio_base, fb_base, fb_size, aperture_base;
 550         /* fb_rsrc and aper_rsrc aren't really used currently, but still exist
 551          * in case we decide we need information on the BAR for BSD in the
 552          * future.
 553          */
 554         unsigned int fb_rsrc, aper_rsrc;
 555         int ret = 0;
 556
 557         dev_priv = drm_alloc(sizeof(drm_savage_private_t), DRM_MEM_DRIVER);
 558         if (dev_priv == NULL)
 559                 return DRM_ERR(ENOMEM);
 560
 561         memset(dev_priv, 0, sizeof(drm_savage_private_t));
 562         dev->dev_private = (void *)dev_priv;
 563         dev_priv->chipset = (enum savage_family)chipset;
 564
 565         dev_priv->mtrr[0].handle = -1;
 566         dev_priv->mtrr[1].handle = -1;
 567         dev_priv->mtrr[2].handle = -1;
 568         if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
 569                 fb_rsrc = 0;
 570                 fb_base = drm_get_resource_start(dev, 0);
 571                 fb_size = SAVAGE_FB_SIZE_S3;
 572                 mmio_base = fb_base + SAVAGE_FB_SIZE_S3;
 573                 aper_rsrc = 0;
 574                 aperture_base = fb_base + SAVAGE_APERTURE_OFFSET;
 575                 /* this should always be true */
 576                 if (drm_get_resource_len(dev, 0) == 0x08000000) {
 577                         /* Don't make MMIO write-cobining! We need 3
 578                          * MTRRs. */
 579                         dev_priv->mtrr[0].base = fb_base;
 580                         dev_priv->mtrr[0].size = 0x01000000;
 581                         dev_priv->mtrr[0].handle = mtrr_add(
 582                                 dev_priv->mtrr[0].base, dev_priv->mtrr[0].size,
 583                                 MTRR_TYPE_WRCOMB, 1);
 584                         dev_priv->mtrr[1].base = fb_base+0x02000000;
 585                         dev_priv->mtrr[1].size = 0x02000000;
 586                         dev_priv->mtrr[1].handle = mtrr_add(
 587                                 dev_priv->mtrr[1].base, dev_priv->mtrr[1].size,
 588                                 MTRR_TYPE_WRCOMB, 1);
 589                         dev_priv->mtrr[2].base = fb_base+0x04000000;
 590                         dev_priv->mtrr[2].size = 0x04000000;
 591                         dev_priv->mtrr[2].handle = mtrr_add(
 592                                 dev_priv->mtrr[2].base, dev_priv->mtrr[2].size,
 593                                 MTRR_TYPE_WRCOMB, 1);
 594                 } else {
 595                         DRM_ERROR("strange pci_resource_len %08lx\n",
 596                                   drm_get_resource_len(dev, 0));
 597                 }
 598         } else if (chipset != S3_SUPERSAVAGE && chipset != S3_SAVAGE2000) {
 599                 mmio_base = drm_get_resource_start(dev, 0);
 600                 fb_rsrc = 1;
 601                 fb_base = drm_get_resource_start(dev, 1);
 602                 fb_size = SAVAGE_FB_SIZE_S4;
 603                 aper_rsrc = 1;
 604                 aperture_base = fb_base + SAVAGE_APERTURE_OFFSET;
 605                 /* this should always be true */
 606                 if (drm_get_resource_len(dev, 1) == 0x08000000) {
 607                         /* Can use one MTRR to cover both fb and
 608                          * aperture. */
 609                         dev_priv->mtrr[0].base = fb_base;
 610                         dev_priv->mtrr[0].size = 0x08000000;
 611                         dev_priv->mtrr[0].handle = mtrr_add(
 612                                 dev_priv->mtrr[0].base, dev_priv->mtrr[0].size,
 613                                 MTRR_TYPE_WRCOMB, 1);
 614                 } else {
 615                         DRM_ERROR("strange pci_resource_len %08lx\n",
 616                                   drm_get_resource_len(dev, 1));
 617                 }
 618         } else {
 619                 mmio_base = drm_get_resource_start(dev, 0);
 620                 fb_rsrc = 1;
 621                 fb_base = drm_get_resource_start(dev, 1);
 622                 fb_size = drm_get_resource_len(dev, 1);
 623                 aper_rsrc = 2;
 624                 aperture_base = drm_get_resource_start(dev, 2);
 625                 /* Automatic MTRR setup will do the right thing. */
 626         }
 627
 628         ret = drm_addmap(dev, mmio_base, SAVAGE_MMIO_SIZE, _DRM_REGISTERS,
 629                          _DRM_READ_ONLY, &dev_priv->mmio);
 630         if (ret)
 631                 return ret;
 632
 633         ret = drm_addmap(dev, fb_base, fb_size, _DRM_FRAME_BUFFER,
 634                          _DRM_WRITE_COMBINING, &dev_priv->fb);
 635         if (ret)
 636                 return ret;
 637
 638         ret = drm_addmap(dev, aperture_base, SAVAGE_APERTURE_SIZE,
 639                          _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING,
 640                          &dev_priv->aperture);
 641         if (ret)
 642                 return ret;
 643
 644         return ret;
 645 }
 646
 647 /*
 648  * Delete MTRRs and free device-private data.
 649  */
 650 int savage_postcleanup(drm_device_t *dev)
 651 {
 652         drm_savage_private_t *dev_priv = dev->dev_private;
 653         int i;
 654
 655         for (i = 0; i < 3; ++i)
 656                 if (dev_priv->mtrr[i].handle >= 0)
 657                         mtrr_del(dev_priv->mtrr[i].handle,
 658                                  dev_priv->mtrr[i].base,
 659                                  dev_priv->mtrr[i].size);
 660
 661         drm_free(dev_priv, sizeof(drm_savage_private_t), DRM_MEM_DRIVER);
 662
 663         return 0;
 664 }
 665
 666 static int savage_do_init_bci(drm_device_t *dev, drm_savage_init_t *init)
 667 {
 668         drm_savage_private_t *dev_priv = dev->dev_private;
 669
 670         if (init->fb_bpp != 16 && init->fb_bpp != 32) {
 671                 DRM_ERROR("invalid frame buffer bpp %d!\n", init->fb_bpp);
 672                 return DRM_ERR(EINVAL);
 673         }
 674         if (init->depth_bpp != 16 && init->depth_bpp != 32) {
 675                 DRM_ERROR("invalid depth buffer bpp %d!\n", init->fb_bpp);
 676                 return DRM_ERR(EINVAL);
 677         }
 678         if (init->dma_type != SAVAGE_DMA_AGP &&
 679             init->dma_type != SAVAGE_DMA_PCI) {
 680                 DRM_ERROR("invalid dma memory type %d!\n", init->dma_type);
 681                 return DRM_ERR(EINVAL);
 682         }
 683
 684         dev_priv->cob_size = init->cob_size;
 685         dev_priv->bci_threshold_lo = init->bci_threshold_lo;
 686         dev_priv->bci_threshold_hi = init->bci_threshold_hi;
 687         dev_priv->dma_type = init->dma_type;
 688
 689         dev_priv->fb_bpp = init->fb_bpp;
 690         dev_priv->front_offset = init->front_offset;
 691         dev_priv->front_pitch = init->front_pitch;
 692         dev_priv->back_offset = init->back_offset;
 693         dev_priv->back_pitch = init->back_pitch;
 694         dev_priv->depth_bpp = init->depth_bpp;
 695         dev_priv->depth_offset = init->depth_offset;
 696         dev_priv->depth_pitch = init->depth_pitch;
 697
 698         dev_priv->texture_offset = init->texture_offset;
 699         dev_priv->texture_size = init->texture_size;
 700
 701         DRM_GETSAREA();
 702         if (!dev_priv->sarea) {
 703                 DRM_ERROR("could not find sarea!\n");
 704                 savage_do_cleanup_bci(dev);
 705                 return DRM_ERR(EINVAL);
 706         }
 707         if (init->status_offset != 0) {
 708                 dev_priv->status = drm_core_findmap(dev, init->status_offset);
 709                 if (!dev_priv->status) {
 710                         DRM_ERROR("could not find shadow status region!\n");
 711                         savage_do_cleanup_bci(dev);
 712                         return DRM_ERR(EINVAL);
 713                 }
 714         } else {
 715                 dev_priv->status = NULL;
 716         }
 717         if (dev_priv->dma_type == SAVAGE_DMA_AGP && init->buffers_offset) {
 718                 dev->agp_buffer_map = drm_core_findmap(dev,
 719                                                        init->buffers_offset);
 720                 if (!dev->agp_buffer_map) {
 721                         DRM_ERROR("could not find DMA buffer region!\n");
 722                         savage_do_cleanup_bci(dev);
 723                         return DRM_ERR(EINVAL);
 724                 }
 725                 drm_core_ioremap(dev->agp_buffer_map, dev);
 726                 if (!dev->agp_buffer_map) {
 727                         DRM_ERROR("failed to ioremap DMA buffer region!\n");
 728                         savage_do_cleanup_bci(dev);
 729                         return DRM_ERR(ENOMEM);
 730                 }
 731         }
 732         if (init->agp_textures_offset) {
 733                 dev_priv->agp_textures =
 734                         drm_core_findmap(dev, init->agp_textures_offset);
 735                 if (!dev_priv->agp_textures) {
 736                         DRM_ERROR("could not find agp texture region!\n");
 737                         savage_do_cleanup_bci(dev);
 738                         return DRM_ERR(EINVAL);
 739                 }
 740         } else {
 741                 dev_priv->agp_textures = NULL;
 742         }
 743
 744         if (init->cmd_dma_offset) {
 745                 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
 746                         DRM_ERROR("command DMA not supported on "
 747                                   "Savage3D/MX/IX.\n");
 748                         savage_do_cleanup_bci(dev);
 749                         return DRM_ERR(EINVAL);
 750                 }
 751                 if (dev->dma && dev->dma->buflist) {
 752                         DRM_ERROR("command and vertex DMA not supported "
 753                                   "at the same time.\n");
 754                         savage_do_cleanup_bci(dev);
 755                         return DRM_ERR(EINVAL);
 756                 }
 757                 dev_priv->cmd_dma = drm_core_findmap(dev, init->cmd_dma_offset);
 758                 if (!dev_priv->cmd_dma) {
 759                         DRM_ERROR("could not find command DMA region!\n");
 760                         savage_do_cleanup_bci(dev);
 761                         return DRM_ERR(EINVAL);
 762                 }
 763                 if (dev_priv->dma_type == SAVAGE_DMA_AGP) {
 764                         if (dev_priv->cmd_dma->type != _DRM_AGP) {
 765                                 DRM_ERROR("AGP command DMA region is not a "
 766                                           "_DRM_AGP map!\n");
 767                                 savage_do_cleanup_bci(dev);
 768                                 return DRM_ERR(EINVAL);
 769                         }
 770                         drm_core_ioremap(dev_priv->cmd_dma, dev);
 771                         if (!dev_priv->cmd_dma->handle) {
 772                                 DRM_ERROR("failed to ioremap command "
 773                                           "DMA region!\n");
 774                                 savage_do_cleanup_bci(dev);
 775                                 return DRM_ERR(ENOMEM);
 776                         }
 777                 } else if (dev_priv->cmd_dma->type != _DRM_CONSISTENT) {
 778                         DRM_ERROR("PCI command DMA region is not a "
 779                                   "_DRM_CONSISTENT map!\n");
 780                         savage_do_cleanup_bci(dev);
 781                         return DRM_ERR(EINVAL);
 782                 }
 783         } else {
 784                 dev_priv->cmd_dma = NULL;
 785         }
 786
 787         dev_priv->dma_flush = savage_dma_flush;
 788         if (!dev_priv->cmd_dma) {
 789                 DRM_DEBUG("falling back to faked command DMA.\n");
 790                 dev_priv->fake_dma.offset = 0;
 791                 dev_priv->fake_dma.size = SAVAGE_FAKE_DMA_SIZE;
 792                 dev_priv->fake_dma.type = _DRM_SHM;
 793                 dev_priv->fake_dma.handle = drm_alloc(SAVAGE_FAKE_DMA_SIZE,
 794                                                       DRM_MEM_DRIVER);
 795                 if (!dev_priv->fake_dma.handle) {
 796                         DRM_ERROR("could not allocate faked DMA buffer!\n");
 797                         savage_do_cleanup_bci(dev);
 798                         return DRM_ERR(ENOMEM);
 799                 }
 800                 dev_priv->cmd_dma = &dev_priv->fake_dma;
 801                 dev_priv->dma_flush = savage_fake_dma_flush;
 802         }
 803
 804         dev_priv->sarea_priv =
 805                 (drm_savage_sarea_t *)((uint8_t *)dev_priv->sarea->handle +
 806                                        init->sarea_priv_offset);
 807
 808         /* setup bitmap descriptors */
 809         {
 810                 unsigned int color_tile_format;
 811                 unsigned int depth_tile_format;
 812                 unsigned int front_stride, back_stride, depth_stride;
 813                 if (dev_priv->chipset <= S3_SAVAGE4) {
 814                         color_tile_format = dev_priv->fb_bpp == 16 ?
 815                                 SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP;
 816                         depth_tile_format = dev_priv->depth_bpp == 16 ?
 817                                 SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP;
 818                 } else {
 819                         color_tile_format = SAVAGE_BD_TILE_DEST;
 820                         depth_tile_format = SAVAGE_BD_TILE_DEST;
 821                 }
 822                 front_stride = dev_priv->front_pitch / (dev_priv->fb_bpp/8);
 823                 back_stride  = dev_priv-> back_pitch / (dev_priv->fb_bpp/8);
 824                 depth_stride = dev_priv->depth_pitch / (dev_priv->depth_bpp/8);
 825
 826                 dev_priv->front_bd = front_stride | SAVAGE_BD_BW_DISABLE |
 827                         (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) |
 828                         (color_tile_format << SAVAGE_BD_TILE_SHIFT);
 829
 830                 dev_priv-> back_bd =  back_stride | SAVAGE_BD_BW_DISABLE |
 831                         (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) |
 832                         (color_tile_format << SAVAGE_BD_TILE_SHIFT);
 833
 834                 dev_priv->depth_bd = depth_stride | SAVAGE_BD_BW_DISABLE |
 835                         (dev_priv->depth_bpp << SAVAGE_BD_BPP_SHIFT) |
 836                         (depth_tile_format << SAVAGE_BD_TILE_SHIFT);
 837         }
 838
 839         /* setup status and bci ptr */
 840         dev_priv->event_counter = 0;
 841         dev_priv->event_wrap = 0;
 842         dev_priv->bci_ptr = (volatile uint32_t *)
 843             ((uint8_t *)dev_priv->mmio->handle + SAVAGE_BCI_OFFSET);
 844         if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
 845                 dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S3D;
 846         } else {
 847                 dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S4;
 848         }
 849         if (dev_priv->status != NULL) {
 850                 dev_priv->status_ptr =
 851                         (volatile uint32_t *)dev_priv->status->handle;
 852                 dev_priv->wait_fifo = savage_bci_wait_fifo_shadow;
 853                 dev_priv->wait_evnt = savage_bci_wait_event_shadow;
 854                 dev_priv->status_ptr[1023] = dev_priv->event_counter;
 855         } else {
 856                 dev_priv->status_ptr = NULL;
 857                 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
 858                         dev_priv->wait_fifo = savage_bci_wait_fifo_s3d;
 859                 } else {
 860                         dev_priv->wait_fifo = savage_bci_wait_fifo_s4;
 861                 }
 862                 dev_priv->wait_evnt = savage_bci_wait_event_reg;
 863         }
 864
 865         /* cliprect functions */
 866         if (S3_SAVAGE3D_SERIES(dev_priv->chipset))
 867                 dev_priv->emit_clip_rect = savage_emit_clip_rect_s3d;
 868         else
 869                 dev_priv->emit_clip_rect = savage_emit_clip_rect_s4;
 870
 871         if (savage_freelist_init(dev) < 0) {
 872                 DRM_ERROR("could not initialize freelist\n");
 873                 savage_do_cleanup_bci(dev);
 874                 return DRM_ERR(ENOMEM);
 875         }
 876
 877         if (savage_dma_init(dev_priv) <  0) {
 878                 DRM_ERROR("could not initialize command DMA\n");
 879                 savage_do_cleanup_bci(dev);
 880                 return DRM_ERR(ENOMEM);
 881         }
 882
 883         return 0;
 884 }
 885
 886 int savage_do_cleanup_bci(drm_device_t *dev)
 887 {
 888         drm_savage_private_t *dev_priv = dev->dev_private;
 889
 890         if (dev_priv->cmd_dma == &dev_priv->fake_dma) {
 891                 if (dev_priv->fake_dma.handle)
 892                         drm_free(dev_priv->fake_dma.handle,
 893                                  SAVAGE_FAKE_DMA_SIZE, DRM_MEM_DRIVER);
 894         } else if (dev_priv->cmd_dma && dev_priv->cmd_dma->handle &&
 895                    dev_priv->cmd_dma->type == _DRM_AGP &&
 896                    dev_priv->dma_type == SAVAGE_DMA_AGP)
 897                 drm_core_ioremapfree(dev_priv->cmd_dma, dev);
 898
 899         if (dev_priv->dma_type == SAVAGE_DMA_AGP &&
 900             dev->agp_buffer_map && dev->agp_buffer_map->handle) {
 901                 drm_core_ioremapfree(dev->agp_buffer_map, dev);
 902                 /* make sure the next instance (which may be running
 903                  * in PCI mode) doesn't try to use an old
 904                  * agp_buffer_map. */
 905                 dev->agp_buffer_map = NULL;
 906         }
 907
 908         if (dev_priv->dma_pages)
 909                 drm_free(dev_priv->dma_pages,
 910                          sizeof(drm_savage_dma_page_t)*dev_priv->nr_dma_pages,
 911                          DRM_MEM_DRIVER);
 912
 913         return 0;
 914 }
 915
 916 static int savage_bci_init(DRM_IOCTL_ARGS)
 917 {
 918         DRM_DEVICE;
 919         drm_savage_init_t init;
 920
 921         LOCK_TEST_WITH_RETURN(dev, filp);
 922
 923         DRM_COPY_FROM_USER_IOCTL(init, (drm_savage_init_t __user *)data,
 924                                  sizeof(init));
 925
 926         switch (init.func) {
 927         case SAVAGE_INIT_BCI:
 928                 return savage_do_init_bci(dev, &init);
 929         case SAVAGE_CLEANUP_BCI:
 930                 return savage_do_cleanup_bci(dev);
 931         }
 932
 933         return DRM_ERR(EINVAL);
 934 }
 935
 936 static int savage_bci_event_emit(DRM_IOCTL_ARGS)
 937 {
 938         DRM_DEVICE;
 939         drm_savage_private_t *dev_priv = dev->dev_private;
 940         drm_savage_event_emit_t event;
 941
 942         DRM_DEBUG("\n");
 943
 944         LOCK_TEST_WITH_RETURN(dev, filp);
 945
 946         DRM_COPY_FROM_USER_IOCTL(event, (drm_savage_event_emit_t __user *)data,
 947                                  sizeof(event));
 948
 949         event.count = savage_bci_emit_event(dev_priv, event.flags);
 950         event.count |= dev_priv->event_wrap << 16;
 951         DRM_COPY_TO_USER_IOCTL(&((drm_savage_event_emit_t __user *)data)->count,
 952                                event.count, sizeof(event.count));
 953         return 0;
 954 }
 955
 956 static int savage_bci_event_wait(DRM_IOCTL_ARGS)
 957 {
 958         DRM_DEVICE;
 959         drm_savage_private_t *dev_priv = dev->dev_private;
 960         drm_savage_event_wait_t event;
 961         unsigned int event_e, hw_e;
 962         unsigned int event_w, hw_w;
 963
 964         DRM_DEBUG("\n");
 965
 966         DRM_COPY_FROM_USER_IOCTL(event, (drm_savage_event_wait_t __user *)data,
 967                                  sizeof(event));
 968
 969         UPDATE_EVENT_COUNTER();
 970         if (dev_priv->status_ptr)
 971                 hw_e = dev_priv->status_ptr[1] & 0xffff;
 972         else
 973                 hw_e = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff;
 974         hw_w = dev_priv->event_wrap;
 975         if (hw_e > dev_priv->event_counter)
 976                 hw_w--; /* hardware hasn't passed the last wrap yet */
 977
 978         event_e = event.count & 0xffff;
 979         event_w = event.count >> 16;
 980
 981         /* Don't need to wait if
 982          * - event counter wrapped since the event was emitted or
 983          * - the hardware has advanced up to or over the event to wait for.
 984          */
 985         if (event_w < hw_w || (event_w == hw_w && event_e <= hw_e) )
 986                 return 0;
 987         else
 988                 return dev_priv->wait_evnt(dev_priv, event_e);
 989 }
 990
 991 /*
 992  * DMA buffer management
 993  */
 994
 995 static int savage_bci_get_buffers(DRMFILE filp, drm_device_t *dev, drm_dma_t *d)
 996 {
 997         drm_buf_t *buf;
 998         int i;
 999
1000         for (i = d->granted_count; i < d->request_count; i++) {
1001                 buf = savage_freelist_get(dev);
1002                 if (!buf)
1003                         return DRM_ERR(EAGAIN);
1004
1005                 buf->filp = filp;
1006
1007                 if (DRM_COPY_TO_USER(&d->request_indices[i],
1008                                      &buf->idx, sizeof(buf->idx)))
1009                         return DRM_ERR(EFAULT);
1010                 if (DRM_COPY_TO_USER(&d->request_sizes[i],
1011                                      &buf->total, sizeof(buf->total)))
1012                         return DRM_ERR(EFAULT);
1013
1014                 d->granted_count++;
1015         }
1016         return 0;
1017 }
1018
1019 int savage_bci_buffers(DRM_IOCTL_ARGS)
1020 {
1021         DRM_DEVICE;
1022         drm_device_dma_t *dma = dev->dma;
1023         drm_dma_t d;
1024         int ret = 0;
1025
1026         LOCK_TEST_WITH_RETURN(dev, filp);
1027
1028         DRM_COPY_FROM_USER_IOCTL(d, (drm_dma_t __user *)data, sizeof(d));
1029
1030         /* Please don't send us buffers.
1031          */
1032         if (d.send_count != 0) {
1033                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1034                           DRM_CURRENTPID, d.send_count);
1035                 return DRM_ERR(EINVAL);
1036         }
1037
1038         /* We'll send you buffers.
1039          */
1040         if (d.request_count < 0 || d.request_count > dma->buf_count) {
1041                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1042                           DRM_CURRENTPID, d.request_count, dma->buf_count);
1043                 return DRM_ERR(EINVAL);
1044         }
1045
1046         d.granted_count = 0;
1047
1048         if (d.request_count) {
1049                 ret = savage_bci_get_buffers(filp, dev, &d);
1050         }
1051
1052         DRM_COPY_TO_USER_IOCTL((drm_dma_t __user *)data, d, sizeof(d));
1053
1054         return ret;
1055 }
1056
1057 void savage_reclaim_buffers(drm_device_t *dev, DRMFILE filp) {
1058         drm_device_dma_t *dma = dev->dma;
1059         drm_savage_private_t *dev_priv = dev->dev_private;
1060         int i;
1061
1062         if (!dma)
1063                 return;
1064         if (!dev_priv)
1065                 return;
1066         if (!dma->buflist)
1067                 return;
1068
1069         /*i830_flush_queue(dev);*/
1070
1071         for (i = 0; i < dma->buf_count; i++) {
1072                 drm_buf_t *buf = dma->buflist[i];
1073                 drm_savage_buf_priv_t *buf_priv = buf->dev_private;
1074
1075                 if (buf->filp == filp && buf_priv &&
1076                     buf_priv->next == NULL && buf_priv->prev == NULL) {
1077                         uint16_t event;
1078                         DRM_DEBUG("reclaimed from client\n");
1079                         event = savage_bci_emit_event(dev_priv, SAVAGE_WAIT_3D);
1080                         SET_AGE(&buf_priv->age, event, dev_priv->event_wrap);
1081                         savage_freelist_put(dev, buf);
1082                 }
1083         }
1084
1085         drm_core_reclaim_buffers(dev, filp);
1086 }
1087
1088
1089 drm_ioctl_desc_t savage_ioctls[] = {
1090         [DRM_IOCTL_NR(DRM_SAVAGE_BCI_INIT)] = {savage_bci_init, 1, 1},
1091         [DRM_IOCTL_NR(DRM_SAVAGE_BCI_CMDBUF)] = {savage_bci_cmdbuf, 1, 0},
1092         [DRM_IOCTL_NR(DRM_SAVAGE_BCI_EVENT_EMIT)] = {savage_bci_event_emit, 1, 0},
1093         [DRM_IOCTL_NR(DRM_SAVAGE_BCI_EVENT_WAIT)] = {savage_bci_event_wait, 1, 0},
1094 };
1095
1096 int savage_max_ioctl = DRM_ARRAY_SIZE(savage_ioctls);