2 * Copyright 2001-2003 SuSE Labs.
3 * Distributed under the GNU public license, v2.
5 * This is a GART driver for the AMD Opteron/Athlon64 on-CPU northbridge.
6 * It also includes support for the AMD 8151 AGP bridge,
7 * although it doesn't actually do much, as all the real
8 * work is done in the northbridge(s).
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/init.h>
14 #include <linux/agp_backend.h>
15 #include <linux/mmzone.h>
16 #include <asm/page.h> /* PAGE_SIZE */
22 /* NVIDIA K8 registers */
23 #define NVIDIA_X86_64_0_APBASE 0x10
24 #define NVIDIA_X86_64_1_APBASE1 0x50
25 #define NVIDIA_X86_64_1_APLIMIT1 0x54
26 #define NVIDIA_X86_64_1_APSIZE 0xa8
27 #define NVIDIA_X86_64_1_APBASE2 0xd8
28 #define NVIDIA_X86_64_1_APLIMIT2 0xdc
30 /* ULi K8 registers */
31 #define ULI_X86_64_BASE_ADDR 0x10
32 #define ULI_X86_64_HTT_FEA_REG 0x50
33 #define ULI_X86_64_ENU_SCR_REG 0x54
35 static struct resource *aperture_resource;
36 static int __initdata agp_try_unsupported = 1;
37 static int agp_bridges_found;
39 static void amd64_tlbflush(struct agp_memory *temp)
44 static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
46 int i, j, num_entries;
49 struct agp_bridge_data *bridge = mem->bridge;
52 num_entries = agp_num_entries();
54 if (type != mem->type)
56 mask_type = bridge->driver->agp_type_to_mask_type(bridge, type);
61 /* Make sure we can fit the range in the gatt table. */
62 /* FIXME: could wrap */
63 if (((unsigned long)pg_start + mem->page_count) > num_entries)
68 /* gatt table should be empty. */
69 while (j < (pg_start + mem->page_count)) {
70 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j)))
75 if (!mem->is_flushed) {
77 mem->is_flushed = true;
80 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
81 tmp = agp_bridge->driver->mask_memory(agp_bridge,
82 page_to_phys(mem->pages[i]),
85 BUG_ON(tmp & 0xffffff0000000ffcULL);
86 pte = (tmp & 0x000000ff00000000ULL) >> 28;
87 pte |=(tmp & 0x00000000fffff000ULL);
88 pte |= GPTE_VALID | GPTE_COHERENT;
90 writel(pte, agp_bridge->gatt_table+j);
91 readl(agp_bridge->gatt_table+j); /* PCI Posting. */
98 * This hack alters the order element according
99 * to the size of a long. It sucks. I totally disown this, even
100 * though it does appear to work for the most part.
102 static struct aper_size_info_32 amd64_aperture_sizes[7] =
104 {32, 8192, 3+(sizeof(long)/8), 0 },
105 {64, 16384, 4+(sizeof(long)/8), 1<<1 },
106 {128, 32768, 5+(sizeof(long)/8), 1<<2 },
107 {256, 65536, 6+(sizeof(long)/8), 1<<1 | 1<<2 },
108 {512, 131072, 7+(sizeof(long)/8), 1<<3 },
109 {1024, 262144, 8+(sizeof(long)/8), 1<<1 | 1<<3},
110 {2048, 524288, 9+(sizeof(long)/8), 1<<2 | 1<<3}
115 * Get the current Aperture size from the x86-64.
116 * Note, that there may be multiple x86-64's, but we just return
117 * the value from the first one we find. The set_size functions
118 * keep the rest coherent anyway. Or at least should do.
120 static int amd64_fetch_size(void)
125 struct aper_size_info_32 *values;
127 dev = k8_northbridges[0];
131 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &temp);
133 values = A_SIZE_32(amd64_aperture_sizes);
135 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
136 if (temp == values[i].size_value) {
137 agp_bridge->previous_size =
138 agp_bridge->current_size = (void *) (values + i);
140 agp_bridge->aperture_size_idx = i;
141 return values[i].size;
148 * In a multiprocessor x86-64 system, this function gets
149 * called once for each CPU.
151 static u64 amd64_configure(struct pci_dev *hammer, u64 gatt_table)
157 /* Address to map to */
158 pci_read_config_dword(hammer, AMD64_GARTAPERTUREBASE, &tmp);
159 aperturebase = tmp << 25;
160 aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK);
162 enable_gart_translation(hammer, gatt_table);
168 static const struct aper_size_info_32 amd_8151_sizes[7] =
170 {2048, 524288, 9, 0x00000000 }, /* 0 0 0 0 0 0 */
171 {1024, 262144, 8, 0x00000400 }, /* 1 0 0 0 0 0 */
172 {512, 131072, 7, 0x00000600 }, /* 1 1 0 0 0 0 */
173 {256, 65536, 6, 0x00000700 }, /* 1 1 1 0 0 0 */
174 {128, 32768, 5, 0x00000720 }, /* 1 1 1 1 0 0 */
175 {64, 16384, 4, 0x00000730 }, /* 1 1 1 1 1 0 */
176 {32, 8192, 3, 0x00000738 } /* 1 1 1 1 1 1 */
179 static int amd_8151_configure(void)
181 unsigned long gatt_bus = virt_to_phys(agp_bridge->gatt_table_real);
184 /* Configure AGP regs in each x86-64 host bridge. */
185 for (i = 0; i < num_k8_northbridges; i++) {
186 agp_bridge->gart_bus_addr =
187 amd64_configure(k8_northbridges[i], gatt_bus);
194 static void amd64_cleanup(void)
198 for (i = 0; i < num_k8_northbridges; i++) {
199 struct pci_dev *dev = k8_northbridges[i];
200 /* disable gart translation */
201 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &tmp);
202 tmp &= ~AMD64_GARTEN;
203 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, tmp);
208 static const struct agp_bridge_driver amd_8151_driver = {
209 .owner = THIS_MODULE,
210 .aperture_sizes = amd_8151_sizes,
211 .size_type = U32_APER_SIZE,
212 .num_aperture_sizes = 7,
213 .needs_scratch_page = true,
214 .configure = amd_8151_configure,
215 .fetch_size = amd64_fetch_size,
216 .cleanup = amd64_cleanup,
217 .tlb_flush = amd64_tlbflush,
218 .mask_memory = agp_generic_mask_memory,
220 .agp_enable = agp_generic_enable,
221 .cache_flush = global_cache_flush,
222 .create_gatt_table = agp_generic_create_gatt_table,
223 .free_gatt_table = agp_generic_free_gatt_table,
224 .insert_memory = amd64_insert_memory,
225 .remove_memory = agp_generic_remove_memory,
226 .alloc_by_type = agp_generic_alloc_by_type,
227 .free_by_type = agp_generic_free_by_type,
228 .agp_alloc_page = agp_generic_alloc_page,
229 .agp_alloc_pages = agp_generic_alloc_pages,
230 .agp_destroy_page = agp_generic_destroy_page,
231 .agp_destroy_pages = agp_generic_destroy_pages,
232 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
235 /* Some basic sanity checks for the aperture. */
236 static int __devinit agp_aperture_valid(u64 aper, u32 size)
238 if (!aperture_valid(aper, size, 32*1024*1024))
241 /* Request the Aperture. This catches cases when someone else
242 already put a mapping in there - happens with some very broken BIOS
244 Maybe better to use pci_assign_resource/pci_enable_device instead
245 trusting the bridges? */
246 if (!aperture_resource &&
247 !(aperture_resource = request_mem_region(aper, size, "aperture"))) {
248 printk(KERN_ERR PFX "Aperture conflicts with PCI mapping.\n");
255 * W*s centric BIOS sometimes only set up the aperture in the AGP
256 * bridge, not the northbridge. On AMD64 this is handled early
257 * in aperture.c, but when IOMMU is not enabled or we run
258 * on a 32bit kernel this needs to be redone.
259 * Unfortunately it is impossible to fix the aperture here because it's too late
260 * to allocate that much memory. But at least error out cleanly instead of
263 static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
266 u32 aper_low, aper_hi;
269 u32 nb_order, nb_base;
272 pci_read_config_dword(nb, AMD64_GARTAPERTURECTL, &nb_order);
273 nb_order = (nb_order >> 1) & 7;
274 pci_read_config_dword(nb, AMD64_GARTAPERTUREBASE, &nb_base);
275 nb_aper = nb_base << 25;
277 /* Northbridge seems to contain crap. Try the AGP bridge. */
279 pci_read_config_word(agp, cap+0x14, &apsize);
280 if (apsize == 0xffff) {
281 if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order))
287 /* Some BIOS use weird encodings not in the AGPv3 table. */
290 order = 7 - hweight16(apsize);
292 pci_read_config_dword(agp, 0x10, &aper_low);
293 pci_read_config_dword(agp, 0x14, &aper_hi);
294 aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
297 * On some sick chips APSIZE is 0. This means it wants 4G
298 * so let double check that order, and lets trust the AMD NB settings
300 if (order >=0 && aper + (32ULL<<(20 + order)) > 0x100000000ULL) {
301 dev_info(&agp->dev, "aperture size %u MB is not right, using settings from NB\n",
306 if (nb_order >= order) {
307 if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order))
311 dev_info(&agp->dev, "aperture from AGP @ %Lx size %u MB\n",
313 if (order < 0 || !agp_aperture_valid(aper, (32*1024*1024)<<order))
316 pci_write_config_dword(nb, AMD64_GARTAPERTURECTL, order << 1);
317 pci_write_config_dword(nb, AMD64_GARTAPERTUREBASE, aper >> 25);
322 static __devinit int cache_nbs (struct pci_dev *pdev, u32 cap_ptr)
326 if (cache_k8_northbridges() < 0)
330 for (i = 0; i < num_k8_northbridges; i++) {
331 struct pci_dev *dev = k8_northbridges[i];
332 if (fix_northbridge(dev, pdev, cap_ptr) < 0) {
333 dev_err(&dev->dev, "no usable aperture found\n");
335 /* should port this to i386 */
336 dev_err(&dev->dev, "consider rebooting with iommu=memaper=2 to get a good aperture\n");
344 /* Handle AMD 8151 quirks */
345 static void __devinit amd8151_init(struct pci_dev *pdev, struct agp_bridge_data *bridge)
349 switch (pdev->revision) {
350 case 0x01: revstring="A0"; break;
351 case 0x02: revstring="A1"; break;
352 case 0x11: revstring="B0"; break;
353 case 0x12: revstring="B1"; break;
354 case 0x13: revstring="B2"; break;
355 case 0x14: revstring="B3"; break;
356 default: revstring="??"; break;
359 dev_info(&pdev->dev, "AMD 8151 AGP Bridge rev %s\n", revstring);
362 * Work around errata.
363 * Chips before B2 stepping incorrectly reporting v3.5
365 if (pdev->revision < 0x13) {
366 dev_info(&pdev->dev, "correcting AGP revision (reports 3.5, is really 3.0)\n");
367 bridge->major_version = 3;
368 bridge->minor_version = 0;
373 static const struct aper_size_info_32 uli_sizes[7] =
383 static int __devinit uli_agp_init(struct pci_dev *pdev)
385 u32 httfea,baseaddr,enuscr;
386 struct pci_dev *dev1;
388 unsigned size = amd64_fetch_size();
390 dev_info(&pdev->dev, "setting up ULi AGP\n");
391 dev1 = pci_get_slot (pdev->bus,PCI_DEVFN(0,0));
393 dev_info(&pdev->dev, "can't find ULi secondary device\n");
397 for (i = 0; i < ARRAY_SIZE(uli_sizes); i++)
398 if (uli_sizes[i].size == size)
401 if (i == ARRAY_SIZE(uli_sizes)) {
402 dev_info(&pdev->dev, "no ULi size found for %d\n", size);
406 /* shadow x86-64 registers into ULi registers */
407 pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &httfea);
409 /* if x86-64 aperture base is beyond 4G, exit here */
410 if ((httfea & 0x7fff) >> (32 - 25))
413 httfea = (httfea& 0x7fff) << 25;
415 pci_read_config_dword(pdev, ULI_X86_64_BASE_ADDR, &baseaddr);
416 baseaddr&= ~PCI_BASE_ADDRESS_MEM_MASK;
418 pci_write_config_dword(pdev, ULI_X86_64_BASE_ADDR, baseaddr);
420 enuscr= httfea+ (size * 1024 * 1024) - 1;
421 pci_write_config_dword(dev1, ULI_X86_64_HTT_FEA_REG, httfea);
422 pci_write_config_dword(dev1, ULI_X86_64_ENU_SCR_REG, enuscr);
429 static const struct aper_size_info_32 nforce3_sizes[5] =
431 {512, 131072, 7, 0x00000000 },
432 {256, 65536, 6, 0x00000008 },
433 {128, 32768, 5, 0x0000000C },
434 {64, 16384, 4, 0x0000000E },
435 {32, 8192, 3, 0x0000000F }
438 /* Handle shadow device of the Nvidia NForce3 */
439 /* CHECK-ME original 2.4 version set up some IORRs. Check if that is needed. */
440 static int nforce3_agp_init(struct pci_dev *pdev)
442 u32 tmp, apbase, apbar, aplimit;
443 struct pci_dev *dev1;
445 unsigned size = amd64_fetch_size();
447 dev_info(&pdev->dev, "setting up Nforce3 AGP\n");
449 dev1 = pci_get_slot(pdev->bus, PCI_DEVFN(11, 0));
451 dev_info(&pdev->dev, "can't find Nforce3 secondary device\n");
455 for (i = 0; i < ARRAY_SIZE(nforce3_sizes); i++)
456 if (nforce3_sizes[i].size == size)
459 if (i == ARRAY_SIZE(nforce3_sizes)) {
460 dev_info(&pdev->dev, "no NForce3 size found for %d\n", size);
464 pci_read_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, &tmp);
466 tmp |= nforce3_sizes[i].size_value;
467 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp);
469 /* shadow x86-64 registers into NVIDIA registers */
470 pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &apbase);
472 /* if x86-64 aperture base is beyond 4G, exit here */
473 if ( (apbase & 0x7fff) >> (32 - 25) ) {
474 dev_info(&pdev->dev, "aperture base > 4G\n");
478 apbase = (apbase & 0x7fff) << 25;
480 pci_read_config_dword(pdev, NVIDIA_X86_64_0_APBASE, &apbar);
481 apbar &= ~PCI_BASE_ADDRESS_MEM_MASK;
483 pci_write_config_dword(pdev, NVIDIA_X86_64_0_APBASE, apbar);
485 aplimit = apbase + (size * 1024 * 1024) - 1;
486 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE1, apbase);
487 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT1, aplimit);
488 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE2, apbase);
489 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT2, aplimit);
496 static int __devinit agp_amd64_probe(struct pci_dev *pdev,
497 const struct pci_device_id *ent)
499 struct agp_bridge_data *bridge;
503 /* The Highlander principle */
504 if (agp_bridges_found)
507 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
511 /* Could check for AGPv3 here */
513 bridge = agp_alloc_bridge();
517 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
518 pdev->device == PCI_DEVICE_ID_AMD_8151_0) {
519 amd8151_init(pdev, bridge);
521 dev_info(&pdev->dev, "AGP bridge [%04x/%04x]\n",
522 pdev->vendor, pdev->device);
525 bridge->driver = &amd_8151_driver;
527 bridge->capndx = cap_ptr;
529 /* Fill in the mode register */
530 pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
532 if (cache_nbs(pdev, cap_ptr) == -1) {
533 agp_put_bridge(bridge);
537 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) {
538 int ret = nforce3_agp_init(pdev);
540 agp_put_bridge(bridge);
545 if (pdev->vendor == PCI_VENDOR_ID_AL) {
546 int ret = uli_agp_init(pdev);
548 agp_put_bridge(bridge);
553 pci_set_drvdata(pdev, bridge);
554 err = agp_add_bridge(bridge);
562 static void __devexit agp_amd64_remove(struct pci_dev *pdev)
564 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
566 release_mem_region(virt_to_phys(bridge->gatt_table_real),
567 amd64_aperture_sizes[bridge->aperture_size_idx].size);
568 agp_remove_bridge(bridge);
569 agp_put_bridge(bridge);
576 static int agp_amd64_suspend(struct pci_dev *pdev, pm_message_t state)
578 pci_save_state(pdev);
579 pci_set_power_state(pdev, pci_choose_state(pdev, state));
584 static int agp_amd64_resume(struct pci_dev *pdev)
586 pci_set_power_state(pdev, PCI_D0);
587 pci_restore_state(pdev);
589 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA)
590 nforce3_agp_init(pdev);
592 return amd_8151_configure();
595 #endif /* CONFIG_PM */
597 static struct pci_device_id agp_amd64_pci_table[] = {
599 .class = (PCI_CLASS_BRIDGE_HOST << 8),
601 .vendor = PCI_VENDOR_ID_AMD,
602 .device = PCI_DEVICE_ID_AMD_8151_0,
603 .subvendor = PCI_ANY_ID,
604 .subdevice = PCI_ANY_ID,
608 .class = (PCI_CLASS_BRIDGE_HOST << 8),
610 .vendor = PCI_VENDOR_ID_AL,
611 .device = PCI_DEVICE_ID_AL_M1689,
612 .subvendor = PCI_ANY_ID,
613 .subdevice = PCI_ANY_ID,
617 .class = (PCI_CLASS_BRIDGE_HOST << 8),
619 .vendor = PCI_VENDOR_ID_VIA,
620 .device = PCI_DEVICE_ID_VIA_K8T800PRO_0,
621 .subvendor = PCI_ANY_ID,
622 .subdevice = PCI_ANY_ID,
626 .class = (PCI_CLASS_BRIDGE_HOST << 8),
628 .vendor = PCI_VENDOR_ID_VIA,
629 .device = PCI_DEVICE_ID_VIA_8385_0,
630 .subvendor = PCI_ANY_ID,
631 .subdevice = PCI_ANY_ID,
633 /* VIA K8M800 / K8N800 */
635 .class = (PCI_CLASS_BRIDGE_HOST << 8),
637 .vendor = PCI_VENDOR_ID_VIA,
638 .device = PCI_DEVICE_ID_VIA_8380_0,
639 .subvendor = PCI_ANY_ID,
640 .subdevice = PCI_ANY_ID,
642 /* VIA K8M890 / K8N890 */
644 .class = (PCI_CLASS_BRIDGE_HOST << 8),
646 .vendor = PCI_VENDOR_ID_VIA,
647 .device = PCI_DEVICE_ID_VIA_VT3336,
648 .subvendor = PCI_ANY_ID,
649 .subdevice = PCI_ANY_ID,
653 .class = (PCI_CLASS_BRIDGE_HOST << 8),
655 .vendor = PCI_VENDOR_ID_VIA,
656 .device = PCI_DEVICE_ID_VIA_3238_0,
657 .subvendor = PCI_ANY_ID,
658 .subdevice = PCI_ANY_ID,
660 /* VIA K8T800/K8M800/K8N800 */
662 .class = (PCI_CLASS_BRIDGE_HOST << 8),
664 .vendor = PCI_VENDOR_ID_VIA,
665 .device = PCI_DEVICE_ID_VIA_838X_1,
666 .subvendor = PCI_ANY_ID,
667 .subdevice = PCI_ANY_ID,
671 .class = (PCI_CLASS_BRIDGE_HOST << 8),
673 .vendor = PCI_VENDOR_ID_NVIDIA,
674 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3,
675 .subvendor = PCI_ANY_ID,
676 .subdevice = PCI_ANY_ID,
679 .class = (PCI_CLASS_BRIDGE_HOST << 8),
681 .vendor = PCI_VENDOR_ID_NVIDIA,
682 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3S,
683 .subvendor = PCI_ANY_ID,
684 .subdevice = PCI_ANY_ID,
688 .class = (PCI_CLASS_BRIDGE_HOST << 8),
690 .vendor = PCI_VENDOR_ID_SI,
691 .device = PCI_DEVICE_ID_SI_755,
692 .subvendor = PCI_ANY_ID,
693 .subdevice = PCI_ANY_ID,
697 .class = (PCI_CLASS_BRIDGE_HOST << 8),
699 .vendor = PCI_VENDOR_ID_SI,
700 .device = PCI_DEVICE_ID_SI_760,
701 .subvendor = PCI_ANY_ID,
702 .subdevice = PCI_ANY_ID,
706 .class = (PCI_CLASS_BRIDGE_HOST << 8),
708 .vendor = PCI_VENDOR_ID_AL,
710 .subvendor = PCI_ANY_ID,
711 .subdevice = PCI_ANY_ID,
717 MODULE_DEVICE_TABLE(pci, agp_amd64_pci_table);
719 static DEFINE_PCI_DEVICE_TABLE(agp_amd64_pci_promisc_table) = {
720 { PCI_DEVICE_CLASS(0, 0) },
724 static struct pci_driver agp_amd64_pci_driver = {
725 .name = "agpgart-amd64",
726 .id_table = agp_amd64_pci_table,
727 .probe = agp_amd64_probe,
728 .remove = agp_amd64_remove,
730 .suspend = agp_amd64_suspend,
731 .resume = agp_amd64_resume,
736 /* Not static due to IOMMU code calling it early. */
737 int __init agp_amd64_init(void)
744 err = pci_register_driver(&agp_amd64_pci_driver);
748 if (agp_bridges_found == 0) {
749 if (!agp_try_unsupported && !agp_try_unsupported_boot) {
750 printk(KERN_INFO PFX "No supported AGP bridge found.\n");
752 printk(KERN_INFO PFX "You can try agp_try_unsupported=1\n");
754 printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n");
759 /* First check that we have at least one AMD64 NB */
760 if (!pci_dev_present(k8_nb_ids))
763 /* Look for any AGP bridge */
764 agp_amd64_pci_driver.id_table = agp_amd64_pci_promisc_table;
765 err = driver_attach(&agp_amd64_pci_driver.driver);
766 if (err == 0 && agp_bridges_found == 0)
772 static int __init agp_amd64_mod_init(void)
775 if (gart_iommu_aperture)
776 return agp_bridges_found ? 0 : -ENODEV;
778 return agp_amd64_init();
781 static void __exit agp_amd64_cleanup(void)
784 if (gart_iommu_aperture)
787 if (aperture_resource)
788 release_resource(aperture_resource);
789 pci_unregister_driver(&agp_amd64_pci_driver);
792 module_init(agp_amd64_mod_init);
793 module_exit(agp_amd64_cleanup);
795 MODULE_AUTHOR("Dave Jones <davej@redhat.com>, Andi Kleen");
796 module_param(agp_try_unsupported, bool, 0);
797 MODULE_LICENSE("GPL");