2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
4 * Copyright 2005 Tejun Heo
6 * Based on preview driver from Silicon Image.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/blkdev.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/device.h>
28 #include <scsi/scsi_host.h>
29 #include <scsi/scsi_cmnd.h>
30 #include <linux/libata.h>
32 #define DRV_NAME "sata_sil24"
33 #define DRV_VERSION "0.9"
36 * Port request block (PRB) 32 bytes
46 * Scatter gather entry (SGE) 16 bytes
57 struct sil24_port_multiplier {
67 * Global controller registers (128 bytes @ BAR0)
70 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
74 HOST_BIST_CTRL = 0x50,
75 HOST_BIST_PTRN = 0x54,
76 HOST_BIST_STAT = 0x58,
77 HOST_MEM_BIST_STAT = 0x5c,
78 HOST_FLASH_CMD = 0x70,
80 HOST_FLASH_DATA = 0x74,
81 HOST_TRANSITION_DETECT = 0x75,
82 HOST_GPIO_CTRL = 0x76,
83 HOST_I2C_ADDR = 0x78, /* 32 bit */
85 HOST_I2C_XFER_CNT = 0x7e,
88 /* HOST_SLOT_STAT bits */
89 HOST_SSTAT_ATTN = (1 << 31),
92 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
93 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
94 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
95 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
96 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
97 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
101 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
103 PORT_REGS_SIZE = 0x2000,
105 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
106 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
108 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
109 PORT_PMP_STATUS = 0x0000, /* port device status offset */
110 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
111 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
114 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
115 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
116 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
117 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
118 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
119 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
120 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
121 PORT_CMD_ERR = 0x1024, /* command error number */
122 PORT_FIS_CFG = 0x1028,
123 PORT_FIFO_THRES = 0x102c,
125 PORT_DECODE_ERR_CNT = 0x1040,
126 PORT_DECODE_ERR_THRESH = 0x1042,
127 PORT_CRC_ERR_CNT = 0x1044,
128 PORT_CRC_ERR_THRESH = 0x1046,
129 PORT_HSHK_ERR_CNT = 0x1048,
130 PORT_HSHK_ERR_THRESH = 0x104a,
132 PORT_PHY_CFG = 0x1050,
133 PORT_SLOT_STAT = 0x1800,
134 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
135 PORT_CONTEXT = 0x1e04,
136 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
137 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
138 PORT_SCONTROL = 0x1f00,
139 PORT_SSTATUS = 0x1f04,
140 PORT_SERROR = 0x1f08,
141 PORT_SACTIVE = 0x1f0c,
143 /* PORT_CTRL_STAT bits */
144 PORT_CS_PORT_RST = (1 << 0), /* port reset */
145 PORT_CS_DEV_RST = (1 << 1), /* device reset */
146 PORT_CS_INIT = (1 << 2), /* port initialize */
147 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
148 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
149 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
150 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
151 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
152 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
154 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
155 /* bits[11:0] are masked */
156 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
157 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
158 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
159 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
160 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
161 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
162 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
163 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
164 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
165 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
166 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
167 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
169 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
170 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
173 /* bits[27:16] are unmasked (raw) */
174 PORT_IRQ_RAW_SHIFT = 16,
175 PORT_IRQ_MASKED_MASK = 0x7ff,
176 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
178 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
179 PORT_IRQ_STEER_SHIFT = 30,
180 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
182 /* PORT_CMD_ERR constants */
183 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
184 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
185 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
186 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
187 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
188 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
189 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
190 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
191 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
192 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
193 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
194 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
195 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
196 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
197 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
198 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
199 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
200 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
201 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
202 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
203 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
204 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
206 /* bits of PRB control field */
207 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
208 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
209 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
210 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
211 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
213 /* PRB protocol field */
214 PRB_PROT_PACKET = (1 << 0),
215 PRB_PROT_TCQ = (1 << 1),
216 PRB_PROT_NCQ = (1 << 2),
217 PRB_PROT_READ = (1 << 3),
218 PRB_PROT_WRITE = (1 << 4),
219 PRB_PROT_TRANSPARENT = (1 << 5),
224 SGE_TRM = (1 << 31), /* Last SGE in chain */
225 SGE_LNK = (1 << 30), /* linked list
226 Points to SGT, not SGE */
227 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
228 data address ignored */
238 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
239 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
240 ATA_FLAG_NCQ | ATA_FLAG_SKIP_D2H_BSY |
242 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
244 IRQ_STAT_4PORTS = 0xf,
247 struct sil24_ata_block {
248 struct sil24_prb prb;
249 struct sil24_sge sge[LIBATA_MAX_PRD];
252 struct sil24_atapi_block {
253 struct sil24_prb prb;
255 struct sil24_sge sge[LIBATA_MAX_PRD - 1];
258 union sil24_cmd_block {
259 struct sil24_ata_block ata;
260 struct sil24_atapi_block atapi;
263 static struct sil24_cerr_info {
264 unsigned int err_mask, action;
266 } sil24_cerr_db[] = {
267 [0] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
269 [PORT_CERR_DEV] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
270 "device error via D2H FIS" },
271 [PORT_CERR_SDB] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
272 "device error via SDB FIS" },
273 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
274 "error in data FIS" },
275 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
276 "failed to transmit command FIS" },
277 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
278 "protocol mismatch" },
279 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
280 "data directon mismatch" },
281 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
282 "ran out of SGEs while writing" },
283 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
284 "ran out of SGEs while reading" },
285 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
286 "invalid data directon for ATAPI CDB" },
287 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
288 "SGT no on qword boundary" },
289 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
290 "PCI target abort while fetching SGT" },
291 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
292 "PCI master abort while fetching SGT" },
293 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
294 "PCI parity error while fetching SGT" },
295 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
296 "PRB not on qword boundary" },
297 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
298 "PCI target abort while fetching PRB" },
299 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
300 "PCI master abort while fetching PRB" },
301 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
302 "PCI parity error while fetching PRB" },
303 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
304 "undefined error while transferring data" },
305 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
306 "PCI target abort while transferring data" },
307 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
308 "PCI master abort while transferring data" },
309 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
310 "PCI parity error while transferring data" },
311 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
312 "FIS received while sending service FIS" },
318 * The preview driver always returned 0 for status. We emulate it
319 * here from the previous interrupt.
321 struct sil24_port_priv {
322 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
323 dma_addr_t cmd_block_dma; /* DMA base addr for them */
324 struct ata_taskfile tf; /* Cached taskfile registers */
327 static void sil24_dev_config(struct ata_device *dev);
328 static u8 sil24_check_status(struct ata_port *ap);
329 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
330 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
331 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
332 static void sil24_qc_prep(struct ata_queued_cmd *qc);
333 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
334 static void sil24_irq_clear(struct ata_port *ap);
335 static void sil24_freeze(struct ata_port *ap);
336 static void sil24_thaw(struct ata_port *ap);
337 static void sil24_error_handler(struct ata_port *ap);
338 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
339 static int sil24_port_start(struct ata_port *ap);
340 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
342 static int sil24_pci_device_resume(struct pci_dev *pdev);
345 static const struct pci_device_id sil24_pci_tbl[] = {
346 { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
347 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
348 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
349 { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
350 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
351 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
353 { } /* terminate list */
356 static struct pci_driver sil24_pci_driver = {
358 .id_table = sil24_pci_tbl,
359 .probe = sil24_init_one,
360 .remove = ata_pci_remove_one,
362 .suspend = ata_pci_device_suspend,
363 .resume = sil24_pci_device_resume,
367 static struct scsi_host_template sil24_sht = {
368 .module = THIS_MODULE,
370 .ioctl = ata_scsi_ioctl,
371 .queuecommand = ata_scsi_queuecmd,
372 .change_queue_depth = ata_scsi_change_queue_depth,
373 .can_queue = SIL24_MAX_CMDS,
374 .this_id = ATA_SHT_THIS_ID,
375 .sg_tablesize = LIBATA_MAX_PRD,
376 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
377 .emulated = ATA_SHT_EMULATED,
378 .use_clustering = ATA_SHT_USE_CLUSTERING,
379 .proc_name = DRV_NAME,
380 .dma_boundary = ATA_DMA_BOUNDARY,
381 .slave_configure = ata_scsi_slave_config,
382 .slave_destroy = ata_scsi_slave_destroy,
383 .bios_param = ata_std_bios_param,
386 static const struct ata_port_operations sil24_ops = {
387 .port_disable = ata_port_disable,
389 .dev_config = sil24_dev_config,
391 .check_status = sil24_check_status,
392 .check_altstatus = sil24_check_status,
393 .dev_select = ata_noop_dev_select,
395 .tf_read = sil24_tf_read,
397 .qc_prep = sil24_qc_prep,
398 .qc_issue = sil24_qc_issue,
400 .irq_clear = sil24_irq_clear,
401 .irq_on = ata_dummy_irq_on,
402 .irq_ack = ata_dummy_irq_ack,
404 .scr_read = sil24_scr_read,
405 .scr_write = sil24_scr_write,
407 .freeze = sil24_freeze,
409 .error_handler = sil24_error_handler,
410 .post_internal_cmd = sil24_post_internal_cmd,
412 .port_start = sil24_port_start,
416 * Use bits 30-31 of port_flags to encode available port numbers.
417 * Current maxium is 4.
419 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
420 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
422 static const struct ata_port_info sil24_port_info[] = {
425 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
426 SIL24_FLAG_PCIX_IRQ_WOC,
427 .pio_mask = 0x1f, /* pio0-4 */
428 .mwdma_mask = 0x07, /* mwdma0-2 */
429 .udma_mask = ATA_UDMA5, /* udma0-5 */
430 .port_ops = &sil24_ops,
434 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
435 .pio_mask = 0x1f, /* pio0-4 */
436 .mwdma_mask = 0x07, /* mwdma0-2 */
437 .udma_mask = ATA_UDMA5, /* udma0-5 */
438 .port_ops = &sil24_ops,
440 /* sil_3131/sil_3531 */
442 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
443 .pio_mask = 0x1f, /* pio0-4 */
444 .mwdma_mask = 0x07, /* mwdma0-2 */
445 .udma_mask = ATA_UDMA5, /* udma0-5 */
446 .port_ops = &sil24_ops,
450 static int sil24_tag(int tag)
452 if (unlikely(ata_tag_internal(tag)))
457 static void sil24_dev_config(struct ata_device *dev)
459 void __iomem *port = dev->ap->ioaddr.cmd_addr;
461 if (dev->cdb_len == 16)
462 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
464 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
467 static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf)
469 void __iomem *port = ap->ioaddr.cmd_addr;
470 struct sil24_prb __iomem *prb;
473 prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ;
474 memcpy_fromio(fis, prb->fis, sizeof(fis));
475 ata_tf_from_fis(fis, tf);
478 static u8 sil24_check_status(struct ata_port *ap)
480 struct sil24_port_priv *pp = ap->private_data;
481 return pp->tf.command;
484 static int sil24_scr_map[] = {
491 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg)
493 void __iomem *scr_addr = ap->ioaddr.scr_addr;
494 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
496 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
497 return readl(scr_addr + sil24_scr_map[sc_reg] * 4);
502 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
504 void __iomem *scr_addr = ap->ioaddr.scr_addr;
505 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
507 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
508 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
512 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
514 struct sil24_port_priv *pp = ap->private_data;
518 static int sil24_init_port(struct ata_port *ap)
520 void __iomem *port = ap->ioaddr.cmd_addr;
523 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
524 ata_wait_register(port + PORT_CTRL_STAT,
525 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
526 tmp = ata_wait_register(port + PORT_CTRL_STAT,
527 PORT_CS_RDY, 0, 10, 100);
529 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
534 static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp,
535 const struct ata_taskfile *tf,
536 int is_cmd, u32 ctrl,
537 unsigned long timeout_msec)
539 void __iomem *port = ap->ioaddr.cmd_addr;
540 struct sil24_port_priv *pp = ap->private_data;
541 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
542 dma_addr_t paddr = pp->cmd_block_dma;
543 u32 irq_enabled, irq_mask, irq_stat;
546 prb->ctrl = cpu_to_le16(ctrl);
547 ata_tf_to_fis(tf, pmp, is_cmd, prb->fis);
549 /* temporarily plug completion and error interrupts */
550 irq_enabled = readl(port + PORT_IRQ_ENABLE_SET);
551 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
553 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
554 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
556 irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
557 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask, 0x0,
560 writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */
561 irq_stat >>= PORT_IRQ_RAW_SHIFT;
563 if (irq_stat & PORT_IRQ_COMPLETE)
566 /* force port into known state */
569 if (irq_stat & PORT_IRQ_ERROR)
575 /* restore IRQ enabled */
576 writel(irq_enabled, port + PORT_IRQ_ENABLE_SET);
581 static int sil24_softreset(struct ata_port *ap, unsigned int *class,
582 unsigned long deadline)
584 unsigned long timeout_msec = 0;
585 struct ata_taskfile tf;
591 if (ata_port_offline(ap)) {
592 DPRINTK("PHY reports no device\n");
593 *class = ATA_DEV_NONE;
597 /* put the port into known state */
598 if (sil24_init_port(ap)) {
599 reason ="port not ready";
604 if (time_after(deadline, jiffies))
605 timeout_msec = jiffies_to_msecs(deadline - jiffies);
607 ata_tf_init(ap->device, &tf); /* doesn't really matter */
608 rc = sil24_exec_polled_cmd(ap, 0, &tf, 0, PRB_CTRL_SRST, timeout_msec);
613 reason = "SRST command error";
617 sil24_read_tf(ap, 0, &tf);
618 *class = ata_dev_classify(&tf);
620 if (*class == ATA_DEV_UNKNOWN)
621 *class = ATA_DEV_NONE;
624 DPRINTK("EXIT, class=%u\n", *class);
628 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
632 static int sil24_hardreset(struct ata_port *ap, unsigned int *class,
633 unsigned long deadline)
635 void __iomem *port = ap->ioaddr.cmd_addr;
640 /* sil24 does the right thing(tm) without any protection */
644 if (ata_port_online(ap))
647 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
648 tmp = ata_wait_register(port + PORT_CTRL_STAT,
649 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, tout_msec);
651 /* SStatus oscillates between zero and valid status after
652 * DEV_RST, debounce it.
654 rc = sata_phy_debounce(ap, sata_deb_timing_long, deadline);
656 reason = "PHY debouncing failed";
660 if (tmp & PORT_CS_DEV_RST) {
661 if (ata_port_offline(ap))
663 reason = "link not ready";
667 /* Sil24 doesn't store signature FIS after hardreset, so we
668 * can't wait for BSY to clear. Some devices take a long time
669 * to get ready and those devices will choke if we don't wait
670 * for BSY clearance here. Tell libata to perform follow-up
676 ata_port_printk(ap, KERN_ERR, "hardreset failed (%s)\n", reason);
680 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
681 struct sil24_sge *sge)
683 struct scatterlist *sg;
685 ata_for_each_sg(sg, qc) {
686 sge->addr = cpu_to_le64(sg_dma_address(sg));
687 sge->cnt = cpu_to_le32(sg_dma_len(sg));
688 if (ata_sg_is_last(sg, qc))
689 sge->flags = cpu_to_le32(SGE_TRM);
696 static void sil24_qc_prep(struct ata_queued_cmd *qc)
698 struct ata_port *ap = qc->ap;
699 struct sil24_port_priv *pp = ap->private_data;
700 union sil24_cmd_block *cb;
701 struct sil24_prb *prb;
702 struct sil24_sge *sge;
705 cb = &pp->cmd_block[sil24_tag(qc->tag)];
707 switch (qc->tf.protocol) {
711 case ATA_PROT_NODATA:
717 case ATA_PROT_ATAPI_DMA:
718 case ATA_PROT_ATAPI_NODATA:
719 prb = &cb->atapi.prb;
721 memset(cb->atapi.cdb, 0, 32);
722 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
724 if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) {
725 if (qc->tf.flags & ATA_TFLAG_WRITE)
726 ctrl = PRB_CTRL_PACKET_WRITE;
728 ctrl = PRB_CTRL_PACKET_READ;
733 prb = NULL; /* shut up, gcc */
738 prb->ctrl = cpu_to_le16(ctrl);
739 ata_tf_to_fis(&qc->tf, 0, 1, prb->fis);
741 if (qc->flags & ATA_QCFLAG_DMAMAP)
742 sil24_fill_sg(qc, sge);
745 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
747 struct ata_port *ap = qc->ap;
748 struct sil24_port_priv *pp = ap->private_data;
749 void __iomem *port = ap->ioaddr.cmd_addr;
750 unsigned int tag = sil24_tag(qc->tag);
752 void __iomem *activate;
754 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
755 activate = port + PORT_CMD_ACTIVATE + tag * 8;
757 writel((u32)paddr, activate);
758 writel((u64)paddr >> 32, activate + 4);
763 static void sil24_irq_clear(struct ata_port *ap)
768 static void sil24_freeze(struct ata_port *ap)
770 void __iomem *port = ap->ioaddr.cmd_addr;
772 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
773 * PORT_IRQ_ENABLE instead.
775 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
778 static void sil24_thaw(struct ata_port *ap)
780 void __iomem *port = ap->ioaddr.cmd_addr;
784 tmp = readl(port + PORT_IRQ_STAT);
785 writel(tmp, port + PORT_IRQ_STAT);
787 /* turn IRQ back on */
788 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
791 static void sil24_error_intr(struct ata_port *ap)
793 void __iomem *port = ap->ioaddr.cmd_addr;
794 struct sil24_port_priv *pp = ap->private_data;
795 struct ata_eh_info *ehi = &ap->eh_info;
799 /* on error, we need to clear IRQ explicitly */
800 irq_stat = readl(port + PORT_IRQ_STAT);
801 writel(irq_stat, port + PORT_IRQ_STAT);
803 /* first, analyze and record host port events */
804 ata_ehi_clear_desc(ehi);
806 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
808 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
809 ata_ehi_hotplugged(ehi);
810 ata_ehi_push_desc(ehi, ", %s",
811 irq_stat & PORT_IRQ_PHYRDY_CHG ?
812 "PHY RDY changed" : "device exchanged");
816 if (irq_stat & PORT_IRQ_UNK_FIS) {
817 ehi->err_mask |= AC_ERR_HSM;
818 ehi->action |= ATA_EH_SOFTRESET;
819 ata_ehi_push_desc(ehi , ", unknown FIS");
823 /* deal with command error */
824 if (irq_stat & PORT_IRQ_ERROR) {
825 struct sil24_cerr_info *ci = NULL;
826 unsigned int err_mask = 0, action = 0;
827 struct ata_queued_cmd *qc;
830 /* analyze CMD_ERR */
831 cerr = readl(port + PORT_CMD_ERR);
832 if (cerr < ARRAY_SIZE(sil24_cerr_db))
833 ci = &sil24_cerr_db[cerr];
835 if (ci && ci->desc) {
836 err_mask |= ci->err_mask;
837 action |= ci->action;
838 ata_ehi_push_desc(ehi, ", %s", ci->desc);
840 err_mask |= AC_ERR_OTHER;
841 action |= ATA_EH_SOFTRESET;
842 ata_ehi_push_desc(ehi, ", unknown command error %d",
846 /* record error info */
847 qc = ata_qc_from_tag(ap, ap->active_tag);
849 sil24_read_tf(ap, qc->tag, &pp->tf);
850 qc->err_mask |= err_mask;
852 ehi->err_mask |= err_mask;
854 ehi->action |= action;
857 /* freeze or abort */
864 static void sil24_finish_qc(struct ata_queued_cmd *qc)
866 struct ata_port *ap = qc->ap;
867 struct sil24_port_priv *pp = ap->private_data;
869 if (qc->flags & ATA_QCFLAG_RESULT_TF)
870 sil24_read_tf(ap, qc->tag, &pp->tf);
873 static inline void sil24_host_intr(struct ata_port *ap)
875 void __iomem *port = ap->ioaddr.cmd_addr;
876 u32 slot_stat, qc_active;
879 slot_stat = readl(port + PORT_SLOT_STAT);
881 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
882 sil24_error_intr(ap);
886 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
887 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
889 qc_active = slot_stat & ~HOST_SSTAT_ATTN;
890 rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc);
894 struct ata_eh_info *ehi = &ap->eh_info;
895 ehi->err_mask |= AC_ERR_HSM;
896 ehi->action |= ATA_EH_SOFTRESET;
902 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
903 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
904 slot_stat, ap->active_tag, ap->sactive);
907 static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
909 struct ata_host *host = dev_instance;
910 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
911 unsigned handled = 0;
915 status = readl(host_base + HOST_IRQ_STAT);
917 if (status == 0xffffffff) {
918 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
919 "PCI fault or device removal?\n");
923 if (!(status & IRQ_STAT_4PORTS))
926 spin_lock(&host->lock);
928 for (i = 0; i < host->n_ports; i++)
929 if (status & (1 << i)) {
930 struct ata_port *ap = host->ports[i];
931 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
935 printk(KERN_ERR DRV_NAME
936 ": interrupt from disabled port %d\n", i);
939 spin_unlock(&host->lock);
941 return IRQ_RETVAL(handled);
944 static void sil24_error_handler(struct ata_port *ap)
946 struct ata_eh_context *ehc = &ap->eh_context;
948 if (sil24_init_port(ap)) {
949 ata_eh_freeze_port(ap);
950 ehc->i.action |= ATA_EH_HARDRESET;
953 /* perform recovery */
954 ata_do_eh(ap, ata_std_prereset, sil24_softreset, sil24_hardreset,
958 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
960 struct ata_port *ap = qc->ap;
962 /* make DMA engine forget about the failed command */
963 if (qc->flags & ATA_QCFLAG_FAILED)
967 static int sil24_port_start(struct ata_port *ap)
969 struct device *dev = ap->host->dev;
970 struct sil24_port_priv *pp;
971 union sil24_cmd_block *cb;
972 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
976 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
980 pp->tf.command = ATA_DRDY;
982 cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
985 memset(cb, 0, cb_size);
987 rc = ata_pad_alloc(ap, dev);
992 pp->cmd_block_dma = cb_dma;
994 ap->private_data = pp;
999 static void sil24_init_controller(struct ata_host *host)
1001 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1002 void __iomem *port_base = host->iomap[SIL24_PORT_BAR];
1007 writel(0, host_base + HOST_FLASH_CMD);
1009 /* clear global reset & mask interrupts during initialization */
1010 writel(0, host_base + HOST_CTRL);
1013 for (i = 0; i < host->n_ports; i++) {
1014 void __iomem *port = port_base + i * PORT_REGS_SIZE;
1016 /* Initial PHY setting */
1017 writel(0x20c, port + PORT_PHY_CFG);
1019 /* Clear port RST */
1020 tmp = readl(port + PORT_CTRL_STAT);
1021 if (tmp & PORT_CS_PORT_RST) {
1022 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
1023 tmp = ata_wait_register(port + PORT_CTRL_STAT,
1025 PORT_CS_PORT_RST, 10, 100);
1026 if (tmp & PORT_CS_PORT_RST)
1027 dev_printk(KERN_ERR, host->dev,
1028 "failed to clear port RST\n");
1031 /* Configure IRQ WoC */
1032 if (host->ports[0]->flags & SIL24_FLAG_PCIX_IRQ_WOC)
1033 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
1035 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
1037 /* Zero error counters. */
1038 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
1039 writel(0x8000, port + PORT_CRC_ERR_THRESH);
1040 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
1041 writel(0x0000, port + PORT_DECODE_ERR_CNT);
1042 writel(0x0000, port + PORT_CRC_ERR_CNT);
1043 writel(0x0000, port + PORT_HSHK_ERR_CNT);
1045 /* Always use 64bit activation */
1046 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
1048 /* Clear port multiplier enable and resume bits */
1049 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME,
1050 port + PORT_CTRL_CLR);
1053 /* Turn on interrupts */
1054 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1057 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1059 static int printed_version = 0;
1060 struct ata_port_info pi = sil24_port_info[ent->driver_data];
1061 const struct ata_port_info *ppi[] = { &pi, NULL };
1062 void __iomem * const *iomap;
1063 struct ata_host *host;
1067 if (!printed_version++)
1068 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1070 /* acquire resources */
1071 rc = pcim_enable_device(pdev);
1075 rc = pcim_iomap_regions(pdev,
1076 (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR),
1080 iomap = pcim_iomap_table(pdev);
1082 /* apply workaround for completion IRQ loss on PCI-X errata */
1083 if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1084 tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL);
1085 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1086 dev_printk(KERN_INFO, &pdev->dev,
1087 "Applying completion IRQ loss on PCI-X "
1090 pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1093 /* allocate and fill host */
1094 host = ata_host_alloc_pinfo(&pdev->dev, ppi,
1095 SIL24_FLAG2NPORTS(ppi[0]->flags));
1098 host->iomap = iomap;
1100 for (i = 0; i < host->n_ports; i++) {
1101 void __iomem *port = iomap[SIL24_PORT_BAR] + i * PORT_REGS_SIZE;
1103 host->ports[i]->ioaddr.cmd_addr = port;
1104 host->ports[i]->ioaddr.scr_addr = port + PORT_SCONTROL;
1106 ata_std_ports(&host->ports[i]->ioaddr);
1109 /* configure and activate the device */
1110 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1111 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1113 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1115 dev_printk(KERN_ERR, &pdev->dev,
1116 "64-bit DMA enable failed\n");
1121 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1123 dev_printk(KERN_ERR, &pdev->dev,
1124 "32-bit DMA enable failed\n");
1127 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1129 dev_printk(KERN_ERR, &pdev->dev,
1130 "32-bit consistent DMA enable failed\n");
1135 sil24_init_controller(host);
1137 pci_set_master(pdev);
1138 return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED,
1143 static int sil24_pci_device_resume(struct pci_dev *pdev)
1145 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1146 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1149 rc = ata_pci_device_do_resume(pdev);
1153 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
1154 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
1156 sil24_init_controller(host);
1158 ata_host_resume(host);
1164 static int __init sil24_init(void)
1166 return pci_register_driver(&sil24_pci_driver);
1169 static void __exit sil24_exit(void)
1171 pci_unregister_driver(&sil24_pci_driver);
1174 MODULE_AUTHOR("Tejun Heo");
1175 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1176 MODULE_LICENSE("GPL");
1177 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1179 module_init(sil24_init);
1180 module_exit(sil24_exit);