2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
4 * Copyright 2005 Tejun Heo
6 * Based on preview driver from Silicon Image.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/blkdev.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/device.h>
28 #include <scsi/scsi_host.h>
29 #include <scsi/scsi_cmnd.h>
30 #include <linux/libata.h>
32 #define DRV_NAME "sata_sil24"
33 #define DRV_VERSION "1.1"
36 * Port request block (PRB) 32 bytes
46 * Scatter gather entry (SGE) 16 bytes
57 struct sil24_port_multiplier {
67 * Global controller registers (128 bytes @ BAR0)
70 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
74 HOST_BIST_CTRL = 0x50,
75 HOST_BIST_PTRN = 0x54,
76 HOST_BIST_STAT = 0x58,
77 HOST_MEM_BIST_STAT = 0x5c,
78 HOST_FLASH_CMD = 0x70,
80 HOST_FLASH_DATA = 0x74,
81 HOST_TRANSITION_DETECT = 0x75,
82 HOST_GPIO_CTRL = 0x76,
83 HOST_I2C_ADDR = 0x78, /* 32 bit */
85 HOST_I2C_XFER_CNT = 0x7e,
88 /* HOST_SLOT_STAT bits */
89 HOST_SSTAT_ATTN = (1 << 31),
92 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
93 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
94 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
95 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
96 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
97 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
101 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
103 PORT_REGS_SIZE = 0x2000,
105 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
106 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
108 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
109 PORT_PMP_STATUS = 0x0000, /* port device status offset */
110 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
111 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
114 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
115 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
116 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
117 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
118 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
119 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
120 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
121 PORT_CMD_ERR = 0x1024, /* command error number */
122 PORT_FIS_CFG = 0x1028,
123 PORT_FIFO_THRES = 0x102c,
125 PORT_DECODE_ERR_CNT = 0x1040,
126 PORT_DECODE_ERR_THRESH = 0x1042,
127 PORT_CRC_ERR_CNT = 0x1044,
128 PORT_CRC_ERR_THRESH = 0x1046,
129 PORT_HSHK_ERR_CNT = 0x1048,
130 PORT_HSHK_ERR_THRESH = 0x104a,
132 PORT_PHY_CFG = 0x1050,
133 PORT_SLOT_STAT = 0x1800,
134 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
135 PORT_CONTEXT = 0x1e04,
136 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
137 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
138 PORT_SCONTROL = 0x1f00,
139 PORT_SSTATUS = 0x1f04,
140 PORT_SERROR = 0x1f08,
141 PORT_SACTIVE = 0x1f0c,
143 /* PORT_CTRL_STAT bits */
144 PORT_CS_PORT_RST = (1 << 0), /* port reset */
145 PORT_CS_DEV_RST = (1 << 1), /* device reset */
146 PORT_CS_INIT = (1 << 2), /* port initialize */
147 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
148 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
149 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
150 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
151 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
152 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
154 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
155 /* bits[11:0] are masked */
156 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
157 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
158 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
159 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
160 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
161 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
162 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
163 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
164 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
165 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
166 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
167 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
169 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
170 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
171 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
173 /* bits[27:16] are unmasked (raw) */
174 PORT_IRQ_RAW_SHIFT = 16,
175 PORT_IRQ_MASKED_MASK = 0x7ff,
176 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
178 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
179 PORT_IRQ_STEER_SHIFT = 30,
180 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
182 /* PORT_CMD_ERR constants */
183 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
184 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
185 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
186 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
187 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
188 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
189 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
190 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
191 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
192 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
193 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
194 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
195 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
196 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
197 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
198 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
199 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
200 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
201 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
202 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
203 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
204 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
206 /* bits of PRB control field */
207 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
208 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
209 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
210 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
211 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
213 /* PRB protocol field */
214 PRB_PROT_PACKET = (1 << 0),
215 PRB_PROT_TCQ = (1 << 1),
216 PRB_PROT_NCQ = (1 << 2),
217 PRB_PROT_READ = (1 << 3),
218 PRB_PROT_WRITE = (1 << 4),
219 PRB_PROT_TRANSPARENT = (1 << 5),
224 SGE_TRM = (1 << 31), /* Last SGE in chain */
225 SGE_LNK = (1 << 30), /* linked list
226 Points to SGT, not SGE */
227 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
228 data address ignored */
238 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
239 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
240 ATA_FLAG_NCQ | ATA_FLAG_ACPI_SATA |
241 ATA_FLAG_AN | ATA_FLAG_PMP,
242 SIL24_COMMON_LFLAGS = ATA_LFLAG_SKIP_D2H_BSY,
243 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
245 IRQ_STAT_4PORTS = 0xf,
248 struct sil24_ata_block {
249 struct sil24_prb prb;
250 struct sil24_sge sge[LIBATA_MAX_PRD];
253 struct sil24_atapi_block {
254 struct sil24_prb prb;
256 struct sil24_sge sge[LIBATA_MAX_PRD - 1];
259 union sil24_cmd_block {
260 struct sil24_ata_block ata;
261 struct sil24_atapi_block atapi;
264 static struct sil24_cerr_info {
265 unsigned int err_mask, action;
267 } sil24_cerr_db[] = {
268 [0] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
270 [PORT_CERR_DEV] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
271 "device error via D2H FIS" },
272 [PORT_CERR_SDB] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
273 "device error via SDB FIS" },
274 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
275 "error in data FIS" },
276 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
277 "failed to transmit command FIS" },
278 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
279 "protocol mismatch" },
280 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
281 "data directon mismatch" },
282 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
283 "ran out of SGEs while writing" },
284 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
285 "ran out of SGEs while reading" },
286 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
287 "invalid data directon for ATAPI CDB" },
288 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
289 "SGT no on qword boundary" },
290 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
291 "PCI target abort while fetching SGT" },
292 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
293 "PCI master abort while fetching SGT" },
294 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
295 "PCI parity error while fetching SGT" },
296 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
297 "PRB not on qword boundary" },
298 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
299 "PCI target abort while fetching PRB" },
300 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
301 "PCI master abort while fetching PRB" },
302 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
303 "PCI parity error while fetching PRB" },
304 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
305 "undefined error while transferring data" },
306 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
307 "PCI target abort while transferring data" },
308 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
309 "PCI master abort while transferring data" },
310 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
311 "PCI parity error while transferring data" },
312 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
313 "FIS received while sending service FIS" },
319 * The preview driver always returned 0 for status. We emulate it
320 * here from the previous interrupt.
322 struct sil24_port_priv {
323 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
324 dma_addr_t cmd_block_dma; /* DMA base addr for them */
325 struct ata_taskfile tf; /* Cached taskfile registers */
329 static void sil24_dev_config(struct ata_device *dev);
330 static u8 sil24_check_status(struct ata_port *ap);
331 static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val);
332 static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
333 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
334 static int sil24_qc_defer(struct ata_queued_cmd *qc);
335 static void sil24_qc_prep(struct ata_queued_cmd *qc);
336 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
337 static void sil24_irq_clear(struct ata_port *ap);
338 static void sil24_pmp_attach(struct ata_port *ap);
339 static void sil24_pmp_detach(struct ata_port *ap);
340 static int sil24_pmp_read(struct ata_device *dev, int pmp, int reg, u32 *r_val);
341 static int sil24_pmp_write(struct ata_device *dev, int pmp, int reg, u32 val);
342 static void sil24_freeze(struct ata_port *ap);
343 static void sil24_thaw(struct ata_port *ap);
344 static void sil24_error_handler(struct ata_port *ap);
345 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
346 static int sil24_port_start(struct ata_port *ap);
347 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
349 static int sil24_pci_device_resume(struct pci_dev *pdev);
350 static int sil24_port_resume(struct ata_port *ap);
353 static const struct pci_device_id sil24_pci_tbl[] = {
354 { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
355 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
356 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
357 { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
358 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
359 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
361 { } /* terminate list */
364 static struct pci_driver sil24_pci_driver = {
366 .id_table = sil24_pci_tbl,
367 .probe = sil24_init_one,
368 .remove = ata_pci_remove_one,
370 .suspend = ata_pci_device_suspend,
371 .resume = sil24_pci_device_resume,
375 static struct scsi_host_template sil24_sht = {
376 .module = THIS_MODULE,
378 .ioctl = ata_scsi_ioctl,
379 .queuecommand = ata_scsi_queuecmd,
380 .change_queue_depth = ata_scsi_change_queue_depth,
381 .can_queue = SIL24_MAX_CMDS,
382 .this_id = ATA_SHT_THIS_ID,
383 .sg_tablesize = LIBATA_MAX_PRD,
384 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
385 .emulated = ATA_SHT_EMULATED,
386 .use_clustering = ATA_SHT_USE_CLUSTERING,
387 .proc_name = DRV_NAME,
388 .dma_boundary = ATA_DMA_BOUNDARY,
389 .slave_configure = ata_scsi_slave_config,
390 .slave_destroy = ata_scsi_slave_destroy,
391 .bios_param = ata_std_bios_param,
394 static const struct ata_port_operations sil24_ops = {
395 .dev_config = sil24_dev_config,
397 .check_status = sil24_check_status,
398 .check_altstatus = sil24_check_status,
399 .dev_select = ata_noop_dev_select,
401 .tf_read = sil24_tf_read,
403 .qc_defer = sil24_qc_defer,
404 .qc_prep = sil24_qc_prep,
405 .qc_issue = sil24_qc_issue,
407 .irq_clear = sil24_irq_clear,
409 .scr_read = sil24_scr_read,
410 .scr_write = sil24_scr_write,
412 .pmp_attach = sil24_pmp_attach,
413 .pmp_detach = sil24_pmp_detach,
414 .pmp_read = sil24_pmp_read,
415 .pmp_write = sil24_pmp_write,
417 .freeze = sil24_freeze,
419 .error_handler = sil24_error_handler,
420 .post_internal_cmd = sil24_post_internal_cmd,
422 .port_start = sil24_port_start,
425 .port_resume = sil24_port_resume,
430 * Use bits 30-31 of port_flags to encode available port numbers.
431 * Current maxium is 4.
433 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
434 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
436 static const struct ata_port_info sil24_port_info[] = {
439 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
440 SIL24_FLAG_PCIX_IRQ_WOC,
441 .link_flags = SIL24_COMMON_LFLAGS,
442 .pio_mask = 0x1f, /* pio0-4 */
443 .mwdma_mask = 0x07, /* mwdma0-2 */
444 .udma_mask = ATA_UDMA5, /* udma0-5 */
445 .port_ops = &sil24_ops,
449 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
450 .link_flags = SIL24_COMMON_LFLAGS,
451 .pio_mask = 0x1f, /* pio0-4 */
452 .mwdma_mask = 0x07, /* mwdma0-2 */
453 .udma_mask = ATA_UDMA5, /* udma0-5 */
454 .port_ops = &sil24_ops,
456 /* sil_3131/sil_3531 */
458 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
459 .link_flags = SIL24_COMMON_LFLAGS,
460 .pio_mask = 0x1f, /* pio0-4 */
461 .mwdma_mask = 0x07, /* mwdma0-2 */
462 .udma_mask = ATA_UDMA5, /* udma0-5 */
463 .port_ops = &sil24_ops,
467 static int sil24_tag(int tag)
469 if (unlikely(ata_tag_internal(tag)))
474 static void sil24_dev_config(struct ata_device *dev)
476 void __iomem *port = dev->link->ap->ioaddr.cmd_addr;
478 if (dev->cdb_len == 16)
479 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
481 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
484 static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf)
486 void __iomem *port = ap->ioaddr.cmd_addr;
487 struct sil24_prb __iomem *prb;
490 prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ;
491 memcpy_fromio(fis, prb->fis, sizeof(fis));
492 ata_tf_from_fis(fis, tf);
495 static u8 sil24_check_status(struct ata_port *ap)
497 struct sil24_port_priv *pp = ap->private_data;
498 return pp->tf.command;
501 static int sil24_scr_map[] = {
508 static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val)
510 void __iomem *scr_addr = ap->ioaddr.scr_addr;
512 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
514 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
515 *val = readl(scr_addr + sil24_scr_map[sc_reg] * 4);
521 static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
523 void __iomem *scr_addr = ap->ioaddr.scr_addr;
525 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
527 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
528 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
534 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
536 struct sil24_port_priv *pp = ap->private_data;
540 static void sil24_config_port(struct ata_port *ap)
542 void __iomem *port = ap->ioaddr.cmd_addr;
544 /* configure IRQ WoC */
545 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
546 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
548 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
550 /* zero error counters. */
551 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
552 writel(0x8000, port + PORT_CRC_ERR_THRESH);
553 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
554 writel(0x0000, port + PORT_DECODE_ERR_CNT);
555 writel(0x0000, port + PORT_CRC_ERR_CNT);
556 writel(0x0000, port + PORT_HSHK_ERR_CNT);
558 /* always use 64bit activation */
559 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
561 /* clear port multiplier enable and resume bits */
562 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
565 static void sil24_config_pmp(struct ata_port *ap, int attached)
567 void __iomem *port = ap->ioaddr.cmd_addr;
570 writel(PORT_CS_PMP_EN, port + PORT_CTRL_STAT);
572 writel(PORT_CS_PMP_EN, port + PORT_CTRL_CLR);
575 static void sil24_clear_pmp(struct ata_port *ap)
577 void __iomem *port = ap->ioaddr.cmd_addr;
580 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
582 for (i = 0; i < SATA_PMP_MAX_PORTS; i++) {
583 void __iomem *pmp_base = port + PORT_PMP + i * PORT_PMP_SIZE;
585 writel(0, pmp_base + PORT_PMP_STATUS);
586 writel(0, pmp_base + PORT_PMP_QACTIVE);
590 static int sil24_init_port(struct ata_port *ap)
592 void __iomem *port = ap->ioaddr.cmd_addr;
593 struct sil24_port_priv *pp = ap->private_data;
596 /* clear PMP error status */
597 if (ap->nr_pmp_links)
600 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
601 ata_wait_register(port + PORT_CTRL_STAT,
602 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
603 tmp = ata_wait_register(port + PORT_CTRL_STAT,
604 PORT_CS_RDY, 0, 10, 100);
606 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) {
608 ap->link.eh_context.i.action |= ATA_EH_HARDRESET;
615 static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp,
616 const struct ata_taskfile *tf,
617 int is_cmd, u32 ctrl,
618 unsigned long timeout_msec)
620 void __iomem *port = ap->ioaddr.cmd_addr;
621 struct sil24_port_priv *pp = ap->private_data;
622 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
623 dma_addr_t paddr = pp->cmd_block_dma;
624 u32 irq_enabled, irq_mask, irq_stat;
627 prb->ctrl = cpu_to_le16(ctrl);
628 ata_tf_to_fis(tf, pmp, is_cmd, prb->fis);
630 /* temporarily plug completion and error interrupts */
631 irq_enabled = readl(port + PORT_IRQ_ENABLE_SET);
632 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
634 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
635 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
637 irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
638 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask, 0x0,
641 writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */
642 irq_stat >>= PORT_IRQ_RAW_SHIFT;
644 if (irq_stat & PORT_IRQ_COMPLETE)
647 /* force port into known state */
650 if (irq_stat & PORT_IRQ_ERROR)
656 /* restore IRQ enabled */
657 writel(irq_enabled, port + PORT_IRQ_ENABLE_SET);
662 static int sil24_do_softreset(struct ata_link *link, unsigned int *class,
663 int pmp, unsigned long deadline)
665 struct ata_port *ap = link->ap;
666 unsigned long timeout_msec = 0;
667 struct ata_taskfile tf;
673 if (ata_link_offline(link)) {
674 DPRINTK("PHY reports no device\n");
675 *class = ATA_DEV_NONE;
679 /* put the port into known state */
680 if (sil24_init_port(ap)) {
681 reason ="port not ready";
686 if (time_after(deadline, jiffies))
687 timeout_msec = jiffies_to_msecs(deadline - jiffies);
689 ata_tf_init(link->device, &tf); /* doesn't really matter */
690 rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST,
696 reason = "SRST command error";
700 sil24_read_tf(ap, 0, &tf);
701 *class = ata_dev_classify(&tf);
703 if (*class == ATA_DEV_UNKNOWN)
704 *class = ATA_DEV_NONE;
707 DPRINTK("EXIT, class=%u\n", *class);
711 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
715 static int sil24_softreset(struct ata_link *link, unsigned int *class,
716 unsigned long deadline)
718 return sil24_do_softreset(link, class, SATA_PMP_CTRL_PORT, deadline);
721 static int sil24_hardreset(struct ata_link *link, unsigned int *class,
722 unsigned long deadline)
724 struct ata_port *ap = link->ap;
725 void __iomem *port = ap->ioaddr.cmd_addr;
726 struct sil24_port_priv *pp = ap->private_data;
727 int did_port_rst = 0;
733 /* Sometimes, DEV_RST is not enough to recover the controller.
734 * This happens often after PM DMA CS errata.
736 if (pp->do_port_rst) {
737 ata_port_printk(ap, KERN_WARNING, "controller in dubious "
738 "state, performing PORT_RST\n");
740 writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT);
742 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
743 ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_RDY, 0,
746 /* restore port configuration */
747 sil24_config_port(ap);
748 sil24_config_pmp(ap, ap->nr_pmp_links);
754 /* sil24 does the right thing(tm) without any protection */
758 if (ata_link_online(link))
761 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
762 tmp = ata_wait_register(port + PORT_CTRL_STAT,
763 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, tout_msec);
765 /* SStatus oscillates between zero and valid status after
766 * DEV_RST, debounce it.
768 rc = sata_link_debounce(link, sata_deb_timing_long, deadline);
770 reason = "PHY debouncing failed";
774 if (tmp & PORT_CS_DEV_RST) {
775 if (ata_link_offline(link))
777 reason = "link not ready";
781 /* Sil24 doesn't store signature FIS after hardreset, so we
782 * can't wait for BSY to clear. Some devices take a long time
783 * to get ready and those devices will choke if we don't wait
784 * for BSY clearance here. Tell libata to perform follow-up
795 ata_link_printk(link, KERN_ERR, "hardreset failed (%s)\n", reason);
799 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
800 struct sil24_sge *sge)
802 struct scatterlist *sg;
804 ata_for_each_sg(sg, qc) {
805 sge->addr = cpu_to_le64(sg_dma_address(sg));
806 sge->cnt = cpu_to_le32(sg_dma_len(sg));
807 if (ata_sg_is_last(sg, qc))
808 sge->flags = cpu_to_le32(SGE_TRM);
815 static int sil24_qc_defer(struct ata_queued_cmd *qc)
817 struct ata_link *link = qc->dev->link;
818 struct ata_port *ap = link->ap;
819 u8 prot = qc->tf.protocol;
820 int is_atapi = (prot == ATA_PROT_ATAPI ||
821 prot == ATA_PROT_ATAPI_NODATA ||
822 prot == ATA_PROT_ATAPI_DMA);
824 /* ATAPI commands completing with CHECK_SENSE cause various
825 * weird problems if other commands are active. PMP DMA CS
826 * errata doesn't cover all and HSM violation occurs even with
827 * only one other device active. Always run an ATAPI command
830 if (unlikely(ap->excl_link)) {
831 if (link == ap->excl_link) {
832 if (ap->nr_active_links)
833 return ATA_DEFER_PORT;
834 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
836 return ATA_DEFER_PORT;
837 } else if (unlikely(is_atapi)) {
838 ap->excl_link = link;
839 if (ap->nr_active_links)
840 return ATA_DEFER_PORT;
841 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
844 return ata_std_qc_defer(qc);
847 static void sil24_qc_prep(struct ata_queued_cmd *qc)
849 struct ata_port *ap = qc->ap;
850 struct sil24_port_priv *pp = ap->private_data;
851 union sil24_cmd_block *cb;
852 struct sil24_prb *prb;
853 struct sil24_sge *sge;
856 cb = &pp->cmd_block[sil24_tag(qc->tag)];
858 switch (qc->tf.protocol) {
862 case ATA_PROT_NODATA:
868 case ATA_PROT_ATAPI_DMA:
869 case ATA_PROT_ATAPI_NODATA:
870 prb = &cb->atapi.prb;
872 memset(cb->atapi.cdb, 0, 32);
873 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
875 if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) {
876 if (qc->tf.flags & ATA_TFLAG_WRITE)
877 ctrl = PRB_CTRL_PACKET_WRITE;
879 ctrl = PRB_CTRL_PACKET_READ;
884 prb = NULL; /* shut up, gcc */
889 prb->ctrl = cpu_to_le16(ctrl);
890 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, prb->fis);
892 if (qc->flags & ATA_QCFLAG_DMAMAP)
893 sil24_fill_sg(qc, sge);
896 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
898 struct ata_port *ap = qc->ap;
899 struct sil24_port_priv *pp = ap->private_data;
900 void __iomem *port = ap->ioaddr.cmd_addr;
901 unsigned int tag = sil24_tag(qc->tag);
903 void __iomem *activate;
905 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
906 activate = port + PORT_CMD_ACTIVATE + tag * 8;
908 writel((u32)paddr, activate);
909 writel((u64)paddr >> 32, activate + 4);
914 static void sil24_irq_clear(struct ata_port *ap)
919 static void sil24_pmp_attach(struct ata_port *ap)
921 sil24_config_pmp(ap, 1);
925 static void sil24_pmp_detach(struct ata_port *ap)
928 sil24_config_pmp(ap, 0);
931 static int sil24_pmp_read(struct ata_device *dev, int pmp, int reg, u32 *r_val)
933 struct ata_port *ap = dev->link->ap;
934 struct ata_taskfile tf;
937 sata_pmp_read_init_tf(&tf, dev, pmp, reg);
938 rc = sil24_exec_polled_cmd(ap, SATA_PMP_CTRL_PORT, &tf, 1, 0,
939 SATA_PMP_SCR_TIMEOUT);
941 sil24_read_tf(ap, 0, &tf);
942 *r_val = sata_pmp_read_val(&tf);
947 static int sil24_pmp_write(struct ata_device *dev, int pmp, int reg, u32 val)
949 struct ata_port *ap = dev->link->ap;
950 struct ata_taskfile tf;
952 sata_pmp_write_init_tf(&tf, dev, pmp, reg, val);
953 return sil24_exec_polled_cmd(ap, SATA_PMP_CTRL_PORT, &tf, 1, 0,
954 SATA_PMP_SCR_TIMEOUT);
957 static int sil24_pmp_softreset(struct ata_link *link, unsigned int *class,
958 unsigned long deadline)
960 return sil24_do_softreset(link, class, link->pmp, deadline);
963 static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
964 unsigned long deadline)
968 rc = sil24_init_port(link->ap);
970 ata_link_printk(link, KERN_ERR,
971 "hardreset failed (port not ready)\n");
975 return sata_pmp_std_hardreset(link, class, deadline);
978 static void sil24_freeze(struct ata_port *ap)
980 void __iomem *port = ap->ioaddr.cmd_addr;
982 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
983 * PORT_IRQ_ENABLE instead.
985 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
988 static void sil24_thaw(struct ata_port *ap)
990 void __iomem *port = ap->ioaddr.cmd_addr;
994 tmp = readl(port + PORT_IRQ_STAT);
995 writel(tmp, port + PORT_IRQ_STAT);
997 /* turn IRQ back on */
998 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
1001 static void sil24_error_intr(struct ata_port *ap)
1003 void __iomem *port = ap->ioaddr.cmd_addr;
1004 struct sil24_port_priv *pp = ap->private_data;
1005 struct ata_queued_cmd *qc = NULL;
1006 struct ata_link *link;
1007 struct ata_eh_info *ehi;
1008 int abort = 0, freeze = 0;
1011 /* on error, we need to clear IRQ explicitly */
1012 irq_stat = readl(port + PORT_IRQ_STAT);
1013 writel(irq_stat, port + PORT_IRQ_STAT);
1015 /* first, analyze and record host port events */
1017 ehi = &link->eh_info;
1018 ata_ehi_clear_desc(ehi);
1020 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
1022 if (irq_stat & PORT_IRQ_SDB_NOTIFY) {
1023 ata_ehi_push_desc(ehi, "SDB notify");
1024 sata_async_notification(ap);
1027 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
1028 ata_ehi_hotplugged(ehi);
1029 ata_ehi_push_desc(ehi, "%s",
1030 irq_stat & PORT_IRQ_PHYRDY_CHG ?
1031 "PHY RDY changed" : "device exchanged");
1035 if (irq_stat & PORT_IRQ_UNK_FIS) {
1036 ehi->err_mask |= AC_ERR_HSM;
1037 ehi->action |= ATA_EH_SOFTRESET;
1038 ata_ehi_push_desc(ehi, "unknown FIS");
1042 /* deal with command error */
1043 if (irq_stat & PORT_IRQ_ERROR) {
1044 struct sil24_cerr_info *ci = NULL;
1045 unsigned int err_mask = 0, action = 0;
1051 /* DMA Context Switch Failure in Port Multiplier Mode
1052 * errata. If we have active commands to 3 or more
1053 * devices, any error condition on active devices can
1054 * corrupt DMA context switching.
1056 if (ap->nr_active_links >= 3) {
1057 ehi->err_mask |= AC_ERR_OTHER;
1058 ehi->action |= ATA_EH_HARDRESET;
1059 ata_ehi_push_desc(ehi, "PMP DMA CS errata");
1060 pp->do_port_rst = 1;
1064 /* find out the offending link and qc */
1065 if (ap->nr_pmp_links) {
1066 context = readl(port + PORT_CONTEXT);
1067 pmp = (context >> 5) & 0xf;
1069 if (pmp < ap->nr_pmp_links) {
1070 link = &ap->pmp_link[pmp];
1071 ehi = &link->eh_info;
1072 qc = ata_qc_from_tag(ap, link->active_tag);
1074 ata_ehi_clear_desc(ehi);
1075 ata_ehi_push_desc(ehi, "irq_stat 0x%08x",
1078 err_mask |= AC_ERR_HSM;
1079 action |= ATA_EH_HARDRESET;
1083 qc = ata_qc_from_tag(ap, link->active_tag);
1085 /* analyze CMD_ERR */
1086 cerr = readl(port + PORT_CMD_ERR);
1087 if (cerr < ARRAY_SIZE(sil24_cerr_db))
1088 ci = &sil24_cerr_db[cerr];
1090 if (ci && ci->desc) {
1091 err_mask |= ci->err_mask;
1092 action |= ci->action;
1093 ata_ehi_push_desc(ehi, "%s", ci->desc);
1095 err_mask |= AC_ERR_OTHER;
1096 action |= ATA_EH_SOFTRESET;
1097 ata_ehi_push_desc(ehi, "unknown command error %d",
1101 /* record error info */
1103 sil24_read_tf(ap, qc->tag, &pp->tf);
1104 qc->err_mask |= err_mask;
1106 ehi->err_mask |= err_mask;
1108 ehi->action |= action;
1110 /* if PMP, resume */
1111 if (ap->nr_pmp_links)
1112 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_STAT);
1115 /* freeze or abort */
1117 ata_port_freeze(ap);
1120 ata_link_abort(qc->dev->link);
1126 static void sil24_finish_qc(struct ata_queued_cmd *qc)
1128 struct ata_port *ap = qc->ap;
1129 struct sil24_port_priv *pp = ap->private_data;
1131 if (qc->flags & ATA_QCFLAG_RESULT_TF)
1132 sil24_read_tf(ap, qc->tag, &pp->tf);
1135 static inline void sil24_host_intr(struct ata_port *ap)
1137 void __iomem *port = ap->ioaddr.cmd_addr;
1138 u32 slot_stat, qc_active;
1141 /* If PCIX_IRQ_WOC, there's an inherent race window between
1142 * clearing IRQ pending status and reading PORT_SLOT_STAT
1143 * which may cause spurious interrupts afterwards. This is
1144 * unavoidable and much better than losing interrupts which
1145 * happens if IRQ pending is cleared after reading
1148 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
1149 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
1151 slot_stat = readl(port + PORT_SLOT_STAT);
1153 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
1154 sil24_error_intr(ap);
1158 qc_active = slot_stat & ~HOST_SSTAT_ATTN;
1159 rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc);
1163 struct ata_eh_info *ehi = &ap->link.eh_info;
1164 ehi->err_mask |= AC_ERR_HSM;
1165 ehi->action |= ATA_EH_SOFTRESET;
1166 ata_port_freeze(ap);
1170 /* spurious interrupts are expected if PCIX_IRQ_WOC */
1171 if (!(ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) && ata_ratelimit())
1172 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1173 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
1174 slot_stat, ap->link.active_tag, ap->link.sactive);
1177 static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
1179 struct ata_host *host = dev_instance;
1180 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1181 unsigned handled = 0;
1185 status = readl(host_base + HOST_IRQ_STAT);
1187 if (status == 0xffffffff) {
1188 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
1189 "PCI fault or device removal?\n");
1193 if (!(status & IRQ_STAT_4PORTS))
1196 spin_lock(&host->lock);
1198 for (i = 0; i < host->n_ports; i++)
1199 if (status & (1 << i)) {
1200 struct ata_port *ap = host->ports[i];
1201 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
1202 sil24_host_intr(ap);
1205 printk(KERN_ERR DRV_NAME
1206 ": interrupt from disabled port %d\n", i);
1209 spin_unlock(&host->lock);
1211 return IRQ_RETVAL(handled);
1214 static void sil24_error_handler(struct ata_port *ap)
1216 struct sil24_port_priv *pp = ap->private_data;
1218 if (sil24_init_port(ap))
1219 ata_eh_freeze_port(ap);
1221 /* perform recovery */
1222 sata_pmp_do_eh(ap, ata_std_prereset, sil24_softreset, sil24_hardreset,
1223 ata_std_postreset, sata_pmp_std_prereset,
1224 sil24_pmp_softreset, sil24_pmp_hardreset,
1225 sata_pmp_std_postreset);
1227 pp->do_port_rst = 0;
1230 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
1232 struct ata_port *ap = qc->ap;
1234 /* make DMA engine forget about the failed command */
1235 if ((qc->flags & ATA_QCFLAG_FAILED) && sil24_init_port(ap))
1236 ata_eh_freeze_port(ap);
1239 static int sil24_port_start(struct ata_port *ap)
1241 struct device *dev = ap->host->dev;
1242 struct sil24_port_priv *pp;
1243 union sil24_cmd_block *cb;
1244 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
1248 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1252 pp->tf.command = ATA_DRDY;
1254 cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
1257 memset(cb, 0, cb_size);
1259 rc = ata_pad_alloc(ap, dev);
1264 pp->cmd_block_dma = cb_dma;
1266 ap->private_data = pp;
1271 static void sil24_init_controller(struct ata_host *host)
1273 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1278 writel(0, host_base + HOST_FLASH_CMD);
1280 /* clear global reset & mask interrupts during initialization */
1281 writel(0, host_base + HOST_CTRL);
1284 for (i = 0; i < host->n_ports; i++) {
1285 struct ata_port *ap = host->ports[i];
1286 void __iomem *port = ap->ioaddr.cmd_addr;
1288 /* Initial PHY setting */
1289 writel(0x20c, port + PORT_PHY_CFG);
1291 /* Clear port RST */
1292 tmp = readl(port + PORT_CTRL_STAT);
1293 if (tmp & PORT_CS_PORT_RST) {
1294 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
1295 tmp = ata_wait_register(port + PORT_CTRL_STAT,
1297 PORT_CS_PORT_RST, 10, 100);
1298 if (tmp & PORT_CS_PORT_RST)
1299 dev_printk(KERN_ERR, host->dev,
1300 "failed to clear port RST\n");
1303 /* configure port */
1304 sil24_config_port(ap);
1307 /* Turn on interrupts */
1308 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1311 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1313 static int printed_version = 0;
1314 struct ata_port_info pi = sil24_port_info[ent->driver_data];
1315 const struct ata_port_info *ppi[] = { &pi, NULL };
1316 void __iomem * const *iomap;
1317 struct ata_host *host;
1321 if (!printed_version++)
1322 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1324 /* acquire resources */
1325 rc = pcim_enable_device(pdev);
1329 rc = pcim_iomap_regions(pdev,
1330 (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR),
1334 iomap = pcim_iomap_table(pdev);
1336 /* apply workaround for completion IRQ loss on PCI-X errata */
1337 if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1338 tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL);
1339 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1340 dev_printk(KERN_INFO, &pdev->dev,
1341 "Applying completion IRQ loss on PCI-X "
1344 pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1347 /* allocate and fill host */
1348 host = ata_host_alloc_pinfo(&pdev->dev, ppi,
1349 SIL24_FLAG2NPORTS(ppi[0]->flags));
1352 host->iomap = iomap;
1354 for (i = 0; i < host->n_ports; i++) {
1355 struct ata_port *ap = host->ports[i];
1356 size_t offset = ap->port_no * PORT_REGS_SIZE;
1357 void __iomem *port = iomap[SIL24_PORT_BAR] + offset;
1359 host->ports[i]->ioaddr.cmd_addr = port;
1360 host->ports[i]->ioaddr.scr_addr = port + PORT_SCONTROL;
1362 ata_port_pbar_desc(ap, SIL24_HOST_BAR, -1, "host");
1363 ata_port_pbar_desc(ap, SIL24_PORT_BAR, offset, "port");
1366 /* configure and activate the device */
1367 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1368 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1370 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1372 dev_printk(KERN_ERR, &pdev->dev,
1373 "64-bit DMA enable failed\n");
1378 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1380 dev_printk(KERN_ERR, &pdev->dev,
1381 "32-bit DMA enable failed\n");
1384 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1386 dev_printk(KERN_ERR, &pdev->dev,
1387 "32-bit consistent DMA enable failed\n");
1392 sil24_init_controller(host);
1394 pci_set_master(pdev);
1395 return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED,
1400 static int sil24_pci_device_resume(struct pci_dev *pdev)
1402 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1403 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1406 rc = ata_pci_device_do_resume(pdev);
1410 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
1411 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
1413 sil24_init_controller(host);
1415 ata_host_resume(host);
1420 static int sil24_port_resume(struct ata_port *ap)
1422 sil24_config_pmp(ap, ap->nr_pmp_links);
1427 static int __init sil24_init(void)
1429 return pci_register_driver(&sil24_pci_driver);
1432 static void __exit sil24_exit(void)
1434 pci_unregister_driver(&sil24_pci_driver);
1437 MODULE_AUTHOR("Tejun Heo");
1438 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1439 MODULE_LICENSE("GPL");
1440 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1442 module_init(sil24_init);
1443 module_exit(sil24_exit);