2 * sata_mv.c - Marvell SATA support
4 * Copyright 2008: Marvell Corporation, all rights reserved.
5 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Copyright 2005 Red Hat, Inc. All rights reserved.
8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 * --> Errata workaround for NCQ device errors.
30 * --> More errata workarounds for PCI-X.
32 * --> Complete a full errata audit for all chipsets to identify others.
34 * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it).
36 * --> Investigate problems with PCI Message Signalled Interrupts (MSI).
38 * --> Cache frequently-accessed registers in mv_port_priv to reduce overhead.
40 * --> Develop a low-power-consumption strategy, and implement it.
42 * --> [Experiment, low priority] Investigate interrupt coalescing.
43 * Quite often, especially with PCI Message Signalled Interrupts (MSI),
44 * the overhead reduced by interrupt mitigation is quite often not
45 * worth the latency cost.
47 * --> [Experiment, Marvell value added] Is it possible to use target
48 * mode to cross-connect two Linux boxes with Marvell cards? If so,
49 * creating LibATA target mode support would be very interesting.
51 * Target mode, for those without docs, is the ability to directly
52 * connect two SATA ports.
55 #include <linux/kernel.h>
56 #include <linux/module.h>
57 #include <linux/pci.h>
58 #include <linux/init.h>
59 #include <linux/blkdev.h>
60 #include <linux/delay.h>
61 #include <linux/interrupt.h>
62 #include <linux/dmapool.h>
63 #include <linux/dma-mapping.h>
64 #include <linux/device.h>
65 #include <linux/platform_device.h>
66 #include <linux/ata_platform.h>
67 #include <linux/mbus.h>
68 #include <scsi/scsi_host.h>
69 #include <scsi/scsi_cmnd.h>
70 #include <scsi/scsi_device.h>
71 #include <linux/libata.h>
73 #define DRV_NAME "sata_mv"
74 #define DRV_VERSION "1.20"
77 /* BAR's are enumerated in terms of pci_resource_start() terms */
78 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
79 MV_IO_BAR = 2, /* offset 0x18: IO space */
80 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
82 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
83 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
86 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
87 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
88 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
89 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
90 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
91 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
93 MV_SATAHC0_REG_BASE = 0x20000,
94 MV_FLASH_CTL_OFS = 0x1046c,
95 MV_GPIO_PORT_CTL_OFS = 0x104f0,
96 MV_RESET_CFG_OFS = 0x180d8,
98 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
99 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
100 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
101 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
104 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
106 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
107 * CRPB needs alignment on a 256B boundary. Size == 256B
108 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
110 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
111 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
113 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
115 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
116 MV_PORT_HC_SHIFT = 2,
117 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
118 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
119 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
122 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
123 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
124 /* SoC integrated controllers, no PCI interface */
125 MV_FLAG_SOC = (1 << 28),
127 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
128 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
129 ATA_FLAG_PIO_POLLING,
130 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
132 CRQB_FLAG_READ = (1 << 0),
134 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
135 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
136 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
137 CRQB_CMD_ADDR_SHIFT = 8,
138 CRQB_CMD_CS = (0x2 << 11),
139 CRQB_CMD_LAST = (1 << 15),
141 CRPB_FLAG_STATUS_SHIFT = 8,
142 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
143 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
145 EPRD_FLAG_END_OF_TBL = (1 << 31),
147 /* PCI interface registers */
149 PCI_COMMAND_OFS = 0xc00,
150 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
152 PCI_MAIN_CMD_STS_OFS = 0xd30,
153 STOP_PCI_MASTER = (1 << 2),
154 PCI_MASTER_EMPTY = (1 << 3),
155 GLOB_SFT_RST = (1 << 4),
157 MV_PCI_MODE_OFS = 0xd00,
158 MV_PCI_MODE_MASK = 0x30,
160 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
161 MV_PCI_DISC_TIMER = 0xd04,
162 MV_PCI_MSI_TRIGGER = 0xc38,
163 MV_PCI_SERR_MASK = 0xc28,
164 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
165 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
166 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
167 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
168 MV_PCI_ERR_COMMAND = 0x1d50,
170 PCI_IRQ_CAUSE_OFS = 0x1d58,
171 PCI_IRQ_MASK_OFS = 0x1d5c,
172 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
174 PCIE_IRQ_CAUSE_OFS = 0x1900,
175 PCIE_IRQ_MASK_OFS = 0x1910,
176 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
178 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
179 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
180 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
181 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
182 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
183 ERR_IRQ = (1 << 0), /* shift by port # */
184 DONE_IRQ = (1 << 1), /* shift by port # */
185 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
186 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
188 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
189 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
190 PORTS_0_3_COAL_DONE = (1 << 8),
191 PORTS_4_7_COAL_DONE = (1 << 17),
192 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
193 GPIO_INT = (1 << 22),
194 SELF_INT = (1 << 23),
195 TWSI_INT = (1 << 24),
196 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
197 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
198 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
199 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
200 PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
201 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
203 HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
205 HC_MAIN_MASKED_IRQS_SOC = (PORTS_0_3_COAL_DONE | HC_MAIN_RSVD_SOC),
207 /* SATAHC registers */
210 HC_IRQ_CAUSE_OFS = 0x14,
211 DMA_IRQ = (1 << 0), /* shift by port # */
212 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
213 DEV_IRQ = (1 << 8), /* shift by port # */
215 /* Shadow block registers */
217 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
220 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
221 SATA_ACTIVE_OFS = 0x350,
222 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
225 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
230 SATA_IFCTL_OFS = 0x344,
231 SATA_TESTCTL_OFS = 0x348,
232 SATA_IFSTAT_OFS = 0x34c,
233 VENDOR_UNIQUE_FIS_OFS = 0x35c,
236 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
237 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
240 MV5_LTMODE_OFS = 0x30,
241 MV5_PHY_CTL_OFS = 0x0C,
242 SATA_INTERFACE_CFG_OFS = 0x050,
244 MV_M2_PREAMP_MASK = 0x7e0,
248 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
249 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
250 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
251 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
252 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
253 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
254 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
256 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
257 EDMA_ERR_IRQ_MASK_OFS = 0xc,
258 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
259 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
260 EDMA_ERR_DEV = (1 << 2), /* device error */
261 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
262 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
263 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
264 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
265 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
266 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
267 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
268 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
269 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
270 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
271 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
273 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
274 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
275 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
276 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
277 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
279 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
281 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
282 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
283 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
284 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
285 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
286 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
288 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
290 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
291 EDMA_ERR_OVERRUN_5 = (1 << 5),
292 EDMA_ERR_UNDERRUN_5 = (1 << 6),
294 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
295 EDMA_ERR_LNK_CTRL_RX_1 |
296 EDMA_ERR_LNK_CTRL_RX_3 |
297 EDMA_ERR_LNK_CTRL_TX,
299 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
309 EDMA_ERR_LNK_CTRL_RX_2 |
310 EDMA_ERR_LNK_DATA_RX |
311 EDMA_ERR_LNK_DATA_TX |
312 EDMA_ERR_TRANS_PROTO,
314 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
319 EDMA_ERR_UNDERRUN_5 |
320 EDMA_ERR_SELF_DIS_5 |
326 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
327 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
329 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
330 EDMA_REQ_Q_PTR_SHIFT = 5,
332 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
333 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
334 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
335 EDMA_RSP_Q_PTR_SHIFT = 3,
337 EDMA_CMD_OFS = 0x28, /* EDMA command register */
338 EDMA_EN = (1 << 0), /* enable EDMA */
339 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
340 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
342 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
343 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
344 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
346 EDMA_IORDY_TMOUT_OFS = 0x34,
347 EDMA_ARB_CFG_OFS = 0x38,
349 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
351 GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */
353 /* Host private flags (hp_flags) */
354 MV_HP_FLAG_MSI = (1 << 0),
355 MV_HP_ERRATA_50XXB0 = (1 << 1),
356 MV_HP_ERRATA_50XXB2 = (1 << 2),
357 MV_HP_ERRATA_60X1B2 = (1 << 3),
358 MV_HP_ERRATA_60X1C0 = (1 << 4),
359 MV_HP_ERRATA_XX42A0 = (1 << 5),
360 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
361 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
362 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
363 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
364 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
366 /* Port private flags (pp_flags) */
367 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
368 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
369 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
370 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
373 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
374 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
375 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
376 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
377 #define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC))
379 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
380 #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
383 /* DMA boundary 0xffff is required by the s/g splitting
384 * we need on /length/ in mv_fill-sg().
386 MV_DMA_BOUNDARY = 0xffffU,
388 /* mask of register bits containing lower 32 bits
389 * of EDMA request queue DMA address
391 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
393 /* ditto, for response queue */
394 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
408 /* Command ReQuest Block: 32B */
424 /* Command ResPonse Block: 8B */
431 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
439 struct mv_port_priv {
440 struct mv_crqb *crqb;
442 struct mv_crpb *crpb;
444 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
445 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
447 unsigned int req_idx;
448 unsigned int resp_idx;
451 unsigned int delayed_eh_pmp_map;
454 struct mv_port_signal {
459 struct mv_host_priv {
461 struct mv_port_signal signal[8];
462 const struct mv_hw_ops *ops;
465 void __iomem *main_irq_cause_addr;
466 void __iomem *main_irq_mask_addr;
471 * These consistent DMA memory pools give us guaranteed
472 * alignment for hardware-accessed data structures,
473 * and less memory waste in accomplishing the alignment.
475 struct dma_pool *crqb_pool;
476 struct dma_pool *crpb_pool;
477 struct dma_pool *sg_tbl_pool;
481 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
483 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
484 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
486 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
488 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
489 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
492 static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
493 static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
494 static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
495 static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
496 static int mv_port_start(struct ata_port *ap);
497 static void mv_port_stop(struct ata_port *ap);
498 static int mv_qc_defer(struct ata_queued_cmd *qc);
499 static void mv_qc_prep(struct ata_queued_cmd *qc);
500 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
501 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
502 static int mv_hardreset(struct ata_link *link, unsigned int *class,
503 unsigned long deadline);
504 static void mv_eh_freeze(struct ata_port *ap);
505 static void mv_eh_thaw(struct ata_port *ap);
506 static void mv6_dev_config(struct ata_device *dev);
508 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
510 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
511 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
513 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
515 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
516 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
518 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
520 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
521 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
523 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
525 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
526 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
528 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
530 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
531 void __iomem *mmio, unsigned int n_hc);
532 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
534 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
535 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
536 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
537 unsigned int port_no);
538 static int mv_stop_edma(struct ata_port *ap);
539 static int mv_stop_edma_engine(void __iomem *port_mmio);
540 static void mv_edma_cfg(struct ata_port *ap, int want_ncq);
542 static void mv_pmp_select(struct ata_port *ap, int pmp);
543 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
544 unsigned long deadline);
545 static int mv_softreset(struct ata_link *link, unsigned int *class,
546 unsigned long deadline);
547 static void mv_pmp_error_handler(struct ata_port *ap);
548 static void mv_process_crpb_entries(struct ata_port *ap,
549 struct mv_port_priv *pp);
551 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
552 * because we have to allow room for worst case splitting of
553 * PRDs for 64K boundaries in mv_fill_sg().
555 static struct scsi_host_template mv5_sht = {
556 ATA_BASE_SHT(DRV_NAME),
557 .sg_tablesize = MV_MAX_SG_CT / 2,
558 .dma_boundary = MV_DMA_BOUNDARY,
561 static struct scsi_host_template mv6_sht = {
562 ATA_NCQ_SHT(DRV_NAME),
563 .can_queue = MV_MAX_Q_DEPTH - 1,
564 .sg_tablesize = MV_MAX_SG_CT / 2,
565 .dma_boundary = MV_DMA_BOUNDARY,
568 static struct ata_port_operations mv5_ops = {
569 .inherits = &ata_sff_port_ops,
571 .qc_defer = mv_qc_defer,
572 .qc_prep = mv_qc_prep,
573 .qc_issue = mv_qc_issue,
575 .freeze = mv_eh_freeze,
577 .hardreset = mv_hardreset,
578 .error_handler = ata_std_error_handler, /* avoid SFF EH */
579 .post_internal_cmd = ATA_OP_NULL,
581 .scr_read = mv5_scr_read,
582 .scr_write = mv5_scr_write,
584 .port_start = mv_port_start,
585 .port_stop = mv_port_stop,
588 static struct ata_port_operations mv6_ops = {
589 .inherits = &mv5_ops,
590 .dev_config = mv6_dev_config,
591 .scr_read = mv_scr_read,
592 .scr_write = mv_scr_write,
594 .pmp_hardreset = mv_pmp_hardreset,
595 .pmp_softreset = mv_softreset,
596 .softreset = mv_softreset,
597 .error_handler = mv_pmp_error_handler,
600 static struct ata_port_operations mv_iie_ops = {
601 .inherits = &mv6_ops,
602 .dev_config = ATA_OP_NULL,
603 .qc_prep = mv_qc_prep_iie,
606 static const struct ata_port_info mv_port_info[] = {
608 .flags = MV_COMMON_FLAGS,
609 .pio_mask = 0x1f, /* pio0-4 */
610 .udma_mask = ATA_UDMA6,
611 .port_ops = &mv5_ops,
614 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
615 .pio_mask = 0x1f, /* pio0-4 */
616 .udma_mask = ATA_UDMA6,
617 .port_ops = &mv5_ops,
620 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
621 .pio_mask = 0x1f, /* pio0-4 */
622 .udma_mask = ATA_UDMA6,
623 .port_ops = &mv5_ops,
626 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
627 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
629 .pio_mask = 0x1f, /* pio0-4 */
630 .udma_mask = ATA_UDMA6,
631 .port_ops = &mv6_ops,
634 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
635 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
636 ATA_FLAG_NCQ | MV_FLAG_DUAL_HC,
637 .pio_mask = 0x1f, /* pio0-4 */
638 .udma_mask = ATA_UDMA6,
639 .port_ops = &mv6_ops,
642 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
643 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
645 .pio_mask = 0x1f, /* pio0-4 */
646 .udma_mask = ATA_UDMA6,
647 .port_ops = &mv_iie_ops,
650 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
651 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
653 .pio_mask = 0x1f, /* pio0-4 */
654 .udma_mask = ATA_UDMA6,
655 .port_ops = &mv_iie_ops,
658 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
659 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
660 ATA_FLAG_NCQ | MV_FLAG_SOC,
661 .pio_mask = 0x1f, /* pio0-4 */
662 .udma_mask = ATA_UDMA6,
663 .port_ops = &mv_iie_ops,
667 static const struct pci_device_id mv_pci_tbl[] = {
668 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
669 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
670 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
671 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
672 /* RocketRAID 1740/174x have different identifiers */
673 { PCI_VDEVICE(TTI, 0x1740), chip_508x },
674 { PCI_VDEVICE(TTI, 0x1742), chip_508x },
676 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
677 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
678 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
679 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
680 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
682 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
685 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
687 /* Marvell 7042 support */
688 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
690 /* Highpoint RocketRAID PCIe series */
691 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
692 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
694 { } /* terminate list */
697 static const struct mv_hw_ops mv5xxx_ops = {
698 .phy_errata = mv5_phy_errata,
699 .enable_leds = mv5_enable_leds,
700 .read_preamp = mv5_read_preamp,
701 .reset_hc = mv5_reset_hc,
702 .reset_flash = mv5_reset_flash,
703 .reset_bus = mv5_reset_bus,
706 static const struct mv_hw_ops mv6xxx_ops = {
707 .phy_errata = mv6_phy_errata,
708 .enable_leds = mv6_enable_leds,
709 .read_preamp = mv6_read_preamp,
710 .reset_hc = mv6_reset_hc,
711 .reset_flash = mv6_reset_flash,
712 .reset_bus = mv_reset_pci_bus,
715 static const struct mv_hw_ops mv_soc_ops = {
716 .phy_errata = mv6_phy_errata,
717 .enable_leds = mv_soc_enable_leds,
718 .read_preamp = mv_soc_read_preamp,
719 .reset_hc = mv_soc_reset_hc,
720 .reset_flash = mv_soc_reset_flash,
721 .reset_bus = mv_soc_reset_bus,
728 static inline void writelfl(unsigned long data, void __iomem *addr)
731 (void) readl(addr); /* flush to avoid PCI posted write */
734 static inline unsigned int mv_hc_from_port(unsigned int port)
736 return port >> MV_PORT_HC_SHIFT;
739 static inline unsigned int mv_hardport_from_port(unsigned int port)
741 return port & MV_PORT_MASK;
745 * Consolidate some rather tricky bit shift calculations.
746 * This is hot-path stuff, so not a function.
747 * Simple code, with two return values, so macro rather than inline.
749 * port is the sole input, in range 0..7.
750 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
751 * hardport is the other output, in range 0..3.
753 * Note that port and hardport may be the same variable in some cases.
755 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
757 shift = mv_hc_from_port(port) * HC_SHIFT; \
758 hardport = mv_hardport_from_port(port); \
759 shift += hardport * 2; \
762 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
764 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
767 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
770 return mv_hc_base(base, mv_hc_from_port(port));
773 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
775 return mv_hc_base_from_port(base, port) +
776 MV_SATAHC_ARBTR_REG_SZ +
777 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
780 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
782 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
783 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
785 return hc_mmio + ofs;
788 static inline void __iomem *mv_host_base(struct ata_host *host)
790 struct mv_host_priv *hpriv = host->private_data;
794 static inline void __iomem *mv_ap_base(struct ata_port *ap)
796 return mv_port_base(mv_host_base(ap->host), ap->port_no);
799 static inline int mv_get_hc_count(unsigned long port_flags)
801 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
804 static void mv_set_edma_ptrs(void __iomem *port_mmio,
805 struct mv_host_priv *hpriv,
806 struct mv_port_priv *pp)
811 * initialize request queue
813 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
814 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
816 WARN_ON(pp->crqb_dma & 0x3ff);
817 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
818 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
819 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
821 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
822 writelfl((pp->crqb_dma & 0xffffffff) | index,
823 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
825 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
828 * initialize response queue
830 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
831 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
833 WARN_ON(pp->crpb_dma & 0xff);
834 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
836 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
837 writelfl((pp->crpb_dma & 0xffffffff) | index,
838 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
840 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
842 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
843 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
847 * mv_start_dma - Enable eDMA engine
848 * @base: port base address
849 * @pp: port private data
851 * Verify the local cache of the eDMA state is accurate with a
855 * Inherited from caller.
857 static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio,
858 struct mv_port_priv *pp, u8 protocol)
860 int want_ncq = (protocol == ATA_PROT_NCQ);
862 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
863 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
864 if (want_ncq != using_ncq)
867 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
868 struct mv_host_priv *hpriv = ap->host->private_data;
869 int hardport = mv_hardport_from_port(ap->port_no);
870 void __iomem *hc_mmio = mv_hc_base_from_port(
871 mv_host_base(ap->host), hardport);
872 u32 hc_irq_cause, ipending;
874 /* clear EDMA event indicators, if any */
875 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
877 /* clear EDMA interrupt indicator, if any */
878 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
879 ipending = (DEV_IRQ | DMA_IRQ) << hardport;
880 if (hc_irq_cause & ipending) {
881 writelfl(hc_irq_cause & ~ipending,
882 hc_mmio + HC_IRQ_CAUSE_OFS);
885 mv_edma_cfg(ap, want_ncq);
887 /* clear FIS IRQ Cause */
888 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
890 mv_set_edma_ptrs(port_mmio, hpriv, pp);
892 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
893 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
897 static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
899 void __iomem *port_mmio = mv_ap_base(ap);
900 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
901 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
905 * Wait for the EDMA engine to finish transactions in progress.
907 for (i = 0; i < timeout; ++i) {
908 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS);
909 if ((edma_stat & empty_idle) == empty_idle)
913 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
917 * mv_stop_edma_engine - Disable eDMA engine
918 * @port_mmio: io base address
921 * Inherited from caller.
923 static int mv_stop_edma_engine(void __iomem *port_mmio)
927 /* Disable eDMA. The disable bit auto clears. */
928 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
930 /* Wait for the chip to confirm eDMA is off. */
931 for (i = 10000; i > 0; i--) {
932 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
933 if (!(reg & EDMA_EN))
940 static int mv_stop_edma(struct ata_port *ap)
942 void __iomem *port_mmio = mv_ap_base(ap);
943 struct mv_port_priv *pp = ap->private_data;
945 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
947 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
948 mv_wait_for_edma_empty_idle(ap);
949 if (mv_stop_edma_engine(port_mmio)) {
950 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
957 static void mv_dump_mem(void __iomem *start, unsigned bytes)
960 for (b = 0; b < bytes; ) {
961 DPRINTK("%p: ", start + b);
962 for (w = 0; b < bytes && w < 4; w++) {
963 printk("%08x ", readl(start + b));
971 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
976 for (b = 0; b < bytes; ) {
977 DPRINTK("%02x: ", b);
978 for (w = 0; b < bytes && w < 4; w++) {
979 (void) pci_read_config_dword(pdev, b, &dw);
987 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
988 struct pci_dev *pdev)
991 void __iomem *hc_base = mv_hc_base(mmio_base,
992 port >> MV_PORT_HC_SHIFT);
993 void __iomem *port_base;
994 int start_port, num_ports, p, start_hc, num_hcs, hc;
997 start_hc = start_port = 0;
998 num_ports = 8; /* shld be benign for 4 port devs */
1001 start_hc = port >> MV_PORT_HC_SHIFT;
1003 num_ports = num_hcs = 1;
1005 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
1006 num_ports > 1 ? num_ports - 1 : start_port);
1009 DPRINTK("PCI config space regs:\n");
1010 mv_dump_pci_cfg(pdev, 0x68);
1012 DPRINTK("PCI regs:\n");
1013 mv_dump_mem(mmio_base+0xc00, 0x3c);
1014 mv_dump_mem(mmio_base+0xd00, 0x34);
1015 mv_dump_mem(mmio_base+0xf00, 0x4);
1016 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1017 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
1018 hc_base = mv_hc_base(mmio_base, hc);
1019 DPRINTK("HC regs (HC %i):\n", hc);
1020 mv_dump_mem(hc_base, 0x1c);
1022 for (p = start_port; p < start_port + num_ports; p++) {
1023 port_base = mv_port_base(mmio_base, p);
1024 DPRINTK("EDMA regs (port %i):\n", p);
1025 mv_dump_mem(port_base, 0x54);
1026 DPRINTK("SATA regs (port %i):\n", p);
1027 mv_dump_mem(port_base+0x300, 0x60);
1032 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1036 switch (sc_reg_in) {
1040 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1043 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1052 static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
1054 unsigned int ofs = mv_scr_offset(sc_reg_in);
1056 if (ofs != 0xffffffffU) {
1057 *val = readl(mv_ap_base(ap) + ofs);
1063 static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1065 unsigned int ofs = mv_scr_offset(sc_reg_in);
1067 if (ofs != 0xffffffffU) {
1068 writelfl(val, mv_ap_base(ap) + ofs);
1074 static void mv6_dev_config(struct ata_device *adev)
1077 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1079 * Gen-II does not support NCQ over a port multiplier
1080 * (no FIS-based switching).
1082 * We don't have hob_nsect when doing NCQ commands on Gen-II.
1083 * See mv_qc_prep() for more info.
1085 if (adev->flags & ATA_DFLAG_NCQ) {
1086 if (sata_pmp_attached(adev->link->ap)) {
1087 adev->flags &= ~ATA_DFLAG_NCQ;
1088 ata_dev_printk(adev, KERN_INFO,
1089 "NCQ disabled for command-based switching\n");
1090 } else if (adev->max_sectors > GEN_II_NCQ_MAX_SECTORS) {
1091 adev->max_sectors = GEN_II_NCQ_MAX_SECTORS;
1092 ata_dev_printk(adev, KERN_INFO,
1093 "max_sectors limited to %u for NCQ\n",
1099 static int mv_qc_defer(struct ata_queued_cmd *qc)
1101 struct ata_link *link = qc->dev->link;
1102 struct ata_port *ap = link->ap;
1103 struct mv_port_priv *pp = ap->private_data;
1106 * Don't allow new commands if we're in a delayed EH state
1107 * for NCQ and/or FIS-based switching.
1109 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1110 return ATA_DEFER_PORT;
1112 * If the port is completely idle, then allow the new qc.
1114 if (ap->nr_active_links == 0)
1117 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1119 * The port is operating in host queuing mode (EDMA).
1120 * It can accomodate a new qc if the qc protocol
1121 * is compatible with the current host queue mode.
1123 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1125 * The host queue (EDMA) is in NCQ mode.
1126 * If the new qc is also an NCQ command,
1127 * then allow the new qc.
1129 if (qc->tf.protocol == ATA_PROT_NCQ)
1133 * The host queue (EDMA) is in non-NCQ, DMA mode.
1134 * If the new qc is also a non-NCQ, DMA command,
1135 * then allow the new qc.
1137 if (qc->tf.protocol == ATA_PROT_DMA)
1141 return ATA_DEFER_PORT;
1144 static void mv_config_fbs(void __iomem *port_mmio, int want_ncq, int want_fbs)
1146 u32 new_fiscfg, old_fiscfg;
1147 u32 new_ltmode, old_ltmode;
1148 u32 new_haltcond, old_haltcond;
1150 old_fiscfg = readl(port_mmio + FISCFG_OFS);
1151 old_ltmode = readl(port_mmio + LTMODE_OFS);
1152 old_haltcond = readl(port_mmio + EDMA_HALTCOND_OFS);
1154 new_fiscfg = old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1155 new_ltmode = old_ltmode & ~LTMODE_BIT8;
1156 new_haltcond = old_haltcond | EDMA_ERR_DEV;
1159 new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC;
1160 new_ltmode = old_ltmode | LTMODE_BIT8;
1162 new_haltcond &= ~EDMA_ERR_DEV;
1164 new_fiscfg |= FISCFG_WAIT_DEV_ERR;
1167 if (new_fiscfg != old_fiscfg)
1168 writelfl(new_fiscfg, port_mmio + FISCFG_OFS);
1169 if (new_ltmode != old_ltmode)
1170 writelfl(new_ltmode, port_mmio + LTMODE_OFS);
1171 if (new_haltcond != old_haltcond)
1172 writelfl(new_haltcond, port_mmio + EDMA_HALTCOND_OFS);
1175 static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1177 struct mv_host_priv *hpriv = ap->host->private_data;
1180 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1181 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS);
1183 new = old | (1 << 22);
1185 new = old & ~(1 << 22);
1187 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS);
1190 static void mv_edma_cfg(struct ata_port *ap, int want_ncq)
1193 struct mv_port_priv *pp = ap->private_data;
1194 struct mv_host_priv *hpriv = ap->host->private_data;
1195 void __iomem *port_mmio = mv_ap_base(ap);
1197 /* set up non-NCQ EDMA configuration */
1198 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
1199 pp->pp_flags &= ~MV_PP_FLAG_FBS_EN;
1201 if (IS_GEN_I(hpriv))
1202 cfg |= (1 << 8); /* enab config burst size mask */
1204 else if (IS_GEN_II(hpriv)) {
1205 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
1206 mv_60x1_errata_sata25(ap, want_ncq);
1208 } else if (IS_GEN_IIE(hpriv)) {
1209 int want_fbs = sata_pmp_attached(ap);
1211 * Possible future enhancement:
1213 * The chip can use FBS with non-NCQ, if we allow it,
1214 * But first we need to have the error handling in place
1215 * for this mode (datasheet section 7.3.15.4.2.3).
1216 * So disallow non-NCQ FBS for now.
1218 want_fbs &= want_ncq;
1220 mv_config_fbs(port_mmio, want_ncq, want_fbs);
1223 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1224 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1227 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1228 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1229 if (HAS_PCI(ap->host))
1230 cfg |= (1 << 18); /* enab early completion */
1231 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1232 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
1236 cfg |= EDMA_CFG_NCQ;
1237 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1239 pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN;
1241 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1244 static void mv_port_free_dma_mem(struct ata_port *ap)
1246 struct mv_host_priv *hpriv = ap->host->private_data;
1247 struct mv_port_priv *pp = ap->private_data;
1251 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1255 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1259 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1260 * For later hardware, we have one unique sg_tbl per NCQ tag.
1262 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1263 if (pp->sg_tbl[tag]) {
1264 if (tag == 0 || !IS_GEN_I(hpriv))
1265 dma_pool_free(hpriv->sg_tbl_pool,
1267 pp->sg_tbl_dma[tag]);
1268 pp->sg_tbl[tag] = NULL;
1274 * mv_port_start - Port specific init/start routine.
1275 * @ap: ATA channel to manipulate
1277 * Allocate and point to DMA memory, init port private memory,
1281 * Inherited from caller.
1283 static int mv_port_start(struct ata_port *ap)
1285 struct device *dev = ap->host->dev;
1286 struct mv_host_priv *hpriv = ap->host->private_data;
1287 struct mv_port_priv *pp;
1290 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1293 ap->private_data = pp;
1295 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1298 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
1300 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1302 goto out_port_free_dma_mem;
1303 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
1306 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1307 * For later hardware, we need one unique sg_tbl per NCQ tag.
1309 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1310 if (tag == 0 || !IS_GEN_I(hpriv)) {
1311 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1312 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1313 if (!pp->sg_tbl[tag])
1314 goto out_port_free_dma_mem;
1316 pp->sg_tbl[tag] = pp->sg_tbl[0];
1317 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1322 out_port_free_dma_mem:
1323 mv_port_free_dma_mem(ap);
1328 * mv_port_stop - Port specific cleanup/stop routine.
1329 * @ap: ATA channel to manipulate
1331 * Stop DMA, cleanup port memory.
1334 * This routine uses the host lock to protect the DMA stop.
1336 static void mv_port_stop(struct ata_port *ap)
1339 mv_port_free_dma_mem(ap);
1343 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1344 * @qc: queued command whose SG list to source from
1346 * Populate the SG list and mark the last entry.
1349 * Inherited from caller.
1351 static void mv_fill_sg(struct ata_queued_cmd *qc)
1353 struct mv_port_priv *pp = qc->ap->private_data;
1354 struct scatterlist *sg;
1355 struct mv_sg *mv_sg, *last_sg = NULL;
1358 mv_sg = pp->sg_tbl[qc->tag];
1359 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1360 dma_addr_t addr = sg_dma_address(sg);
1361 u32 sg_len = sg_dma_len(sg);
1364 u32 offset = addr & 0xffff;
1367 if ((offset + sg_len > 0x10000))
1368 len = 0x10000 - offset;
1370 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1371 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1372 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
1382 if (likely(last_sg))
1383 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1386 static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
1388 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1389 (last ? CRQB_CMD_LAST : 0);
1390 *cmdw = cpu_to_le16(tmp);
1394 * mv_qc_prep - Host specific command preparation.
1395 * @qc: queued command to prepare
1397 * This routine simply redirects to the general purpose routine
1398 * if command is not DMA. Else, it handles prep of the CRQB
1399 * (command request block), does some sanity checking, and calls
1400 * the SG load routine.
1403 * Inherited from caller.
1405 static void mv_qc_prep(struct ata_queued_cmd *qc)
1407 struct ata_port *ap = qc->ap;
1408 struct mv_port_priv *pp = ap->private_data;
1410 struct ata_taskfile *tf;
1414 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1415 (qc->tf.protocol != ATA_PROT_NCQ))
1418 /* Fill in command request block
1420 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1421 flags |= CRQB_FLAG_READ;
1422 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1423 flags |= qc->tag << CRQB_TAG_SHIFT;
1424 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
1426 /* get current queue index from software */
1427 in_index = pp->req_idx;
1429 pp->crqb[in_index].sg_addr =
1430 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1431 pp->crqb[in_index].sg_addr_hi =
1432 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
1433 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
1435 cw = &pp->crqb[in_index].ata_cmd[0];
1438 /* Sadly, the CRQB cannot accomodate all registers--there are
1439 * only 11 bytes...so we must pick and choose required
1440 * registers based on the command. So, we drop feature and
1441 * hob_feature for [RW] DMA commands, but they are needed for
1442 * NCQ. NCQ will drop hob_nsect.
1444 switch (tf->command) {
1446 case ATA_CMD_READ_EXT:
1448 case ATA_CMD_WRITE_EXT:
1449 case ATA_CMD_WRITE_FUA_EXT:
1450 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1452 case ATA_CMD_FPDMA_READ:
1453 case ATA_CMD_FPDMA_WRITE:
1454 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1455 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1458 /* The only other commands EDMA supports in non-queued and
1459 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1460 * of which are defined/used by Linux. If we get here, this
1461 * driver needs work.
1463 * FIXME: modify libata to give qc_prep a return value and
1464 * return error here.
1466 BUG_ON(tf->command);
1469 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1470 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1471 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1472 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1473 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1474 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1475 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1476 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1477 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1479 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1485 * mv_qc_prep_iie - Host specific command preparation.
1486 * @qc: queued command to prepare
1488 * This routine simply redirects to the general purpose routine
1489 * if command is not DMA. Else, it handles prep of the CRQB
1490 * (command request block), does some sanity checking, and calls
1491 * the SG load routine.
1494 * Inherited from caller.
1496 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1498 struct ata_port *ap = qc->ap;
1499 struct mv_port_priv *pp = ap->private_data;
1500 struct mv_crqb_iie *crqb;
1501 struct ata_taskfile *tf;
1505 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1506 (qc->tf.protocol != ATA_PROT_NCQ))
1509 /* Fill in Gen IIE command request block */
1510 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1511 flags |= CRQB_FLAG_READ;
1513 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1514 flags |= qc->tag << CRQB_TAG_SHIFT;
1515 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
1516 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
1518 /* get current queue index from software */
1519 in_index = pp->req_idx;
1521 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
1522 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1523 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
1524 crqb->flags = cpu_to_le32(flags);
1527 crqb->ata_cmd[0] = cpu_to_le32(
1528 (tf->command << 16) |
1531 crqb->ata_cmd[1] = cpu_to_le32(
1537 crqb->ata_cmd[2] = cpu_to_le32(
1538 (tf->hob_lbal << 0) |
1539 (tf->hob_lbam << 8) |
1540 (tf->hob_lbah << 16) |
1541 (tf->hob_feature << 24)
1543 crqb->ata_cmd[3] = cpu_to_le32(
1545 (tf->hob_nsect << 8)
1548 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1554 * mv_qc_issue - Initiate a command to the host
1555 * @qc: queued command to start
1557 * This routine simply redirects to the general purpose routine
1558 * if command is not DMA. Else, it sanity checks our local
1559 * caches of the request producer/consumer indices then enables
1560 * DMA and bumps the request producer index.
1563 * Inherited from caller.
1565 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
1567 struct ata_port *ap = qc->ap;
1568 void __iomem *port_mmio = mv_ap_base(ap);
1569 struct mv_port_priv *pp = ap->private_data;
1572 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1573 (qc->tf.protocol != ATA_PROT_NCQ)) {
1575 * We're about to send a non-EDMA capable command to the
1576 * port. Turn off EDMA so there won't be problems accessing
1577 * shadow block, etc registers.
1580 mv_pmp_select(ap, qc->dev->link->pmp);
1581 return ata_sff_qc_issue(qc);
1584 mv_start_dma(ap, port_mmio, pp, qc->tf.protocol);
1586 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1587 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
1589 /* and write the request in pointer to kick the EDMA to life */
1590 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
1591 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1596 static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
1598 struct mv_port_priv *pp = ap->private_data;
1599 struct ata_queued_cmd *qc;
1601 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1603 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1604 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1609 static void mv_pmp_error_handler(struct ata_port *ap)
1611 unsigned int pmp, pmp_map;
1612 struct mv_port_priv *pp = ap->private_data;
1614 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
1616 * Perform NCQ error analysis on failed PMPs
1617 * before we freeze the port entirely.
1619 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
1621 pmp_map = pp->delayed_eh_pmp_map;
1622 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
1623 for (pmp = 0; pmp_map != 0; pmp++) {
1624 unsigned int this_pmp = (1 << pmp);
1625 if (pmp_map & this_pmp) {
1626 struct ata_link *link = &ap->pmp_link[pmp];
1627 pmp_map &= ~this_pmp;
1628 ata_eh_analyze_ncq_error(link);
1631 ata_port_freeze(ap);
1633 sata_pmp_error_handler(ap);
1636 static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
1638 void __iomem *port_mmio = mv_ap_base(ap);
1640 return readl(port_mmio + SATA_TESTCTL_OFS) >> 16;
1643 static int mv_count_pmp_links(unsigned int pmp_map)
1645 unsigned int link_count = 0;
1648 link_count += (pmp_map & 1);
1654 static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
1656 struct ata_eh_info *ehi;
1660 * Initialize EH info for PMPs which saw device errors
1662 ehi = &ap->link.eh_info;
1663 for (pmp = 0; pmp_map != 0; pmp++) {
1664 unsigned int this_pmp = (1 << pmp);
1665 if (pmp_map & this_pmp) {
1666 struct ata_link *link = &ap->pmp_link[pmp];
1668 pmp_map &= ~this_pmp;
1669 ehi = &link->eh_info;
1670 ata_ehi_clear_desc(ehi);
1671 ata_ehi_push_desc(ehi, "dev err");
1672 ehi->err_mask |= AC_ERR_DEV;
1673 ehi->action |= ATA_EH_RESET;
1674 ata_link_abort(link);
1679 static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
1681 struct mv_port_priv *pp = ap->private_data;
1683 unsigned int old_map, new_map;
1686 * Device error during FBS+NCQ operation:
1688 * Set a port flag to prevent further I/O being enqueued.
1689 * Leave the EDMA running to drain outstanding commands from this port.
1690 * Perform the post-mortem/EH only when all responses are complete.
1691 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
1693 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
1694 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
1695 pp->delayed_eh_pmp_map = 0;
1697 old_map = pp->delayed_eh_pmp_map;
1698 new_map = old_map | mv_get_err_pmp_map(ap);
1700 if (old_map != new_map) {
1701 pp->delayed_eh_pmp_map = new_map;
1702 mv_pmp_eh_prep(ap, new_map & ~old_map);
1704 failed_links = mv_count_pmp_links(new_map);
1706 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
1707 "failed_links=%d nr_active_links=%d\n",
1708 __func__, pp->delayed_eh_pmp_map,
1709 ap->qc_active, failed_links,
1710 ap->nr_active_links);
1712 if (ap->nr_active_links <= failed_links) {
1713 mv_process_crpb_entries(ap, pp);
1716 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
1717 return 1; /* handled */
1719 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
1720 return 1; /* handled */
1723 static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
1726 * Possible future enhancement:
1728 * FBS+non-NCQ operation is not yet implemented.
1729 * See related notes in mv_edma_cfg().
1731 * Device error during FBS+non-NCQ operation:
1733 * We need to snapshot the shadow registers for each failed command.
1734 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
1736 return 0; /* not handled */
1739 static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
1741 struct mv_port_priv *pp = ap->private_data;
1743 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1744 return 0; /* EDMA was not active: not handled */
1745 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
1746 return 0; /* FBS was not active: not handled */
1748 if (!(edma_err_cause & EDMA_ERR_DEV))
1749 return 0; /* non DEV error: not handled */
1750 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
1751 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
1752 return 0; /* other problems: not handled */
1754 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1756 * EDMA should NOT have self-disabled for this case.
1757 * If it did, then something is wrong elsewhere,
1758 * and we cannot handle it here.
1760 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
1761 ata_port_printk(ap, KERN_WARNING,
1762 "%s: err_cause=0x%x pp_flags=0x%x\n",
1763 __func__, edma_err_cause, pp->pp_flags);
1764 return 0; /* not handled */
1766 return mv_handle_fbs_ncq_dev_err(ap);
1769 * EDMA should have self-disabled for this case.
1770 * If it did not, then something is wrong elsewhere,
1771 * and we cannot handle it here.
1773 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
1774 ata_port_printk(ap, KERN_WARNING,
1775 "%s: err_cause=0x%x pp_flags=0x%x\n",
1776 __func__, edma_err_cause, pp->pp_flags);
1777 return 0; /* not handled */
1779 return mv_handle_fbs_non_ncq_dev_err(ap);
1781 return 0; /* not handled */
1784 static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
1786 struct ata_eh_info *ehi = &ap->link.eh_info;
1787 char *when = "idle";
1789 ata_ehi_clear_desc(ehi);
1790 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
1792 } else if (edma_was_enabled) {
1793 when = "EDMA enabled";
1795 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
1796 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1799 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
1800 ehi->err_mask |= AC_ERR_OTHER;
1801 ehi->action |= ATA_EH_RESET;
1802 ata_port_freeze(ap);
1806 * mv_err_intr - Handle error interrupts on the port
1807 * @ap: ATA channel to manipulate
1808 * @qc: affected command (non-NCQ), or NULL
1810 * Most cases require a full reset of the chip's state machine,
1811 * which also performs a COMRESET.
1812 * Also, if the port disabled DMA, update our cached copy to match.
1815 * Inherited from caller.
1817 static void mv_err_intr(struct ata_port *ap)
1819 void __iomem *port_mmio = mv_ap_base(ap);
1820 u32 edma_err_cause, eh_freeze_mask, serr = 0;
1821 struct mv_port_priv *pp = ap->private_data;
1822 struct mv_host_priv *hpriv = ap->host->private_data;
1823 unsigned int action = 0, err_mask = 0;
1824 struct ata_eh_info *ehi = &ap->link.eh_info;
1825 struct ata_queued_cmd *qc;
1829 * Read and clear the SError and err_cause bits.
1831 sata_scr_read(&ap->link, SCR_ERROR, &serr);
1832 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
1834 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1835 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1837 ata_port_printk(ap, KERN_INFO, "%s: err_cause=%08x pp_flags=0x%x\n",
1838 __func__, edma_err_cause, pp->pp_flags);
1840 if (edma_err_cause & EDMA_ERR_DEV) {
1842 * Device errors during FIS-based switching operation
1843 * require special handling.
1845 if (mv_handle_dev_err(ap, edma_err_cause))
1849 qc = mv_get_active_qc(ap);
1850 ata_ehi_clear_desc(ehi);
1851 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
1852 edma_err_cause, pp->pp_flags);
1854 * All generations share these EDMA error cause bits:
1856 if (edma_err_cause & EDMA_ERR_DEV) {
1857 err_mask |= AC_ERR_DEV;
1858 action |= ATA_EH_RESET;
1859 ata_ehi_push_desc(ehi, "dev error");
1861 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
1862 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
1863 EDMA_ERR_INTRL_PAR)) {
1864 err_mask |= AC_ERR_ATA_BUS;
1865 action |= ATA_EH_RESET;
1866 ata_ehi_push_desc(ehi, "parity error");
1868 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
1869 ata_ehi_hotplugged(ehi);
1870 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
1871 "dev disconnect" : "dev connect");
1872 action |= ATA_EH_RESET;
1876 * Gen-I has a different SELF_DIS bit,
1877 * different FREEZE bits, and no SERR bit:
1879 if (IS_GEN_I(hpriv)) {
1880 eh_freeze_mask = EDMA_EH_FREEZE_5;
1881 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
1882 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1883 ata_ehi_push_desc(ehi, "EDMA self-disable");
1886 eh_freeze_mask = EDMA_EH_FREEZE;
1887 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
1888 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1889 ata_ehi_push_desc(ehi, "EDMA self-disable");
1891 if (edma_err_cause & EDMA_ERR_SERR) {
1892 ata_ehi_push_desc(ehi, "SError=%08x", serr);
1893 err_mask |= AC_ERR_ATA_BUS;
1894 action |= ATA_EH_RESET;
1899 err_mask = AC_ERR_OTHER;
1900 action |= ATA_EH_RESET;
1903 ehi->serror |= serr;
1904 ehi->action |= action;
1907 qc->err_mask |= err_mask;
1909 ehi->err_mask |= err_mask;
1911 if (err_mask == AC_ERR_DEV) {
1913 * Cannot do ata_port_freeze() here,
1914 * because it would kill PIO access,
1915 * which is needed for further diagnosis.
1919 } else if (edma_err_cause & eh_freeze_mask) {
1921 * Note to self: ata_port_freeze() calls ata_port_abort()
1923 ata_port_freeze(ap);
1930 ata_link_abort(qc->dev->link);
1936 static void mv_process_crpb_response(struct ata_port *ap,
1937 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
1939 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
1943 u16 edma_status = le16_to_cpu(response->flags);
1945 * edma_status from a response queue entry:
1946 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
1947 * MSB is saved ATA status from command completion.
1950 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
1953 * Error will be seen/handled by mv_err_intr().
1954 * So do nothing at all here.
1959 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
1960 if (!ac_err_mask(ata_status))
1961 ata_qc_complete(qc);
1962 /* else: leave it for mv_err_intr() */
1964 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
1969 static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
1971 void __iomem *port_mmio = mv_ap_base(ap);
1972 struct mv_host_priv *hpriv = ap->host->private_data;
1974 bool work_done = false;
1975 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
1977 /* Get the hardware queue position index */
1978 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
1979 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1981 /* Process new responses from since the last time we looked */
1982 while (in_index != pp->resp_idx) {
1984 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
1986 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1988 if (IS_GEN_I(hpriv)) {
1989 /* 50xx: no NCQ, only one command active at a time */
1990 tag = ap->link.active_tag;
1992 /* Gen II/IIE: get command tag from CRPB entry */
1993 tag = le16_to_cpu(response->id) & 0x1f;
1995 mv_process_crpb_response(ap, response, tag, ncq_enabled);
1999 /* Update the software queue position index in hardware */
2001 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
2002 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
2003 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
2006 static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2008 struct mv_port_priv *pp;
2009 int edma_was_enabled;
2011 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2012 mv_unexpected_intr(ap, 0);
2016 * Grab a snapshot of the EDMA_EN flag setting,
2017 * so that we have a consistent view for this port,
2018 * even if something we call of our routines changes it.
2020 pp = ap->private_data;
2021 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2023 * Process completed CRPB response(s) before other events.
2025 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2026 mv_process_crpb_entries(ap, pp);
2027 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2028 mv_handle_fbs_ncq_dev_err(ap);
2031 * Handle chip-reported errors, or continue on to handle PIO.
2033 if (unlikely(port_cause & ERR_IRQ)) {
2035 } else if (!edma_was_enabled) {
2036 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2038 ata_sff_host_intr(ap, qc);
2040 mv_unexpected_intr(ap, edma_was_enabled);
2045 * mv_host_intr - Handle all interrupts on the given host controller
2046 * @host: host specific structure
2047 * @main_irq_cause: Main interrupt cause register for the chip.
2050 * Inherited from caller.
2052 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
2054 struct mv_host_priv *hpriv = host->private_data;
2055 void __iomem *mmio = hpriv->base, *hc_mmio;
2056 unsigned int handled = 0, port;
2058 for (port = 0; port < hpriv->n_ports; port++) {
2059 struct ata_port *ap = host->ports[port];
2060 unsigned int p, shift, hardport, port_cause;
2062 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2064 * Each hc within the host has its own hc_irq_cause register,
2065 * where the interrupting ports bits get ack'd.
2067 if (hardport == 0) { /* first port on this hc ? */
2068 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2069 u32 port_mask, ack_irqs;
2071 * Skip this entire hc if nothing pending for any ports
2074 port += MV_PORTS_PER_HC - 1;
2078 * We don't need/want to read the hc_irq_cause register,
2079 * because doing so hurts performance, and
2080 * main_irq_cause already gives us everything we need.
2082 * But we do have to *write* to the hc_irq_cause to ack
2083 * the ports that we are handling this time through.
2085 * This requires that we create a bitmap for those
2086 * ports which interrupted us, and use that bitmap
2087 * to ack (only) those ports via hc_irq_cause.
2090 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2091 if ((port + p) >= hpriv->n_ports)
2093 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2094 if (hc_cause & port_mask)
2095 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2097 hc_mmio = mv_hc_base_from_port(mmio, port);
2098 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS);
2102 * Handle interrupts signalled for this port:
2104 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2106 mv_port_intr(ap, port_cause);
2111 static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
2113 struct mv_host_priv *hpriv = host->private_data;
2114 struct ata_port *ap;
2115 struct ata_queued_cmd *qc;
2116 struct ata_eh_info *ehi;
2117 unsigned int i, err_mask, printed = 0;
2120 err_cause = readl(mmio + hpriv->irq_cause_ofs);
2122 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2125 DPRINTK("All regs @ PCI error\n");
2126 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2128 writelfl(0, mmio + hpriv->irq_cause_ofs);
2130 for (i = 0; i < host->n_ports; i++) {
2131 ap = host->ports[i];
2132 if (!ata_link_offline(&ap->link)) {
2133 ehi = &ap->link.eh_info;
2134 ata_ehi_clear_desc(ehi);
2136 ata_ehi_push_desc(ehi,
2137 "PCI err cause 0x%08x", err_cause);
2138 err_mask = AC_ERR_HOST_BUS;
2139 ehi->action = ATA_EH_RESET;
2140 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2142 qc->err_mask |= err_mask;
2144 ehi->err_mask |= err_mask;
2146 ata_port_freeze(ap);
2149 return 1; /* handled */
2153 * mv_interrupt - Main interrupt event handler
2155 * @dev_instance: private data; in this case the host structure
2157 * Read the read only register to determine if any host
2158 * controllers have pending interrupts. If so, call lower level
2159 * routine to handle. Also check for PCI errors which are only
2163 * This routine holds the host lock while processing pending
2166 static irqreturn_t mv_interrupt(int irq, void *dev_instance)
2168 struct ata_host *host = dev_instance;
2169 struct mv_host_priv *hpriv = host->private_data;
2170 unsigned int handled = 0;
2171 u32 main_irq_cause, main_irq_mask;
2173 spin_lock(&host->lock);
2174 main_irq_cause = readl(hpriv->main_irq_cause_addr);
2175 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2177 * Deal with cases where we either have nothing pending, or have read
2178 * a bogus register value which can indicate HW removal or PCI fault.
2180 if ((main_irq_cause & main_irq_mask) && (main_irq_cause != 0xffffffffU)) {
2181 if (unlikely((main_irq_cause & PCI_ERR) && HAS_PCI(host)))
2182 handled = mv_pci_error(host, hpriv->base);
2184 handled = mv_host_intr(host, main_irq_cause);
2186 spin_unlock(&host->lock);
2187 return IRQ_RETVAL(handled);
2190 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2194 switch (sc_reg_in) {
2198 ofs = sc_reg_in * sizeof(u32);
2207 static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
2209 struct mv_host_priv *hpriv = ap->host->private_data;
2210 void __iomem *mmio = hpriv->base;
2211 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
2212 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2214 if (ofs != 0xffffffffU) {
2215 *val = readl(addr + ofs);
2221 static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
2223 struct mv_host_priv *hpriv = ap->host->private_data;
2224 void __iomem *mmio = hpriv->base;
2225 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
2226 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2228 if (ofs != 0xffffffffU) {
2229 writelfl(val, addr + ofs);
2235 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
2237 struct pci_dev *pdev = to_pci_dev(host->dev);
2240 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
2243 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2245 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2248 mv_reset_pci_bus(host, mmio);
2251 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2253 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
2256 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
2259 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
2262 tmp = readl(phy_mmio + MV5_PHY_MODE);
2264 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
2265 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
2268 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
2272 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
2274 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
2276 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2278 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2281 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2284 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
2285 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
2287 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
2290 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
2292 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
2294 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
2297 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
2300 tmp = readl(phy_mmio + MV5_PHY_MODE);
2302 tmp |= hpriv->signal[port].pre;
2303 tmp |= hpriv->signal[port].amps;
2304 writel(tmp, phy_mmio + MV5_PHY_MODE);
2309 #define ZERO(reg) writel(0, port_mmio + (reg))
2310 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
2313 void __iomem *port_mmio = mv_port_base(mmio, port);
2315 mv_reset_channel(hpriv, mmio, port);
2317 ZERO(0x028); /* command */
2318 writel(0x11f, port_mmio + EDMA_CFG_OFS);
2319 ZERO(0x004); /* timer */
2320 ZERO(0x008); /* irq err cause */
2321 ZERO(0x00c); /* irq err mask */
2322 ZERO(0x010); /* rq bah */
2323 ZERO(0x014); /* rq inp */
2324 ZERO(0x018); /* rq outp */
2325 ZERO(0x01c); /* respq bah */
2326 ZERO(0x024); /* respq outp */
2327 ZERO(0x020); /* respq inp */
2328 ZERO(0x02c); /* test control */
2329 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
2333 #define ZERO(reg) writel(0, hc_mmio + (reg))
2334 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2337 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2345 tmp = readl(hc_mmio + 0x20);
2348 writel(tmp, hc_mmio + 0x20);
2352 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2355 unsigned int hc, port;
2357 for (hc = 0; hc < n_hc; hc++) {
2358 for (port = 0; port < MV_PORTS_PER_HC; port++)
2359 mv5_reset_hc_port(hpriv, mmio,
2360 (hc * MV_PORTS_PER_HC) + port);
2362 mv5_reset_one_hc(hpriv, mmio, hc);
2369 #define ZERO(reg) writel(0, mmio + (reg))
2370 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
2372 struct mv_host_priv *hpriv = host->private_data;
2375 tmp = readl(mmio + MV_PCI_MODE_OFS);
2377 writel(tmp, mmio + MV_PCI_MODE_OFS);
2379 ZERO(MV_PCI_DISC_TIMER);
2380 ZERO(MV_PCI_MSI_TRIGGER);
2381 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
2382 ZERO(PCI_HC_MAIN_IRQ_MASK_OFS);
2383 ZERO(MV_PCI_SERR_MASK);
2384 ZERO(hpriv->irq_cause_ofs);
2385 ZERO(hpriv->irq_mask_ofs);
2386 ZERO(MV_PCI_ERR_LOW_ADDRESS);
2387 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
2388 ZERO(MV_PCI_ERR_ATTRIBUTE);
2389 ZERO(MV_PCI_ERR_COMMAND);
2393 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2397 mv5_reset_flash(hpriv, mmio);
2399 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
2401 tmp |= (1 << 5) | (1 << 6);
2402 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
2406 * mv6_reset_hc - Perform the 6xxx global soft reset
2407 * @mmio: base address of the HBA
2409 * This routine only applies to 6xxx parts.
2412 * Inherited from caller.
2414 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2417 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
2421 /* Following procedure defined in PCI "main command and status
2425 writel(t | STOP_PCI_MASTER, reg);
2427 for (i = 0; i < 1000; i++) {
2430 if (PCI_MASTER_EMPTY & t)
2433 if (!(PCI_MASTER_EMPTY & t)) {
2434 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
2442 writel(t | GLOB_SFT_RST, reg);
2445 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
2447 if (!(GLOB_SFT_RST & t)) {
2448 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
2453 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
2456 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
2459 } while ((GLOB_SFT_RST & t) && (i-- > 0));
2461 if (GLOB_SFT_RST & t) {
2462 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
2469 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
2472 void __iomem *port_mmio;
2475 tmp = readl(mmio + MV_RESET_CFG_OFS);
2476 if ((tmp & (1 << 0)) == 0) {
2477 hpriv->signal[idx].amps = 0x7 << 8;
2478 hpriv->signal[idx].pre = 0x1 << 5;
2482 port_mmio = mv_port_base(mmio, idx);
2483 tmp = readl(port_mmio + PHY_MODE2);
2485 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2486 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2489 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
2491 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
2494 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2497 void __iomem *port_mmio = mv_port_base(mmio, port);
2499 u32 hp_flags = hpriv->hp_flags;
2501 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2503 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2506 if (fix_phy_mode2) {
2507 m2 = readl(port_mmio + PHY_MODE2);
2510 writel(m2, port_mmio + PHY_MODE2);
2514 m2 = readl(port_mmio + PHY_MODE2);
2515 m2 &= ~((1 << 16) | (1 << 31));
2516 writel(m2, port_mmio + PHY_MODE2);
2521 /* who knows what this magic does */
2522 tmp = readl(port_mmio + PHY_MODE3);
2525 writel(tmp, port_mmio + PHY_MODE3);
2527 if (fix_phy_mode4) {
2530 m4 = readl(port_mmio + PHY_MODE4);
2532 if (hp_flags & MV_HP_ERRATA_60X1B2)
2533 tmp = readl(port_mmio + PHY_MODE3);
2535 /* workaround for errata FEr SATA#10 (part 1) */
2536 m4 = (m4 & ~(1 << 1)) | (1 << 0);
2538 writel(m4, port_mmio + PHY_MODE4);
2540 if (hp_flags & MV_HP_ERRATA_60X1B2)
2541 writel(tmp, port_mmio + PHY_MODE3);
2544 /* Revert values of pre-emphasis and signal amps to the saved ones */
2545 m2 = readl(port_mmio + PHY_MODE2);
2547 m2 &= ~MV_M2_PREAMP_MASK;
2548 m2 |= hpriv->signal[port].amps;
2549 m2 |= hpriv->signal[port].pre;
2552 /* according to mvSata 3.6.1, some IIE values are fixed */
2553 if (IS_GEN_IIE(hpriv)) {
2558 writel(m2, port_mmio + PHY_MODE2);
2561 /* TODO: use the generic LED interface to configure the SATA Presence */
2562 /* & Acitivy LEDs on the board */
2563 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
2569 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
2572 void __iomem *port_mmio;
2575 port_mmio = mv_port_base(mmio, idx);
2576 tmp = readl(port_mmio + PHY_MODE2);
2578 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2579 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2583 #define ZERO(reg) writel(0, port_mmio + (reg))
2584 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
2585 void __iomem *mmio, unsigned int port)
2587 void __iomem *port_mmio = mv_port_base(mmio, port);
2589 mv_reset_channel(hpriv, mmio, port);
2591 ZERO(0x028); /* command */
2592 writel(0x101f, port_mmio + EDMA_CFG_OFS);
2593 ZERO(0x004); /* timer */
2594 ZERO(0x008); /* irq err cause */
2595 ZERO(0x00c); /* irq err mask */
2596 ZERO(0x010); /* rq bah */
2597 ZERO(0x014); /* rq inp */
2598 ZERO(0x018); /* rq outp */
2599 ZERO(0x01c); /* respq bah */
2600 ZERO(0x024); /* respq outp */
2601 ZERO(0x020); /* respq inp */
2602 ZERO(0x02c); /* test control */
2603 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
2608 #define ZERO(reg) writel(0, hc_mmio + (reg))
2609 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
2612 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
2622 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
2623 void __iomem *mmio, unsigned int n_hc)
2627 for (port = 0; port < hpriv->n_ports; port++)
2628 mv_soc_reset_hc_port(hpriv, mmio, port);
2630 mv_soc_reset_one_hc(hpriv, mmio);
2635 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
2641 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
2646 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
2648 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
2650 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
2652 ifcfg |= (1 << 7); /* enable gen2i speed */
2653 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
2656 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
2657 unsigned int port_no)
2659 void __iomem *port_mmio = mv_port_base(mmio, port_no);
2662 * The datasheet warns against setting EDMA_RESET when EDMA is active
2663 * (but doesn't say what the problem might be). So we first try
2664 * to disable the EDMA engine before doing the EDMA_RESET operation.
2666 mv_stop_edma_engine(port_mmio);
2667 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
2669 if (!IS_GEN_I(hpriv)) {
2670 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
2671 mv_setup_ifcfg(port_mmio, 1);
2674 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
2675 * link, and physical layers. It resets all SATA interface registers
2676 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
2678 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
2679 udelay(25); /* allow reset propagation */
2680 writelfl(0, port_mmio + EDMA_CMD_OFS);
2682 hpriv->ops->phy_errata(hpriv, mmio, port_no);
2684 if (IS_GEN_I(hpriv))
2688 static void mv_pmp_select(struct ata_port *ap, int pmp)
2690 if (sata_pmp_supported(ap)) {
2691 void __iomem *port_mmio = mv_ap_base(ap);
2692 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
2693 int old = reg & 0xf;
2696 reg = (reg & ~0xf) | pmp;
2697 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
2702 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
2703 unsigned long deadline)
2705 mv_pmp_select(link->ap, sata_srst_pmp(link));
2706 return sata_std_hardreset(link, class, deadline);
2709 static int mv_softreset(struct ata_link *link, unsigned int *class,
2710 unsigned long deadline)
2712 mv_pmp_select(link->ap, sata_srst_pmp(link));
2713 return ata_sff_softreset(link, class, deadline);
2716 static int mv_hardreset(struct ata_link *link, unsigned int *class,
2717 unsigned long deadline)
2719 struct ata_port *ap = link->ap;
2720 struct mv_host_priv *hpriv = ap->host->private_data;
2721 struct mv_port_priv *pp = ap->private_data;
2722 void __iomem *mmio = hpriv->base;
2723 int rc, attempts = 0, extra = 0;
2727 mv_reset_channel(hpriv, mmio, ap->port_no);
2728 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2730 /* Workaround for errata FEr SATA#10 (part 2) */
2732 const unsigned long *timing =
2733 sata_ehc_deb_timing(&link->eh_context);
2735 rc = sata_link_hardreset(link, timing, deadline + extra,
2739 sata_scr_read(link, SCR_STATUS, &sstatus);
2740 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
2741 /* Force 1.5gb/s link speed and try again */
2742 mv_setup_ifcfg(mv_ap_base(ap), 0);
2743 if (time_after(jiffies + HZ, deadline))
2744 extra = HZ; /* only extend it once, max */
2746 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
2751 static void mv_eh_freeze(struct ata_port *ap)
2753 struct mv_host_priv *hpriv = ap->host->private_data;
2754 unsigned int shift, hardport, port = ap->port_no;
2757 /* FIXME: handle coalescing completion events properly */
2760 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2762 /* disable assertion of portN err, done events */
2763 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2764 main_irq_mask &= ~((DONE_IRQ | ERR_IRQ) << shift);
2765 writelfl(main_irq_mask, hpriv->main_irq_mask_addr);
2768 static void mv_eh_thaw(struct ata_port *ap)
2770 struct mv_host_priv *hpriv = ap->host->private_data;
2771 unsigned int shift, hardport, port = ap->port_no;
2772 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
2773 void __iomem *port_mmio = mv_ap_base(ap);
2774 u32 main_irq_mask, hc_irq_cause;
2776 /* FIXME: handle coalescing completion events properly */
2778 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2780 /* clear EDMA errors on this port */
2781 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2783 /* clear pending irq events */
2784 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
2785 hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hardport);
2786 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
2788 /* enable assertion of portN err, done events */
2789 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2790 main_irq_mask |= ((DONE_IRQ | ERR_IRQ) << shift);
2791 writelfl(main_irq_mask, hpriv->main_irq_mask_addr);
2795 * mv_port_init - Perform some early initialization on a single port.
2796 * @port: libata data structure storing shadow register addresses
2797 * @port_mmio: base address of the port
2799 * Initialize shadow register mmio addresses, clear outstanding
2800 * interrupts on the port, and unmask interrupts for the future
2801 * start of the port.
2804 * Inherited from caller.
2806 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
2808 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
2811 /* PIO related setup
2813 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
2815 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2816 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2817 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2818 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2819 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2820 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
2822 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2823 /* special case: control/altstatus doesn't have ATA_REG_ address */
2824 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2827 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
2829 /* Clear any currently outstanding port interrupt conditions */
2830 serr_ofs = mv_scr_offset(SCR_ERROR);
2831 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2832 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2834 /* unmask all non-transient EDMA error interrupts */
2835 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
2837 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
2838 readl(port_mmio + EDMA_CFG_OFS),
2839 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2840 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
2843 static unsigned int mv_in_pcix_mode(struct ata_host *host)
2845 struct mv_host_priv *hpriv = host->private_data;
2846 void __iomem *mmio = hpriv->base;
2849 if (!HAS_PCI(host) || !IS_PCIE(hpriv))
2850 return 0; /* not PCI-X capable */
2851 reg = readl(mmio + MV_PCI_MODE_OFS);
2852 if ((reg & MV_PCI_MODE_MASK) == 0)
2853 return 0; /* conventional PCI mode */
2854 return 1; /* chip is in PCI-X mode */
2857 static int mv_pci_cut_through_okay(struct ata_host *host)
2859 struct mv_host_priv *hpriv = host->private_data;
2860 void __iomem *mmio = hpriv->base;
2863 if (!mv_in_pcix_mode(host)) {
2864 reg = readl(mmio + PCI_COMMAND_OFS);
2865 if (reg & PCI_COMMAND_MRDTRIG)
2866 return 0; /* not okay */
2868 return 1; /* okay */
2871 static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
2873 struct pci_dev *pdev = to_pci_dev(host->dev);
2874 struct mv_host_priv *hpriv = host->private_data;
2875 u32 hp_flags = hpriv->hp_flags;
2877 switch (board_idx) {
2879 hpriv->ops = &mv5xxx_ops;
2880 hp_flags |= MV_HP_GEN_I;
2882 switch (pdev->revision) {
2884 hp_flags |= MV_HP_ERRATA_50XXB0;
2887 hp_flags |= MV_HP_ERRATA_50XXB2;
2890 dev_printk(KERN_WARNING, &pdev->dev,
2891 "Applying 50XXB2 workarounds to unknown rev\n");
2892 hp_flags |= MV_HP_ERRATA_50XXB2;
2899 hpriv->ops = &mv5xxx_ops;
2900 hp_flags |= MV_HP_GEN_I;
2902 switch (pdev->revision) {
2904 hp_flags |= MV_HP_ERRATA_50XXB0;
2907 hp_flags |= MV_HP_ERRATA_50XXB2;
2910 dev_printk(KERN_WARNING, &pdev->dev,
2911 "Applying B2 workarounds to unknown rev\n");
2912 hp_flags |= MV_HP_ERRATA_50XXB2;
2919 hpriv->ops = &mv6xxx_ops;
2920 hp_flags |= MV_HP_GEN_II;
2922 switch (pdev->revision) {
2924 hp_flags |= MV_HP_ERRATA_60X1B2;
2927 hp_flags |= MV_HP_ERRATA_60X1C0;
2930 dev_printk(KERN_WARNING, &pdev->dev,
2931 "Applying B2 workarounds to unknown rev\n");
2932 hp_flags |= MV_HP_ERRATA_60X1B2;
2938 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
2939 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
2940 (pdev->device == 0x2300 || pdev->device == 0x2310))
2943 * Highpoint RocketRAID PCIe 23xx series cards:
2945 * Unconfigured drives are treated as "Legacy"
2946 * by the BIOS, and it overwrites sector 8 with
2947 * a "Lgcy" metadata block prior to Linux boot.
2949 * Configured drives (RAID or JBOD) leave sector 8
2950 * alone, but instead overwrite a high numbered
2951 * sector for the RAID metadata. This sector can
2952 * be determined exactly, by truncating the physical
2953 * drive capacity to a nice even GB value.
2955 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
2957 * Warn the user, lest they think we're just buggy.
2959 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
2960 " BIOS CORRUPTS DATA on all attached drives,"
2961 " regardless of if/how they are configured."
2963 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
2964 " use sectors 8-9 on \"Legacy\" drives,"
2965 " and avoid the final two gigabytes on"
2966 " all RocketRAID BIOS initialized drives.\n");
2970 hpriv->ops = &mv6xxx_ops;
2971 hp_flags |= MV_HP_GEN_IIE;
2972 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
2973 hp_flags |= MV_HP_CUT_THROUGH;
2975 switch (pdev->revision) {
2977 hp_flags |= MV_HP_ERRATA_XX42A0;
2980 hp_flags |= MV_HP_ERRATA_60X1C0;
2983 dev_printk(KERN_WARNING, &pdev->dev,
2984 "Applying 60X1C0 workarounds to unknown rev\n");
2985 hp_flags |= MV_HP_ERRATA_60X1C0;
2990 hpriv->ops = &mv_soc_ops;
2991 hp_flags |= MV_HP_ERRATA_60X1C0;
2995 dev_printk(KERN_ERR, host->dev,
2996 "BUG: invalid board index %u\n", board_idx);
3000 hpriv->hp_flags = hp_flags;
3001 if (hp_flags & MV_HP_PCIE) {
3002 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
3003 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
3004 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3006 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
3007 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
3008 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3015 * mv_init_host - Perform some early initialization of the host.
3016 * @host: ATA host to initialize
3017 * @board_idx: controller index
3019 * If possible, do an early global reset of the host. Then do
3020 * our port init and clear/unmask all/relevant host interrupts.
3023 * Inherited from caller.
3025 static int mv_init_host(struct ata_host *host, unsigned int board_idx)
3027 int rc = 0, n_hc, port, hc;
3028 struct mv_host_priv *hpriv = host->private_data;
3029 void __iomem *mmio = hpriv->base;
3031 rc = mv_chip_id(host, board_idx);
3035 if (HAS_PCI(host)) {
3036 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
3037 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
3039 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
3040 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
3043 /* global interrupt mask: 0 == mask everything */
3044 writel(0, hpriv->main_irq_mask_addr);
3046 n_hc = mv_get_hc_count(host->ports[0]->flags);
3048 for (port = 0; port < host->n_ports; port++)
3049 hpriv->ops->read_preamp(hpriv, port, mmio);
3051 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
3055 hpriv->ops->reset_flash(hpriv, mmio);
3056 hpriv->ops->reset_bus(host, mmio);
3057 hpriv->ops->enable_leds(hpriv, mmio);
3059 for (port = 0; port < host->n_ports; port++) {
3060 struct ata_port *ap = host->ports[port];
3061 void __iomem *port_mmio = mv_port_base(mmio, port);
3063 mv_port_init(&ap->ioaddr, port_mmio);
3066 if (HAS_PCI(host)) {
3067 unsigned int offset = port_mmio - mmio;
3068 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
3069 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
3074 for (hc = 0; hc < n_hc; hc++) {
3075 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3077 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3078 "(before clear)=0x%08x\n", hc,
3079 readl(hc_mmio + HC_CFG_OFS),
3080 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
3082 /* Clear any currently outstanding hc interrupt conditions */
3083 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
3086 if (HAS_PCI(host)) {
3087 /* Clear any currently outstanding host interrupt conditions */
3088 writelfl(0, mmio + hpriv->irq_cause_ofs);
3090 /* and unmask interrupt generation for host regs */
3091 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
3092 if (IS_GEN_I(hpriv))
3093 writelfl(~HC_MAIN_MASKED_IRQS_5,
3094 hpriv->main_irq_mask_addr);
3096 writelfl(~HC_MAIN_MASKED_IRQS,
3097 hpriv->main_irq_mask_addr);
3099 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
3100 "PCI int cause/mask=0x%08x/0x%08x\n",
3101 readl(hpriv->main_irq_cause_addr),
3102 readl(hpriv->main_irq_mask_addr),
3103 readl(mmio + hpriv->irq_cause_ofs),
3104 readl(mmio + hpriv->irq_mask_ofs));
3106 writelfl(~HC_MAIN_MASKED_IRQS_SOC,
3107 hpriv->main_irq_mask_addr);
3108 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x\n",
3109 readl(hpriv->main_irq_cause_addr),
3110 readl(hpriv->main_irq_mask_addr));
3116 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3118 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3120 if (!hpriv->crqb_pool)
3123 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3125 if (!hpriv->crpb_pool)
3128 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3130 if (!hpriv->sg_tbl_pool)
3136 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3137 struct mbus_dram_target_info *dram)
3141 for (i = 0; i < 4; i++) {
3142 writel(0, hpriv->base + WINDOW_CTRL(i));
3143 writel(0, hpriv->base + WINDOW_BASE(i));
3146 for (i = 0; i < dram->num_cs; i++) {
3147 struct mbus_dram_window *cs = dram->cs + i;
3149 writel(((cs->size - 1) & 0xffff0000) |
3150 (cs->mbus_attr << 8) |
3151 (dram->mbus_dram_target_id << 4) | 1,
3152 hpriv->base + WINDOW_CTRL(i));
3153 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3158 * mv_platform_probe - handle a positive probe of an soc Marvell
3160 * @pdev: platform device found
3163 * Inherited from caller.
3165 static int mv_platform_probe(struct platform_device *pdev)
3167 static int printed_version;
3168 const struct mv_sata_platform_data *mv_platform_data;
3169 const struct ata_port_info *ppi[] =
3170 { &mv_port_info[chip_soc], NULL };
3171 struct ata_host *host;
3172 struct mv_host_priv *hpriv;
3173 struct resource *res;
3176 if (!printed_version++)
3177 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
3180 * Simple resource validation ..
3182 if (unlikely(pdev->num_resources != 2)) {
3183 dev_err(&pdev->dev, "invalid number of resources\n");
3188 * Get the register base first
3190 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3195 mv_platform_data = pdev->dev.platform_data;
3196 n_ports = mv_platform_data->n_ports;
3198 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3199 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3201 if (!host || !hpriv)
3203 host->private_data = hpriv;
3204 hpriv->n_ports = n_ports;
3207 hpriv->base = devm_ioremap(&pdev->dev, res->start,
3208 res->end - res->start + 1);
3209 hpriv->base -= MV_SATAHC0_REG_BASE;
3212 * (Re-)program MBUS remapping windows if we are asked to.
3214 if (mv_platform_data->dram != NULL)
3215 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
3217 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3221 /* initialize adapter */
3222 rc = mv_init_host(host, chip_soc);
3226 dev_printk(KERN_INFO, &pdev->dev,
3227 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
3230 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
3231 IRQF_SHARED, &mv6_sht);
3236 * mv_platform_remove - unplug a platform interface
3237 * @pdev: platform device
3239 * A platform bus SATA device has been unplugged. Perform the needed
3240 * cleanup. Also called on module unload for any active devices.
3242 static int __devexit mv_platform_remove(struct platform_device *pdev)
3244 struct device *dev = &pdev->dev;
3245 struct ata_host *host = dev_get_drvdata(dev);
3247 ata_host_detach(host);
3251 static struct platform_driver mv_platform_driver = {
3252 .probe = mv_platform_probe,
3253 .remove = __devexit_p(mv_platform_remove),
3256 .owner = THIS_MODULE,
3262 static int mv_pci_init_one(struct pci_dev *pdev,
3263 const struct pci_device_id *ent);
3266 static struct pci_driver mv_pci_driver = {
3268 .id_table = mv_pci_tbl,
3269 .probe = mv_pci_init_one,
3270 .remove = ata_pci_remove_one,
3276 static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
3279 /* move to PCI layer or libata core? */
3280 static int pci_go_64(struct pci_dev *pdev)
3284 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3285 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3287 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3289 dev_printk(KERN_ERR, &pdev->dev,
3290 "64-bit DMA enable failed\n");
3295 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3297 dev_printk(KERN_ERR, &pdev->dev,
3298 "32-bit DMA enable failed\n");
3301 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3303 dev_printk(KERN_ERR, &pdev->dev,
3304 "32-bit consistent DMA enable failed\n");
3313 * mv_print_info - Dump key info to kernel log for perusal.
3314 * @host: ATA host to print info about
3316 * FIXME: complete this.
3319 * Inherited from caller.
3321 static void mv_print_info(struct ata_host *host)
3323 struct pci_dev *pdev = to_pci_dev(host->dev);
3324 struct mv_host_priv *hpriv = host->private_data;
3326 const char *scc_s, *gen;
3328 /* Use this to determine the HW stepping of the chip so we know
3329 * what errata to workaround
3331 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
3334 else if (scc == 0x01)
3339 if (IS_GEN_I(hpriv))
3341 else if (IS_GEN_II(hpriv))
3343 else if (IS_GEN_IIE(hpriv))
3348 dev_printk(KERN_INFO, &pdev->dev,
3349 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3350 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
3351 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
3355 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
3356 * @pdev: PCI device found
3357 * @ent: PCI device ID entry for the matched host
3360 * Inherited from caller.
3362 static int mv_pci_init_one(struct pci_dev *pdev,
3363 const struct pci_device_id *ent)
3365 static int printed_version;
3366 unsigned int board_idx = (unsigned int)ent->driver_data;
3367 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
3368 struct ata_host *host;
3369 struct mv_host_priv *hpriv;
3372 if (!printed_version++)
3373 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
3376 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
3378 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3379 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3380 if (!host || !hpriv)
3382 host->private_data = hpriv;
3383 hpriv->n_ports = n_ports;
3385 /* acquire resources */
3386 rc = pcim_enable_device(pdev);
3390 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
3392 pcim_pin_device(pdev);
3395 host->iomap = pcim_iomap_table(pdev);
3396 hpriv->base = host->iomap[MV_PRIMARY_BAR];
3398 rc = pci_go_64(pdev);
3402 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3406 /* initialize adapter */
3407 rc = mv_init_host(host, board_idx);
3411 /* Enable interrupts */
3412 if (msi && pci_enable_msi(pdev))
3415 mv_dump_pci_cfg(pdev, 0x68);
3416 mv_print_info(host);
3418 pci_set_master(pdev);
3419 pci_try_set_mwi(pdev);
3420 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
3421 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
3425 static int mv_platform_probe(struct platform_device *pdev);
3426 static int __devexit mv_platform_remove(struct platform_device *pdev);
3428 static int __init mv_init(void)
3432 rc = pci_register_driver(&mv_pci_driver);
3436 rc = platform_driver_register(&mv_platform_driver);
3440 pci_unregister_driver(&mv_pci_driver);
3445 static void __exit mv_exit(void)
3448 pci_unregister_driver(&mv_pci_driver);
3450 platform_driver_unregister(&mv_platform_driver);
3453 MODULE_AUTHOR("Brett Russ");
3454 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
3455 MODULE_LICENSE("GPL");
3456 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
3457 MODULE_VERSION(DRV_VERSION);
3458 MODULE_ALIAS("platform:" DRV_NAME);
3461 module_param(msi, int, 0444);
3462 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
3465 module_init(mv_init);
3466 module_exit(mv_exit);