2 * libata-sff.c - helper library for PCI IDE BMDMA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2006 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2006 Jeff Garzik
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
35 #include <linux/kernel.h>
36 #include <linux/pci.h>
37 #include <linux/libata.h>
38 #include <linux/highmem.h>
42 const struct ata_port_operations ata_sff_port_ops = {
43 .inherits = &ata_base_port_ops,
45 .qc_prep = ata_sff_qc_prep,
46 .qc_issue = ata_sff_qc_issue,
47 .qc_fill_rtf = ata_sff_qc_fill_rtf,
49 .freeze = ata_sff_freeze,
51 .prereset = ata_sff_prereset,
52 .softreset = ata_sff_softreset,
53 .hardreset = sata_sff_hardreset,
54 .postreset = ata_sff_postreset,
55 .error_handler = ata_sff_error_handler,
56 .post_internal_cmd = ata_sff_post_internal_cmd,
58 .sff_dev_select = ata_sff_dev_select,
59 .sff_check_status = ata_sff_check_status,
60 .sff_tf_load = ata_sff_tf_load,
61 .sff_tf_read = ata_sff_tf_read,
62 .sff_exec_command = ata_sff_exec_command,
63 .sff_data_xfer = ata_sff_data_xfer,
64 .sff_irq_on = ata_sff_irq_on,
65 .sff_irq_clear = ata_sff_irq_clear,
67 .port_start = ata_sff_port_start,
70 const struct ata_port_operations ata_bmdma_port_ops = {
71 .inherits = &ata_sff_port_ops,
73 .mode_filter = ata_bmdma_mode_filter,
75 .bmdma_setup = ata_bmdma_setup,
76 .bmdma_start = ata_bmdma_start,
77 .bmdma_stop = ata_bmdma_stop,
78 .bmdma_status = ata_bmdma_status,
81 const struct ata_port_operations ata_bmdma32_port_ops = {
82 .inherits = &ata_bmdma_port_ops,
84 .sff_data_xfer = ata_sff_data_xfer32,
86 EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops);
89 * ata_fill_sg - Fill PCI IDE PRD table
90 * @qc: Metadata associated with taskfile to be transferred
92 * Fill PCI IDE PRD (scatter-gather) table with segments
93 * associated with the current disk command.
96 * spin_lock_irqsave(host lock)
99 static void ata_fill_sg(struct ata_queued_cmd *qc)
101 struct ata_port *ap = qc->ap;
102 struct scatterlist *sg;
106 for_each_sg(qc->sg, sg, qc->n_elem, si) {
110 /* determine if physical DMA addr spans 64K boundary.
111 * Note h/w doesn't support 64-bit, so we unconditionally
112 * truncate dma_addr_t to u32.
114 addr = (u32) sg_dma_address(sg);
115 sg_len = sg_dma_len(sg);
118 offset = addr & 0xffff;
120 if ((offset + sg_len) > 0x10000)
121 len = 0x10000 - offset;
123 ap->prd[pi].addr = cpu_to_le32(addr);
124 ap->prd[pi].flags_len = cpu_to_le32(len & 0xffff);
125 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
133 ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
137 * ata_fill_sg_dumb - Fill PCI IDE PRD table
138 * @qc: Metadata associated with taskfile to be transferred
140 * Fill PCI IDE PRD (scatter-gather) table with segments
141 * associated with the current disk command. Perform the fill
142 * so that we avoid writing any length 64K records for
143 * controllers that don't follow the spec.
146 * spin_lock_irqsave(host lock)
149 static void ata_fill_sg_dumb(struct ata_queued_cmd *qc)
151 struct ata_port *ap = qc->ap;
152 struct scatterlist *sg;
156 for_each_sg(qc->sg, sg, qc->n_elem, si) {
158 u32 sg_len, len, blen;
160 /* determine if physical DMA addr spans 64K boundary.
161 * Note h/w doesn't support 64-bit, so we unconditionally
162 * truncate dma_addr_t to u32.
164 addr = (u32) sg_dma_address(sg);
165 sg_len = sg_dma_len(sg);
168 offset = addr & 0xffff;
170 if ((offset + sg_len) > 0x10000)
171 len = 0x10000 - offset;
174 ap->prd[pi].addr = cpu_to_le32(addr);
176 /* Some PATA chipsets like the CS5530 can't
177 cope with 0x0000 meaning 64K as the spec says */
178 ap->prd[pi].flags_len = cpu_to_le32(0x8000);
180 ap->prd[++pi].addr = cpu_to_le32(addr + 0x8000);
182 ap->prd[pi].flags_len = cpu_to_le32(blen);
183 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
191 ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
195 * ata_sff_qc_prep - Prepare taskfile for submission
196 * @qc: Metadata associated with taskfile to be prepared
198 * Prepare ATA taskfile for submission.
201 * spin_lock_irqsave(host lock)
203 void ata_sff_qc_prep(struct ata_queued_cmd *qc)
205 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
212 * ata_sff_dumb_qc_prep - Prepare taskfile for submission
213 * @qc: Metadata associated with taskfile to be prepared
215 * Prepare ATA taskfile for submission.
218 * spin_lock_irqsave(host lock)
220 void ata_sff_dumb_qc_prep(struct ata_queued_cmd *qc)
222 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
225 ata_fill_sg_dumb(qc);
229 * ata_sff_check_status - Read device status reg & clear interrupt
230 * @ap: port where the device is
232 * Reads ATA taskfile status register for currently-selected device
233 * and return its value. This also clears pending interrupts
237 * Inherited from caller.
239 u8 ata_sff_check_status(struct ata_port *ap)
241 return ioread8(ap->ioaddr.status_addr);
245 * ata_sff_altstatus - Read device alternate status reg
246 * @ap: port where the device is
248 * Reads ATA taskfile alternate status register for
249 * currently-selected device and return its value.
251 * Note: may NOT be used as the check_altstatus() entry in
252 * ata_port_operations.
255 * Inherited from caller.
257 static u8 ata_sff_altstatus(struct ata_port *ap)
259 if (ap->ops->sff_check_altstatus)
260 return ap->ops->sff_check_altstatus(ap);
262 return ioread8(ap->ioaddr.altstatus_addr);
266 * ata_sff_irq_status - Check if the device is busy
267 * @ap: port where the device is
269 * Determine if the port is currently busy. Uses altstatus
270 * if available in order to avoid clearing shared IRQ status
271 * when finding an IRQ source. Non ctl capable devices don't
272 * share interrupt lines fortunately for us.
275 * Inherited from caller.
277 static u8 ata_sff_irq_status(struct ata_port *ap)
281 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
282 status = ata_sff_altstatus(ap);
283 /* Not us: We are busy */
284 if (status & ATA_BUSY)
287 /* Clear INTRQ latch */
288 status = ap->ops->sff_check_status(ap);
293 * ata_sff_sync - Flush writes
294 * @ap: Port to wait for.
297 * If we have an mmio device with no ctl and no altstatus
298 * method this will fail. No such devices are known to exist.
301 * Inherited from caller.
304 static void ata_sff_sync(struct ata_port *ap)
306 if (ap->ops->sff_check_altstatus)
307 ap->ops->sff_check_altstatus(ap);
308 else if (ap->ioaddr.altstatus_addr)
309 ioread8(ap->ioaddr.altstatus_addr);
313 * ata_sff_pause - Flush writes and wait 400nS
314 * @ap: Port to pause for.
317 * If we have an mmio device with no ctl and no altstatus
318 * method this will fail. No such devices are known to exist.
321 * Inherited from caller.
324 void ata_sff_pause(struct ata_port *ap)
331 * ata_sff_dma_pause - Pause before commencing DMA
332 * @ap: Port to pause for.
334 * Perform I/O fencing and ensure sufficient cycle delays occur
335 * for the HDMA1:0 transition
338 void ata_sff_dma_pause(struct ata_port *ap)
340 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
341 /* An altstatus read will cause the needed delay without
342 messing up the IRQ status */
343 ata_sff_altstatus(ap);
346 /* There are no DMA controllers without ctl. BUG here to ensure
347 we never violate the HDMA1:0 transition timing and risk
353 * ata_sff_busy_sleep - sleep until BSY clears, or timeout
354 * @ap: port containing status register to be polled
355 * @tmout_pat: impatience timeout in msecs
356 * @tmout: overall timeout in msecs
358 * Sleep until ATA Status register bit BSY clears,
359 * or a timeout occurs.
362 * Kernel thread context (may sleep).
365 * 0 on success, -errno otherwise.
367 int ata_sff_busy_sleep(struct ata_port *ap,
368 unsigned long tmout_pat, unsigned long tmout)
370 unsigned long timer_start, timeout;
373 status = ata_sff_busy_wait(ap, ATA_BUSY, 300);
374 timer_start = jiffies;
375 timeout = ata_deadline(timer_start, tmout_pat);
376 while (status != 0xff && (status & ATA_BUSY) &&
377 time_before(jiffies, timeout)) {
379 status = ata_sff_busy_wait(ap, ATA_BUSY, 3);
382 if (status != 0xff && (status & ATA_BUSY))
383 ata_port_printk(ap, KERN_WARNING,
384 "port is slow to respond, please be patient "
385 "(Status 0x%x)\n", status);
387 timeout = ata_deadline(timer_start, tmout);
388 while (status != 0xff && (status & ATA_BUSY) &&
389 time_before(jiffies, timeout)) {
391 status = ap->ops->sff_check_status(ap);
397 if (status & ATA_BUSY) {
398 ata_port_printk(ap, KERN_ERR, "port failed to respond "
399 "(%lu secs, Status 0x%x)\n",
400 DIV_ROUND_UP(tmout, 1000), status);
407 static int ata_sff_check_ready(struct ata_link *link)
409 u8 status = link->ap->ops->sff_check_status(link->ap);
411 return ata_check_ready(status);
415 * ata_sff_wait_ready - sleep until BSY clears, or timeout
416 * @link: SFF link to wait ready status for
417 * @deadline: deadline jiffies for the operation
419 * Sleep until ATA Status register bit BSY clears, or timeout
423 * Kernel thread context (may sleep).
426 * 0 on success, -errno otherwise.
428 int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline)
430 return ata_wait_ready(link, deadline, ata_sff_check_ready);
434 * ata_sff_dev_select - Select device 0/1 on ATA bus
435 * @ap: ATA channel to manipulate
436 * @device: ATA device (numbered from zero) to select
438 * Use the method defined in the ATA specification to
439 * make either device 0, or device 1, active on the
440 * ATA channel. Works with both PIO and MMIO.
442 * May be used as the dev_select() entry in ata_port_operations.
447 void ata_sff_dev_select(struct ata_port *ap, unsigned int device)
452 tmp = ATA_DEVICE_OBS;
454 tmp = ATA_DEVICE_OBS | ATA_DEV1;
456 iowrite8(tmp, ap->ioaddr.device_addr);
457 ata_sff_pause(ap); /* needed; also flushes, for mmio */
461 * ata_dev_select - Select device 0/1 on ATA bus
462 * @ap: ATA channel to manipulate
463 * @device: ATA device (numbered from zero) to select
464 * @wait: non-zero to wait for Status register BSY bit to clear
465 * @can_sleep: non-zero if context allows sleeping
467 * Use the method defined in the ATA specification to
468 * make either device 0, or device 1, active on the
471 * This is a high-level version of ata_sff_dev_select(), which
472 * additionally provides the services of inserting the proper
473 * pauses and status polling, where needed.
478 void ata_dev_select(struct ata_port *ap, unsigned int device,
479 unsigned int wait, unsigned int can_sleep)
481 if (ata_msg_probe(ap))
482 ata_port_printk(ap, KERN_INFO, "ata_dev_select: ENTER, "
483 "device %u, wait %u\n", device, wait);
488 ap->ops->sff_dev_select(ap, device);
491 if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI)
498 * ata_sff_irq_on - Enable interrupts on a port.
499 * @ap: Port on which interrupts are enabled.
501 * Enable interrupts on a legacy IDE device using MMIO or PIO,
502 * wait for idle, clear any pending interrupts.
505 * Inherited from caller.
507 u8 ata_sff_irq_on(struct ata_port *ap)
509 struct ata_ioports *ioaddr = &ap->ioaddr;
512 ap->ctl &= ~ATA_NIEN;
513 ap->last_ctl = ap->ctl;
515 if (ioaddr->ctl_addr)
516 iowrite8(ap->ctl, ioaddr->ctl_addr);
517 tmp = ata_wait_idle(ap);
519 ap->ops->sff_irq_clear(ap);
525 * ata_sff_irq_clear - Clear PCI IDE BMDMA interrupt.
526 * @ap: Port associated with this ATA transaction.
528 * Clear interrupt and error flags in DMA status register.
530 * May be used as the irq_clear() entry in ata_port_operations.
533 * spin_lock_irqsave(host lock)
535 void ata_sff_irq_clear(struct ata_port *ap)
537 void __iomem *mmio = ap->ioaddr.bmdma_addr;
542 iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
546 * ata_sff_tf_load - send taskfile registers to host controller
547 * @ap: Port to which output is sent
548 * @tf: ATA taskfile register set
550 * Outputs ATA taskfile to standard ATA host controller.
553 * Inherited from caller.
555 void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
557 struct ata_ioports *ioaddr = &ap->ioaddr;
558 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
560 if (tf->ctl != ap->last_ctl) {
561 if (ioaddr->ctl_addr)
562 iowrite8(tf->ctl, ioaddr->ctl_addr);
563 ap->last_ctl = tf->ctl;
567 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
568 WARN_ON(!ioaddr->ctl_addr);
569 iowrite8(tf->hob_feature, ioaddr->feature_addr);
570 iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
571 iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
572 iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
573 iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
574 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
583 iowrite8(tf->feature, ioaddr->feature_addr);
584 iowrite8(tf->nsect, ioaddr->nsect_addr);
585 iowrite8(tf->lbal, ioaddr->lbal_addr);
586 iowrite8(tf->lbam, ioaddr->lbam_addr);
587 iowrite8(tf->lbah, ioaddr->lbah_addr);
588 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
596 if (tf->flags & ATA_TFLAG_DEVICE) {
597 iowrite8(tf->device, ioaddr->device_addr);
598 VPRINTK("device 0x%X\n", tf->device);
605 * ata_sff_tf_read - input device's ATA taskfile shadow registers
606 * @ap: Port from which input is read
607 * @tf: ATA taskfile register set for storing input
609 * Reads ATA taskfile registers for currently-selected device
610 * into @tf. Assumes the device has a fully SFF compliant task file
611 * layout and behaviour. If you device does not (eg has a different
612 * status method) then you will need to provide a replacement tf_read
615 * Inherited from caller.
617 void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
619 struct ata_ioports *ioaddr = &ap->ioaddr;
621 tf->command = ata_sff_check_status(ap);
622 tf->feature = ioread8(ioaddr->error_addr);
623 tf->nsect = ioread8(ioaddr->nsect_addr);
624 tf->lbal = ioread8(ioaddr->lbal_addr);
625 tf->lbam = ioread8(ioaddr->lbam_addr);
626 tf->lbah = ioread8(ioaddr->lbah_addr);
627 tf->device = ioread8(ioaddr->device_addr);
629 if (tf->flags & ATA_TFLAG_LBA48) {
630 if (likely(ioaddr->ctl_addr)) {
631 iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
632 tf->hob_feature = ioread8(ioaddr->error_addr);
633 tf->hob_nsect = ioread8(ioaddr->nsect_addr);
634 tf->hob_lbal = ioread8(ioaddr->lbal_addr);
635 tf->hob_lbam = ioread8(ioaddr->lbam_addr);
636 tf->hob_lbah = ioread8(ioaddr->lbah_addr);
637 iowrite8(tf->ctl, ioaddr->ctl_addr);
638 ap->last_ctl = tf->ctl;
645 * ata_sff_exec_command - issue ATA command to host controller
646 * @ap: port to which command is being issued
647 * @tf: ATA taskfile register set
649 * Issues ATA command, with proper synchronization with interrupt
650 * handler / other threads.
653 * spin_lock_irqsave(host lock)
655 void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
657 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
659 iowrite8(tf->command, ap->ioaddr.command_addr);
664 * ata_tf_to_host - issue ATA taskfile to host controller
665 * @ap: port to which command is being issued
666 * @tf: ATA taskfile register set
668 * Issues ATA taskfile register set to ATA host controller,
669 * with proper synchronization with interrupt handler and
673 * spin_lock_irqsave(host lock)
675 static inline void ata_tf_to_host(struct ata_port *ap,
676 const struct ata_taskfile *tf)
678 ap->ops->sff_tf_load(ap, tf);
679 ap->ops->sff_exec_command(ap, tf);
683 * ata_sff_data_xfer - Transfer data by PIO
684 * @dev: device to target
686 * @buflen: buffer length
689 * Transfer data from/to the device data register by PIO.
692 * Inherited from caller.
697 unsigned int ata_sff_data_xfer(struct ata_device *dev, unsigned char *buf,
698 unsigned int buflen, int rw)
700 struct ata_port *ap = dev->link->ap;
701 void __iomem *data_addr = ap->ioaddr.data_addr;
702 unsigned int words = buflen >> 1;
704 /* Transfer multiple of 2 bytes */
706 ioread16_rep(data_addr, buf, words);
708 iowrite16_rep(data_addr, buf, words);
710 /* Transfer trailing 1 byte, if any. */
711 if (unlikely(buflen & 0x01)) {
712 __le16 align_buf[1] = { 0 };
713 unsigned char *trailing_buf = buf + buflen - 1;
716 align_buf[0] = cpu_to_le16(ioread16(data_addr));
717 memcpy(trailing_buf, align_buf, 1);
719 memcpy(align_buf, trailing_buf, 1);
720 iowrite16(le16_to_cpu(align_buf[0]), data_addr);
729 * ata_sff_data_xfer32 - Transfer data by PIO
730 * @dev: device to target
732 * @buflen: buffer length
735 * Transfer data from/to the device data register by PIO using 32bit
739 * Inherited from caller.
745 unsigned int ata_sff_data_xfer32(struct ata_device *dev, unsigned char *buf,
746 unsigned int buflen, int rw)
748 struct ata_port *ap = dev->link->ap;
749 void __iomem *data_addr = ap->ioaddr.data_addr;
750 unsigned int words = buflen >> 2;
751 int slop = buflen & 3;
753 /* Transfer multiple of 4 bytes */
755 ioread32_rep(data_addr, buf, words);
757 iowrite32_rep(data_addr, buf, words);
759 if (unlikely(slop)) {
762 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
763 memcpy(buf + buflen - slop, &pad, slop);
765 memcpy(&pad, buf + buflen - slop, slop);
766 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
772 EXPORT_SYMBOL_GPL(ata_sff_data_xfer32);
775 * ata_sff_data_xfer_noirq - Transfer data by PIO
776 * @dev: device to target
778 * @buflen: buffer length
781 * Transfer data from/to the device data register by PIO. Do the
782 * transfer with interrupts disabled.
785 * Inherited from caller.
790 unsigned int ata_sff_data_xfer_noirq(struct ata_device *dev, unsigned char *buf,
791 unsigned int buflen, int rw)
794 unsigned int consumed;
796 local_irq_save(flags);
797 consumed = ata_sff_data_xfer(dev, buf, buflen, rw);
798 local_irq_restore(flags);
804 * ata_pio_sector - Transfer a sector of data.
805 * @qc: Command on going
807 * Transfer qc->sect_size bytes of data from/to the ATA device.
810 * Inherited from caller.
812 static void ata_pio_sector(struct ata_queued_cmd *qc)
814 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
815 struct ata_port *ap = qc->ap;
820 if (qc->curbytes == qc->nbytes - qc->sect_size)
821 ap->hsm_task_state = HSM_ST_LAST;
823 page = sg_page(qc->cursg);
824 offset = qc->cursg->offset + qc->cursg_ofs;
826 /* get the current page and offset */
827 page = nth_page(page, (offset >> PAGE_SHIFT));
830 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
832 if (PageHighMem(page)) {
835 /* FIXME: use a bounce buffer */
836 local_irq_save(flags);
837 buf = kmap_atomic(page, KM_IRQ0);
839 /* do the actual data transfer */
840 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
843 kunmap_atomic(buf, KM_IRQ0);
844 local_irq_restore(flags);
846 buf = page_address(page);
847 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
851 qc->curbytes += qc->sect_size;
852 qc->cursg_ofs += qc->sect_size;
854 if (qc->cursg_ofs == qc->cursg->length) {
855 qc->cursg = sg_next(qc->cursg);
861 * ata_pio_sectors - Transfer one or many sectors.
862 * @qc: Command on going
864 * Transfer one or many sectors of data from/to the
865 * ATA device for the DRQ request.
868 * Inherited from caller.
870 static void ata_pio_sectors(struct ata_queued_cmd *qc)
872 if (is_multi_taskfile(&qc->tf)) {
873 /* READ/WRITE MULTIPLE */
876 WARN_ON(qc->dev->multi_count == 0);
878 nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size,
879 qc->dev->multi_count);
885 ata_sff_sync(qc->ap); /* flush */
889 * atapi_send_cdb - Write CDB bytes to hardware
890 * @ap: Port to which ATAPI device is attached.
891 * @qc: Taskfile currently active
893 * When device has indicated its readiness to accept
894 * a CDB, this function is called. Send the CDB.
899 static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
902 DPRINTK("send cdb\n");
903 WARN_ON(qc->dev->cdb_len < 12);
905 ap->ops->sff_data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1);
907 /* FIXME: If the CDB is for DMA do we need to do the transition delay
908 or is bmdma_start guaranteed to do it ? */
909 switch (qc->tf.protocol) {
911 ap->hsm_task_state = HSM_ST;
913 case ATAPI_PROT_NODATA:
914 ap->hsm_task_state = HSM_ST_LAST;
917 ap->hsm_task_state = HSM_ST_LAST;
919 ap->ops->bmdma_start(qc);
925 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
926 * @qc: Command on going
927 * @bytes: number of bytes
929 * Transfer Transfer data from/to the ATAPI device.
932 * Inherited from caller.
935 static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
937 int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ;
938 struct ata_port *ap = qc->ap;
939 struct ata_device *dev = qc->dev;
940 struct ata_eh_info *ehi = &dev->link->eh_info;
941 struct scatterlist *sg;
944 unsigned int offset, count, consumed;
949 ata_ehi_push_desc(ehi, "unexpected or too much trailing data "
950 "buf=%u cur=%u bytes=%u",
951 qc->nbytes, qc->curbytes, bytes);
956 offset = sg->offset + qc->cursg_ofs;
958 /* get the current page and offset */
959 page = nth_page(page, (offset >> PAGE_SHIFT));
962 /* don't overrun current sg */
963 count = min(sg->length - qc->cursg_ofs, bytes);
965 /* don't cross page boundaries */
966 count = min(count, (unsigned int)PAGE_SIZE - offset);
968 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
970 if (PageHighMem(page)) {
973 /* FIXME: use bounce buffer */
974 local_irq_save(flags);
975 buf = kmap_atomic(page, KM_IRQ0);
977 /* do the actual data transfer */
978 consumed = ap->ops->sff_data_xfer(dev, buf + offset, count, rw);
980 kunmap_atomic(buf, KM_IRQ0);
981 local_irq_restore(flags);
983 buf = page_address(page);
984 consumed = ap->ops->sff_data_xfer(dev, buf + offset, count, rw);
987 bytes -= min(bytes, consumed);
988 qc->curbytes += count;
989 qc->cursg_ofs += count;
991 if (qc->cursg_ofs == sg->length) {
992 qc->cursg = sg_next(qc->cursg);
996 /* consumed can be larger than count only for the last transfer */
997 WARN_ON(qc->cursg && count != consumed);
1005 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
1006 * @qc: Command on going
1008 * Transfer Transfer data from/to the ATAPI device.
1011 * Inherited from caller.
1013 static void atapi_pio_bytes(struct ata_queued_cmd *qc)
1015 struct ata_port *ap = qc->ap;
1016 struct ata_device *dev = qc->dev;
1017 struct ata_eh_info *ehi = &dev->link->eh_info;
1018 unsigned int ireason, bc_lo, bc_hi, bytes;
1019 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
1021 /* Abuse qc->result_tf for temp storage of intermediate TF
1022 * here to save some kernel stack usage.
1023 * For normal completion, qc->result_tf is not relevant. For
1024 * error, qc->result_tf is later overwritten by ata_qc_complete().
1025 * So, the correctness of qc->result_tf is not affected.
1027 ap->ops->sff_tf_read(ap, &qc->result_tf);
1028 ireason = qc->result_tf.nsect;
1029 bc_lo = qc->result_tf.lbam;
1030 bc_hi = qc->result_tf.lbah;
1031 bytes = (bc_hi << 8) | bc_lo;
1033 /* shall be cleared to zero, indicating xfer of data */
1034 if (unlikely(ireason & (1 << 0)))
1037 /* make sure transfer direction matches expected */
1038 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
1039 if (unlikely(do_write != i_write))
1042 if (unlikely(!bytes))
1045 VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes);
1047 if (unlikely(__atapi_pio_bytes(qc, bytes)))
1049 ata_sff_sync(ap); /* flush */
1054 ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)",
1057 qc->err_mask |= AC_ERR_HSM;
1058 ap->hsm_task_state = HSM_ST_ERR;
1062 * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
1063 * @ap: the target ata_port
1067 * 1 if ok in workqueue, 0 otherwise.
1069 static inline int ata_hsm_ok_in_wq(struct ata_port *ap, struct ata_queued_cmd *qc)
1071 if (qc->tf.flags & ATA_TFLAG_POLLING)
1074 if (ap->hsm_task_state == HSM_ST_FIRST) {
1075 if (qc->tf.protocol == ATA_PROT_PIO &&
1076 (qc->tf.flags & ATA_TFLAG_WRITE))
1079 if (ata_is_atapi(qc->tf.protocol) &&
1080 !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1088 * ata_hsm_qc_complete - finish a qc running on standard HSM
1089 * @qc: Command to complete
1090 * @in_wq: 1 if called from workqueue, 0 otherwise
1092 * Finish @qc which is running on standard HSM.
1095 * If @in_wq is zero, spin_lock_irqsave(host lock).
1096 * Otherwise, none on entry and grabs host lock.
1098 static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
1100 struct ata_port *ap = qc->ap;
1101 unsigned long flags;
1103 if (ap->ops->error_handler) {
1105 spin_lock_irqsave(ap->lock, flags);
1107 /* EH might have kicked in while host lock is
1110 qc = ata_qc_from_tag(ap, qc->tag);
1112 if (likely(!(qc->err_mask & AC_ERR_HSM))) {
1113 ap->ops->sff_irq_on(ap);
1114 ata_qc_complete(qc);
1116 ata_port_freeze(ap);
1119 spin_unlock_irqrestore(ap->lock, flags);
1121 if (likely(!(qc->err_mask & AC_ERR_HSM)))
1122 ata_qc_complete(qc);
1124 ata_port_freeze(ap);
1128 spin_lock_irqsave(ap->lock, flags);
1129 ap->ops->sff_irq_on(ap);
1130 ata_qc_complete(qc);
1131 spin_unlock_irqrestore(ap->lock, flags);
1133 ata_qc_complete(qc);
1138 * ata_sff_hsm_move - move the HSM to the next state.
1139 * @ap: the target ata_port
1141 * @status: current device status
1142 * @in_wq: 1 if called from workqueue, 0 otherwise
1145 * 1 when poll next status needed, 0 otherwise.
1147 int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
1148 u8 status, int in_wq)
1150 struct ata_eh_info *ehi = &ap->link.eh_info;
1151 unsigned long flags = 0;
1154 WARN_ON((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
1156 /* Make sure ata_sff_qc_issue() does not throw things
1157 * like DMA polling into the workqueue. Notice that
1158 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
1160 WARN_ON(in_wq != ata_hsm_ok_in_wq(ap, qc));
1163 DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
1164 ap->print_id, qc->tf.protocol, ap->hsm_task_state, status);
1166 switch (ap->hsm_task_state) {
1168 /* Send first data block or PACKET CDB */
1170 /* If polling, we will stay in the work queue after
1171 * sending the data. Otherwise, interrupt handler
1172 * takes over after sending the data.
1174 poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
1176 /* check device status */
1177 if (unlikely((status & ATA_DRQ) == 0)) {
1178 /* handle BSY=0, DRQ=0 as error */
1179 if (likely(status & (ATA_ERR | ATA_DF)))
1180 /* device stops HSM for abort/error */
1181 qc->err_mask |= AC_ERR_DEV;
1183 /* HSM violation. Let EH handle this */
1184 ata_ehi_push_desc(ehi,
1185 "ST_FIRST: !(DRQ|ERR|DF)");
1186 qc->err_mask |= AC_ERR_HSM;
1189 ap->hsm_task_state = HSM_ST_ERR;
1193 /* Device should not ask for data transfer (DRQ=1)
1194 * when it finds something wrong.
1195 * We ignore DRQ here and stop the HSM by
1196 * changing hsm_task_state to HSM_ST_ERR and
1197 * let the EH abort the command or reset the device.
1199 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1200 /* Some ATAPI tape drives forget to clear the ERR bit
1201 * when doing the next command (mostly request sense).
1202 * We ignore ERR here to workaround and proceed sending
1205 if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
1206 ata_ehi_push_desc(ehi, "ST_FIRST: "
1207 "DRQ=1 with device error, "
1208 "dev_stat 0x%X", status);
1209 qc->err_mask |= AC_ERR_HSM;
1210 ap->hsm_task_state = HSM_ST_ERR;
1215 /* Send the CDB (atapi) or the first data block (ata pio out).
1216 * During the state transition, interrupt handler shouldn't
1217 * be invoked before the data transfer is complete and
1218 * hsm_task_state is changed. Hence, the following locking.
1221 spin_lock_irqsave(ap->lock, flags);
1223 if (qc->tf.protocol == ATA_PROT_PIO) {
1224 /* PIO data out protocol.
1225 * send first data block.
1228 /* ata_pio_sectors() might change the state
1229 * to HSM_ST_LAST. so, the state is changed here
1230 * before ata_pio_sectors().
1232 ap->hsm_task_state = HSM_ST;
1233 ata_pio_sectors(qc);
1236 atapi_send_cdb(ap, qc);
1239 spin_unlock_irqrestore(ap->lock, flags);
1241 /* if polling, ata_pio_task() handles the rest.
1242 * otherwise, interrupt handler takes over from here.
1247 /* complete command or read/write the data register */
1248 if (qc->tf.protocol == ATAPI_PROT_PIO) {
1249 /* ATAPI PIO protocol */
1250 if ((status & ATA_DRQ) == 0) {
1251 /* No more data to transfer or device error.
1252 * Device error will be tagged in HSM_ST_LAST.
1254 ap->hsm_task_state = HSM_ST_LAST;
1258 /* Device should not ask for data transfer (DRQ=1)
1259 * when it finds something wrong.
1260 * We ignore DRQ here and stop the HSM by
1261 * changing hsm_task_state to HSM_ST_ERR and
1262 * let the EH abort the command or reset the device.
1264 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1265 ata_ehi_push_desc(ehi, "ST-ATAPI: "
1266 "DRQ=1 with device error, "
1267 "dev_stat 0x%X", status);
1268 qc->err_mask |= AC_ERR_HSM;
1269 ap->hsm_task_state = HSM_ST_ERR;
1273 atapi_pio_bytes(qc);
1275 if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
1276 /* bad ireason reported by device */
1280 /* ATA PIO protocol */
1281 if (unlikely((status & ATA_DRQ) == 0)) {
1282 /* handle BSY=0, DRQ=0 as error */
1283 if (likely(status & (ATA_ERR | ATA_DF))) {
1284 /* device stops HSM for abort/error */
1285 qc->err_mask |= AC_ERR_DEV;
1287 /* If diagnostic failed and this is
1288 * IDENTIFY, it's likely a phantom
1289 * device. Mark hint.
1291 if (qc->dev->horkage &
1292 ATA_HORKAGE_DIAGNOSTIC)
1296 /* HSM violation. Let EH handle this.
1297 * Phantom devices also trigger this
1298 * condition. Mark hint.
1300 ata_ehi_push_desc(ehi, "ST-ATA: "
1301 "DRQ=1 with device error, "
1302 "dev_stat 0x%X", status);
1303 qc->err_mask |= AC_ERR_HSM |
1307 ap->hsm_task_state = HSM_ST_ERR;
1311 /* For PIO reads, some devices may ask for
1312 * data transfer (DRQ=1) alone with ERR=1.
1313 * We respect DRQ here and transfer one
1314 * block of junk data before changing the
1315 * hsm_task_state to HSM_ST_ERR.
1317 * For PIO writes, ERR=1 DRQ=1 doesn't make
1318 * sense since the data block has been
1319 * transferred to the device.
1321 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1322 /* data might be corrputed */
1323 qc->err_mask |= AC_ERR_DEV;
1325 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
1326 ata_pio_sectors(qc);
1327 status = ata_wait_idle(ap);
1330 if (status & (ATA_BUSY | ATA_DRQ)) {
1331 ata_ehi_push_desc(ehi, "ST-ATA: "
1332 "BUSY|DRQ persists on ERR|DF, "
1333 "dev_stat 0x%X", status);
1334 qc->err_mask |= AC_ERR_HSM;
1337 /* ata_pio_sectors() might change the
1338 * state to HSM_ST_LAST. so, the state
1339 * is changed after ata_pio_sectors().
1341 ap->hsm_task_state = HSM_ST_ERR;
1345 ata_pio_sectors(qc);
1347 if (ap->hsm_task_state == HSM_ST_LAST &&
1348 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
1350 status = ata_wait_idle(ap);
1359 if (unlikely(!ata_ok(status))) {
1360 qc->err_mask |= __ac_err_mask(status);
1361 ap->hsm_task_state = HSM_ST_ERR;
1365 /* no more data to transfer */
1366 DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
1367 ap->print_id, qc->dev->devno, status);
1369 WARN_ON(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM));
1371 ap->hsm_task_state = HSM_ST_IDLE;
1373 /* complete taskfile transaction */
1374 ata_hsm_qc_complete(qc, in_wq);
1380 ap->hsm_task_state = HSM_ST_IDLE;
1382 /* complete taskfile transaction */
1383 ata_hsm_qc_complete(qc, in_wq);
1395 void ata_pio_task(struct work_struct *work)
1397 struct ata_port *ap =
1398 container_of(work, struct ata_port, port_task.work);
1399 struct ata_queued_cmd *qc = ap->port_task_data;
1404 WARN_ON(ap->hsm_task_state == HSM_ST_IDLE);
1407 * This is purely heuristic. This is a fast path.
1408 * Sometimes when we enter, BSY will be cleared in
1409 * a chk-status or two. If not, the drive is probably seeking
1410 * or something. Snooze for a couple msecs, then
1411 * chk-status again. If still busy, queue delayed work.
1413 status = ata_sff_busy_wait(ap, ATA_BUSY, 5);
1414 if (status & ATA_BUSY) {
1416 status = ata_sff_busy_wait(ap, ATA_BUSY, 10);
1417 if (status & ATA_BUSY) {
1418 ata_pio_queue_task(ap, qc, ATA_SHORT_PAUSE);
1424 poll_next = ata_sff_hsm_move(ap, qc, status, 1);
1426 /* another command or interrupt handler
1427 * may be running at this point.
1434 * ata_sff_qc_issue - issue taskfile to device in proto-dependent manner
1435 * @qc: command to issue to device
1437 * Using various libata functions and hooks, this function
1438 * starts an ATA command. ATA commands are grouped into
1439 * classes called "protocols", and issuing each type of protocol
1440 * is slightly different.
1442 * May be used as the qc_issue() entry in ata_port_operations.
1445 * spin_lock_irqsave(host lock)
1448 * Zero on success, AC_ERR_* mask on failure
1450 unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
1452 struct ata_port *ap = qc->ap;
1454 /* Use polling pio if the LLD doesn't handle
1455 * interrupt driven pio and atapi CDB interrupt.
1457 if (ap->flags & ATA_FLAG_PIO_POLLING) {
1458 switch (qc->tf.protocol) {
1460 case ATA_PROT_NODATA:
1461 case ATAPI_PROT_PIO:
1462 case ATAPI_PROT_NODATA:
1463 qc->tf.flags |= ATA_TFLAG_POLLING;
1465 case ATAPI_PROT_DMA:
1466 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
1467 /* see ata_dma_blacklisted() */
1475 /* select the device */
1476 ata_dev_select(ap, qc->dev->devno, 1, 0);
1478 /* start the command */
1479 switch (qc->tf.protocol) {
1480 case ATA_PROT_NODATA:
1481 if (qc->tf.flags & ATA_TFLAG_POLLING)
1482 ata_qc_set_polling(qc);
1484 ata_tf_to_host(ap, &qc->tf);
1485 ap->hsm_task_state = HSM_ST_LAST;
1487 if (qc->tf.flags & ATA_TFLAG_POLLING)
1488 ata_pio_queue_task(ap, qc, 0);
1493 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
1495 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
1496 ap->ops->bmdma_setup(qc); /* set up bmdma */
1497 ap->ops->bmdma_start(qc); /* initiate bmdma */
1498 ap->hsm_task_state = HSM_ST_LAST;
1502 if (qc->tf.flags & ATA_TFLAG_POLLING)
1503 ata_qc_set_polling(qc);
1505 ata_tf_to_host(ap, &qc->tf);
1507 if (qc->tf.flags & ATA_TFLAG_WRITE) {
1508 /* PIO data out protocol */
1509 ap->hsm_task_state = HSM_ST_FIRST;
1510 ata_pio_queue_task(ap, qc, 0);
1512 /* always send first data block using
1513 * the ata_pio_task() codepath.
1516 /* PIO data in protocol */
1517 ap->hsm_task_state = HSM_ST;
1519 if (qc->tf.flags & ATA_TFLAG_POLLING)
1520 ata_pio_queue_task(ap, qc, 0);
1522 /* if polling, ata_pio_task() handles the rest.
1523 * otherwise, interrupt handler takes over from here.
1529 case ATAPI_PROT_PIO:
1530 case ATAPI_PROT_NODATA:
1531 if (qc->tf.flags & ATA_TFLAG_POLLING)
1532 ata_qc_set_polling(qc);
1534 ata_tf_to_host(ap, &qc->tf);
1536 ap->hsm_task_state = HSM_ST_FIRST;
1538 /* send cdb by polling if no cdb interrupt */
1539 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
1540 (qc->tf.flags & ATA_TFLAG_POLLING))
1541 ata_pio_queue_task(ap, qc, 0);
1544 case ATAPI_PROT_DMA:
1545 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
1547 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
1548 ap->ops->bmdma_setup(qc); /* set up bmdma */
1549 ap->hsm_task_state = HSM_ST_FIRST;
1551 /* send cdb by polling if no cdb interrupt */
1552 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1553 ata_pio_queue_task(ap, qc, 0);
1558 return AC_ERR_SYSTEM;
1565 * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read
1566 * @qc: qc to fill result TF for
1568 * @qc is finished and result TF needs to be filled. Fill it
1569 * using ->sff_tf_read.
1572 * spin_lock_irqsave(host lock)
1575 * true indicating that result TF is successfully filled.
1577 bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc)
1579 qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf);
1584 * ata_sff_host_intr - Handle host interrupt for given (port, task)
1585 * @ap: Port on which interrupt arrived (possibly...)
1586 * @qc: Taskfile currently active in engine
1588 * Handle host interrupt for given queued command. Currently,
1589 * only DMA interrupts are handled. All other commands are
1590 * handled via polling with interrupts disabled (nIEN bit).
1593 * spin_lock_irqsave(host lock)
1596 * One if interrupt was handled, zero if not (shared irq).
1598 inline unsigned int ata_sff_host_intr(struct ata_port *ap,
1599 struct ata_queued_cmd *qc)
1601 struct ata_eh_info *ehi = &ap->link.eh_info;
1602 u8 status, host_stat = 0;
1604 VPRINTK("ata%u: protocol %d task_state %d\n",
1605 ap->print_id, qc->tf.protocol, ap->hsm_task_state);
1607 /* Check whether we are expecting interrupt in this state */
1608 switch (ap->hsm_task_state) {
1610 /* Some pre-ATAPI-4 devices assert INTRQ
1611 * at this state when ready to receive CDB.
1614 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
1615 * The flag was turned on only for atapi devices. No
1616 * need to check ata_is_atapi(qc->tf.protocol) again.
1618 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1622 if (qc->tf.protocol == ATA_PROT_DMA ||
1623 qc->tf.protocol == ATAPI_PROT_DMA) {
1624 /* check status of DMA engine */
1625 host_stat = ap->ops->bmdma_status(ap);
1626 VPRINTK("ata%u: host_stat 0x%X\n",
1627 ap->print_id, host_stat);
1629 /* if it's not our irq... */
1630 if (!(host_stat & ATA_DMA_INTR))
1633 /* before we do anything else, clear DMA-Start bit */
1634 ap->ops->bmdma_stop(qc);
1636 if (unlikely(host_stat & ATA_DMA_ERR)) {
1637 /* error when transfering data to/from memory */
1638 qc->err_mask |= AC_ERR_HOST_BUS;
1639 ap->hsm_task_state = HSM_ST_ERR;
1650 /* check main status, clearing INTRQ if needed */
1651 status = ata_sff_irq_status(ap);
1652 if (status & ATA_BUSY)
1655 /* ack bmdma irq events */
1656 ap->ops->sff_irq_clear(ap);
1658 ata_sff_hsm_move(ap, qc, status, 0);
1660 if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA ||
1661 qc->tf.protocol == ATAPI_PROT_DMA))
1662 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
1664 return 1; /* irq handled */
1667 ap->stats.idle_irq++;
1670 if ((ap->stats.idle_irq % 1000) == 0) {
1671 ap->ops->sff_check_status(ap);
1672 ap->ops->sff_irq_clear(ap);
1673 ata_port_printk(ap, KERN_WARNING, "irq trap\n");
1677 return 0; /* irq not handled */
1681 * ata_sff_interrupt - Default ATA host interrupt handler
1682 * @irq: irq line (unused)
1683 * @dev_instance: pointer to our ata_host information structure
1685 * Default interrupt handler for PCI IDE devices. Calls
1686 * ata_sff_host_intr() for each port that is not disabled.
1689 * Obtains host lock during operation.
1692 * IRQ_NONE or IRQ_HANDLED.
1694 irqreturn_t ata_sff_interrupt(int irq, void *dev_instance)
1696 struct ata_host *host = dev_instance;
1698 unsigned int handled = 0;
1699 unsigned long flags;
1701 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
1702 spin_lock_irqsave(&host->lock, flags);
1704 for (i = 0; i < host->n_ports; i++) {
1705 struct ata_port *ap;
1707 ap = host->ports[i];
1709 !(ap->flags & ATA_FLAG_DISABLED)) {
1710 struct ata_queued_cmd *qc;
1712 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1713 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) &&
1714 (qc->flags & ATA_QCFLAG_ACTIVE))
1715 handled |= ata_sff_host_intr(ap, qc);
1719 spin_unlock_irqrestore(&host->lock, flags);
1721 return IRQ_RETVAL(handled);
1725 * ata_sff_freeze - Freeze SFF controller port
1726 * @ap: port to freeze
1728 * Freeze BMDMA controller port.
1731 * Inherited from caller.
1733 void ata_sff_freeze(struct ata_port *ap)
1735 struct ata_ioports *ioaddr = &ap->ioaddr;
1737 ap->ctl |= ATA_NIEN;
1738 ap->last_ctl = ap->ctl;
1740 if (ioaddr->ctl_addr)
1741 iowrite8(ap->ctl, ioaddr->ctl_addr);
1743 /* Under certain circumstances, some controllers raise IRQ on
1744 * ATA_NIEN manipulation. Also, many controllers fail to mask
1745 * previously pending IRQ on ATA_NIEN assertion. Clear it.
1747 ap->ops->sff_check_status(ap);
1749 ap->ops->sff_irq_clear(ap);
1753 * ata_sff_thaw - Thaw SFF controller port
1756 * Thaw SFF controller port.
1759 * Inherited from caller.
1761 void ata_sff_thaw(struct ata_port *ap)
1763 /* clear & re-enable interrupts */
1764 ap->ops->sff_check_status(ap);
1765 ap->ops->sff_irq_clear(ap);
1766 ap->ops->sff_irq_on(ap);
1770 * ata_sff_prereset - prepare SFF link for reset
1771 * @link: SFF link to be reset
1772 * @deadline: deadline jiffies for the operation
1774 * SFF link @link is about to be reset. Initialize it. It first
1775 * calls ata_std_prereset() and wait for !BSY if the port is
1779 * Kernel thread context (may sleep)
1782 * 0 on success, -errno otherwise.
1784 int ata_sff_prereset(struct ata_link *link, unsigned long deadline)
1786 struct ata_eh_context *ehc = &link->eh_context;
1789 rc = ata_std_prereset(link, deadline);
1793 /* if we're about to do hardreset, nothing more to do */
1794 if (ehc->i.action & ATA_EH_HARDRESET)
1797 /* wait for !BSY if we don't know that no device is attached */
1798 if (!ata_link_offline(link)) {
1799 rc = ata_sff_wait_ready(link, deadline);
1800 if (rc && rc != -ENODEV) {
1801 ata_link_printk(link, KERN_WARNING, "device not ready "
1802 "(errno=%d), forcing hardreset\n", rc);
1803 ehc->i.action |= ATA_EH_HARDRESET;
1811 * ata_devchk - PATA device presence detection
1812 * @ap: ATA channel to examine
1813 * @device: Device to examine (starting at zero)
1815 * This technique was originally described in
1816 * Hale Landis's ATADRVR (www.ata-atapi.com), and
1817 * later found its way into the ATA/ATAPI spec.
1819 * Write a pattern to the ATA shadow registers,
1820 * and if a device is present, it will respond by
1821 * correctly storing and echoing back the
1822 * ATA shadow register contents.
1827 static unsigned int ata_devchk(struct ata_port *ap, unsigned int device)
1829 struct ata_ioports *ioaddr = &ap->ioaddr;
1832 ap->ops->sff_dev_select(ap, device);
1834 iowrite8(0x55, ioaddr->nsect_addr);
1835 iowrite8(0xaa, ioaddr->lbal_addr);
1837 iowrite8(0xaa, ioaddr->nsect_addr);
1838 iowrite8(0x55, ioaddr->lbal_addr);
1840 iowrite8(0x55, ioaddr->nsect_addr);
1841 iowrite8(0xaa, ioaddr->lbal_addr);
1843 nsect = ioread8(ioaddr->nsect_addr);
1844 lbal = ioread8(ioaddr->lbal_addr);
1846 if ((nsect == 0x55) && (lbal == 0xaa))
1847 return 1; /* we found a device */
1849 return 0; /* nothing found */
1853 * ata_sff_dev_classify - Parse returned ATA device signature
1854 * @dev: ATA device to classify (starting at zero)
1855 * @present: device seems present
1856 * @r_err: Value of error register on completion
1858 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
1859 * an ATA/ATAPI-defined set of values is placed in the ATA
1860 * shadow registers, indicating the results of device detection
1863 * Select the ATA device, and read the values from the ATA shadow
1864 * registers. Then parse according to the Error register value,
1865 * and the spec-defined values examined by ata_dev_classify().
1871 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1873 unsigned int ata_sff_dev_classify(struct ata_device *dev, int present,
1876 struct ata_port *ap = dev->link->ap;
1877 struct ata_taskfile tf;
1881 ap->ops->sff_dev_select(ap, dev->devno);
1883 memset(&tf, 0, sizeof(tf));
1885 ap->ops->sff_tf_read(ap, &tf);
1890 /* see if device passed diags: continue and warn later */
1892 /* diagnostic fail : do nothing _YET_ */
1893 dev->horkage |= ATA_HORKAGE_DIAGNOSTIC;
1896 else if ((dev->devno == 0) && (err == 0x81))
1899 return ATA_DEV_NONE;
1901 /* determine if device is ATA or ATAPI */
1902 class = ata_dev_classify(&tf);
1904 if (class == ATA_DEV_UNKNOWN) {
1905 /* If the device failed diagnostic, it's likely to
1906 * have reported incorrect device signature too.
1907 * Assume ATA device if the device seems present but
1908 * device signature is invalid with diagnostic
1911 if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC))
1912 class = ATA_DEV_ATA;
1914 class = ATA_DEV_NONE;
1915 } else if ((class == ATA_DEV_ATA) &&
1916 (ap->ops->sff_check_status(ap) == 0))
1917 class = ATA_DEV_NONE;
1923 * ata_sff_wait_after_reset - wait for devices to become ready after reset
1924 * @link: SFF link which is just reset
1925 * @devmask: mask of present devices
1926 * @deadline: deadline jiffies for the operation
1928 * Wait devices attached to SFF @link to become ready after
1929 * reset. It contains preceding 150ms wait to avoid accessing TF
1930 * status register too early.
1933 * Kernel thread context (may sleep).
1936 * 0 on success, -ENODEV if some or all of devices in @devmask
1937 * don't seem to exist. -errno on other errors.
1939 int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask,
1940 unsigned long deadline)
1942 struct ata_port *ap = link->ap;
1943 struct ata_ioports *ioaddr = &ap->ioaddr;
1944 unsigned int dev0 = devmask & (1 << 0);
1945 unsigned int dev1 = devmask & (1 << 1);
1948 msleep(ATA_WAIT_AFTER_RESET);
1950 /* always check readiness of the master device */
1951 rc = ata_sff_wait_ready(link, deadline);
1952 /* -ENODEV means the odd clown forgot the D7 pulldown resistor
1953 * and TF status is 0xff, bail out on it too.
1958 /* if device 1 was found in ata_devchk, wait for register
1959 * access briefly, then wait for BSY to clear.
1964 ap->ops->sff_dev_select(ap, 1);
1966 /* Wait for register access. Some ATAPI devices fail
1967 * to set nsect/lbal after reset, so don't waste too
1968 * much time on it. We're gonna wait for !BSY anyway.
1970 for (i = 0; i < 2; i++) {
1973 nsect = ioread8(ioaddr->nsect_addr);
1974 lbal = ioread8(ioaddr->lbal_addr);
1975 if ((nsect == 1) && (lbal == 1))
1977 msleep(50); /* give drive a breather */
1980 rc = ata_sff_wait_ready(link, deadline);
1988 /* is all this really necessary? */
1989 ap->ops->sff_dev_select(ap, 0);
1991 ap->ops->sff_dev_select(ap, 1);
1993 ap->ops->sff_dev_select(ap, 0);
1998 static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
1999 unsigned long deadline)
2001 struct ata_ioports *ioaddr = &ap->ioaddr;
2003 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
2005 /* software reset. causes dev0 to be selected */
2006 iowrite8(ap->ctl, ioaddr->ctl_addr);
2007 udelay(20); /* FIXME: flush */
2008 iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
2009 udelay(20); /* FIXME: flush */
2010 iowrite8(ap->ctl, ioaddr->ctl_addr);
2012 /* wait the port to become ready */
2013 return ata_sff_wait_after_reset(&ap->link, devmask, deadline);
2017 * ata_sff_softreset - reset host port via ATA SRST
2018 * @link: ATA link to reset
2019 * @classes: resulting classes of attached devices
2020 * @deadline: deadline jiffies for the operation
2022 * Reset host port using ATA SRST.
2025 * Kernel thread context (may sleep)
2028 * 0 on success, -errno otherwise.
2030 int ata_sff_softreset(struct ata_link *link, unsigned int *classes,
2031 unsigned long deadline)
2033 struct ata_port *ap = link->ap;
2034 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2035 unsigned int devmask = 0;
2041 /* determine if device 0/1 are present */
2042 if (ata_devchk(ap, 0))
2043 devmask |= (1 << 0);
2044 if (slave_possible && ata_devchk(ap, 1))
2045 devmask |= (1 << 1);
2047 /* select device 0 again */
2048 ap->ops->sff_dev_select(ap, 0);
2050 /* issue bus reset */
2051 DPRINTK("about to softreset, devmask=%x\n", devmask);
2052 rc = ata_bus_softreset(ap, devmask, deadline);
2053 /* if link is occupied, -ENODEV too is an error */
2054 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
2055 ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc);
2059 /* determine by signature whether we have ATA or ATAPI devices */
2060 classes[0] = ata_sff_dev_classify(&link->device[0],
2061 devmask & (1 << 0), &err);
2062 if (slave_possible && err != 0x81)
2063 classes[1] = ata_sff_dev_classify(&link->device[1],
2064 devmask & (1 << 1), &err);
2066 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
2071 * sata_sff_hardreset - reset host port via SATA phy reset
2072 * @link: link to reset
2073 * @class: resulting class of attached device
2074 * @deadline: deadline jiffies for the operation
2076 * SATA phy-reset host port using DET bits of SControl register,
2077 * wait for !BSY and classify the attached device.
2080 * Kernel thread context (may sleep)
2083 * 0 on success, -errno otherwise.
2085 int sata_sff_hardreset(struct ata_link *link, unsigned int *class,
2086 unsigned long deadline)
2088 struct ata_eh_context *ehc = &link->eh_context;
2089 const unsigned long *timing = sata_ehc_deb_timing(ehc);
2093 rc = sata_link_hardreset(link, timing, deadline, &online,
2094 ata_sff_check_ready);
2096 *class = ata_sff_dev_classify(link->device, 1, NULL);
2098 DPRINTK("EXIT, class=%u\n", *class);
2103 * ata_sff_postreset - SFF postreset callback
2104 * @link: the target SFF ata_link
2105 * @classes: classes of attached devices
2107 * This function is invoked after a successful reset. It first
2108 * calls ata_std_postreset() and performs SFF specific postreset
2112 * Kernel thread context (may sleep)
2114 void ata_sff_postreset(struct ata_link *link, unsigned int *classes)
2116 struct ata_port *ap = link->ap;
2118 ata_std_postreset(link, classes);
2120 /* is double-select really necessary? */
2121 if (classes[0] != ATA_DEV_NONE)
2122 ap->ops->sff_dev_select(ap, 1);
2123 if (classes[1] != ATA_DEV_NONE)
2124 ap->ops->sff_dev_select(ap, 0);
2126 /* bail out if no device is present */
2127 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
2128 DPRINTK("EXIT, no device\n");
2132 /* set up device control */
2133 if (ap->ioaddr.ctl_addr)
2134 iowrite8(ap->ctl, ap->ioaddr.ctl_addr);
2138 * ata_sff_error_handler - Stock error handler for BMDMA controller
2139 * @ap: port to handle error for
2141 * Stock error handler for SFF controller. It can handle both
2142 * PATA and SATA controllers. Many controllers should be able to
2143 * use this EH as-is or with some added handling before and
2147 * Kernel thread context (may sleep)
2149 void ata_sff_error_handler(struct ata_port *ap)
2151 ata_reset_fn_t softreset = ap->ops->softreset;
2152 ata_reset_fn_t hardreset = ap->ops->hardreset;
2153 struct ata_queued_cmd *qc;
2154 unsigned long flags;
2157 qc = __ata_qc_from_tag(ap, ap->link.active_tag);
2158 if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
2161 /* reset PIO HSM and stop DMA engine */
2162 spin_lock_irqsave(ap->lock, flags);
2164 ap->hsm_task_state = HSM_ST_IDLE;
2166 if (ap->ioaddr.bmdma_addr &&
2167 qc && (qc->tf.protocol == ATA_PROT_DMA ||
2168 qc->tf.protocol == ATAPI_PROT_DMA)) {
2171 host_stat = ap->ops->bmdma_status(ap);
2173 /* BMDMA controllers indicate host bus error by
2174 * setting DMA_ERR bit and timing out. As it wasn't
2175 * really a timeout event, adjust error mask and
2176 * cancel frozen state.
2178 if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) {
2179 qc->err_mask = AC_ERR_HOST_BUS;
2183 ap->ops->bmdma_stop(qc);
2186 ata_sff_sync(ap); /* FIXME: We don't need this */
2187 ap->ops->sff_check_status(ap);
2188 ap->ops->sff_irq_clear(ap);
2190 spin_unlock_irqrestore(ap->lock, flags);
2193 ata_eh_thaw_port(ap);
2195 /* PIO and DMA engines have been stopped, perform recovery */
2197 /* Ignore ata_sff_softreset if ctl isn't accessible and
2198 * built-in hardresets if SCR access isn't available.
2200 if (softreset == ata_sff_softreset && !ap->ioaddr.ctl_addr)
2202 if (ata_is_builtin_hardreset(hardreset) && !sata_scr_valid(&ap->link))
2205 ata_do_eh(ap, ap->ops->prereset, softreset, hardreset,
2206 ap->ops->postreset);
2210 * ata_sff_post_internal_cmd - Stock post_internal_cmd for SFF controller
2211 * @qc: internal command to clean up
2214 * Kernel thread context (may sleep)
2216 void ata_sff_post_internal_cmd(struct ata_queued_cmd *qc)
2218 struct ata_port *ap = qc->ap;
2219 unsigned long flags;
2221 spin_lock_irqsave(ap->lock, flags);
2223 ap->hsm_task_state = HSM_ST_IDLE;
2225 if (ap->ioaddr.bmdma_addr)
2228 spin_unlock_irqrestore(ap->lock, flags);
2232 * ata_sff_port_start - Set port up for dma.
2233 * @ap: Port to initialize
2235 * Called just after data structures for each port are
2236 * initialized. Allocates space for PRD table if the device
2237 * is DMA capable SFF.
2239 * May be used as the port_start() entry in ata_port_operations.
2242 * Inherited from caller.
2244 int ata_sff_port_start(struct ata_port *ap)
2246 if (ap->ioaddr.bmdma_addr)
2247 return ata_port_start(ap);
2252 * ata_sff_std_ports - initialize ioaddr with standard port offsets.
2253 * @ioaddr: IO address structure to be initialized
2255 * Utility function which initializes data_addr, error_addr,
2256 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
2257 * device_addr, status_addr, and command_addr to standard offsets
2258 * relative to cmd_addr.
2260 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
2262 void ata_sff_std_ports(struct ata_ioports *ioaddr)
2264 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
2265 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
2266 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
2267 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
2268 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
2269 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
2270 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
2271 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
2272 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
2273 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
2276 unsigned long ata_bmdma_mode_filter(struct ata_device *adev,
2277 unsigned long xfer_mask)
2279 /* Filter out DMA modes if the device has been configured by
2280 the BIOS as PIO only */
2282 if (adev->link->ap->ioaddr.bmdma_addr == NULL)
2283 xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
2288 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
2289 * @qc: Info associated with this ATA transaction.
2292 * spin_lock_irqsave(host lock)
2294 void ata_bmdma_setup(struct ata_queued_cmd *qc)
2296 struct ata_port *ap = qc->ap;
2297 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
2300 /* load PRD table addr. */
2301 mb(); /* make sure PRD table writes are visible to controller */
2302 iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
2304 /* specify data direction, triple-check start bit is clear */
2305 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2306 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
2308 dmactl |= ATA_DMA_WR;
2309 iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2311 /* issue r/w command */
2312 ap->ops->sff_exec_command(ap, &qc->tf);
2316 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
2317 * @qc: Info associated with this ATA transaction.
2320 * spin_lock_irqsave(host lock)
2322 void ata_bmdma_start(struct ata_queued_cmd *qc)
2324 struct ata_port *ap = qc->ap;
2327 /* start host DMA transaction */
2328 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2329 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2331 /* Strictly, one may wish to issue an ioread8() here, to
2332 * flush the mmio write. However, control also passes
2333 * to the hardware at this point, and it will interrupt
2334 * us when we are to resume control. So, in effect,
2335 * we don't care when the mmio write flushes.
2336 * Further, a read of the DMA status register _immediately_
2337 * following the write may not be what certain flaky hardware
2338 * is expected, so I think it is best to not add a readb()
2339 * without first all the MMIO ATA cards/mobos.
2340 * Or maybe I'm just being paranoid.
2342 * FIXME: The posting of this write means I/O starts are
2343 * unneccessarily delayed for MMIO
2348 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
2349 * @qc: Command we are ending DMA for
2351 * Clears the ATA_DMA_START flag in the dma control register
2353 * May be used as the bmdma_stop() entry in ata_port_operations.
2356 * spin_lock_irqsave(host lock)
2358 void ata_bmdma_stop(struct ata_queued_cmd *qc)
2360 struct ata_port *ap = qc->ap;
2361 void __iomem *mmio = ap->ioaddr.bmdma_addr;
2363 /* clear start/stop bit */
2364 iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
2365 mmio + ATA_DMA_CMD);
2367 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
2368 ata_sff_dma_pause(ap);
2372 * ata_bmdma_status - Read PCI IDE BMDMA status
2373 * @ap: Port associated with this ATA transaction.
2375 * Read and return BMDMA status register.
2377 * May be used as the bmdma_status() entry in ata_port_operations.
2380 * spin_lock_irqsave(host lock)
2382 u8 ata_bmdma_status(struct ata_port *ap)
2384 return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
2388 * ata_bus_reset - reset host port and associated ATA channel
2389 * @ap: port to reset
2391 * This is typically the first time we actually start issuing
2392 * commands to the ATA channel. We wait for BSY to clear, then
2393 * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its
2394 * result. Determine what devices, if any, are on the channel
2395 * by looking at the device 0/1 error register. Look at the signature
2396 * stored in each device's taskfile registers, to determine if
2397 * the device is ATA or ATAPI.
2400 * PCI/etc. bus probe sem.
2401 * Obtains host lock.
2404 * Sets ATA_FLAG_DISABLED if bus reset fails.
2407 * This function is only for drivers which still use old EH and
2408 * will be removed soon.
2410 void ata_bus_reset(struct ata_port *ap)
2412 struct ata_device *device = ap->link.device;
2413 struct ata_ioports *ioaddr = &ap->ioaddr;
2414 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2416 unsigned int dev0, dev1 = 0, devmask = 0;
2419 DPRINTK("ENTER, host %u, port %u\n", ap->print_id, ap->port_no);
2421 /* determine if device 0/1 are present */
2422 if (ap->flags & ATA_FLAG_SATA_RESET)
2425 dev0 = ata_devchk(ap, 0);
2427 dev1 = ata_devchk(ap, 1);
2431 devmask |= (1 << 0);
2433 devmask |= (1 << 1);
2435 /* select device 0 again */
2436 ap->ops->sff_dev_select(ap, 0);
2438 /* issue bus reset */
2439 if (ap->flags & ATA_FLAG_SRST) {
2440 rc = ata_bus_softreset(ap, devmask,
2441 ata_deadline(jiffies, 40000));
2442 if (rc && rc != -ENODEV)
2447 * determine by signature whether we have ATA or ATAPI devices
2449 device[0].class = ata_sff_dev_classify(&device[0], dev0, &err);
2450 if ((slave_possible) && (err != 0x81))
2451 device[1].class = ata_sff_dev_classify(&device[1], dev1, &err);
2453 /* is double-select really necessary? */
2454 if (device[1].class != ATA_DEV_NONE)
2455 ap->ops->sff_dev_select(ap, 1);
2456 if (device[0].class != ATA_DEV_NONE)
2457 ap->ops->sff_dev_select(ap, 0);
2459 /* if no devices were detected, disable this port */
2460 if ((device[0].class == ATA_DEV_NONE) &&
2461 (device[1].class == ATA_DEV_NONE))
2464 if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) {
2465 /* set up device control for ATA_FLAG_SATA_RESET */
2466 iowrite8(ap->ctl, ioaddr->ctl_addr);
2473 ata_port_printk(ap, KERN_ERR, "disabling port\n");
2474 ata_port_disable(ap);
2482 * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex
2485 * Some PCI ATA devices report simplex mode but in fact can be told to
2486 * enter non simplex mode. This implements the necessary logic to
2487 * perform the task on such devices. Calling it on other devices will
2488 * have -undefined- behaviour.
2490 int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev)
2492 unsigned long bmdma = pci_resource_start(pdev, 4);
2498 simplex = inb(bmdma + 0x02);
2499 outb(simplex & 0x60, bmdma + 0x02);
2500 simplex = inb(bmdma + 0x02);
2507 * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host
2508 * @host: target ATA host
2510 * Acquire PCI BMDMA resources and initialize @host accordingly.
2513 * Inherited from calling layer (may sleep).
2516 * 0 on success, -errno otherwise.
2518 int ata_pci_bmdma_init(struct ata_host *host)
2520 struct device *gdev = host->dev;
2521 struct pci_dev *pdev = to_pci_dev(gdev);
2524 /* No BAR4 allocation: No DMA */
2525 if (pci_resource_start(pdev, 4) == 0)
2528 /* TODO: If we get no DMA mask we should fall back to PIO */
2529 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
2532 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
2536 /* request and iomap DMA region */
2537 rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev));
2539 dev_printk(KERN_ERR, gdev, "failed to request/iomap BAR4\n");
2542 host->iomap = pcim_iomap_table(pdev);
2544 for (i = 0; i < 2; i++) {
2545 struct ata_port *ap = host->ports[i];
2546 void __iomem *bmdma = host->iomap[4] + 8 * i;
2548 if (ata_port_is_dummy(ap))
2551 ap->ioaddr.bmdma_addr = bmdma;
2552 if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) &&
2553 (ioread8(bmdma + 2) & 0x80))
2554 host->flags |= ATA_HOST_SIMPLEX;
2556 ata_port_desc(ap, "bmdma 0x%llx",
2557 (unsigned long long)pci_resource_start(pdev, 4) + 8 * i);
2563 static int ata_resources_present(struct pci_dev *pdev, int port)
2567 /* Check the PCI resources for this channel are enabled */
2569 for (i = 0; i < 2; i ++) {
2570 if (pci_resource_start(pdev, port + i) == 0 ||
2571 pci_resource_len(pdev, port + i) == 0)
2578 * ata_pci_sff_init_host - acquire native PCI ATA resources and init host
2579 * @host: target ATA host
2581 * Acquire native PCI ATA resources for @host and initialize the
2582 * first two ports of @host accordingly. Ports marked dummy are
2583 * skipped and allocation failure makes the port dummy.
2585 * Note that native PCI resources are valid even for legacy hosts
2586 * as we fix up pdev resources array early in boot, so this
2587 * function can be used for both native and legacy SFF hosts.
2590 * Inherited from calling layer (may sleep).
2593 * 0 if at least one port is initialized, -ENODEV if no port is
2596 int ata_pci_sff_init_host(struct ata_host *host)
2598 struct device *gdev = host->dev;
2599 struct pci_dev *pdev = to_pci_dev(gdev);
2600 unsigned int mask = 0;
2603 /* request, iomap BARs and init port addresses accordingly */
2604 for (i = 0; i < 2; i++) {
2605 struct ata_port *ap = host->ports[i];
2607 void __iomem * const *iomap;
2609 if (ata_port_is_dummy(ap))
2612 /* Discard disabled ports. Some controllers show
2613 * their unused channels this way. Disabled ports are
2616 if (!ata_resources_present(pdev, i)) {
2617 ap->ops = &ata_dummy_port_ops;
2621 rc = pcim_iomap_regions(pdev, 0x3 << base,
2622 dev_driver_string(gdev));
2624 dev_printk(KERN_WARNING, gdev,
2625 "failed to request/iomap BARs for port %d "
2626 "(errno=%d)\n", i, rc);
2628 pcim_pin_device(pdev);
2629 ap->ops = &ata_dummy_port_ops;
2632 host->iomap = iomap = pcim_iomap_table(pdev);
2634 ap->ioaddr.cmd_addr = iomap[base];
2635 ap->ioaddr.altstatus_addr =
2636 ap->ioaddr.ctl_addr = (void __iomem *)
2637 ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS);
2638 ata_sff_std_ports(&ap->ioaddr);
2640 ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
2641 (unsigned long long)pci_resource_start(pdev, base),
2642 (unsigned long long)pci_resource_start(pdev, base + 1));
2648 dev_printk(KERN_ERR, gdev, "no available native port\n");
2656 * ata_pci_sff_prepare_host - helper to prepare native PCI ATA host
2657 * @pdev: target PCI device
2658 * @ppi: array of port_info, must be enough for two ports
2659 * @r_host: out argument for the initialized ATA host
2661 * Helper to allocate ATA host for @pdev, acquire all native PCI
2662 * resources and initialize it accordingly in one go.
2665 * Inherited from calling layer (may sleep).
2668 * 0 on success, -errno otherwise.
2670 int ata_pci_sff_prepare_host(struct pci_dev *pdev,
2671 const struct ata_port_info * const * ppi,
2672 struct ata_host **r_host)
2674 struct ata_host *host;
2677 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
2680 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
2682 dev_printk(KERN_ERR, &pdev->dev,
2683 "failed to allocate ATA host\n");
2688 rc = ata_pci_sff_init_host(host);
2692 /* init DMA related stuff */
2693 rc = ata_pci_bmdma_init(host);
2697 devres_remove_group(&pdev->dev, NULL);
2702 /* This is necessary because PCI and iomap resources are
2703 * merged and releasing the top group won't release the
2704 * acquired resources if some of those have been acquired
2705 * before entering this function.
2707 pcim_iounmap_regions(pdev, 0xf);
2709 devres_release_group(&pdev->dev, NULL);
2714 * ata_pci_sff_activate_host - start SFF host, request IRQ and register it
2715 * @host: target SFF ATA host
2716 * @irq_handler: irq_handler used when requesting IRQ(s)
2717 * @sht: scsi_host_template to use when registering the host
2719 * This is the counterpart of ata_host_activate() for SFF ATA
2720 * hosts. This separate helper is necessary because SFF hosts
2721 * use two separate interrupts in legacy mode.
2724 * Inherited from calling layer (may sleep).
2727 * 0 on success, -errno otherwise.
2729 int ata_pci_sff_activate_host(struct ata_host *host,
2730 irq_handler_t irq_handler,
2731 struct scsi_host_template *sht)
2733 struct device *dev = host->dev;
2734 struct pci_dev *pdev = to_pci_dev(dev);
2735 const char *drv_name = dev_driver_string(host->dev);
2736 int legacy_mode = 0, rc;
2738 rc = ata_host_start(host);
2742 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
2745 /* TODO: What if one channel is in native mode ... */
2746 pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
2747 mask = (1 << 2) | (1 << 0);
2748 if ((tmp8 & mask) != mask)
2750 #if defined(CONFIG_NO_ATA_LEGACY)
2751 /* Some platforms with PCI limits cannot address compat
2752 port space. In that case we punt if their firmware has
2753 left a device in compatibility mode */
2755 printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n");
2761 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2764 if (!legacy_mode && pdev->irq) {
2765 rc = devm_request_irq(dev, pdev->irq, irq_handler,
2766 IRQF_SHARED, drv_name, host);
2770 ata_port_desc(host->ports[0], "irq %d", pdev->irq);
2771 ata_port_desc(host->ports[1], "irq %d", pdev->irq);
2772 } else if (legacy_mode) {
2773 if (!ata_port_is_dummy(host->ports[0])) {
2774 rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev),
2775 irq_handler, IRQF_SHARED,
2780 ata_port_desc(host->ports[0], "irq %d",
2781 ATA_PRIMARY_IRQ(pdev));
2784 if (!ata_port_is_dummy(host->ports[1])) {
2785 rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev),
2786 irq_handler, IRQF_SHARED,
2791 ata_port_desc(host->ports[1], "irq %d",
2792 ATA_SECONDARY_IRQ(pdev));
2796 rc = ata_host_register(host, sht);
2799 devres_remove_group(dev, NULL);
2801 devres_release_group(dev, NULL);
2807 * ata_pci_sff_init_one - Initialize/register PCI IDE host controller
2808 * @pdev: Controller to be initialized
2809 * @ppi: array of port_info, must be enough for two ports
2810 * @sht: scsi_host_template to use when registering the host
2811 * @host_priv: host private_data
2813 * This is a helper function which can be called from a driver's
2814 * xxx_init_one() probe function if the hardware uses traditional
2815 * IDE taskfile registers.
2817 * This function calls pci_enable_device(), reserves its register
2818 * regions, sets the dma mask, enables bus master mode, and calls
2822 * Nobody makes a single channel controller that appears solely as
2823 * the secondary legacy port on PCI.
2826 * Inherited from PCI layer (may sleep).
2829 * Zero on success, negative on errno-based value on error.
2831 int ata_pci_sff_init_one(struct pci_dev *pdev,
2832 const struct ata_port_info * const * ppi,
2833 struct scsi_host_template *sht, void *host_priv)
2835 struct device *dev = &pdev->dev;
2836 const struct ata_port_info *pi = NULL;
2837 struct ata_host *host = NULL;
2842 /* look up the first valid port_info */
2843 for (i = 0; i < 2 && ppi[i]; i++) {
2844 if (ppi[i]->port_ops != &ata_dummy_port_ops) {
2851 dev_printk(KERN_ERR, &pdev->dev,
2852 "no valid port_info specified\n");
2856 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2859 rc = pcim_enable_device(pdev);
2863 /* prepare and activate SFF host */
2864 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
2867 host->private_data = host_priv;
2869 pci_set_master(pdev);
2870 rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht);
2873 devres_remove_group(&pdev->dev, NULL);
2875 devres_release_group(&pdev->dev, NULL);
2880 #endif /* CONFIG_PCI */
2882 EXPORT_SYMBOL_GPL(ata_sff_port_ops);
2883 EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
2884 EXPORT_SYMBOL_GPL(ata_sff_qc_prep);
2885 EXPORT_SYMBOL_GPL(ata_sff_dumb_qc_prep);
2886 EXPORT_SYMBOL_GPL(ata_sff_dev_select);
2887 EXPORT_SYMBOL_GPL(ata_sff_check_status);
2888 EXPORT_SYMBOL_GPL(ata_sff_dma_pause);
2889 EXPORT_SYMBOL_GPL(ata_sff_pause);
2890 EXPORT_SYMBOL_GPL(ata_sff_busy_sleep);
2891 EXPORT_SYMBOL_GPL(ata_sff_wait_ready);
2892 EXPORT_SYMBOL_GPL(ata_sff_tf_load);
2893 EXPORT_SYMBOL_GPL(ata_sff_tf_read);
2894 EXPORT_SYMBOL_GPL(ata_sff_exec_command);
2895 EXPORT_SYMBOL_GPL(ata_sff_data_xfer);
2896 EXPORT_SYMBOL_GPL(ata_sff_data_xfer_noirq);
2897 EXPORT_SYMBOL_GPL(ata_sff_irq_on);
2898 EXPORT_SYMBOL_GPL(ata_sff_irq_clear);
2899 EXPORT_SYMBOL_GPL(ata_sff_hsm_move);
2900 EXPORT_SYMBOL_GPL(ata_sff_qc_issue);
2901 EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf);
2902 EXPORT_SYMBOL_GPL(ata_sff_host_intr);
2903 EXPORT_SYMBOL_GPL(ata_sff_interrupt);
2904 EXPORT_SYMBOL_GPL(ata_sff_freeze);
2905 EXPORT_SYMBOL_GPL(ata_sff_thaw);
2906 EXPORT_SYMBOL_GPL(ata_sff_prereset);
2907 EXPORT_SYMBOL_GPL(ata_sff_dev_classify);
2908 EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset);
2909 EXPORT_SYMBOL_GPL(ata_sff_softreset);
2910 EXPORT_SYMBOL_GPL(sata_sff_hardreset);
2911 EXPORT_SYMBOL_GPL(ata_sff_postreset);
2912 EXPORT_SYMBOL_GPL(ata_sff_error_handler);
2913 EXPORT_SYMBOL_GPL(ata_sff_post_internal_cmd);
2914 EXPORT_SYMBOL_GPL(ata_sff_port_start);
2915 EXPORT_SYMBOL_GPL(ata_sff_std_ports);
2916 EXPORT_SYMBOL_GPL(ata_bmdma_mode_filter);
2917 EXPORT_SYMBOL_GPL(ata_bmdma_setup);
2918 EXPORT_SYMBOL_GPL(ata_bmdma_start);
2919 EXPORT_SYMBOL_GPL(ata_bmdma_stop);
2920 EXPORT_SYMBOL_GPL(ata_bmdma_status);
2921 EXPORT_SYMBOL_GPL(ata_bus_reset);
2923 EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex);
2924 EXPORT_SYMBOL_GPL(ata_pci_bmdma_init);
2925 EXPORT_SYMBOL_GPL(ata_pci_sff_init_host);
2926 EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host);
2927 EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host);
2928 EXPORT_SYMBOL_GPL(ata_pci_sff_init_one);
2929 #endif /* CONFIG_PCI */