2 * mmconfig-shared.c - Low-level direct PCI config space access via
3 * MMCONFIG - common code between i386 and x86-64.
6 * - known chipset handling
7 * - ACPI decoding and validation
9 * Per-architecture code takes care of the mappings and accesses
13 #include <linux/pci.h>
14 #include <linux/init.h>
15 #include <linux/acpi.h>
16 #include <linux/sfi_acpi.h>
17 #include <linux/bitmap.h>
18 #include <linux/dmi.h>
19 #include <linux/sort.h>
21 #include <asm/pci_x86.h>
24 #define PREFIX "PCI: "
26 /* Indicate if the mmcfg resources have been placed into the resource table. */
27 static int __initdata pci_mmcfg_resources_inserted;
29 static __init int extend_mmcfg(int num)
31 struct acpi_mcfg_allocation *new;
32 int new_num = pci_mmcfg_config_num + num;
34 new = kzalloc(sizeof(pci_mmcfg_config[0]) * new_num, GFP_KERNEL);
38 if (pci_mmcfg_config) {
39 memcpy(new, pci_mmcfg_config,
40 sizeof(pci_mmcfg_config[0]) * new_num);
41 kfree(pci_mmcfg_config);
43 pci_mmcfg_config = new;
48 static __init void fill_one_mmcfg(u64 addr, int segment, int start, int end)
50 int i = pci_mmcfg_config_num;
52 pci_mmcfg_config_num++;
53 pci_mmcfg_config[i].address = addr;
54 pci_mmcfg_config[i].pci_segment = segment;
55 pci_mmcfg_config[i].start_bus_number = start;
56 pci_mmcfg_config[i].end_bus_number = end;
59 static const char __init *pci_mmcfg_e7520(void)
62 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
65 if (win == 0x0000 || win == 0xf000)
68 if (extend_mmcfg(1) == -1)
71 fill_one_mmcfg(win << 16, 0, 0, 255);
73 return "Intel Corporation E7520 Memory Controller Hub";
76 static const char __init *pci_mmcfg_intel_945(void)
78 u32 pciexbar, mask = 0, len = 0;
80 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
87 switch ((pciexbar >> 1) & 3) {
104 /* Errata #2, things break when not aligned on a 256Mb boundary */
105 /* Can only happen in 64M/128M mode */
107 if ((pciexbar & mask) & 0x0fffffffU)
110 /* Don't hit the APIC registers and their friends */
111 if ((pciexbar & mask) >= 0xf0000000U)
114 if (extend_mmcfg(1) == -1)
117 fill_one_mmcfg(pciexbar & mask, 0, 0, (len >> 20) - 1);
119 return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
122 static const char __init *pci_mmcfg_amd_fam10h(void)
124 u32 low, high, address;
127 unsigned segnbits = 0, busnbits;
129 if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
132 address = MSR_FAM10H_MMIO_CONF_BASE;
133 if (rdmsr_safe(address, &low, &high))
140 /* mmconfig is not enable */
141 if (!(msr & FAM10H_MMIO_CONF_ENABLE))
144 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
146 busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
147 FAM10H_MMIO_CONF_BUSRANGE_MASK;
150 * only handle bus 0 ?
157 segnbits = busnbits - 8;
161 if (extend_mmcfg(1 << segnbits) == -1)
164 for (i = 0; i < (1 << segnbits); i++)
165 fill_one_mmcfg(base + (1<<28) * i, i, 0, (1 << busnbits) - 1);
167 return "AMD Family 10h NB";
170 static bool __initdata mcp55_checked;
171 static const char __init *pci_mmcfg_nvidia_mcp55(void)
174 int mcp55_mmconf_found = 0;
176 static const u32 extcfg_regnum = 0x90;
177 static const u32 extcfg_regsize = 4;
178 static const u32 extcfg_enable_mask = 1<<31;
179 static const u32 extcfg_start_mask = 0xff<<16;
180 static const int extcfg_start_shift = 16;
181 static const u32 extcfg_size_mask = 0x3<<28;
182 static const int extcfg_size_shift = 28;
183 static const int extcfg_sizebus[] = {0x100, 0x80, 0x40, 0x20};
184 static const u32 extcfg_base_mask[] = {0x7ff8, 0x7ffc, 0x7ffe, 0x7fff};
185 static const int extcfg_base_lshift = 25;
188 * do check if amd fam10h already took over
190 if (!acpi_disabled || pci_mmcfg_config_num || mcp55_checked)
193 mcp55_checked = true;
194 for (bus = 0; bus < 256; bus++) {
198 int start, size_index, end;
200 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l);
202 device = (l >> 16) & 0xffff;
204 if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device)
207 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum,
208 extcfg_regsize, &extcfg);
210 if (!(extcfg & extcfg_enable_mask))
213 if (extend_mmcfg(1) == -1)
216 size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
217 base = extcfg & extcfg_base_mask[size_index];
218 /* base could > 4G */
219 base <<= extcfg_base_lshift;
220 start = (extcfg & extcfg_start_mask) >> extcfg_start_shift;
221 end = start + extcfg_sizebus[size_index] - 1;
222 fill_one_mmcfg(base, 0, start, end);
223 mcp55_mmconf_found++;
226 if (!mcp55_mmconf_found)
229 return "nVidia MCP55";
232 struct pci_mmcfg_hostbridge_probe {
237 const char *(*probe)(void);
240 static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
241 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
242 PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
243 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
244 PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
245 { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
246 0x1200, pci_mmcfg_amd_fam10h },
247 { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
248 0x1200, pci_mmcfg_amd_fam10h },
249 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
250 0x0369, pci_mmcfg_nvidia_mcp55 },
253 static int __init cmp_mmcfg(const void *x1, const void *x2)
255 const typeof(pci_mmcfg_config[0]) *m1 = x1;
256 const typeof(pci_mmcfg_config[0]) *m2 = x2;
259 start1 = m1->start_bus_number;
260 start2 = m2->start_bus_number;
262 return start1 - start2;
265 static void __init pci_mmcfg_check_end_bus_number(void)
268 typeof(pci_mmcfg_config[0]) *cfg, *cfgx;
270 /* sort them at first */
271 sort(pci_mmcfg_config, pci_mmcfg_config_num,
272 sizeof(pci_mmcfg_config[0]), cmp_mmcfg, NULL);
275 if (pci_mmcfg_config_num > 0) {
276 i = pci_mmcfg_config_num - 1;
277 cfg = &pci_mmcfg_config[i];
278 if (cfg->end_bus_number < cfg->start_bus_number)
279 cfg->end_bus_number = 255;
282 /* don't overlap please */
283 for (i = 0; i < pci_mmcfg_config_num - 1; i++) {
284 cfg = &pci_mmcfg_config[i];
285 cfgx = &pci_mmcfg_config[i+1];
287 if (cfg->end_bus_number < cfg->start_bus_number)
288 cfg->end_bus_number = 255;
290 if (cfg->end_bus_number >= cfgx->start_bus_number)
291 cfg->end_bus_number = cfgx->start_bus_number - 1;
295 static int __init pci_mmcfg_check_hostbridge(void)
306 pci_mmcfg_config_num = 0;
307 pci_mmcfg_config = NULL;
309 for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
310 bus = pci_mmcfg_probes[i].bus;
311 devfn = pci_mmcfg_probes[i].devfn;
312 raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
314 device = (l >> 16) & 0xffff;
317 if (pci_mmcfg_probes[i].vendor == vendor &&
318 pci_mmcfg_probes[i].device == device)
319 name = pci_mmcfg_probes[i].probe();
322 printk(KERN_INFO "PCI: Found %s with MMCONFIG support.\n",
326 /* some end_bus_number is crazy, fix it */
327 pci_mmcfg_check_end_bus_number();
329 return pci_mmcfg_config_num != 0;
332 static void __init pci_mmcfg_insert_resources(void)
334 #define PCI_MMCFG_RESOURCE_NAME_LEN 24
336 struct resource *res;
340 res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res),
341 pci_mmcfg_config_num, GFP_KERNEL);
343 printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n");
347 names = (void *)&res[pci_mmcfg_config_num];
348 for (i = 0; i < pci_mmcfg_config_num; i++, res++) {
349 struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i];
350 num_buses = cfg->end_bus_number - cfg->start_bus_number + 1;
352 snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN,
353 "PCI MMCONFIG %u [%02x-%02x]", cfg->pci_segment,
354 cfg->start_bus_number, cfg->end_bus_number);
355 res->start = cfg->address + (cfg->start_bus_number << 20);
356 res->end = res->start + (num_buses << 20) - 1;
357 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
358 insert_resource(&iomem_resource, res);
359 names += PCI_MMCFG_RESOURCE_NAME_LEN;
362 /* Mark that the resources have been inserted. */
363 pci_mmcfg_resources_inserted = 1;
366 static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
369 struct resource *mcfg_res = data;
370 struct acpi_resource_address64 address;
373 if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
374 struct acpi_resource_fixed_memory32 *fixmem32 =
375 &res->data.fixed_memory32;
378 if ((mcfg_res->start >= fixmem32->address) &&
379 (mcfg_res->end < (fixmem32->address +
380 fixmem32->address_length))) {
382 return AE_CTRL_TERMINATE;
385 if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
386 (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
389 status = acpi_resource_to_address64(res, &address);
390 if (ACPI_FAILURE(status) ||
391 (address.address_length <= 0) ||
392 (address.resource_type != ACPI_MEMORY_RANGE))
395 if ((mcfg_res->start >= address.minimum) &&
396 (mcfg_res->end < (address.minimum + address.address_length))) {
398 return AE_CTRL_TERMINATE;
403 static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
404 void *context, void **rv)
406 struct resource *mcfg_res = context;
408 acpi_walk_resources(handle, METHOD_NAME__CRS,
409 check_mcfg_resource, context);
412 return AE_CTRL_TERMINATE;
417 static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used)
419 struct resource mcfg_res;
421 mcfg_res.start = start;
422 mcfg_res.end = end - 1;
425 acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
428 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
431 return mcfg_res.flags;
434 typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);
436 static int __init is_mmconf_reserved(check_reserved_t is_reserved,
437 u64 addr, u64 size, int i,
438 typeof(pci_mmcfg_config[0]) *cfg, int with_e820)
443 while (!is_reserved(addr, addr + size, E820_RESERVED)) {
445 if (size < (16UL<<20))
449 if (size >= (16UL<<20) || size == old_size) {
451 "PCI: MCFG area at %Lx reserved in %s\n",
452 addr, with_e820?"E820":"ACPI motherboard resources");
455 if (old_size != size) {
456 /* update end_bus_number */
457 cfg->end_bus_number = cfg->start_bus_number + ((size>>20) - 1);
458 printk(KERN_NOTICE "PCI: updated MCFG configuration %d: base %lx "
459 "segment %hu buses %u - %u\n",
460 i, (unsigned long)cfg->address, cfg->pci_segment,
461 (unsigned int)cfg->start_bus_number,
462 (unsigned int)cfg->end_bus_number);
469 static void __init pci_mmcfg_reject_broken(int early)
471 typeof(pci_mmcfg_config[0]) *cfg;
474 if ((pci_mmcfg_config_num == 0) ||
475 (pci_mmcfg_config == NULL) ||
476 (pci_mmcfg_config[0].address == 0))
479 for (i = 0; i < pci_mmcfg_config_num; i++) {
483 cfg = &pci_mmcfg_config[i];
484 addr = cfg->start_bus_number;
486 addr += cfg->address;
487 size = cfg->end_bus_number + 1 - cfg->start_bus_number;
489 printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx "
490 "segment %hu buses %u - %u\n",
491 i, (unsigned long)cfg->address, cfg->pci_segment,
492 (unsigned int)cfg->start_bus_number,
493 (unsigned int)cfg->end_bus_number);
495 if (!early && !acpi_disabled)
496 valid = is_mmconf_reserved(is_acpi_reserved, addr, size, i, cfg, 0);
502 printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not"
503 " reserved in ACPI motherboard resources\n",
506 /* Don't try to do this check unless configuration
507 type 1 is available. how about type 2 ?*/
509 valid = is_mmconf_reserved(e820_all_mapped, addr, size, i, cfg, 1);
518 printk(KERN_INFO "PCI: Not using MMCONFIG.\n");
519 pci_mmcfg_arch_free();
520 kfree(pci_mmcfg_config);
521 pci_mmcfg_config = NULL;
522 pci_mmcfg_config_num = 0;
525 static int __initdata known_bridge;
527 /* The physical address of the MMCONFIG aperture. Set from ACPI tables. */
528 struct acpi_mcfg_allocation *pci_mmcfg_config;
529 int pci_mmcfg_config_num;
531 static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
532 struct acpi_mcfg_allocation *cfg)
536 if (cfg->address < 0xFFFFFFFF)
539 if (!strcmp(mcfg->header.oem_id, "SGI"))
542 if (mcfg->header.revision >= 1) {
543 if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
548 printk(KERN_ERR PREFIX "MCFG region for %04x:%02x-%02x at %#llx "
549 "is above 4GB, ignored\n", cfg->pci_segment,
550 cfg->start_bus_number, cfg->end_bus_number, cfg->address);
554 static int __init pci_parse_mcfg(struct acpi_table_header *header)
556 struct acpi_table_mcfg *mcfg;
563 mcfg = (struct acpi_table_mcfg *)header;
565 /* how many config structures do we have */
566 pci_mmcfg_config_num = 0;
567 i = header->length - sizeof(struct acpi_table_mcfg);
568 while (i >= sizeof(struct acpi_mcfg_allocation)) {
569 ++pci_mmcfg_config_num;
570 i -= sizeof(struct acpi_mcfg_allocation);
572 if (pci_mmcfg_config_num == 0) {
573 printk(KERN_ERR PREFIX "MMCONFIG has no entries\n");
577 config_size = pci_mmcfg_config_num * sizeof(*pci_mmcfg_config);
578 pci_mmcfg_config = kmalloc(config_size, GFP_KERNEL);
579 if (!pci_mmcfg_config) {
580 printk(KERN_WARNING PREFIX
581 "No memory for MCFG config tables\n");
585 memcpy(pci_mmcfg_config, &mcfg[1], config_size);
587 for (i = 0; i < pci_mmcfg_config_num; ++i) {
588 if (acpi_mcfg_check_entry(mcfg, &pci_mmcfg_config[i])) {
589 kfree(pci_mmcfg_config);
590 pci_mmcfg_config_num = 0;
598 static void __init __pci_mmcfg_init(int early)
600 /* MMCONFIG disabled */
601 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
604 /* MMCONFIG already enabled */
605 if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
608 /* for late to exit */
613 if (pci_mmcfg_check_hostbridge())
618 acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
620 pci_mmcfg_reject_broken(early);
622 if ((pci_mmcfg_config_num == 0) ||
623 (pci_mmcfg_config == NULL) ||
624 (pci_mmcfg_config[0].address == 0))
627 if (pci_mmcfg_arch_init())
628 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
631 * Signal not to attempt to insert mmcfg resources because
632 * the architecture mmcfg setup could not initialize.
634 pci_mmcfg_resources_inserted = 1;
638 void __init pci_mmcfg_early_init(void)
643 void __init pci_mmcfg_late_init(void)
648 static int __init pci_mmcfg_late_insert_resources(void)
651 * If resources are already inserted or we are not using MMCONFIG,
652 * don't insert the resources.
654 if ((pci_mmcfg_resources_inserted == 1) ||
655 (pci_probe & PCI_PROBE_MMCONF) == 0 ||
656 (pci_mmcfg_config_num == 0) ||
657 (pci_mmcfg_config == NULL) ||
658 (pci_mmcfg_config[0].address == 0))
662 * Attempt to insert the mmcfg resources but not with the busy flag
663 * marked so it won't cause request errors when __request_region is
666 pci_mmcfg_insert_resources();
672 * Perform MMCONFIG resource insertion after PCI initialization to allow for
673 * misprogrammed MCFG tables that state larger sizes but actually conflict
674 * with other system resources.
676 late_initcall(pci_mmcfg_late_insert_resources);