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   1 /*
   2  * @file op_model_ppro.h
   3  * Family 6 perfmon and architectural perfmon MSR operations
   4  *
   5  * @remark Copyright 2002 OProfile authors
   6  * @remark Copyright 2008 Intel Corporation
   7  * @remark Read the file COPYING
   8  *
   9  * @author John Levon
  10  * @author Philippe Elie
  11  * @author Graydon Hoare
  12  * @author Andi Kleen
  13  * @author Robert Richter <robert.richter@amd.com>
  14  */
  15
  16 #include <linux/oprofile.h>
  17 #include <linux/slab.h>
  18 #include <asm/ptrace.h>
  19 #include <asm/msr.h>
  20 #include <asm/apic.h>
  21 #include <asm/nmi.h>
  22
  23 #include "op_x86_model.h"
  24 #include "op_counter.h"
  25
  26 static int num_counters = 2;
  27 static int counter_width = 32;
  28
  29 #define MSR_PPRO_EVENTSEL_RESERVED      ((0xFFFFFFFFULL<<32)|(1ULL<<21))
  30
  31 static u64 *reset_value;
  32
  33 static void ppro_fill_in_addresses(struct op_msrs * const msrs)
  34 {
  35         int i;
  36
  37         for (i = 0; i < num_counters; i++) {
  38                 if (reserve_perfctr_nmi(MSR_P6_PERFCTR0 + i))
  39                         msrs->counters[i].addr = MSR_P6_PERFCTR0 + i;
  40                 else
  41                         msrs->counters[i].addr = 0;
  42         }
  43
  44         for (i = 0; i < num_counters; i++) {
  45                 if (reserve_evntsel_nmi(MSR_P6_EVNTSEL0 + i))
  46                         msrs->controls[i].addr = MSR_P6_EVNTSEL0 + i;
  47                 else
  48                         msrs->controls[i].addr = 0;
  49         }
  50 }
  51
  52
  53 static void ppro_setup_ctrs(struct op_x86_model_spec const *model,
  54                             struct op_msrs const * const msrs)
  55 {
  56         u64 val;
  57         int i;
  58
  59         if (!reset_value) {
  60                 reset_value = kmalloc(sizeof(reset_value[0]) * num_counters,
  61                                         GFP_ATOMIC);
  62                 if (!reset_value)
  63                         return;
  64         }
  65
  66         if (cpu_has_arch_perfmon) {
  67                 union cpuid10_eax eax;
  68                 eax.full = cpuid_eax(0xa);
  69
  70                 /*
  71                  * For Core2 (family 6, model 15), don't reset the
  72                  * counter width:
  73                  */
  74                 if (!(eax.split.version_id == 0 &&
  75                         current_cpu_data.x86 == 6 &&
  76                                 current_cpu_data.x86_model == 15)) {
  77
  78                         if (counter_width < eax.split.bit_width)
  79                                 counter_width = eax.split.bit_width;
  80                 }
  81         }
  82
  83         /* clear all counters */
  84         for (i = 0; i < num_counters; ++i) {
  85                 if (unlikely(!msrs->controls[i].addr)) {
  86                         if (counter_config[i].enabled && !smp_processor_id())
  87                                 /*
  88                                  * counter is reserved, this is on all
  89                                  * cpus, so report only for cpu #0
  90                                  */
  91                                 op_x86_warn_reserved(i);
  92                         continue;
  93                 }
  94                 rdmsrl(msrs->controls[i].addr, val);
  95                 if (val & ARCH_PERFMON_EVENTSEL0_ENABLE)
  96                         op_x86_warn_in_use(i);
  97                 val &= model->reserved;
  98                 wrmsrl(msrs->controls[i].addr, val);
  99         }
 100
 101         /* avoid a false detection of ctr overflows in NMI handler */
 102         for (i = 0; i < num_counters; ++i) {
 103                 if (unlikely(!msrs->counters[i].addr))
 104                         continue;
 105                 wrmsrl(msrs->counters[i].addr, -1LL);
 106         }
 107
 108         /* enable active counters */
 109         for (i = 0; i < num_counters; ++i) {
 110                 if (counter_config[i].enabled && msrs->counters[i].addr) {
 111                         reset_value[i] = counter_config[i].count;
 112                         wrmsrl(msrs->counters[i].addr, -reset_value[i]);
 113                         rdmsrl(msrs->controls[i].addr, val);
 114                         val &= model->reserved;
 115                         val |= op_x86_get_ctrl(model, &counter_config[i]);
 116                         wrmsrl(msrs->controls[i].addr, val);
 117                 } else {
 118                         reset_value[i] = 0;
 119                 }
 120         }
 121 }
 122
 123
 124 static int ppro_check_ctrs(struct pt_regs * const regs,
 125                            struct op_msrs const * const msrs)
 126 {
 127         u64 val;
 128         int i;
 129
 130         /*
 131          * This can happen if perf counters are in use when
 132          * we steal the die notifier NMI.
 133          */
 134         if (unlikely(!reset_value))
 135                 goto out;
 136
 137         for (i = 0; i < num_counters; ++i) {
 138                 if (!reset_value[i])
 139                         continue;
 140                 rdmsrl(msrs->counters[i].addr, val);
 141                 if (val & (1ULL << (counter_width - 1)))
 142                         continue;
 143                 oprofile_add_sample(regs, i);
 144                 wrmsrl(msrs->counters[i].addr, -reset_value[i]);
 145         }
 146
 147 out:
 148         /* Only P6 based Pentium M need to re-unmask the apic vector but it
 149          * doesn't hurt other P6 variant */
 150         apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED);
 151
 152         /* We can't work out if we really handled an interrupt. We
 153          * might have caught a *second* counter just after overflowing
 154          * the interrupt for this counter then arrives
 155          * and we don't find a counter that's overflowed, so we
 156          * would return 0 and get dazed + confused. Instead we always
 157          * assume we found an overflow. This sucks.
 158          */
 159         return 1;
 160 }
 161
 162
 163 static void ppro_start(struct op_msrs const * const msrs)
 164 {
 165         u64 val;
 166         int i;
 167
 168         if (!reset_value)
 169                 return;
 170         for (i = 0; i < num_counters; ++i) {
 171                 if (reset_value[i]) {
 172                         rdmsrl(msrs->controls[i].addr, val);
 173                         val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
 174                         wrmsrl(msrs->controls[i].addr, val);
 175                 }
 176         }
 177 }
 178
 179
 180 static void ppro_stop(struct op_msrs const * const msrs)
 181 {
 182         u64 val;
 183         int i;
 184
 185         if (!reset_value)
 186                 return;
 187         for (i = 0; i < num_counters; ++i) {
 188                 if (!reset_value[i])
 189                         continue;
 190                 rdmsrl(msrs->controls[i].addr, val);
 191                 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
 192                 wrmsrl(msrs->controls[i].addr, val);
 193         }
 194 }
 195
 196 static void ppro_shutdown(struct op_msrs const * const msrs)
 197 {
 198         int i;
 199
 200         for (i = 0; i < num_counters; ++i) {
 201                 if (msrs->counters[i].addr)
 202                         release_perfctr_nmi(MSR_P6_PERFCTR0 + i);
 203         }
 204         for (i = 0; i < num_counters; ++i) {
 205                 if (msrs->controls[i].addr)
 206                         release_evntsel_nmi(MSR_P6_EVNTSEL0 + i);
 207         }
 208         if (reset_value) {
 209                 kfree(reset_value);
 210                 reset_value = NULL;
 211         }
 212 }
 213
 214
 215 struct op_x86_model_spec op_ppro_spec = {
 216         .num_counters           = 2,
 217         .num_controls           = 2,
 218         .reserved               = MSR_PPRO_EVENTSEL_RESERVED,
 219         .fill_in_addresses      = &ppro_fill_in_addresses,
 220         .setup_ctrs             = &ppro_setup_ctrs,
 221         .check_ctrs             = &ppro_check_ctrs,
 222         .start                  = &ppro_start,
 223         .stop                   = &ppro_stop,
 224         .shutdown               = &ppro_shutdown
 225 };
 226
 227 /*
 228  * Architectural performance monitoring.
 229  *
 230  * Newer Intel CPUs (Core1+) have support for architectural
 231  * events described in CPUID 0xA. See the IA32 SDM Vol3b.18 for details.
 232  * The advantage of this is that it can be done without knowing about
 233  * the specific CPU.
 234  */
 235
 236 static void arch_perfmon_setup_counters(void)
 237 {
 238         union cpuid10_eax eax;
 239
 240         eax.full = cpuid_eax(0xa);
 241
 242         /* Workaround for BIOS bugs in 6/15. Taken from perfmon2 */
 243         if (eax.split.version_id == 0 && current_cpu_data.x86 == 6 &&
 244                 current_cpu_data.x86_model == 15) {
 245                 eax.split.version_id = 2;
 246                 eax.split.num_events = 2;
 247                 eax.split.bit_width = 40;
 248         }
 249
 250         num_counters = eax.split.num_events;
 251
 252         op_arch_perfmon_spec.num_counters = num_counters;
 253         op_arch_perfmon_spec.num_controls = num_counters;
 254 }
 255
 256 static int arch_perfmon_init(struct oprofile_operations *ignore)
 257 {
 258         arch_perfmon_setup_counters();
 259         return 0;
 260 }
 261
 262 struct op_x86_model_spec op_arch_perfmon_spec = {
 263         .reserved               = MSR_PPRO_EVENTSEL_RESERVED,
 264         .init                   = &arch_perfmon_init,
 265         /* num_counters/num_controls filled in at runtime */
 266         .fill_in_addresses      = &ppro_fill_in_addresses,
 267         /* user space does the cpuid check for available events */
 268         .setup_ctrs             = &ppro_setup_ctrs,
 269         .check_ctrs             = &ppro_check_ctrs,
 270         .start                  = &ppro_start,
 271         .stop                   = &ppro_stop,
 272         .shutdown               = &ppro_shutdown
 273 };