SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/x86/oprofile/op_model_ppro.c

   1 /*
   2  * @file op_model_ppro.h
   3  * Family 6 perfmon and architectural perfmon MSR operations
   4  *
   5  * @remark Copyright 2002 OProfile authors
   6  * @remark Copyright 2008 Intel Corporation
   7  * @remark Read the file COPYING
   8  *
   9  * @author John Levon
  10  * @author Philippe Elie
  11  * @author Graydon Hoare
  12  * @author Andi Kleen
  13  */
  14
  15 #include <linux/oprofile.h>
  16 #include <linux/slab.h>
  17 #include <asm/ptrace.h>
  18 #include <asm/msr.h>
  19 #include <asm/apic.h>
  20 #include <asm/nmi.h>
  21 #include <asm/intel_arch_perfmon.h>
  22
  23 #include "op_x86_model.h"
  24 #include "op_counter.h"
  25
  26 static int num_counters = 2;
  27 static int counter_width = 32;
  28
  29 #define CTR_OVERFLOWED(n) (!((n) & (1ULL<<(counter_width-1))))
  30
  31 #define CTRL_READ(l, h, msrs, c) do {rdmsr((msrs->controls[(c)].addr), (l), (h)); } while (0)
  32 #define CTRL_WRITE(l, h, msrs, c) do {wrmsr((msrs->controls[(c)].addr), (l), (h)); } while (0)
  33 #define CTRL_CLEAR(x) (x &= (1<<21))
  34 #define CTRL_SET_EVENT(val, e) (val |= e)
  35
  36 static u64 *reset_value;
  37
  38 static void ppro_fill_in_addresses(struct op_msrs * const msrs)
  39 {
  40         int i;
  41
  42         for (i = 0; i < num_counters; i++) {
  43                 if (reserve_perfctr_nmi(MSR_P6_PERFCTR0 + i))
  44                         msrs->counters[i].addr = MSR_P6_PERFCTR0 + i;
  45                 else
  46                         msrs->counters[i].addr = 0;
  47         }
  48
  49         for (i = 0; i < num_counters; i++) {
  50                 if (reserve_evntsel_nmi(MSR_P6_EVNTSEL0 + i))
  51                         msrs->controls[i].addr = MSR_P6_EVNTSEL0 + i;
  52                 else
  53                         msrs->controls[i].addr = 0;
  54         }
  55 }
  56
  57
  58 static void ppro_setup_ctrs(struct op_msrs const * const msrs)
  59 {
  60         unsigned int low, high;
  61         int i;
  62
  63         if (!reset_value) {
  64                 reset_value = kmalloc(sizeof(reset_value[0]) * num_counters,
  65                                         GFP_ATOMIC);
  66                 if (!reset_value)
  67                         return;
  68         }
  69
  70         if (cpu_has_arch_perfmon) {
  71                 union cpuid10_eax eax;
  72                 eax.full = cpuid_eax(0xa);
  73
  74                 /*
  75                  * For Core2 (family 6, model 15), don't reset the
  76                  * counter width:
  77                  */
  78                 if (!(eax.split.version_id == 0 &&
  79                         current_cpu_data.x86 == 6 &&
  80                                 current_cpu_data.x86_model == 15)) {
  81
  82                         if (counter_width < eax.split.bit_width)
  83                                 counter_width = eax.split.bit_width;
  84                 }
  85         }
  86
  87         /* clear all counters */
  88         for (i = 0 ; i < num_counters; ++i) {
  89                 if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
  90                         continue;
  91                 CTRL_READ(low, high, msrs, i);
  92                 CTRL_CLEAR(low);
  93                 CTRL_WRITE(low, high, msrs, i);
  94         }
  95
  96         /* avoid a false detection of ctr overflows in NMI handler */
  97         for (i = 0; i < num_counters; ++i) {
  98                 if (unlikely(!CTR_IS_RESERVED(msrs, i)))
  99                         continue;
 100                 wrmsrl(msrs->counters[i].addr, -1LL);
 101         }
 102
 103         /* enable active counters */
 104         for (i = 0; i < num_counters; ++i) {
 105                 if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) {
 106                         reset_value[i] = counter_config[i].count;
 107
 108                         wrmsrl(msrs->counters[i].addr, -reset_value[i]);
 109
 110                         CTRL_READ(low, high, msrs, i);
 111                         CTRL_CLEAR(low);
 112                         CTRL_SET_ENABLE(low);
 113                         CTRL_SET_USR(low, counter_config[i].user);
 114                         CTRL_SET_KERN(low, counter_config[i].kernel);
 115                         CTRL_SET_UM(low, counter_config[i].unit_mask);
 116                         CTRL_SET_EVENT(low, counter_config[i].event);
 117                         CTRL_WRITE(low, high, msrs, i);
 118                 } else {
 119                         reset_value[i] = 0;
 120                 }
 121         }
 122 }
 123
 124
 125 static int ppro_check_ctrs(struct pt_regs * const regs,
 126                            struct op_msrs const * const msrs)
 127 {
 128         u64 val;
 129         int i;
 130
 131         for (i = 0 ; i < num_counters; ++i) {
 132                 if (!reset_value[i])
 133                         continue;
 134                 rdmsrl(msrs->counters[i].addr, val);
 135                 if (CTR_OVERFLOWED(val)) {
 136                         oprofile_add_sample(regs, i);
 137                         wrmsrl(msrs->counters[i].addr, -reset_value[i]);
 138                 }
 139         }
 140
 141         /* Only P6 based Pentium M need to re-unmask the apic vector but it
 142          * doesn't hurt other P6 variant */
 143         apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED);
 144
 145         /* We can't work out if we really handled an interrupt. We
 146          * might have caught a *second* counter just after overflowing
 147          * the interrupt for this counter then arrives
 148          * and we don't find a counter that's overflowed, so we
 149          * would return 0 and get dazed + confused. Instead we always
 150          * assume we found an overflow. This sucks.
 151          */
 152         return 1;
 153 }
 154
 155
 156 static void ppro_start(struct op_msrs const * const msrs)
 157 {
 158         unsigned int low, high;
 159         int i;
 160
 161         if (!reset_value)
 162                 return;
 163         for (i = 0; i < num_counters; ++i) {
 164                 if (reset_value[i]) {
 165                         CTRL_READ(low, high, msrs, i);
 166                         CTRL_SET_ACTIVE(low);
 167                         CTRL_WRITE(low, high, msrs, i);
 168                 }
 169         }
 170 }
 171
 172
 173 static void ppro_stop(struct op_msrs const * const msrs)
 174 {
 175         unsigned int low, high;
 176         int i;
 177
 178         if (!reset_value)
 179                 return;
 180         for (i = 0; i < num_counters; ++i) {
 181                 if (!reset_value[i])
 182                         continue;
 183                 CTRL_READ(low, high, msrs, i);
 184                 CTRL_SET_INACTIVE(low);
 185                 CTRL_WRITE(low, high, msrs, i);
 186         }
 187 }
 188
 189 static void ppro_shutdown(struct op_msrs const * const msrs)
 190 {
 191         int i;
 192
 193         for (i = 0 ; i < num_counters ; ++i) {
 194                 if (CTR_IS_RESERVED(msrs, i))
 195                         release_perfctr_nmi(MSR_P6_PERFCTR0 + i);
 196         }
 197         for (i = 0 ; i < num_counters ; ++i) {
 198                 if (CTRL_IS_RESERVED(msrs, i))
 199                         release_evntsel_nmi(MSR_P6_EVNTSEL0 + i);
 200         }
 201         if (reset_value) {
 202                 kfree(reset_value);
 203                 reset_value = NULL;
 204         }
 205 }
 206
 207
 208 struct op_x86_model_spec const op_ppro_spec = {
 209         .num_counters           = 2,
 210         .num_controls           = 2,
 211         .fill_in_addresses      = &ppro_fill_in_addresses,
 212         .setup_ctrs             = &ppro_setup_ctrs,
 213         .check_ctrs             = &ppro_check_ctrs,
 214         .start                  = &ppro_start,
 215         .stop                   = &ppro_stop,
 216         .shutdown               = &ppro_shutdown
 217 };
 218
 219 /*
 220  * Architectural performance monitoring.
 221  *
 222  * Newer Intel CPUs (Core1+) have support for architectural
 223  * events described in CPUID 0xA. See the IA32 SDM Vol3b.18 for details.
 224  * The advantage of this is that it can be done without knowing about
 225  * the specific CPU.
 226  */
 227
 228 static void arch_perfmon_setup_counters(void)
 229 {
 230         union cpuid10_eax eax;
 231
 232         eax.full = cpuid_eax(0xa);
 233
 234         /* Workaround for BIOS bugs in 6/15. Taken from perfmon2 */
 235         if (eax.split.version_id == 0 && current_cpu_data.x86 == 6 &&
 236                 current_cpu_data.x86_model == 15) {
 237                 eax.split.version_id = 2;
 238                 eax.split.num_counters = 2;
 239                 eax.split.bit_width = 40;
 240         }
 241
 242         num_counters = eax.split.num_counters;
 243
 244         op_arch_perfmon_spec.num_counters = num_counters;
 245         op_arch_perfmon_spec.num_controls = num_counters;
 246 }
 247
 248 static int arch_perfmon_init(struct oprofile_operations *ignore)
 249 {
 250         arch_perfmon_setup_counters();
 251         return 0;
 252 }
 253
 254 struct op_x86_model_spec op_arch_perfmon_spec = {
 255         .init                   = &arch_perfmon_init,
 256         /* num_counters/num_controls filled in at runtime */
 257         .fill_in_addresses      = &ppro_fill_in_addresses,
 258         /* user space does the cpuid check for available events */
 259         .setup_ctrs             = &ppro_setup_ctrs,
 260         .check_ctrs             = &ppro_check_ctrs,
 261         .start                  = &ppro_start,
 262         .stop                   = &ppro_stop,
 263         .shutdown               = &ppro_shutdown
 264 };