SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/x86/oprofile/op_model_ppro.c

   1 /*
   2  * @file op_model_ppro.h
   3  * Family 6 perfmon and architectural perfmon MSR operations
   4  *
   5  * @remark Copyright 2002 OProfile authors
   6  * @remark Copyright 2008 Intel Corporation
   7  * @remark Read the file COPYING
   8  *
   9  * @author John Levon
  10  * @author Philippe Elie
  11  * @author Graydon Hoare
  12  * @author Andi Kleen
  13  * @author Robert Richter <robert.richter@amd.com>
  14  */
  15
  16 #include <linux/oprofile.h>
  17 #include <linux/slab.h>
  18 #include <asm/ptrace.h>
  19 #include <asm/msr.h>
  20 #include <asm/apic.h>
  21 #include <asm/nmi.h>
  22
  23 #include "op_x86_model.h"
  24 #include "op_counter.h"
  25
  26 static int num_counters = 2;
  27 static int counter_width = 32;
  28
  29 #define MSR_PPRO_EVENTSEL_RESERVED      ((0xFFFFFFFFULL<<32)|(1ULL<<21))
  30
  31 static u64 *reset_value;
  32
  33 static void ppro_fill_in_addresses(struct op_msrs * const msrs)
  34 {
  35         int i;
  36
  37         for (i = 0; i < num_counters; i++) {
  38                 if (reserve_perfctr_nmi(MSR_P6_PERFCTR0 + i))
  39                         msrs->counters[i].addr = MSR_P6_PERFCTR0 + i;
  40                 else
  41                         msrs->counters[i].addr = 0;
  42         }
  43
  44         for (i = 0; i < num_counters; i++) {
  45                 if (reserve_evntsel_nmi(MSR_P6_EVNTSEL0 + i))
  46                         msrs->controls[i].addr = MSR_P6_EVNTSEL0 + i;
  47                 else
  48                         msrs->controls[i].addr = 0;
  49         }
  50 }
  51
  52
  53 static void ppro_setup_ctrs(struct op_x86_model_spec const *model,
  54                             struct op_msrs const * const msrs)
  55 {
  56         u64 val;
  57         int i;
  58
  59         if (!reset_value) {
  60                 reset_value = kmalloc(sizeof(reset_value[0]) * num_counters,
  61                                         GFP_ATOMIC);
  62                 if (!reset_value)
  63                         return;
  64         }
  65
  66         if (cpu_has_arch_perfmon) {
  67                 union cpuid10_eax eax;
  68                 eax.full = cpuid_eax(0xa);
  69
  70                 /*
  71                  * For Core2 (family 6, model 15), don't reset the
  72                  * counter width:
  73                  */
  74                 if (!(eax.split.version_id == 0 &&
  75                         current_cpu_data.x86 == 6 &&
  76                                 current_cpu_data.x86_model == 15)) {
  77
  78                         if (counter_width < eax.split.bit_width)
  79                                 counter_width = eax.split.bit_width;
  80                 }
  81         }
  82
  83         /* clear all counters */
  84         for (i = 0 ; i < num_counters; ++i) {
  85                 if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
  86                         continue;
  87                 rdmsrl(msrs->controls[i].addr, val);
  88                 val &= model->reserved;
  89                 wrmsrl(msrs->controls[i].addr, val);
  90         }
  91
  92         /* avoid a false detection of ctr overflows in NMI handler */
  93         for (i = 0; i < num_counters; ++i) {
  94                 if (unlikely(!CTR_IS_RESERVED(msrs, i)))
  95                         continue;
  96                 wrmsrl(msrs->counters[i].addr, -1LL);
  97         }
  98
  99         /* enable active counters */
 100         for (i = 0; i < num_counters; ++i) {
 101                 if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) {
 102                         reset_value[i] = counter_config[i].count;
 103                         wrmsrl(msrs->counters[i].addr, -reset_value[i]);
 104                         rdmsrl(msrs->controls[i].addr, val);
 105                         val &= model->reserved;
 106                         val |= op_x86_get_ctrl(model, &counter_config[i]);
 107                         wrmsrl(msrs->controls[i].addr, val);
 108                 } else {
 109                         reset_value[i] = 0;
 110                 }
 111         }
 112 }
 113
 114
 115 static int ppro_check_ctrs(struct pt_regs * const regs,
 116                            struct op_msrs const * const msrs)
 117 {
 118         u64 val;
 119         int i;
 120
 121         for (i = 0 ; i < num_counters; ++i) {
 122                 if (!reset_value[i])
 123                         continue;
 124                 rdmsrl(msrs->counters[i].addr, val);
 125                 if (val & (1ULL << (counter_width - 1)))
 126                         continue;
 127                 oprofile_add_sample(regs, i);
 128                 wrmsrl(msrs->counters[i].addr, -reset_value[i]);
 129         }
 130
 131         /* Only P6 based Pentium M need to re-unmask the apic vector but it
 132          * doesn't hurt other P6 variant */
 133         apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED);
 134
 135         /* We can't work out if we really handled an interrupt. We
 136          * might have caught a *second* counter just after overflowing
 137          * the interrupt for this counter then arrives
 138          * and we don't find a counter that's overflowed, so we
 139          * would return 0 and get dazed + confused. Instead we always
 140          * assume we found an overflow. This sucks.
 141          */
 142         return 1;
 143 }
 144
 145
 146 static void ppro_start(struct op_msrs const * const msrs)
 147 {
 148         unsigned int low, high;
 149         int i;
 150
 151         if (!reset_value)
 152                 return;
 153         for (i = 0; i < num_counters; ++i) {
 154                 if (reset_value[i]) {
 155                         rdmsr(msrs->controls[i].addr, low, high);
 156                         CTRL_SET_ACTIVE(low);
 157                         wrmsr(msrs->controls[i].addr, low, high);
 158                 }
 159         }
 160 }
 161
 162
 163 static void ppro_stop(struct op_msrs const * const msrs)
 164 {
 165         unsigned int low, high;
 166         int i;
 167
 168         if (!reset_value)
 169                 return;
 170         for (i = 0; i < num_counters; ++i) {
 171                 if (!reset_value[i])
 172                         continue;
 173                 rdmsr(msrs->controls[i].addr, low, high);
 174                 CTRL_SET_INACTIVE(low);
 175                 wrmsr(msrs->controls[i].addr, low, high);
 176         }
 177 }
 178
 179 static void ppro_shutdown(struct op_msrs const * const msrs)
 180 {
 181         int i;
 182
 183         for (i = 0 ; i < num_counters ; ++i) {
 184                 if (CTR_IS_RESERVED(msrs, i))
 185                         release_perfctr_nmi(MSR_P6_PERFCTR0 + i);
 186         }
 187         for (i = 0 ; i < num_counters ; ++i) {
 188                 if (CTRL_IS_RESERVED(msrs, i))
 189                         release_evntsel_nmi(MSR_P6_EVNTSEL0 + i);
 190         }
 191         if (reset_value) {
 192                 kfree(reset_value);
 193                 reset_value = NULL;
 194         }
 195 }
 196
 197
 198 struct op_x86_model_spec const op_ppro_spec = {
 199         .num_counters           = 2,
 200         .num_controls           = 2,
 201         .reserved               = MSR_PPRO_EVENTSEL_RESERVED,
 202         .fill_in_addresses      = &ppro_fill_in_addresses,
 203         .setup_ctrs             = &ppro_setup_ctrs,
 204         .check_ctrs             = &ppro_check_ctrs,
 205         .start                  = &ppro_start,
 206         .stop                   = &ppro_stop,
 207         .shutdown               = &ppro_shutdown
 208 };
 209
 210 /*
 211  * Architectural performance monitoring.
 212  *
 213  * Newer Intel CPUs (Core1+) have support for architectural
 214  * events described in CPUID 0xA. See the IA32 SDM Vol3b.18 for details.
 215  * The advantage of this is that it can be done without knowing about
 216  * the specific CPU.
 217  */
 218
 219 static void arch_perfmon_setup_counters(void)
 220 {
 221         union cpuid10_eax eax;
 222
 223         eax.full = cpuid_eax(0xa);
 224
 225         /* Workaround for BIOS bugs in 6/15. Taken from perfmon2 */
 226         if (eax.split.version_id == 0 && current_cpu_data.x86 == 6 &&
 227                 current_cpu_data.x86_model == 15) {
 228                 eax.split.version_id = 2;
 229                 eax.split.num_counters = 2;
 230                 eax.split.bit_width = 40;
 231         }
 232
 233         num_counters = eax.split.num_counters;
 234
 235         op_arch_perfmon_spec.num_counters = num_counters;
 236         op_arch_perfmon_spec.num_controls = num_counters;
 237 }
 238
 239 static int arch_perfmon_init(struct oprofile_operations *ignore)
 240 {
 241         arch_perfmon_setup_counters();
 242         return 0;
 243 }
 244
 245 struct op_x86_model_spec op_arch_perfmon_spec = {
 246         .reserved               = MSR_PPRO_EVENTSEL_RESERVED,
 247         .init                   = &arch_perfmon_init,
 248         /* num_counters/num_controls filled in at runtime */
 249         .fill_in_addresses      = &ppro_fill_in_addresses,
 250         /* user space does the cpuid check for available events */
 251         .setup_ctrs             = &ppro_setup_ctrs,
 252         .check_ctrs             = &ppro_check_ctrs,
 253         .start                  = &ppro_start,
 254         .stop                   = &ppro_stop,
 255         .shutdown               = &ppro_shutdown
 256 };