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   1 /*
   2  * @file op_model_amd.c
   3  * athlon / K7 / K8 / Family 10h model-specific MSR operations
   4  *
   5  * @remark Copyright 2002-2009 OProfile authors
   6  * @remark Read the file COPYING
   7  *
   8  * @author John Levon
   9  * @author Philippe Elie
  10  * @author Graydon Hoare
  11  * @author Robert Richter <robert.richter@amd.com>
  12  * @author Barry Kasindorf <barry.kasindorf@amd.com>
  13  * @author Jason Yeh <jason.yeh@amd.com>
  14  * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
  15  */
  16
  17 #include <linux/oprofile.h>
  18 #include <linux/device.h>
  19 #include <linux/pci.h>
  20 #include <linux/percpu.h>
  21
  22 #include <asm/ptrace.h>
  23 #include <asm/msr.h>
  24 #include <asm/nmi.h>
  25 #include <asm/apic.h>
  26 #include <asm/processor.h>
  27 #include <asm/cpufeature.h>
  28
  29 #include "op_x86_model.h"
  30 #include "op_counter.h"
  31
  32 #define NUM_COUNTERS 4
  33 #define NUM_CONTROLS 4
  34 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
  35 #define NUM_VIRT_COUNTERS 32
  36 #define NUM_VIRT_CONTROLS 32
  37 #else
  38 #define NUM_VIRT_COUNTERS NUM_COUNTERS
  39 #define NUM_VIRT_CONTROLS NUM_CONTROLS
  40 #endif
  41
  42 #define OP_EVENT_MASK                   0x0FFF
  43 #define OP_CTR_OVERFLOW                 (1ULL<<31)
  44
  45 #define MSR_AMD_EVENTSEL_RESERVED       ((0xFFFFFCF0ULL<<32)|(1ULL<<21))
  46
  47 static unsigned long reset_value[NUM_VIRT_COUNTERS];
  48
  49 /* IbsFetchCtl bits/masks */
  50 #define IBS_FETCH_RAND_EN               (1ULL<<57)
  51 #define IBS_FETCH_VAL                   (1ULL<<49)
  52 #define IBS_FETCH_ENABLE                (1ULL<<48)
  53 #define IBS_FETCH_CNT_MASK              0xFFFF0000ULL
  54
  55 /* IbsOpCtl bits */
  56 #define IBS_OP_CNT_CTL                  (1ULL<<19)
  57 #define IBS_OP_VAL                      (1ULL<<18)
  58 #define IBS_OP_ENABLE                   (1ULL<<17)
  59
  60 #define IBS_FETCH_SIZE                  6
  61 #define IBS_OP_SIZE                     12
  62
  63 static u32 ibs_caps;
  64
  65 struct op_ibs_config {
  66         unsigned long op_enabled;
  67         unsigned long fetch_enabled;
  68         unsigned long max_cnt_fetch;
  69         unsigned long max_cnt_op;
  70         unsigned long rand_en;
  71         unsigned long dispatched_ops;
  72 };
  73
  74 static struct op_ibs_config ibs_config;
  75 static u64 ibs_op_ctl;
  76
  77 /*
  78  * IBS cpuid feature detection
  79  */
  80
  81 #define IBS_CPUID_FEATURES      0x8000001b
  82
  83 /*
  84  * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
  85  * bit 0 is used to indicate the existence of IBS.
  86  */
  87 #define IBS_CAPS_AVAIL                  (1LL<<0)
  88 #define IBS_CAPS_RDWROPCNT              (1LL<<3)
  89 #define IBS_CAPS_OPCNT                  (1LL<<4)
  90
  91 /*
  92  * IBS randomization macros
  93  */
  94 #define IBS_RANDOM_BITS                 12
  95 #define IBS_RANDOM_MASK                 ((1ULL << IBS_RANDOM_BITS) - 1)
  96 #define IBS_RANDOM_MAXCNT_OFFSET        (1ULL << (IBS_RANDOM_BITS - 5))
  97
  98 static u32 get_ibs_caps(void)
  99 {
 100         u32 ibs_caps;
 101         unsigned int max_level;
 102
 103         if (!boot_cpu_has(X86_FEATURE_IBS))
 104                 return 0;
 105
 106         /* check IBS cpuid feature flags */
 107         max_level = cpuid_eax(0x80000000);
 108         if (max_level < IBS_CPUID_FEATURES)
 109                 return IBS_CAPS_AVAIL;
 110
 111         ibs_caps = cpuid_eax(IBS_CPUID_FEATURES);
 112         if (!(ibs_caps & IBS_CAPS_AVAIL))
 113                 /* cpuid flags not valid */
 114                 return IBS_CAPS_AVAIL;
 115
 116         return ibs_caps;
 117 }
 118
 119 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 120
 121 static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
 122                                struct op_msrs const * const msrs)
 123 {
 124         u64 val;
 125         int i;
 126
 127         /* enable active counters */
 128         for (i = 0; i < NUM_COUNTERS; ++i) {
 129                 int virt = op_x86_phys_to_virt(i);
 130                 if (!counter_config[virt].enabled)
 131                         continue;
 132                 rdmsrl(msrs->controls[i].addr, val);
 133                 val &= model->reserved;
 134                 val |= op_x86_get_ctrl(model, &counter_config[virt]);
 135                 wrmsrl(msrs->controls[i].addr, val);
 136         }
 137 }
 138
 139 #endif
 140
 141 /* functions for op_amd_spec */
 142
 143 static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
 144 {
 145         int i;
 146
 147         for (i = 0; i < NUM_COUNTERS; i++) {
 148                 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
 149                         msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
 150         }
 151
 152         for (i = 0; i < NUM_CONTROLS; i++) {
 153                 if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
 154                         msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
 155         }
 156 }
 157
 158 static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
 159                               struct op_msrs const * const msrs)
 160 {
 161         u64 val;
 162         int i;
 163
 164         /* setup reset_value */
 165         for (i = 0; i < NUM_VIRT_COUNTERS; ++i) {
 166                 if (counter_config[i].enabled)
 167                         reset_value[i] = counter_config[i].count;
 168                 else
 169                         reset_value[i] = 0;
 170         }
 171
 172         /* clear all counters */
 173         for (i = 0; i < NUM_CONTROLS; ++i) {
 174                 if (unlikely(!msrs->controls[i].addr)) {
 175                         if (counter_config[i].enabled && !smp_processor_id())
 176                                 /*
 177                                  * counter is reserved, this is on all
 178                                  * cpus, so report only for cpu #0
 179                                  */
 180                                 op_x86_warn_reserved(i);
 181                         continue;
 182                 }
 183                 rdmsrl(msrs->controls[i].addr, val);
 184                 if (val & ARCH_PERFMON_EVENTSEL0_ENABLE)
 185                         op_x86_warn_in_use(i);
 186                 val &= model->reserved;
 187                 wrmsrl(msrs->controls[i].addr, val);
 188         }
 189
 190         /* avoid a false detection of ctr overflows in NMI handler */
 191         for (i = 0; i < NUM_COUNTERS; ++i) {
 192                 if (unlikely(!msrs->counters[i].addr))
 193                         continue;
 194                 wrmsrl(msrs->counters[i].addr, -1LL);
 195         }
 196
 197         /* enable active counters */
 198         for (i = 0; i < NUM_COUNTERS; ++i) {
 199                 int virt = op_x86_phys_to_virt(i);
 200                 if (!counter_config[virt].enabled)
 201                         continue;
 202                 if (!msrs->counters[i].addr)
 203                         continue;
 204
 205                 /* setup counter registers */
 206                 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
 207
 208                 /* setup control registers */
 209                 rdmsrl(msrs->controls[i].addr, val);
 210                 val &= model->reserved;
 211                 val |= op_x86_get_ctrl(model, &counter_config[virt]);
 212                 wrmsrl(msrs->controls[i].addr, val);
 213         }
 214 }
 215
 216 /*
 217  * 16-bit Linear Feedback Shift Register (LFSR)
 218  *
 219  *                       16   14   13    11
 220  * Feedback polynomial = X  + X  + X  +  X  + 1
 221  */
 222 static unsigned int lfsr_random(void)
 223 {
 224         static unsigned int lfsr_value = 0xF00D;
 225         unsigned int bit;
 226
 227         /* Compute next bit to shift in */
 228         bit = ((lfsr_value >> 0) ^
 229                (lfsr_value >> 2) ^
 230                (lfsr_value >> 3) ^
 231                (lfsr_value >> 5)) & 0x0001;
 232
 233         /* Advance to next register value */
 234         lfsr_value = (lfsr_value >> 1) | (bit << 15);
 235
 236         return lfsr_value;
 237 }
 238
 239 /*
 240  * IBS software randomization
 241  *
 242  * The IBS periodic op counter is randomized in software. The lower 12
 243  * bits of the 20 bit counter are randomized. IbsOpCurCnt is
 244  * initialized with a 12 bit random value.
 245  */
 246 static inline u64 op_amd_randomize_ibs_op(u64 val)
 247 {
 248         unsigned int random = lfsr_random();
 249
 250         if (!(ibs_caps & IBS_CAPS_RDWROPCNT))
 251                 /*
 252                  * Work around if the hw can not write to IbsOpCurCnt
 253                  *
 254                  * Randomize the lower 8 bits of the 16 bit
 255                  * IbsOpMaxCnt [15:0] value in the range of -128 to
 256                  * +127 by adding/subtracting an offset to the
 257                  * maximum count (IbsOpMaxCnt).
 258                  *
 259                  * To avoid over or underflows and protect upper bits
 260                  * starting at bit 16, the initial value for
 261                  * IbsOpMaxCnt must fit in the range from 0x0081 to
 262                  * 0xff80.
 263                  */
 264                 val += (s8)(random >> 4);
 265         else
 266                 val |= (u64)(random & IBS_RANDOM_MASK) << 32;
 267
 268         return val;
 269 }
 270
 271 static inline void
 272 op_amd_handle_ibs(struct pt_regs * const regs,
 273                   struct op_msrs const * const msrs)
 274 {
 275         u64 val, ctl;
 276         struct op_entry entry;
 277
 278         if (!ibs_caps)
 279                 return;
 280
 281         if (ibs_config.fetch_enabled) {
 282                 rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
 283                 if (ctl & IBS_FETCH_VAL) {
 284                         rdmsrl(MSR_AMD64_IBSFETCHLINAD, val);
 285                         oprofile_write_reserve(&entry, regs, val,
 286                                                IBS_FETCH_CODE, IBS_FETCH_SIZE);
 287                         oprofile_add_data64(&entry, val);
 288                         oprofile_add_data64(&entry, ctl);
 289                         rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val);
 290                         oprofile_add_data64(&entry, val);
 291                         oprofile_write_commit(&entry);
 292
 293                         /* reenable the IRQ */
 294                         ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT_MASK);
 295                         ctl |= IBS_FETCH_ENABLE;
 296                         wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
 297                 }
 298         }
 299
 300         if (ibs_config.op_enabled) {
 301                 rdmsrl(MSR_AMD64_IBSOPCTL, ctl);
 302                 if (ctl & IBS_OP_VAL) {
 303                         rdmsrl(MSR_AMD64_IBSOPRIP, val);
 304                         oprofile_write_reserve(&entry, regs, val,
 305                                                IBS_OP_CODE, IBS_OP_SIZE);
 306                         oprofile_add_data64(&entry, val);
 307                         rdmsrl(MSR_AMD64_IBSOPDATA, val);
 308                         oprofile_add_data64(&entry, val);
 309                         rdmsrl(MSR_AMD64_IBSOPDATA2, val);
 310                         oprofile_add_data64(&entry, val);
 311                         rdmsrl(MSR_AMD64_IBSOPDATA3, val);
 312                         oprofile_add_data64(&entry, val);
 313                         rdmsrl(MSR_AMD64_IBSDCLINAD, val);
 314                         oprofile_add_data64(&entry, val);
 315                         rdmsrl(MSR_AMD64_IBSDCPHYSAD, val);
 316                         oprofile_add_data64(&entry, val);
 317                         oprofile_write_commit(&entry);
 318
 319                         /* reenable the IRQ */
 320                         ctl = op_amd_randomize_ibs_op(ibs_op_ctl);
 321                         wrmsrl(MSR_AMD64_IBSOPCTL, ctl);
 322                 }
 323         }
 324 }
 325
 326 static inline void op_amd_start_ibs(void)
 327 {
 328         u64 val;
 329
 330         if (!ibs_caps)
 331                 return;
 332
 333         if (ibs_config.fetch_enabled) {
 334                 val = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
 335                 val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
 336                 val |= IBS_FETCH_ENABLE;
 337                 wrmsrl(MSR_AMD64_IBSFETCHCTL, val);
 338         }
 339
 340         if (ibs_config.op_enabled) {
 341                 ibs_op_ctl = ibs_config.max_cnt_op >> 4;
 342                 if (!(ibs_caps & IBS_CAPS_RDWROPCNT)) {
 343                         /*
 344                          * IbsOpCurCnt not supported.  See
 345                          * op_amd_randomize_ibs_op() for details.
 346                          */
 347                         ibs_op_ctl = clamp(ibs_op_ctl, 0x0081ULL, 0xFF80ULL);
 348                 } else {
 349                         /*
 350                          * The start value is randomized with a
 351                          * positive offset, we need to compensate it
 352                          * with the half of the randomized range. Also
 353                          * avoid underflows.
 354                          */
 355                         ibs_op_ctl = min(ibs_op_ctl + IBS_RANDOM_MAXCNT_OFFSET,
 356                                          0xFFFFULL);
 357                 }
 358                 if (ibs_caps & IBS_CAPS_OPCNT && ibs_config.dispatched_ops)
 359                         ibs_op_ctl |= IBS_OP_CNT_CTL;
 360                 ibs_op_ctl |= IBS_OP_ENABLE;
 361                 val = op_amd_randomize_ibs_op(ibs_op_ctl);
 362                 wrmsrl(MSR_AMD64_IBSOPCTL, val);
 363         }
 364 }
 365
 366 static void op_amd_stop_ibs(void)
 367 {
 368         if (!ibs_caps)
 369                 return;
 370
 371         if (ibs_config.fetch_enabled)
 372                 /* clear max count and enable */
 373                 wrmsrl(MSR_AMD64_IBSFETCHCTL, 0);
 374
 375         if (ibs_config.op_enabled)
 376                 /* clear max count and enable */
 377                 wrmsrl(MSR_AMD64_IBSOPCTL, 0);
 378 }
 379
 380 static int op_amd_check_ctrs(struct pt_regs * const regs,
 381                              struct op_msrs const * const msrs)
 382 {
 383         u64 val;
 384         int i;
 385
 386         for (i = 0; i < NUM_COUNTERS; ++i) {
 387                 int virt = op_x86_phys_to_virt(i);
 388                 if (!reset_value[virt])
 389                         continue;
 390                 rdmsrl(msrs->counters[i].addr, val);
 391                 /* bit is clear if overflowed: */
 392                 if (val & OP_CTR_OVERFLOW)
 393                         continue;
 394                 oprofile_add_sample(regs, virt);
 395                 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
 396         }
 397
 398         op_amd_handle_ibs(regs, msrs);
 399
 400         /* See op_model_ppro.c */
 401         return 1;
 402 }
 403
 404 static void op_amd_start(struct op_msrs const * const msrs)
 405 {
 406         u64 val;
 407         int i;
 408
 409         for (i = 0; i < NUM_COUNTERS; ++i) {
 410                 if (!reset_value[op_x86_phys_to_virt(i)])
 411                         continue;
 412                 rdmsrl(msrs->controls[i].addr, val);
 413                 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
 414                 wrmsrl(msrs->controls[i].addr, val);
 415         }
 416
 417         op_amd_start_ibs();
 418 }
 419
 420 static void op_amd_stop(struct op_msrs const * const msrs)
 421 {
 422         u64 val;
 423         int i;
 424
 425         /*
 426          * Subtle: stop on all counters to avoid race with setting our
 427          * pm callback
 428          */
 429         for (i = 0; i < NUM_COUNTERS; ++i) {
 430                 if (!reset_value[op_x86_phys_to_virt(i)])
 431                         continue;
 432                 rdmsrl(msrs->controls[i].addr, val);
 433                 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
 434                 wrmsrl(msrs->controls[i].addr, val);
 435         }
 436
 437         op_amd_stop_ibs();
 438 }
 439
 440 static void op_amd_shutdown(struct op_msrs const * const msrs)
 441 {
 442         int i;
 443
 444         for (i = 0; i < NUM_COUNTERS; ++i) {
 445                 if (msrs->counters[i].addr)
 446                         release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
 447         }
 448         for (i = 0; i < NUM_CONTROLS; ++i) {
 449                 if (msrs->controls[i].addr)
 450                         release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
 451         }
 452 }
 453
 454 static u8 ibs_eilvt_off;
 455
 456 static inline void apic_init_ibs_nmi_per_cpu(void *arg)
 457 {
 458         ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
 459 }
 460
 461 static inline void apic_clear_ibs_nmi_per_cpu(void *arg)
 462 {
 463         setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
 464 }
 465
 466 static int init_ibs_nmi(void)
 467 {
 468 #define IBSCTL_LVTOFFSETVAL             (1 << 8)
 469 #define IBSCTL                          0x1cc
 470         struct pci_dev *cpu_cfg;
 471         int nodes;
 472         u32 value = 0;
 473
 474         /* per CPU setup */
 475         on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1);
 476
 477         nodes = 0;
 478         cpu_cfg = NULL;
 479         do {
 480                 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
 481                                          PCI_DEVICE_ID_AMD_10H_NB_MISC,
 482                                          cpu_cfg);
 483                 if (!cpu_cfg)
 484                         break;
 485                 ++nodes;
 486                 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
 487                                        | IBSCTL_LVTOFFSETVAL);
 488                 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
 489                 if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) {
 490                         pci_dev_put(cpu_cfg);
 491                         printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
 492                                 "IBSCTL = 0x%08x", value);
 493                         return 1;
 494                 }
 495         } while (1);
 496
 497         if (!nodes) {
 498                 printk(KERN_DEBUG "No CPU node configured for IBS");
 499                 return 1;
 500         }
 501
 502         return 0;
 503 }
 504
 505 /* uninitialize the APIC for the IBS interrupts if needed */
 506 static void clear_ibs_nmi(void)
 507 {
 508         if (ibs_caps)
 509                 on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1);
 510 }
 511
 512 /* initialize the APIC for the IBS interrupts if available */
 513 static void ibs_init(void)
 514 {
 515         ibs_caps = get_ibs_caps();
 516
 517         if (!ibs_caps)
 518                 return;
 519
 520         if (init_ibs_nmi()) {
 521                 ibs_caps = 0;
 522                 return;
 523         }
 524
 525         printk(KERN_INFO "oprofile: AMD IBS detected (0x%08x)\n",
 526                (unsigned)ibs_caps);
 527 }
 528
 529 static void ibs_exit(void)
 530 {
 531         if (!ibs_caps)
 532                 return;
 533
 534         clear_ibs_nmi();
 535 }
 536
 537 static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
 538
 539 static int setup_ibs_files(struct super_block *sb, struct dentry *root)
 540 {
 541         struct dentry *dir;
 542         int ret = 0;
 543
 544         /* architecture specific files */
 545         if (create_arch_files)
 546                 ret = create_arch_files(sb, root);
 547
 548         if (ret)
 549                 return ret;
 550
 551         if (!ibs_caps)
 552                 return ret;
 553
 554         /* model specific files */
 555
 556         /* setup some reasonable defaults */
 557         ibs_config.max_cnt_fetch = 250000;
 558         ibs_config.fetch_enabled = 0;
 559         ibs_config.max_cnt_op = 250000;
 560         ibs_config.op_enabled = 0;
 561         ibs_config.dispatched_ops = 0;
 562
 563         dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
 564         oprofilefs_create_ulong(sb, dir, "enable",
 565                                 &ibs_config.fetch_enabled);
 566         oprofilefs_create_ulong(sb, dir, "max_count",
 567                                 &ibs_config.max_cnt_fetch);
 568         oprofilefs_create_ulong(sb, dir, "rand_enable",
 569                                 &ibs_config.rand_en);
 570
 571         dir = oprofilefs_mkdir(sb, root, "ibs_op");
 572         oprofilefs_create_ulong(sb, dir, "enable",
 573                                 &ibs_config.op_enabled);
 574         oprofilefs_create_ulong(sb, dir, "max_count",
 575                                 &ibs_config.max_cnt_op);
 576         if (ibs_caps & IBS_CAPS_OPCNT)
 577                 oprofilefs_create_ulong(sb, dir, "dispatched_ops",
 578                                         &ibs_config.dispatched_ops);
 579
 580         return 0;
 581 }
 582
 583 static int op_amd_init(struct oprofile_operations *ops)
 584 {
 585         ibs_init();
 586         create_arch_files = ops->create_files;
 587         ops->create_files = setup_ibs_files;
 588         return 0;
 589 }
 590
 591 static void op_amd_exit(void)
 592 {
 593         ibs_exit();
 594 }
 595
 596 struct op_x86_model_spec op_amd_spec = {
 597         .num_counters           = NUM_COUNTERS,
 598         .num_controls           = NUM_CONTROLS,
 599         .num_virt_counters      = NUM_VIRT_COUNTERS,
 600         .reserved               = MSR_AMD_EVENTSEL_RESERVED,
 601         .event_mask             = OP_EVENT_MASK,
 602         .init                   = op_amd_init,
 603         .exit                   = op_amd_exit,
 604         .fill_in_addresses      = &op_amd_fill_in_addresses,
 605         .setup_ctrs             = &op_amd_setup_ctrs,
 606         .check_ctrs             = &op_amd_check_ctrs,
 607         .start                  = &op_amd_start,
 608         .stop                   = &op_amd_stop,
 609         .shutdown               = &op_amd_shutdown,
 610 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 611         .switch_ctrl            = &op_mux_switch_ctrl,
 612 #endif
 613 };