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   1 /*
   2  * @file op_model_amd.c
   3  * athlon / K7 / K8 / Family 10h model-specific MSR operations
   4  *
   5  * @remark Copyright 2002-2009 OProfile authors
   6  * @remark Read the file COPYING
   7  *
   8  * @author John Levon
   9  * @author Philippe Elie
  10  * @author Graydon Hoare
  11  * @author Robert Richter <robert.richter@amd.com>
  12  * @author Barry Kasindorf <barry.kasindorf@amd.com>
  13  * @author Jason Yeh <jason.yeh@amd.com>
  14  * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
  15  */
  16
  17 #include <linux/oprofile.h>
  18 #include <linux/device.h>
  19 #include <linux/pci.h>
  20 #include <linux/percpu.h>
  21
  22 #include <asm/ptrace.h>
  23 #include <asm/msr.h>
  24 #include <asm/nmi.h>
  25 #include <asm/apic.h>
  26 #include <asm/processor.h>
  27 #include <asm/cpufeature.h>
  28
  29 #include "op_x86_model.h"
  30 #include "op_counter.h"
  31
  32 #define NUM_COUNTERS 4
  33 #define NUM_CONTROLS 4
  34 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
  35 #define NUM_VIRT_COUNTERS 32
  36 #define NUM_VIRT_CONTROLS 32
  37 #else
  38 #define NUM_VIRT_COUNTERS NUM_COUNTERS
  39 #define NUM_VIRT_CONTROLS NUM_CONTROLS
  40 #endif
  41
  42 #define OP_EVENT_MASK                   0x0FFF
  43 #define OP_CTR_OVERFLOW                 (1ULL<<31)
  44
  45 #define MSR_AMD_EVENTSEL_RESERVED       ((0xFFFFFCF0ULL<<32)|(1ULL<<21))
  46
  47 static unsigned long reset_value[NUM_VIRT_COUNTERS];
  48
  49 /* IbsFetchCtl bits/masks */
  50 #define IBS_FETCH_RAND_EN               (1ULL<<57)
  51 #define IBS_FETCH_VAL                   (1ULL<<49)
  52 #define IBS_FETCH_ENABLE                (1ULL<<48)
  53 #define IBS_FETCH_CNT_MASK              0xFFFF0000ULL
  54
  55 /* IbsOpCtl bits */
  56 #define IBS_OP_CNT_CTL                  (1ULL<<19)
  57 #define IBS_OP_VAL                      (1ULL<<18)
  58 #define IBS_OP_ENABLE                   (1ULL<<17)
  59
  60 #define IBS_FETCH_SIZE                  6
  61 #define IBS_OP_SIZE                     12
  62
  63 static u32 ibs_caps;
  64
  65 struct op_ibs_config {
  66         unsigned long op_enabled;
  67         unsigned long fetch_enabled;
  68         unsigned long max_cnt_fetch;
  69         unsigned long max_cnt_op;
  70         unsigned long rand_en;
  71         unsigned long dispatched_ops;
  72 };
  73
  74 static struct op_ibs_config ibs_config;
  75 static u64 ibs_op_ctl;
  76
  77 /*
  78  * IBS cpuid feature detection
  79  */
  80
  81 #define IBS_CPUID_FEATURES      0x8000001b
  82
  83 /*
  84  * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
  85  * bit 0 is used to indicate the existence of IBS.
  86  */
  87 #define IBS_CAPS_AVAIL                  (1LL<<0)
  88 #define IBS_CAPS_RDWROPCNT              (1LL<<3)
  89 #define IBS_CAPS_OPCNT                  (1LL<<4)
  90
  91 /*
  92  * IBS randomization macros
  93  */
  94 #define IBS_RANDOM_BITS                 12
  95 #define IBS_RANDOM_MASK                 ((1ULL << IBS_RANDOM_BITS) - 1)
  96 #define IBS_RANDOM_MAXCNT_OFFSET        (1ULL << (IBS_RANDOM_BITS - 5))
  97
  98 static u32 get_ibs_caps(void)
  99 {
 100         u32 ibs_caps;
 101         unsigned int max_level;
 102
 103         if (!boot_cpu_has(X86_FEATURE_IBS))
 104                 return 0;
 105
 106         /* check IBS cpuid feature flags */
 107         max_level = cpuid_eax(0x80000000);
 108         if (max_level < IBS_CPUID_FEATURES)
 109                 return IBS_CAPS_AVAIL;
 110
 111         ibs_caps = cpuid_eax(IBS_CPUID_FEATURES);
 112         if (!(ibs_caps & IBS_CAPS_AVAIL))
 113                 /* cpuid flags not valid */
 114                 return IBS_CAPS_AVAIL;
 115
 116         return ibs_caps;
 117 }
 118
 119 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 120
 121 static void op_mux_fill_in_addresses(struct op_msrs * const msrs)
 122 {
 123         int i;
 124
 125         for (i = 0; i < NUM_VIRT_COUNTERS; i++) {
 126                 int hw_counter = op_x86_virt_to_phys(i);
 127                 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
 128                         msrs->multiplex[i].addr = MSR_K7_PERFCTR0 + hw_counter;
 129                 else
 130                         msrs->multiplex[i].addr = 0;
 131         }
 132 }
 133
 134 static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
 135                                struct op_msrs const * const msrs)
 136 {
 137         u64 val;
 138         int i;
 139
 140         /* enable active counters */
 141         for (i = 0; i < NUM_COUNTERS; ++i) {
 142                 int virt = op_x86_phys_to_virt(i);
 143                 if (!counter_config[virt].enabled)
 144                         continue;
 145                 rdmsrl(msrs->controls[i].addr, val);
 146                 val &= model->reserved;
 147                 val |= op_x86_get_ctrl(model, &counter_config[virt]);
 148                 wrmsrl(msrs->controls[i].addr, val);
 149         }
 150 }
 151
 152 #else
 153
 154 static inline void op_mux_fill_in_addresses(struct op_msrs * const msrs) { }
 155
 156 #endif
 157
 158 /* functions for op_amd_spec */
 159
 160 static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
 161 {
 162         int i;
 163
 164         for (i = 0; i < NUM_COUNTERS; i++) {
 165                 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
 166                         msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
 167                 else
 168                         msrs->counters[i].addr = 0;
 169         }
 170
 171         for (i = 0; i < NUM_CONTROLS; i++) {
 172                 if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
 173                         msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
 174                 else
 175                         msrs->controls[i].addr = 0;
 176         }
 177
 178         op_mux_fill_in_addresses(msrs);
 179 }
 180
 181 static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
 182                               struct op_msrs const * const msrs)
 183 {
 184         u64 val;
 185         int i;
 186
 187         /* setup reset_value */
 188         for (i = 0; i < NUM_VIRT_COUNTERS; ++i) {
 189                 if (counter_config[i].enabled)
 190                         reset_value[i] = counter_config[i].count;
 191                 else
 192                         reset_value[i] = 0;
 193         }
 194
 195         /* clear all counters */
 196         for (i = 0; i < NUM_CONTROLS; ++i) {
 197                 if (unlikely(!msrs->controls[i].addr)) {
 198                         if (counter_config[i].enabled && !smp_processor_id())
 199                                 /*
 200                                  * counter is reserved, this is on all
 201                                  * cpus, so report only for cpu #0
 202                                  */
 203                                 op_x86_warn_reserved(i);
 204                         continue;
 205                 }
 206                 rdmsrl(msrs->controls[i].addr, val);
 207                 if (val & ARCH_PERFMON_EVENTSEL0_ENABLE)
 208                         op_x86_warn_in_use(i);
 209                 val &= model->reserved;
 210                 wrmsrl(msrs->controls[i].addr, val);
 211         }
 212
 213         /* avoid a false detection of ctr overflows in NMI handler */
 214         for (i = 0; i < NUM_COUNTERS; ++i) {
 215                 if (unlikely(!msrs->counters[i].addr))
 216                         continue;
 217                 wrmsrl(msrs->counters[i].addr, -1LL);
 218         }
 219
 220         /* enable active counters */
 221         for (i = 0; i < NUM_COUNTERS; ++i) {
 222                 int virt = op_x86_phys_to_virt(i);
 223                 if (!counter_config[virt].enabled)
 224                         continue;
 225                 if (!msrs->counters[i].addr)
 226                         continue;
 227
 228                 /* setup counter registers */
 229                 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
 230
 231                 /* setup control registers */
 232                 rdmsrl(msrs->controls[i].addr, val);
 233                 val &= model->reserved;
 234                 val |= op_x86_get_ctrl(model, &counter_config[virt]);
 235                 wrmsrl(msrs->controls[i].addr, val);
 236         }
 237 }
 238
 239 /*
 240  * 16-bit Linear Feedback Shift Register (LFSR)
 241  *
 242  *                       16   14   13    11
 243  * Feedback polynomial = X  + X  + X  +  X  + 1
 244  */
 245 static unsigned int lfsr_random(void)
 246 {
 247         static unsigned int lfsr_value = 0xF00D;
 248         unsigned int bit;
 249
 250         /* Compute next bit to shift in */
 251         bit = ((lfsr_value >> 0) ^
 252                (lfsr_value >> 2) ^
 253                (lfsr_value >> 3) ^
 254                (lfsr_value >> 5)) & 0x0001;
 255
 256         /* Advance to next register value */
 257         lfsr_value = (lfsr_value >> 1) | (bit << 15);
 258
 259         return lfsr_value;
 260 }
 261
 262 /*
 263  * IBS software randomization
 264  *
 265  * The IBS periodic op counter is randomized in software. The lower 12
 266  * bits of the 20 bit counter are randomized. IbsOpCurCnt is
 267  * initialized with a 12 bit random value.
 268  */
 269 static inline u64 op_amd_randomize_ibs_op(u64 val)
 270 {
 271         unsigned int random = lfsr_random();
 272
 273         if (!(ibs_caps & IBS_CAPS_RDWROPCNT))
 274                 /*
 275                  * Work around if the hw can not write to IbsOpCurCnt
 276                  *
 277                  * Randomize the lower 8 bits of the 16 bit
 278                  * IbsOpMaxCnt [15:0] value in the range of -128 to
 279                  * +127 by adding/subtracting an offset to the
 280                  * maximum count (IbsOpMaxCnt).
 281                  *
 282                  * To avoid over or underflows and protect upper bits
 283                  * starting at bit 16, the initial value for
 284                  * IbsOpMaxCnt must fit in the range from 0x0081 to
 285                  * 0xff80.
 286                  */
 287                 val += (s8)(random >> 4);
 288         else
 289                 val |= (u64)(random & IBS_RANDOM_MASK) << 32;
 290
 291         return val;
 292 }
 293
 294 static inline void
 295 op_amd_handle_ibs(struct pt_regs * const regs,
 296                   struct op_msrs const * const msrs)
 297 {
 298         u64 val, ctl;
 299         struct op_entry entry;
 300
 301         if (!ibs_caps)
 302                 return;
 303
 304         if (ibs_config.fetch_enabled) {
 305                 rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
 306                 if (ctl & IBS_FETCH_VAL) {
 307                         rdmsrl(MSR_AMD64_IBSFETCHLINAD, val);
 308                         oprofile_write_reserve(&entry, regs, val,
 309                                                IBS_FETCH_CODE, IBS_FETCH_SIZE);
 310                         oprofile_add_data64(&entry, val);
 311                         oprofile_add_data64(&entry, ctl);
 312                         rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val);
 313                         oprofile_add_data64(&entry, val);
 314                         oprofile_write_commit(&entry);
 315
 316                         /* reenable the IRQ */
 317                         ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT_MASK);
 318                         ctl |= IBS_FETCH_ENABLE;
 319                         wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
 320                 }
 321         }
 322
 323         if (ibs_config.op_enabled) {
 324                 rdmsrl(MSR_AMD64_IBSOPCTL, ctl);
 325                 if (ctl & IBS_OP_VAL) {
 326                         rdmsrl(MSR_AMD64_IBSOPRIP, val);
 327                         oprofile_write_reserve(&entry, regs, val,
 328                                                IBS_OP_CODE, IBS_OP_SIZE);
 329                         oprofile_add_data64(&entry, val);
 330                         rdmsrl(MSR_AMD64_IBSOPDATA, val);
 331                         oprofile_add_data64(&entry, val);
 332                         rdmsrl(MSR_AMD64_IBSOPDATA2, val);
 333                         oprofile_add_data64(&entry, val);
 334                         rdmsrl(MSR_AMD64_IBSOPDATA3, val);
 335                         oprofile_add_data64(&entry, val);
 336                         rdmsrl(MSR_AMD64_IBSDCLINAD, val);
 337                         oprofile_add_data64(&entry, val);
 338                         rdmsrl(MSR_AMD64_IBSDCPHYSAD, val);
 339                         oprofile_add_data64(&entry, val);
 340                         oprofile_write_commit(&entry);
 341
 342                         /* reenable the IRQ */
 343                         ctl = op_amd_randomize_ibs_op(ibs_op_ctl);
 344                         wrmsrl(MSR_AMD64_IBSOPCTL, ctl);
 345                 }
 346         }
 347 }
 348
 349 static inline void op_amd_start_ibs(void)
 350 {
 351         u64 val;
 352
 353         if (!ibs_caps)
 354                 return;
 355
 356         if (ibs_config.fetch_enabled) {
 357                 val = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
 358                 val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
 359                 val |= IBS_FETCH_ENABLE;
 360                 wrmsrl(MSR_AMD64_IBSFETCHCTL, val);
 361         }
 362
 363         if (ibs_config.op_enabled) {
 364                 ibs_op_ctl = ibs_config.max_cnt_op >> 4;
 365                 if (!(ibs_caps & IBS_CAPS_RDWROPCNT)) {
 366                         /*
 367                          * IbsOpCurCnt not supported.  See
 368                          * op_amd_randomize_ibs_op() for details.
 369                          */
 370                         ibs_op_ctl = clamp(ibs_op_ctl, 0x0081ULL, 0xFF80ULL);
 371                 } else {
 372                         /*
 373                          * The start value is randomized with a
 374                          * positive offset, we need to compensate it
 375                          * with the half of the randomized range. Also
 376                          * avoid underflows.
 377                          */
 378                         ibs_op_ctl = min(ibs_op_ctl + IBS_RANDOM_MAXCNT_OFFSET,
 379                                          0xFFFFULL);
 380                 }
 381                 if (ibs_caps & IBS_CAPS_OPCNT && ibs_config.dispatched_ops)
 382                         ibs_op_ctl |= IBS_OP_CNT_CTL;
 383                 ibs_op_ctl |= IBS_OP_ENABLE;
 384                 val = op_amd_randomize_ibs_op(ibs_op_ctl);
 385                 wrmsrl(MSR_AMD64_IBSOPCTL, val);
 386         }
 387 }
 388
 389 static void op_amd_stop_ibs(void)
 390 {
 391         if (!ibs_caps)
 392                 return;
 393
 394         if (ibs_config.fetch_enabled)
 395                 /* clear max count and enable */
 396                 wrmsrl(MSR_AMD64_IBSFETCHCTL, 0);
 397
 398         if (ibs_config.op_enabled)
 399                 /* clear max count and enable */
 400                 wrmsrl(MSR_AMD64_IBSOPCTL, 0);
 401 }
 402
 403 static int op_amd_check_ctrs(struct pt_regs * const regs,
 404                              struct op_msrs const * const msrs)
 405 {
 406         u64 val;
 407         int i;
 408
 409         for (i = 0; i < NUM_COUNTERS; ++i) {
 410                 int virt = op_x86_phys_to_virt(i);
 411                 if (!reset_value[virt])
 412                         continue;
 413                 rdmsrl(msrs->counters[i].addr, val);
 414                 /* bit is clear if overflowed: */
 415                 if (val & OP_CTR_OVERFLOW)
 416                         continue;
 417                 oprofile_add_sample(regs, virt);
 418                 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
 419         }
 420
 421         op_amd_handle_ibs(regs, msrs);
 422
 423         /* See op_model_ppro.c */
 424         return 1;
 425 }
 426
 427 static void op_amd_start(struct op_msrs const * const msrs)
 428 {
 429         u64 val;
 430         int i;
 431
 432         for (i = 0; i < NUM_COUNTERS; ++i) {
 433                 if (!reset_value[op_x86_phys_to_virt(i)])
 434                         continue;
 435                 rdmsrl(msrs->controls[i].addr, val);
 436                 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
 437                 wrmsrl(msrs->controls[i].addr, val);
 438         }
 439
 440         op_amd_start_ibs();
 441 }
 442
 443 static void op_amd_stop(struct op_msrs const * const msrs)
 444 {
 445         u64 val;
 446         int i;
 447
 448         /*
 449          * Subtle: stop on all counters to avoid race with setting our
 450          * pm callback
 451          */
 452         for (i = 0; i < NUM_COUNTERS; ++i) {
 453                 if (!reset_value[op_x86_phys_to_virt(i)])
 454                         continue;
 455                 rdmsrl(msrs->controls[i].addr, val);
 456                 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
 457                 wrmsrl(msrs->controls[i].addr, val);
 458         }
 459
 460         op_amd_stop_ibs();
 461 }
 462
 463 static void op_amd_shutdown(struct op_msrs const * const msrs)
 464 {
 465         int i;
 466
 467         for (i = 0; i < NUM_COUNTERS; ++i) {
 468                 if (msrs->counters[i].addr)
 469                         release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
 470         }
 471         for (i = 0; i < NUM_CONTROLS; ++i) {
 472                 if (msrs->controls[i].addr)
 473                         release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
 474         }
 475 }
 476
 477 static u8 ibs_eilvt_off;
 478
 479 static inline void apic_init_ibs_nmi_per_cpu(void *arg)
 480 {
 481         ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
 482 }
 483
 484 static inline void apic_clear_ibs_nmi_per_cpu(void *arg)
 485 {
 486         setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
 487 }
 488
 489 static int init_ibs_nmi(void)
 490 {
 491 #define IBSCTL_LVTOFFSETVAL             (1 << 8)
 492 #define IBSCTL                          0x1cc
 493         struct pci_dev *cpu_cfg;
 494         int nodes;
 495         u32 value = 0;
 496
 497         /* per CPU setup */
 498         on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1);
 499
 500         nodes = 0;
 501         cpu_cfg = NULL;
 502         do {
 503                 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
 504                                          PCI_DEVICE_ID_AMD_10H_NB_MISC,
 505                                          cpu_cfg);
 506                 if (!cpu_cfg)
 507                         break;
 508                 ++nodes;
 509                 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
 510                                        | IBSCTL_LVTOFFSETVAL);
 511                 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
 512                 if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) {
 513                         pci_dev_put(cpu_cfg);
 514                         printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
 515                                 "IBSCTL = 0x%08x", value);
 516                         return 1;
 517                 }
 518         } while (1);
 519
 520         if (!nodes) {
 521                 printk(KERN_DEBUG "No CPU node configured for IBS");
 522                 return 1;
 523         }
 524
 525         return 0;
 526 }
 527
 528 /* uninitialize the APIC for the IBS interrupts if needed */
 529 static void clear_ibs_nmi(void)
 530 {
 531         if (ibs_caps)
 532                 on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1);
 533 }
 534
 535 /* initialize the APIC for the IBS interrupts if available */
 536 static void ibs_init(void)
 537 {
 538         ibs_caps = get_ibs_caps();
 539
 540         if (!ibs_caps)
 541                 return;
 542
 543         if (init_ibs_nmi()) {
 544                 ibs_caps = 0;
 545                 return;
 546         }
 547
 548         printk(KERN_INFO "oprofile: AMD IBS detected (0x%08x)\n",
 549                (unsigned)ibs_caps);
 550 }
 551
 552 static void ibs_exit(void)
 553 {
 554         if (!ibs_caps)
 555                 return;
 556
 557         clear_ibs_nmi();
 558 }
 559
 560 static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
 561
 562 static int setup_ibs_files(struct super_block *sb, struct dentry *root)
 563 {
 564         struct dentry *dir;
 565         int ret = 0;
 566
 567         /* architecture specific files */
 568         if (create_arch_files)
 569                 ret = create_arch_files(sb, root);
 570
 571         if (ret)
 572                 return ret;
 573
 574         if (!ibs_caps)
 575                 return ret;
 576
 577         /* model specific files */
 578
 579         /* setup some reasonable defaults */
 580         ibs_config.max_cnt_fetch = 250000;
 581         ibs_config.fetch_enabled = 0;
 582         ibs_config.max_cnt_op = 250000;
 583         ibs_config.op_enabled = 0;
 584         ibs_config.dispatched_ops = 0;
 585
 586         dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
 587         oprofilefs_create_ulong(sb, dir, "enable",
 588                                 &ibs_config.fetch_enabled);
 589         oprofilefs_create_ulong(sb, dir, "max_count",
 590                                 &ibs_config.max_cnt_fetch);
 591         oprofilefs_create_ulong(sb, dir, "rand_enable",
 592                                 &ibs_config.rand_en);
 593
 594         dir = oprofilefs_mkdir(sb, root, "ibs_op");
 595         oprofilefs_create_ulong(sb, dir, "enable",
 596                                 &ibs_config.op_enabled);
 597         oprofilefs_create_ulong(sb, dir, "max_count",
 598                                 &ibs_config.max_cnt_op);
 599         if (ibs_caps & IBS_CAPS_OPCNT)
 600                 oprofilefs_create_ulong(sb, dir, "dispatched_ops",
 601                                         &ibs_config.dispatched_ops);
 602
 603         return 0;
 604 }
 605
 606 static int op_amd_init(struct oprofile_operations *ops)
 607 {
 608         ibs_init();
 609         create_arch_files = ops->create_files;
 610         ops->create_files = setup_ibs_files;
 611         return 0;
 612 }
 613
 614 static void op_amd_exit(void)
 615 {
 616         ibs_exit();
 617 }
 618
 619 struct op_x86_model_spec op_amd_spec = {
 620         .num_counters           = NUM_COUNTERS,
 621         .num_controls           = NUM_CONTROLS,
 622         .num_virt_counters      = NUM_VIRT_COUNTERS,
 623         .reserved               = MSR_AMD_EVENTSEL_RESERVED,
 624         .event_mask             = OP_EVENT_MASK,
 625         .init                   = op_amd_init,
 626         .exit                   = op_amd_exit,
 627         .fill_in_addresses      = &op_amd_fill_in_addresses,
 628         .setup_ctrs             = &op_amd_setup_ctrs,
 629         .check_ctrs             = &op_amd_check_ctrs,
 630         .start                  = &op_amd_start,
 631         .stop                   = &op_amd_stop,
 632         .shutdown               = &op_amd_shutdown,
 633 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 634         .switch_ctrl            = &op_mux_switch_ctrl,
 635 #endif
 636 };