SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/x86/oprofile/op_model_amd.c

   1 /*
   2  * @file op_model_amd.c
   3  * athlon / K7 / K8 / Family 10h model-specific MSR operations
   4  *
   5  * @remark Copyright 2002-2009 OProfile authors
   6  * @remark Read the file COPYING
   7  *
   8  * @author John Levon
   9  * @author Philippe Elie
  10  * @author Graydon Hoare
  11  * @author Robert Richter <robert.richter@amd.com>
  12  * @author Barry Kasindorf
  13  */
  14
  15 #include <linux/oprofile.h>
  16 #include <linux/device.h>
  17 #include <linux/pci.h>
  18
  19 #include <asm/ptrace.h>
  20 #include <asm/msr.h>
  21 #include <asm/nmi.h>
  22
  23 #include "op_x86_model.h"
  24 #include "op_counter.h"
  25
  26 #define NUM_COUNTERS 4
  27 #define NUM_CONTROLS 4
  28
  29 #define CTR_READ(l, h, msrs, c) do {rdmsr(msrs->counters[(c)].addr, (l), (h)); } while (0)
  30 #define CTR_WRITE(l, msrs, c) do {wrmsr(msrs->counters[(c)].addr, -(unsigned int)(l), -1); } while (0)
  31 #define CTR_OVERFLOWED(n) (!((n) & (1U<<31)))
  32
  33 #define CTRL_READ(l, h, msrs, c) do {rdmsr(msrs->controls[(c)].addr, (l), (h)); } while (0)
  34 #define CTRL_WRITE(l, h, msrs, c) do {wrmsr(msrs->controls[(c)].addr, (l), (h)); } while (0)
  35 #define CTRL_CLEAR_LO(x) (x &= (1<<21))
  36 #define CTRL_CLEAR_HI(x) (x &= 0xfffffcf0)
  37 #define CTRL_SET_EVENT_LOW(val, e) (val |= (e & 0xff))
  38 #define CTRL_SET_EVENT_HIGH(val, e) (val |= ((e >> 8) & 0xf))
  39 #define CTRL_SET_HOST_ONLY(val, h) (val |= ((h & 1) << 9))
  40 #define CTRL_SET_GUEST_ONLY(val, h) (val |= ((h & 1) << 8))
  41
  42 static unsigned long reset_value[NUM_COUNTERS];
  43
  44 #ifdef CONFIG_OPROFILE_IBS
  45
  46 /* IbsFetchCtl bits/masks */
  47 #define IBS_FETCH_HIGH_VALID_BIT        (1UL << 17)     /* bit 49 */
  48 #define IBS_FETCH_HIGH_ENABLE           (1UL << 16)     /* bit 48 */
  49 #define IBS_FETCH_LOW_MAX_CNT_MASK      0x0000FFFFUL    /* MaxCnt mask */
  50
  51 /*IbsOpCtl bits */
  52 #define IBS_OP_LOW_VALID_BIT            (1ULL<<18)      /* bit 18 */
  53 #define IBS_OP_LOW_ENABLE               (1ULL<<17)      /* bit 17 */
  54
  55 #define IBS_FETCH_SIZE  6
  56 #define IBS_OP_SIZE     12
  57
  58 static int has_ibs;     /* AMD Family10h and later */
  59
  60 struct op_ibs_config {
  61         unsigned long op_enabled;
  62         unsigned long fetch_enabled;
  63         unsigned long max_cnt_fetch;
  64         unsigned long max_cnt_op;
  65         unsigned long rand_en;
  66         unsigned long dispatched_ops;
  67 };
  68
  69 static struct op_ibs_config ibs_config;
  70
  71 #endif
  72
  73 /* functions for op_amd_spec */
  74
  75 static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
  76 {
  77         int i;
  78
  79         for (i = 0; i < NUM_COUNTERS; i++) {
  80                 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
  81                         msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
  82                 else
  83                         msrs->counters[i].addr = 0;
  84         }
  85
  86         for (i = 0; i < NUM_CONTROLS; i++) {
  87                 if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
  88                         msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
  89                 else
  90                         msrs->controls[i].addr = 0;
  91         }
  92 }
  93
  94
  95 static void op_amd_setup_ctrs(struct op_msrs const * const msrs)
  96 {
  97         unsigned int low, high;
  98         int i;
  99
 100         /* clear all counters */
 101         for (i = 0 ; i < NUM_CONTROLS; ++i) {
 102                 if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
 103                         continue;
 104                 CTRL_READ(low, high, msrs, i);
 105                 CTRL_CLEAR_LO(low);
 106                 CTRL_CLEAR_HI(high);
 107                 CTRL_WRITE(low, high, msrs, i);
 108         }
 109
 110         /* avoid a false detection of ctr overflows in NMI handler */
 111         for (i = 0; i < NUM_COUNTERS; ++i) {
 112                 if (unlikely(!CTR_IS_RESERVED(msrs, i)))
 113                         continue;
 114                 CTR_WRITE(1, msrs, i);
 115         }
 116
 117         /* enable active counters */
 118         for (i = 0; i < NUM_COUNTERS; ++i) {
 119                 if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) {
 120                         reset_value[i] = counter_config[i].count;
 121
 122                         CTR_WRITE(counter_config[i].count, msrs, i);
 123
 124                         CTRL_READ(low, high, msrs, i);
 125                         CTRL_CLEAR_LO(low);
 126                         CTRL_CLEAR_HI(high);
 127                         CTRL_SET_ENABLE(low);
 128                         CTRL_SET_USR(low, counter_config[i].user);
 129                         CTRL_SET_KERN(low, counter_config[i].kernel);
 130                         CTRL_SET_UM(low, counter_config[i].unit_mask);
 131                         CTRL_SET_EVENT_LOW(low, counter_config[i].event);
 132                         CTRL_SET_EVENT_HIGH(high, counter_config[i].event);
 133                         CTRL_SET_HOST_ONLY(high, 0);
 134                         CTRL_SET_GUEST_ONLY(high, 0);
 135
 136                         CTRL_WRITE(low, high, msrs, i);
 137                 } else {
 138                         reset_value[i] = 0;
 139                 }
 140         }
 141 }
 142
 143 #ifdef CONFIG_OPROFILE_IBS
 144
 145 static inline int
 146 op_amd_handle_ibs(struct pt_regs * const regs,
 147                   struct op_msrs const * const msrs)
 148 {
 149         u32 low, high;
 150         u64 msr;
 151         struct op_entry entry;
 152
 153         if (!has_ibs)
 154                 return 1;
 155
 156         if (ibs_config.fetch_enabled) {
 157                 rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
 158                 if (high & IBS_FETCH_HIGH_VALID_BIT) {
 159                         rdmsrl(MSR_AMD64_IBSFETCHLINAD, msr);
 160                         oprofile_write_reserve(&entry, regs, msr,
 161                                                IBS_FETCH_CODE, IBS_FETCH_SIZE);
 162                         oprofile_add_data(&entry, (u32)msr);
 163                         oprofile_add_data(&entry, (u32)(msr >> 32));
 164                         oprofile_add_data(&entry, low);
 165                         oprofile_add_data(&entry, high);
 166                         rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, msr);
 167                         oprofile_add_data(&entry, (u32)msr);
 168                         oprofile_add_data(&entry, (u32)(msr >> 32));
 169                         oprofile_write_commit(&entry);
 170
 171                         /* reenable the IRQ */
 172                         high &= ~IBS_FETCH_HIGH_VALID_BIT;
 173                         high |= IBS_FETCH_HIGH_ENABLE;
 174                         low &= IBS_FETCH_LOW_MAX_CNT_MASK;
 175                         wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
 176                 }
 177         }
 178
 179         if (ibs_config.op_enabled) {
 180                 rdmsr(MSR_AMD64_IBSOPCTL, low, high);
 181                 if (low & IBS_OP_LOW_VALID_BIT) {
 182                         rdmsrl(MSR_AMD64_IBSOPRIP, msr);
 183                         oprofile_write_reserve(&entry, regs, msr,
 184                                                IBS_OP_CODE, IBS_OP_SIZE);
 185                         oprofile_add_data(&entry, (u32)msr);
 186                         oprofile_add_data(&entry, (u32)(msr >> 32));
 187                         rdmsrl(MSR_AMD64_IBSOPDATA, msr);
 188                         oprofile_add_data(&entry, (u32)msr);
 189                         oprofile_add_data(&entry, (u32)(msr >> 32));
 190                         rdmsrl(MSR_AMD64_IBSOPDATA2, msr);
 191                         oprofile_add_data(&entry, (u32)msr);
 192                         oprofile_add_data(&entry, (u32)(msr >> 32));
 193                         rdmsrl(MSR_AMD64_IBSOPDATA3, msr);
 194                         oprofile_add_data(&entry, (u32)msr);
 195                         oprofile_add_data(&entry, (u32)(msr >> 32));
 196                         rdmsrl(MSR_AMD64_IBSDCLINAD, msr);
 197                         oprofile_add_data(&entry, (u32)msr);
 198                         oprofile_add_data(&entry, (u32)(msr >> 32));
 199                         rdmsrl(MSR_AMD64_IBSDCPHYSAD, msr);
 200                         oprofile_add_data(&entry, (u32)msr);
 201                         oprofile_add_data(&entry, (u32)(msr >> 32));
 202                         oprofile_write_commit(&entry);
 203
 204                         /* reenable the IRQ */
 205                         high = 0;
 206                         low &= ~IBS_OP_LOW_VALID_BIT;
 207                         low |= IBS_OP_LOW_ENABLE;
 208                         wrmsr(MSR_AMD64_IBSOPCTL, low, high);
 209                 }
 210         }
 211
 212         return 1;
 213 }
 214
 215 static inline void op_amd_start_ibs(void)
 216 {
 217         unsigned int low, high;
 218         if (has_ibs && ibs_config.fetch_enabled) {
 219                 low = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
 220                 high = ((ibs_config.rand_en & 0x1) << 25) /* bit 57 */
 221                         + IBS_FETCH_HIGH_ENABLE;
 222                 wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
 223         }
 224
 225         if (has_ibs && ibs_config.op_enabled) {
 226                 low = ((ibs_config.max_cnt_op >> 4) & 0xFFFF)
 227                         + ((ibs_config.dispatched_ops & 0x1) << 19) /* bit 19 */
 228                         + IBS_OP_LOW_ENABLE;
 229                 high = 0;
 230                 wrmsr(MSR_AMD64_IBSOPCTL, low, high);
 231         }
 232 }
 233
 234 static void op_amd_stop_ibs(void)
 235 {
 236         unsigned int low, high;
 237         if (has_ibs && ibs_config.fetch_enabled) {
 238                 /* clear max count and enable */
 239                 low = 0;
 240                 high = 0;
 241                 wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
 242         }
 243
 244         if (has_ibs && ibs_config.op_enabled) {
 245                 /* clear max count and enable */
 246                 low = 0;
 247                 high = 0;
 248                 wrmsr(MSR_AMD64_IBSOPCTL, low, high);
 249         }
 250 }
 251
 252 #else
 253
 254 static inline int op_amd_handle_ibs(struct pt_regs * const regs,
 255                                     struct op_msrs const * const msrs) { }
 256 static inline void op_amd_start_ibs(void) { }
 257 static inline void op_amd_stop_ibs(void) { }
 258
 259 #endif
 260
 261 static int op_amd_check_ctrs(struct pt_regs * const regs,
 262                              struct op_msrs const * const msrs)
 263 {
 264         unsigned int low, high;
 265         int i;
 266
 267         for (i = 0 ; i < NUM_COUNTERS; ++i) {
 268                 if (!reset_value[i])
 269                         continue;
 270                 CTR_READ(low, high, msrs, i);
 271                 if (CTR_OVERFLOWED(low)) {
 272                         oprofile_add_sample(regs, i);
 273                         CTR_WRITE(reset_value[i], msrs, i);
 274                 }
 275         }
 276
 277         op_amd_handle_ibs(regs, msrs);
 278
 279         /* See op_model_ppro.c */
 280         return 1;
 281 }
 282
 283 static void op_amd_start(struct op_msrs const * const msrs)
 284 {
 285         unsigned int low, high;
 286         int i;
 287         for (i = 0 ; i < NUM_COUNTERS ; ++i) {
 288                 if (reset_value[i]) {
 289                         CTRL_READ(low, high, msrs, i);
 290                         CTRL_SET_ACTIVE(low);
 291                         CTRL_WRITE(low, high, msrs, i);
 292                 }
 293         }
 294
 295         op_amd_start_ibs();
 296 }
 297
 298 static void op_amd_stop(struct op_msrs const * const msrs)
 299 {
 300         unsigned int low, high;
 301         int i;
 302
 303         /*
 304          * Subtle: stop on all counters to avoid race with setting our
 305          * pm callback
 306          */
 307         for (i = 0 ; i < NUM_COUNTERS ; ++i) {
 308                 if (!reset_value[i])
 309                         continue;
 310                 CTRL_READ(low, high, msrs, i);
 311                 CTRL_SET_INACTIVE(low);
 312                 CTRL_WRITE(low, high, msrs, i);
 313         }
 314
 315         op_amd_stop_ibs();
 316 }
 317
 318 static void op_amd_shutdown(struct op_msrs const * const msrs)
 319 {
 320         int i;
 321
 322         for (i = 0 ; i < NUM_COUNTERS ; ++i) {
 323                 if (CTR_IS_RESERVED(msrs, i))
 324                         release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
 325         }
 326         for (i = 0 ; i < NUM_CONTROLS ; ++i) {
 327                 if (CTRL_IS_RESERVED(msrs, i))
 328                         release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
 329         }
 330 }
 331
 332 #ifdef CONFIG_OPROFILE_IBS
 333
 334 static u8 ibs_eilvt_off;
 335
 336 static inline void apic_init_ibs_nmi_per_cpu(void *arg)
 337 {
 338         ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
 339 }
 340
 341 static inline void apic_clear_ibs_nmi_per_cpu(void *arg)
 342 {
 343         setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
 344 }
 345
 346 static int init_ibs_nmi(void)
 347 {
 348 #define IBSCTL_LVTOFFSETVAL             (1 << 8)
 349 #define IBSCTL                          0x1cc
 350         struct pci_dev *cpu_cfg;
 351         int nodes;
 352         u32 value = 0;
 353
 354         /* per CPU setup */
 355         on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1);
 356
 357         nodes = 0;
 358         cpu_cfg = NULL;
 359         do {
 360                 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
 361                                          PCI_DEVICE_ID_AMD_10H_NB_MISC,
 362                                          cpu_cfg);
 363                 if (!cpu_cfg)
 364                         break;
 365                 ++nodes;
 366                 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
 367                                        | IBSCTL_LVTOFFSETVAL);
 368                 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
 369                 if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) {
 370                         pci_dev_put(cpu_cfg);
 371                         printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
 372                                 "IBSCTL = 0x%08x", value);
 373                         return 1;
 374                 }
 375         } while (1);
 376
 377         if (!nodes) {
 378                 printk(KERN_DEBUG "No CPU node configured for IBS");
 379                 return 1;
 380         }
 381
 382 #ifdef CONFIG_NUMA
 383         /* Sanity check */
 384         /* Works only for 64bit with proper numa implementation. */
 385         if (nodes != num_possible_nodes()) {
 386                 printk(KERN_DEBUG "Failed to setup CPU node(s) for IBS, "
 387                         "found: %d, expected %d",
 388                         nodes, num_possible_nodes());
 389                 return 1;
 390         }
 391 #endif
 392         return 0;
 393 }
 394
 395 /* uninitialize the APIC for the IBS interrupts if needed */
 396 static void clear_ibs_nmi(void)
 397 {
 398         if (has_ibs)
 399                 on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1);
 400 }
 401
 402 /* initialize the APIC for the IBS interrupts if available */
 403 static void ibs_init(void)
 404 {
 405         has_ibs = boot_cpu_has(X86_FEATURE_IBS);
 406
 407         if (!has_ibs)
 408                 return;
 409
 410         if (init_ibs_nmi()) {
 411                 has_ibs = 0;
 412                 return;
 413         }
 414
 415         printk(KERN_INFO "oprofile: AMD IBS detected\n");
 416 }
 417
 418 static void ibs_exit(void)
 419 {
 420         if (!has_ibs)
 421                 return;
 422
 423         clear_ibs_nmi();
 424 }
 425
 426 static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
 427
 428 static int setup_ibs_files(struct super_block *sb, struct dentry *root)
 429 {
 430         struct dentry *dir;
 431         int ret = 0;
 432
 433         /* architecture specific files */
 434         if (create_arch_files)
 435                 ret = create_arch_files(sb, root);
 436
 437         if (ret)
 438                 return ret;
 439
 440         if (!has_ibs)
 441                 return ret;
 442
 443         /* model specific files */
 444
 445         /* setup some reasonable defaults */
 446         ibs_config.max_cnt_fetch = 250000;
 447         ibs_config.fetch_enabled = 0;
 448         ibs_config.max_cnt_op = 250000;
 449         ibs_config.op_enabled = 0;
 450         ibs_config.dispatched_ops = 1;
 451
 452         dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
 453         oprofilefs_create_ulong(sb, dir, "enable",
 454                                 &ibs_config.fetch_enabled);
 455         oprofilefs_create_ulong(sb, dir, "max_count",
 456                                 &ibs_config.max_cnt_fetch);
 457         oprofilefs_create_ulong(sb, dir, "rand_enable",
 458                                 &ibs_config.rand_en);
 459
 460         dir = oprofilefs_mkdir(sb, root, "ibs_op");
 461         oprofilefs_create_ulong(sb, dir, "enable",
 462                                 &ibs_config.op_enabled);
 463         oprofilefs_create_ulong(sb, dir, "max_count",
 464                                 &ibs_config.max_cnt_op);
 465         oprofilefs_create_ulong(sb, dir, "dispatched_ops",
 466                                 &ibs_config.dispatched_ops);
 467
 468         return 0;
 469 }
 470
 471 static int op_amd_init(struct oprofile_operations *ops)
 472 {
 473         ibs_init();
 474         create_arch_files = ops->create_files;
 475         ops->create_files = setup_ibs_files;
 476         return 0;
 477 }
 478
 479 static void op_amd_exit(void)
 480 {
 481         ibs_exit();
 482 }
 483
 484 #else
 485
 486 /* no IBS support */
 487
 488 static int op_amd_init(struct oprofile_operations *ops)
 489 {
 490         return 0;
 491 }
 492
 493 static void op_amd_exit(void) {}
 494
 495 #endif /* CONFIG_OPROFILE_IBS */
 496
 497 struct op_x86_model_spec const op_amd_spec = {
 498         .init                   = op_amd_init,
 499         .exit                   = op_amd_exit,
 500         .num_counters           = NUM_COUNTERS,
 501         .num_controls           = NUM_CONTROLS,
 502         .fill_in_addresses      = &op_amd_fill_in_addresses,
 503         .setup_ctrs             = &op_amd_setup_ctrs,
 504         .check_ctrs             = &op_amd_check_ctrs,
 505         .start                  = &op_amd_start,
 506         .stop                   = &op_amd_stop,
 507         .shutdown               = &op_amd_shutdown
 508 };