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   1 /*
   2  * @file op_model_amd.c
   3  * athlon / K7 / K8 / Family 10h model-specific MSR operations
   4  *
   5  * @remark Copyright 2002-2009 OProfile authors
   6  * @remark Read the file COPYING
   7  *
   8  * @author John Levon
   9  * @author Philippe Elie
  10  * @author Graydon Hoare
  11  * @author Robert Richter <robert.richter@amd.com>
  12  * @author Barry Kasindorf <barry.kasindorf@amd.com>
  13  * @author Jason Yeh <jason.yeh@amd.com>
  14  * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
  15  */
  16
  17 #include <linux/oprofile.h>
  18 #include <linux/device.h>
  19 #include <linux/pci.h>
  20 #include <linux/percpu.h>
  21
  22 #include <asm/ptrace.h>
  23 #include <asm/msr.h>
  24 #include <asm/nmi.h>
  25 #include <asm/apic.h>
  26 #include <asm/processor.h>
  27 #include <asm/cpufeature.h>
  28
  29 #include "op_x86_model.h"
  30 #include "op_counter.h"
  31
  32 #define NUM_COUNTERS 4
  33 #define NUM_CONTROLS 4
  34 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
  35 #define NUM_VIRT_COUNTERS 32
  36 #define NUM_VIRT_CONTROLS 32
  37 #else
  38 #define NUM_VIRT_COUNTERS NUM_COUNTERS
  39 #define NUM_VIRT_CONTROLS NUM_CONTROLS
  40 #endif
  41
  42 #define OP_EVENT_MASK                   0x0FFF
  43 #define OP_CTR_OVERFLOW                 (1ULL<<31)
  44
  45 #define MSR_AMD_EVENTSEL_RESERVED       ((0xFFFFFCF0ULL<<32)|(1ULL<<21))
  46
  47 static unsigned long reset_value[NUM_VIRT_COUNTERS];
  48
  49 /* IbsFetchCtl bits/masks */
  50 #define IBS_FETCH_RAND_EN               (1ULL<<57)
  51 #define IBS_FETCH_VAL                   (1ULL<<49)
  52 #define IBS_FETCH_ENABLE                (1ULL<<48)
  53 #define IBS_FETCH_CNT_MASK              0xFFFF0000ULL
  54
  55 /* IbsOpCtl bits */
  56 #define IBS_OP_CNT_CTL                  (1ULL<<19)
  57 #define IBS_OP_VAL                      (1ULL<<18)
  58 #define IBS_OP_ENABLE                   (1ULL<<17)
  59
  60 #define IBS_FETCH_SIZE                  6
  61 #define IBS_OP_SIZE                     12
  62
  63 static u32 ibs_caps;
  64
  65 struct op_ibs_config {
  66         unsigned long op_enabled;
  67         unsigned long fetch_enabled;
  68         unsigned long max_cnt_fetch;
  69         unsigned long max_cnt_op;
  70         unsigned long rand_en;
  71         unsigned long dispatched_ops;
  72 };
  73
  74 static struct op_ibs_config ibs_config;
  75 static u64 ibs_op_ctl;
  76
  77 /*
  78  * IBS cpuid feature detection
  79  */
  80
  81 #define IBS_CPUID_FEATURES      0x8000001b
  82
  83 /*
  84  * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
  85  * bit 0 is used to indicate the existence of IBS.
  86  */
  87 #define IBS_CAPS_AVAIL                  (1LL<<0)
  88 #define IBS_CAPS_RDWROPCNT              (1LL<<3)
  89 #define IBS_CAPS_OPCNT                  (1LL<<4)
  90
  91 /*
  92  * IBS randomization macros
  93  */
  94 #define IBS_RANDOM_BITS                 12
  95 #define IBS_RANDOM_MASK                 ((1ULL << IBS_RANDOM_BITS) - 1)
  96 #define IBS_RANDOM_MAXCNT_OFFSET        (1ULL << (IBS_RANDOM_BITS - 5))
  97
  98 static u32 get_ibs_caps(void)
  99 {
 100         u32 ibs_caps;
 101         unsigned int max_level;
 102
 103         if (!boot_cpu_has(X86_FEATURE_IBS))
 104                 return 0;
 105
 106         /* check IBS cpuid feature flags */
 107         max_level = cpuid_eax(0x80000000);
 108         if (max_level < IBS_CPUID_FEATURES)
 109                 return IBS_CAPS_AVAIL;
 110
 111         ibs_caps = cpuid_eax(IBS_CPUID_FEATURES);
 112         if (!(ibs_caps & IBS_CAPS_AVAIL))
 113                 /* cpuid flags not valid */
 114                 return IBS_CAPS_AVAIL;
 115
 116         return ibs_caps;
 117 }
 118
 119 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 120
 121 static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
 122                                struct op_msrs const * const msrs)
 123 {
 124         u64 val;
 125         int i;
 126
 127         /* enable active counters */
 128         for (i = 0; i < NUM_COUNTERS; ++i) {
 129                 int virt = op_x86_phys_to_virt(i);
 130                 if (!counter_config[virt].enabled)
 131                         continue;
 132                 rdmsrl(msrs->controls[i].addr, val);
 133                 val &= model->reserved;
 134                 val |= op_x86_get_ctrl(model, &counter_config[virt]);
 135                 wrmsrl(msrs->controls[i].addr, val);
 136         }
 137 }
 138
 139 #endif
 140
 141 /* functions for op_amd_spec */
 142
 143 static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
 144 {
 145         int i;
 146
 147         for (i = 0; i < NUM_COUNTERS; i++) {
 148                 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
 149                         msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
 150                 else
 151                         msrs->counters[i].addr = 0;
 152         }
 153
 154         for (i = 0; i < NUM_CONTROLS; i++) {
 155                 if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
 156                         msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
 157                 else
 158                         msrs->controls[i].addr = 0;
 159         }
 160 }
 161
 162 static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
 163                               struct op_msrs const * const msrs)
 164 {
 165         u64 val;
 166         int i;
 167
 168         /* setup reset_value */
 169         for (i = 0; i < NUM_VIRT_COUNTERS; ++i) {
 170                 if (counter_config[i].enabled)
 171                         reset_value[i] = counter_config[i].count;
 172                 else
 173                         reset_value[i] = 0;
 174         }
 175
 176         /* clear all counters */
 177         for (i = 0; i < NUM_CONTROLS; ++i) {
 178                 if (unlikely(!msrs->controls[i].addr)) {
 179                         if (counter_config[i].enabled && !smp_processor_id())
 180                                 /*
 181                                  * counter is reserved, this is on all
 182                                  * cpus, so report only for cpu #0
 183                                  */
 184                                 op_x86_warn_reserved(i);
 185                         continue;
 186                 }
 187                 rdmsrl(msrs->controls[i].addr, val);
 188                 if (val & ARCH_PERFMON_EVENTSEL0_ENABLE)
 189                         op_x86_warn_in_use(i);
 190                 val &= model->reserved;
 191                 wrmsrl(msrs->controls[i].addr, val);
 192         }
 193
 194         /* avoid a false detection of ctr overflows in NMI handler */
 195         for (i = 0; i < NUM_COUNTERS; ++i) {
 196                 if (unlikely(!msrs->counters[i].addr))
 197                         continue;
 198                 wrmsrl(msrs->counters[i].addr, -1LL);
 199         }
 200
 201         /* enable active counters */
 202         for (i = 0; i < NUM_COUNTERS; ++i) {
 203                 int virt = op_x86_phys_to_virt(i);
 204                 if (!counter_config[virt].enabled)
 205                         continue;
 206                 if (!msrs->counters[i].addr)
 207                         continue;
 208
 209                 /* setup counter registers */
 210                 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
 211
 212                 /* setup control registers */
 213                 rdmsrl(msrs->controls[i].addr, val);
 214                 val &= model->reserved;
 215                 val |= op_x86_get_ctrl(model, &counter_config[virt]);
 216                 wrmsrl(msrs->controls[i].addr, val);
 217         }
 218 }
 219
 220 /*
 221  * 16-bit Linear Feedback Shift Register (LFSR)
 222  *
 223  *                       16   14   13    11
 224  * Feedback polynomial = X  + X  + X  +  X  + 1
 225  */
 226 static unsigned int lfsr_random(void)
 227 {
 228         static unsigned int lfsr_value = 0xF00D;
 229         unsigned int bit;
 230
 231         /* Compute next bit to shift in */
 232         bit = ((lfsr_value >> 0) ^
 233                (lfsr_value >> 2) ^
 234                (lfsr_value >> 3) ^
 235                (lfsr_value >> 5)) & 0x0001;
 236
 237         /* Advance to next register value */
 238         lfsr_value = (lfsr_value >> 1) | (bit << 15);
 239
 240         return lfsr_value;
 241 }
 242
 243 /*
 244  * IBS software randomization
 245  *
 246  * The IBS periodic op counter is randomized in software. The lower 12
 247  * bits of the 20 bit counter are randomized. IbsOpCurCnt is
 248  * initialized with a 12 bit random value.
 249  */
 250 static inline u64 op_amd_randomize_ibs_op(u64 val)
 251 {
 252         unsigned int random = lfsr_random();
 253
 254         if (!(ibs_caps & IBS_CAPS_RDWROPCNT))
 255                 /*
 256                  * Work around if the hw can not write to IbsOpCurCnt
 257                  *
 258                  * Randomize the lower 8 bits of the 16 bit
 259                  * IbsOpMaxCnt [15:0] value in the range of -128 to
 260                  * +127 by adding/subtracting an offset to the
 261                  * maximum count (IbsOpMaxCnt).
 262                  *
 263                  * To avoid over or underflows and protect upper bits
 264                  * starting at bit 16, the initial value for
 265                  * IbsOpMaxCnt must fit in the range from 0x0081 to
 266                  * 0xff80.
 267                  */
 268                 val += (s8)(random >> 4);
 269         else
 270                 val |= (u64)(random & IBS_RANDOM_MASK) << 32;
 271
 272         return val;
 273 }
 274
 275 static inline void
 276 op_amd_handle_ibs(struct pt_regs * const regs,
 277                   struct op_msrs const * const msrs)
 278 {
 279         u64 val, ctl;
 280         struct op_entry entry;
 281
 282         if (!ibs_caps)
 283                 return;
 284
 285         if (ibs_config.fetch_enabled) {
 286                 rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
 287                 if (ctl & IBS_FETCH_VAL) {
 288                         rdmsrl(MSR_AMD64_IBSFETCHLINAD, val);
 289                         oprofile_write_reserve(&entry, regs, val,
 290                                                IBS_FETCH_CODE, IBS_FETCH_SIZE);
 291                         oprofile_add_data64(&entry, val);
 292                         oprofile_add_data64(&entry, ctl);
 293                         rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val);
 294                         oprofile_add_data64(&entry, val);
 295                         oprofile_write_commit(&entry);
 296
 297                         /* reenable the IRQ */
 298                         ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT_MASK);
 299                         ctl |= IBS_FETCH_ENABLE;
 300                         wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
 301                 }
 302         }
 303
 304         if (ibs_config.op_enabled) {
 305                 rdmsrl(MSR_AMD64_IBSOPCTL, ctl);
 306                 if (ctl & IBS_OP_VAL) {
 307                         rdmsrl(MSR_AMD64_IBSOPRIP, val);
 308                         oprofile_write_reserve(&entry, regs, val,
 309                                                IBS_OP_CODE, IBS_OP_SIZE);
 310                         oprofile_add_data64(&entry, val);
 311                         rdmsrl(MSR_AMD64_IBSOPDATA, val);
 312                         oprofile_add_data64(&entry, val);
 313                         rdmsrl(MSR_AMD64_IBSOPDATA2, val);
 314                         oprofile_add_data64(&entry, val);
 315                         rdmsrl(MSR_AMD64_IBSOPDATA3, val);
 316                         oprofile_add_data64(&entry, val);
 317                         rdmsrl(MSR_AMD64_IBSDCLINAD, val);
 318                         oprofile_add_data64(&entry, val);
 319                         rdmsrl(MSR_AMD64_IBSDCPHYSAD, val);
 320                         oprofile_add_data64(&entry, val);
 321                         oprofile_write_commit(&entry);
 322
 323                         /* reenable the IRQ */
 324                         ctl = op_amd_randomize_ibs_op(ibs_op_ctl);
 325                         wrmsrl(MSR_AMD64_IBSOPCTL, ctl);
 326                 }
 327         }
 328 }
 329
 330 static inline void op_amd_start_ibs(void)
 331 {
 332         u64 val;
 333
 334         if (!ibs_caps)
 335                 return;
 336
 337         if (ibs_config.fetch_enabled) {
 338                 val = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
 339                 val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
 340                 val |= IBS_FETCH_ENABLE;
 341                 wrmsrl(MSR_AMD64_IBSFETCHCTL, val);
 342         }
 343
 344         if (ibs_config.op_enabled) {
 345                 ibs_op_ctl = ibs_config.max_cnt_op >> 4;
 346                 if (!(ibs_caps & IBS_CAPS_RDWROPCNT)) {
 347                         /*
 348                          * IbsOpCurCnt not supported.  See
 349                          * op_amd_randomize_ibs_op() for details.
 350                          */
 351                         ibs_op_ctl = clamp(ibs_op_ctl, 0x0081ULL, 0xFF80ULL);
 352                 } else {
 353                         /*
 354                          * The start value is randomized with a
 355                          * positive offset, we need to compensate it
 356                          * with the half of the randomized range. Also
 357                          * avoid underflows.
 358                          */
 359                         ibs_op_ctl = min(ibs_op_ctl + IBS_RANDOM_MAXCNT_OFFSET,
 360                                          0xFFFFULL);
 361                 }
 362                 if (ibs_caps & IBS_CAPS_OPCNT && ibs_config.dispatched_ops)
 363                         ibs_op_ctl |= IBS_OP_CNT_CTL;
 364                 ibs_op_ctl |= IBS_OP_ENABLE;
 365                 val = op_amd_randomize_ibs_op(ibs_op_ctl);
 366                 wrmsrl(MSR_AMD64_IBSOPCTL, val);
 367         }
 368 }
 369
 370 static void op_amd_stop_ibs(void)
 371 {
 372         if (!ibs_caps)
 373                 return;
 374
 375         if (ibs_config.fetch_enabled)
 376                 /* clear max count and enable */
 377                 wrmsrl(MSR_AMD64_IBSFETCHCTL, 0);
 378
 379         if (ibs_config.op_enabled)
 380                 /* clear max count and enable */
 381                 wrmsrl(MSR_AMD64_IBSOPCTL, 0);
 382 }
 383
 384 static int op_amd_check_ctrs(struct pt_regs * const regs,
 385                              struct op_msrs const * const msrs)
 386 {
 387         u64 val;
 388         int i;
 389
 390         for (i = 0; i < NUM_COUNTERS; ++i) {
 391                 int virt = op_x86_phys_to_virt(i);
 392                 if (!reset_value[virt])
 393                         continue;
 394                 rdmsrl(msrs->counters[i].addr, val);
 395                 /* bit is clear if overflowed: */
 396                 if (val & OP_CTR_OVERFLOW)
 397                         continue;
 398                 oprofile_add_sample(regs, virt);
 399                 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
 400         }
 401
 402         op_amd_handle_ibs(regs, msrs);
 403
 404         /* See op_model_ppro.c */
 405         return 1;
 406 }
 407
 408 static void op_amd_start(struct op_msrs const * const msrs)
 409 {
 410         u64 val;
 411         int i;
 412
 413         for (i = 0; i < NUM_COUNTERS; ++i) {
 414                 if (!reset_value[op_x86_phys_to_virt(i)])
 415                         continue;
 416                 rdmsrl(msrs->controls[i].addr, val);
 417                 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
 418                 wrmsrl(msrs->controls[i].addr, val);
 419         }
 420
 421         op_amd_start_ibs();
 422 }
 423
 424 static void op_amd_stop(struct op_msrs const * const msrs)
 425 {
 426         u64 val;
 427         int i;
 428
 429         /*
 430          * Subtle: stop on all counters to avoid race with setting our
 431          * pm callback
 432          */
 433         for (i = 0; i < NUM_COUNTERS; ++i) {
 434                 if (!reset_value[op_x86_phys_to_virt(i)])
 435                         continue;
 436                 rdmsrl(msrs->controls[i].addr, val);
 437                 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
 438                 wrmsrl(msrs->controls[i].addr, val);
 439         }
 440
 441         op_amd_stop_ibs();
 442 }
 443
 444 static void op_amd_shutdown(struct op_msrs const * const msrs)
 445 {
 446         int i;
 447
 448         for (i = 0; i < NUM_COUNTERS; ++i) {
 449                 if (msrs->counters[i].addr)
 450                         release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
 451         }
 452         for (i = 0; i < NUM_CONTROLS; ++i) {
 453                 if (msrs->controls[i].addr)
 454                         release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
 455         }
 456 }
 457
 458 static u8 ibs_eilvt_off;
 459
 460 static inline void apic_init_ibs_nmi_per_cpu(void *arg)
 461 {
 462         ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
 463 }
 464
 465 static inline void apic_clear_ibs_nmi_per_cpu(void *arg)
 466 {
 467         setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
 468 }
 469
 470 static int init_ibs_nmi(void)
 471 {
 472 #define IBSCTL_LVTOFFSETVAL             (1 << 8)
 473 #define IBSCTL                          0x1cc
 474         struct pci_dev *cpu_cfg;
 475         int nodes;
 476         u32 value = 0;
 477
 478         /* per CPU setup */
 479         on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1);
 480
 481         nodes = 0;
 482         cpu_cfg = NULL;
 483         do {
 484                 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
 485                                          PCI_DEVICE_ID_AMD_10H_NB_MISC,
 486                                          cpu_cfg);
 487                 if (!cpu_cfg)
 488                         break;
 489                 ++nodes;
 490                 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
 491                                        | IBSCTL_LVTOFFSETVAL);
 492                 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
 493                 if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) {
 494                         pci_dev_put(cpu_cfg);
 495                         printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
 496                                 "IBSCTL = 0x%08x", value);
 497                         return 1;
 498                 }
 499         } while (1);
 500
 501         if (!nodes) {
 502                 printk(KERN_DEBUG "No CPU node configured for IBS");
 503                 return 1;
 504         }
 505
 506         return 0;
 507 }
 508
 509 /* uninitialize the APIC for the IBS interrupts if needed */
 510 static void clear_ibs_nmi(void)
 511 {
 512         if (ibs_caps)
 513                 on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1);
 514 }
 515
 516 /* initialize the APIC for the IBS interrupts if available */
 517 static void ibs_init(void)
 518 {
 519         ibs_caps = get_ibs_caps();
 520
 521         if (!ibs_caps)
 522                 return;
 523
 524         if (init_ibs_nmi()) {
 525                 ibs_caps = 0;
 526                 return;
 527         }
 528
 529         printk(KERN_INFO "oprofile: AMD IBS detected (0x%08x)\n",
 530                (unsigned)ibs_caps);
 531 }
 532
 533 static void ibs_exit(void)
 534 {
 535         if (!ibs_caps)
 536                 return;
 537
 538         clear_ibs_nmi();
 539 }
 540
 541 static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
 542
 543 static int setup_ibs_files(struct super_block *sb, struct dentry *root)
 544 {
 545         struct dentry *dir;
 546         int ret = 0;
 547
 548         /* architecture specific files */
 549         if (create_arch_files)
 550                 ret = create_arch_files(sb, root);
 551
 552         if (ret)
 553                 return ret;
 554
 555         if (!ibs_caps)
 556                 return ret;
 557
 558         /* model specific files */
 559
 560         /* setup some reasonable defaults */
 561         ibs_config.max_cnt_fetch = 250000;
 562         ibs_config.fetch_enabled = 0;
 563         ibs_config.max_cnt_op = 250000;
 564         ibs_config.op_enabled = 0;
 565         ibs_config.dispatched_ops = 0;
 566
 567         dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
 568         oprofilefs_create_ulong(sb, dir, "enable",
 569                                 &ibs_config.fetch_enabled);
 570         oprofilefs_create_ulong(sb, dir, "max_count",
 571                                 &ibs_config.max_cnt_fetch);
 572         oprofilefs_create_ulong(sb, dir, "rand_enable",
 573                                 &ibs_config.rand_en);
 574
 575         dir = oprofilefs_mkdir(sb, root, "ibs_op");
 576         oprofilefs_create_ulong(sb, dir, "enable",
 577                                 &ibs_config.op_enabled);
 578         oprofilefs_create_ulong(sb, dir, "max_count",
 579                                 &ibs_config.max_cnt_op);
 580         if (ibs_caps & IBS_CAPS_OPCNT)
 581                 oprofilefs_create_ulong(sb, dir, "dispatched_ops",
 582                                         &ibs_config.dispatched_ops);
 583
 584         return 0;
 585 }
 586
 587 static int op_amd_init(struct oprofile_operations *ops)
 588 {
 589         ibs_init();
 590         create_arch_files = ops->create_files;
 591         ops->create_files = setup_ibs_files;
 592         return 0;
 593 }
 594
 595 static void op_amd_exit(void)
 596 {
 597         ibs_exit();
 598 }
 599
 600 struct op_x86_model_spec op_amd_spec = {
 601         .num_counters           = NUM_COUNTERS,
 602         .num_controls           = NUM_CONTROLS,
 603         .num_virt_counters      = NUM_VIRT_COUNTERS,
 604         .reserved               = MSR_AMD_EVENTSEL_RESERVED,
 605         .event_mask             = OP_EVENT_MASK,
 606         .init                   = op_amd_init,
 607         .exit                   = op_amd_exit,
 608         .fill_in_addresses      = &op_amd_fill_in_addresses,
 609         .setup_ctrs             = &op_amd_setup_ctrs,
 610         .check_ctrs             = &op_amd_check_ctrs,
 611         .start                  = &op_amd_start,
 612         .stop                   = &op_amd_stop,
 613         .shutdown               = &op_amd_shutdown,
 614 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 615         .switch_ctrl            = &op_mux_switch_ctrl,
 616 #endif
 617 };