4 * @remark Copyright 2002-2008 OProfile authors
5 * @remark Read the file COPYING
7 * @author John Levon <levon@movementarian.org>
8 * @author Robert Richter <robert.richter@amd.com>
11 #include <linux/init.h>
12 #include <linux/notifier.h>
13 #include <linux/smp.h>
14 #include <linux/oprofile.h>
15 #include <linux/sysdev.h>
16 #include <linux/slab.h>
17 #include <linux/moduleparam.h>
18 #include <linux/kdebug.h>
19 #include <linux/cpu.h>
24 #include "op_counter.h"
25 #include "op_x86_model.h"
27 static struct op_x86_model_spec const *model;
28 static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
29 static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
31 /* 0 == registered but off, 1 == registered and on */
32 static int nmi_enabled = 0;
34 /* common functions */
36 u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
37 struct op_counter_config *counter_config)
40 u16 event = (u16)counter_config->event;
42 val |= ARCH_PERFMON_EVENTSEL_INT;
43 val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0;
44 val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0;
45 val |= (counter_config->unit_mask & 0xFF) << 8;
46 event &= model->event_mask ? model->event_mask : 0xFF;
48 val |= (event & 0x0F00) << 24;
54 static int profile_exceptions_notify(struct notifier_block *self,
55 unsigned long val, void *data)
57 struct die_args *args = (struct die_args *)data;
58 int ret = NOTIFY_DONE;
59 int cpu = smp_processor_id();
64 model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu));
73 static void nmi_cpu_save_registers(struct op_msrs *msrs)
75 struct op_msr *counters = msrs->counters;
76 struct op_msr *controls = msrs->controls;
79 for (i = 0; i < model->num_counters; ++i) {
81 rdmsrl(counters[i].addr, counters[i].saved);
84 for (i = 0; i < model->num_controls; ++i) {
86 rdmsrl(controls[i].addr, controls[i].saved);
90 static void free_msrs(void)
93 for_each_possible_cpu(i) {
94 kfree(per_cpu(cpu_msrs, i).counters);
95 per_cpu(cpu_msrs, i).counters = NULL;
96 kfree(per_cpu(cpu_msrs, i).controls);
97 per_cpu(cpu_msrs, i).controls = NULL;
101 static int allocate_msrs(void)
104 size_t controls_size = sizeof(struct op_msr) * model->num_controls;
105 size_t counters_size = sizeof(struct op_msr) * model->num_counters;
108 for_each_possible_cpu(i) {
109 per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
111 if (!per_cpu(cpu_msrs, i).counters) {
115 per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
117 if (!per_cpu(cpu_msrs, i).controls) {
129 static void nmi_cpu_setup(void *dummy)
131 int cpu = smp_processor_id();
132 struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
133 nmi_cpu_save_registers(msrs);
134 spin_lock(&oprofilefs_lock);
135 model->setup_ctrs(model, msrs);
136 spin_unlock(&oprofilefs_lock);
137 per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
138 apic_write(APIC_LVTPC, APIC_DM_NMI);
141 static struct notifier_block profile_exceptions_nb = {
142 .notifier_call = profile_exceptions_notify,
147 static int nmi_setup(void)
152 if (!allocate_msrs())
155 err = register_die_notifier(&profile_exceptions_nb);
161 /* We need to serialize save and setup for HT because the subset
162 * of msrs are distinct for save and setup operations
165 /* Assume saved/restored counters are the same on all CPUs */
166 model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
167 for_each_possible_cpu(cpu) {
169 memcpy(per_cpu(cpu_msrs, cpu).counters,
170 per_cpu(cpu_msrs, 0).counters,
171 sizeof(struct op_msr) * model->num_counters);
173 memcpy(per_cpu(cpu_msrs, cpu).controls,
174 per_cpu(cpu_msrs, 0).controls,
175 sizeof(struct op_msr) * model->num_controls);
179 on_each_cpu(nmi_cpu_setup, NULL, 1);
184 static void nmi_cpu_restore_registers(struct op_msrs *msrs)
186 struct op_msr *counters = msrs->counters;
187 struct op_msr *controls = msrs->controls;
190 for (i = 0; i < model->num_controls; ++i) {
191 if (controls[i].addr)
192 wrmsrl(controls[i].addr, controls[i].saved);
195 for (i = 0; i < model->num_counters; ++i) {
196 if (counters[i].addr)
197 wrmsrl(counters[i].addr, counters[i].saved);
201 static void nmi_cpu_shutdown(void *dummy)
204 int cpu = smp_processor_id();
205 struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);
207 /* restoring APIC_LVTPC can trigger an apic error because the delivery
208 * mode and vector nr combination can be illegal. That's by design: on
209 * power on apic lvt contain a zero vector nr which are legal only for
210 * NMI delivery mode. So inhibit apic err before restoring lvtpc
212 v = apic_read(APIC_LVTERR);
213 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
214 apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
215 apic_write(APIC_LVTERR, v);
216 nmi_cpu_restore_registers(msrs);
219 static void nmi_shutdown(void)
221 struct op_msrs *msrs;
224 on_each_cpu(nmi_cpu_shutdown, NULL, 1);
225 unregister_die_notifier(&profile_exceptions_nb);
226 msrs = &get_cpu_var(cpu_msrs);
227 model->shutdown(msrs);
229 put_cpu_var(cpu_msrs);
232 static void nmi_cpu_start(void *dummy)
234 struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
238 static int nmi_start(void)
240 on_each_cpu(nmi_cpu_start, NULL, 1);
244 static void nmi_cpu_stop(void *dummy)
246 struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
250 static void nmi_stop(void)
252 on_each_cpu(nmi_cpu_stop, NULL, 1);
255 struct op_counter_config counter_config[OP_MAX_COUNTER];
257 static int nmi_create_files(struct super_block *sb, struct dentry *root)
261 for (i = 0; i < model->num_counters; ++i) {
265 /* quick little hack to _not_ expose a counter if it is not
266 * available for use. This should protect userspace app.
267 * NOTE: assumes 1:1 mapping here (that counters are organized
268 * sequentially in their struct assignment).
270 if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
273 snprintf(buf, sizeof(buf), "%d", i);
274 dir = oprofilefs_mkdir(sb, root, buf);
275 oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
276 oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
277 oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
278 oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
279 oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
280 oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
287 static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
290 int cpu = (unsigned long)data;
292 case CPU_DOWN_FAILED:
294 smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
296 case CPU_DOWN_PREPARE:
297 smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
303 static struct notifier_block oprofile_cpu_nb = {
304 .notifier_call = oprofile_cpu_notifier
310 static int nmi_suspend(struct sys_device *dev, pm_message_t state)
312 /* Only one CPU left, just stop that one */
313 if (nmi_enabled == 1)
318 static int nmi_resume(struct sys_device *dev)
320 if (nmi_enabled == 1)
325 static struct sysdev_class oprofile_sysclass = {
327 .resume = nmi_resume,
328 .suspend = nmi_suspend,
331 static struct sys_device device_oprofile = {
333 .cls = &oprofile_sysclass,
336 static int __init init_sysfs(void)
340 error = sysdev_class_register(&oprofile_sysclass);
342 error = sysdev_register(&device_oprofile);
346 static void exit_sysfs(void)
348 sysdev_unregister(&device_oprofile);
349 sysdev_class_unregister(&oprofile_sysclass);
353 #define init_sysfs() do { } while (0)
354 #define exit_sysfs() do { } while (0)
355 #endif /* CONFIG_PM */
357 static int __init p4_init(char **cpu_type)
359 __u8 cpu_model = boot_cpu_data.x86_model;
361 if (cpu_model > 6 || cpu_model == 5)
365 *cpu_type = "i386/p4";
369 switch (smp_num_siblings) {
371 *cpu_type = "i386/p4";
376 *cpu_type = "i386/p4-ht";
377 model = &op_p4_ht2_spec;
382 printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
383 printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
387 static int force_arch_perfmon;
388 static int force_cpu_type(const char *str, struct kernel_param *kp)
390 if (!strcmp(str, "arch_perfmon")) {
391 force_arch_perfmon = 1;
392 printk(KERN_INFO "oprofile: forcing architectural perfmon\n");
397 module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0);
399 static int __init ppro_init(char **cpu_type)
401 __u8 cpu_model = boot_cpu_data.x86_model;
402 struct op_x86_model_spec const *spec = &op_ppro_spec; /* default */
404 if (force_arch_perfmon && cpu_has_arch_perfmon)
409 *cpu_type = "i386/ppro";
412 *cpu_type = "i386/pii";
416 *cpu_type = "i386/piii";
420 *cpu_type = "i386/p6_mobile";
423 *cpu_type = "i386/core";
426 *cpu_type = "i386/core_2";
429 spec = &op_arch_perfmon_spec;
430 *cpu_type = "i386/core_i7";
433 *cpu_type = "i386/atom";
444 /* in order to get sysfs right */
445 static int using_nmi;
447 int __init op_nmi_init(struct oprofile_operations *ops)
449 __u8 vendor = boot_cpu_data.x86_vendor;
450 __u8 family = boot_cpu_data.x86;
451 char *cpu_type = NULL;
459 /* Needs to be at least an Athlon (or hammer in 32bit mode) */
463 cpu_type = "i386/athlon";
467 * Actually it could be i386/hammer too, but
468 * give user space an consistent name.
470 cpu_type = "x86-64/hammer";
473 cpu_type = "x86-64/family10";
476 cpu_type = "x86-64/family11h";
481 model = &op_amd_spec;
484 case X86_VENDOR_INTEL:
491 /* A P6-class processor */
493 ppro_init(&cpu_type);
503 if (!cpu_has_arch_perfmon)
506 /* use arch perfmon as fallback */
507 cpu_type = "i386/arch_perfmon";
508 model = &op_arch_perfmon_spec;
516 register_cpu_notifier(&oprofile_cpu_nb);
518 /* default values, can be overwritten by model */
519 ops->create_files = nmi_create_files;
520 ops->setup = nmi_setup;
521 ops->shutdown = nmi_shutdown;
522 ops->start = nmi_start;
523 ops->stop = nmi_stop;
524 ops->cpu_type = cpu_type;
527 ret = model->init(ops);
533 printk(KERN_INFO "oprofile: using NMI interrupt.\n");
537 void op_nmi_exit(void)
542 unregister_cpu_notifier(&oprofile_cpu_nb);