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   1 /**
   2  * @file nmi_int.c
   3  *
   4  * @remark Copyright 2002-2009 OProfile authors
   5  * @remark Read the file COPYING
   6  *
   7  * @author John Levon <levon@movementarian.org>
   8  * @author Robert Richter <robert.richter@amd.com>
   9  * @author Barry Kasindorf <barry.kasindorf@amd.com>
  10  * @author Jason Yeh <jason.yeh@amd.com>
  11  * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/notifier.h>
  16 #include <linux/smp.h>
  17 #include <linux/oprofile.h>
  18 #include <linux/sysdev.h>
  19 #include <linux/slab.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/cpu.h>
  23 #include <asm/nmi.h>
  24 #include <asm/msr.h>
  25 #include <asm/apic.h>
  26
  27 #include "op_counter.h"
  28 #include "op_x86_model.h"
  29
  30 static struct op_x86_model_spec const *model;
  31 static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
  32 static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
  33
  34 /* 0 == registered but off, 1 == registered and on */
  35 static int nmi_enabled = 0;
  36
  37
  38 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
  39 extern atomic_t multiplex_counter;
  40 #endif
  41
  42 struct op_counter_config counter_config[OP_MAX_COUNTER];
  43
  44 /* common functions */
  45
  46 u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
  47                     struct op_counter_config *counter_config)
  48 {
  49         u64 val = 0;
  50         u16 event = (u16)counter_config->event;
  51
  52         val |= ARCH_PERFMON_EVENTSEL_INT;
  53         val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0;
  54         val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0;
  55         val |= (counter_config->unit_mask & 0xFF) << 8;
  56         event &= model->event_mask ? model->event_mask : 0xFF;
  57         val |= event & 0xFF;
  58         val |= (event & 0x0F00) << 24;
  59
  60         return val;
  61 }
  62
  63
  64 static int profile_exceptions_notify(struct notifier_block *self,
  65                                      unsigned long val, void *data)
  66 {
  67         struct die_args *args = (struct die_args *)data;
  68         int ret = NOTIFY_DONE;
  69         int cpu = smp_processor_id();
  70
  71         switch (val) {
  72         case DIE_NMI:
  73         case DIE_NMI_IPI:
  74                 model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu));
  75                 ret = NOTIFY_STOP;
  76                 break;
  77         default:
  78                 break;
  79         }
  80         return ret;
  81 }
  82
  83 static void nmi_cpu_save_registers(struct op_msrs *msrs)
  84 {
  85         struct op_msr *counters = msrs->counters;
  86         struct op_msr *controls = msrs->controls;
  87         unsigned int i;
  88
  89         for (i = 0; i < model->num_counters; ++i) {
  90                 if (counters[i].addr)
  91                         rdmsrl(counters[i].addr, counters[i].saved);
  92         }
  93
  94         for (i = 0; i < model->num_controls; ++i) {
  95                 if (controls[i].addr)
  96                         rdmsrl(controls[i].addr, controls[i].saved);
  97         }
  98 }
  99
 100 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 101
 102 static DEFINE_PER_CPU(int, switch_index);
 103
 104 inline int op_x86_phys_to_virt(int phys)
 105 {
 106         return __get_cpu_var(switch_index) + phys;
 107 }
 108
 109 #else
 110
 111 inline int op_x86_phys_to_virt(int phys) { return phys; }
 112
 113 #endif
 114
 115 static void free_msrs(void)
 116 {
 117         int i;
 118         for_each_possible_cpu(i) {
 119                 kfree(per_cpu(cpu_msrs, i).counters);
 120                 per_cpu(cpu_msrs, i).counters = NULL;
 121                 kfree(per_cpu(cpu_msrs, i).controls);
 122                 per_cpu(cpu_msrs, i).controls = NULL;
 123
 124 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 125                 kfree(per_cpu(cpu_msrs, i).multiplex);
 126                 per_cpu(cpu_msrs, i).multiplex = NULL;
 127 #endif
 128         }
 129 }
 130
 131 static int allocate_msrs(void)
 132 {
 133         int success = 1;
 134         size_t controls_size = sizeof(struct op_msr) * model->num_controls;
 135         size_t counters_size = sizeof(struct op_msr) * model->num_counters;
 136 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 137         size_t multiplex_size = sizeof(struct op_msr) * model->num_virt_counters;
 138 #endif
 139
 140         int i;
 141         for_each_possible_cpu(i) {
 142                 per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
 143                                                                 GFP_KERNEL);
 144                 if (!per_cpu(cpu_msrs, i).counters) {
 145                         success = 0;
 146                         break;
 147                 }
 148                 per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
 149                                                                 GFP_KERNEL);
 150                 if (!per_cpu(cpu_msrs, i).controls) {
 151                         success = 0;
 152                         break;
 153                 }
 154 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 155                 per_cpu(cpu_msrs, i).multiplex =
 156                                 kmalloc(multiplex_size, GFP_KERNEL);
 157                 if (!per_cpu(cpu_msrs, i).multiplex) {
 158                         success = 0;
 159                         break;
 160                 }
 161 #endif
 162         }
 163
 164         if (!success)
 165                 free_msrs();
 166
 167         return success;
 168 }
 169
 170 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 171
 172 static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs)
 173 {
 174         int i;
 175         struct op_msr *multiplex = msrs->multiplex;
 176
 177         for (i = 0; i < model->num_virt_counters; ++i) {
 178                 if (counter_config[i].enabled) {
 179                         multiplex[i].saved = -(u64)counter_config[i].count;
 180                 } else {
 181                         multiplex[i].addr  = 0;
 182                         multiplex[i].saved = 0;
 183                 }
 184         }
 185
 186         per_cpu(switch_index, cpu) = 0;
 187 }
 188
 189 #else
 190
 191 static inline void
 192 nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) { }
 193
 194 #endif
 195
 196 static void nmi_cpu_setup(void *dummy)
 197 {
 198         int cpu = smp_processor_id();
 199         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 200         nmi_cpu_save_registers(msrs);
 201         spin_lock(&oprofilefs_lock);
 202         model->setup_ctrs(model, msrs);
 203         nmi_cpu_setup_mux(cpu, msrs);
 204         spin_unlock(&oprofilefs_lock);
 205         per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
 206         apic_write(APIC_LVTPC, APIC_DM_NMI);
 207 }
 208
 209 static struct notifier_block profile_exceptions_nb = {
 210         .notifier_call = profile_exceptions_notify,
 211         .next = NULL,
 212         .priority = 2
 213 };
 214
 215 static int nmi_setup(void)
 216 {
 217         int err = 0;
 218         int cpu;
 219
 220         if (!allocate_msrs())
 221                 return -ENOMEM;
 222
 223         err = register_die_notifier(&profile_exceptions_nb);
 224         if (err) {
 225                 free_msrs();
 226                 return err;
 227         }
 228
 229         /* We need to serialize save and setup for HT because the subset
 230          * of msrs are distinct for save and setup operations
 231          */
 232
 233         /* Assume saved/restored counters are the same on all CPUs */
 234         model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
 235         for_each_possible_cpu(cpu) {
 236                 if (cpu != 0) {
 237                         memcpy(per_cpu(cpu_msrs, cpu).counters,
 238                                 per_cpu(cpu_msrs, 0).counters,
 239                                 sizeof(struct op_msr) * model->num_counters);
 240
 241                         memcpy(per_cpu(cpu_msrs, cpu).controls,
 242                                 per_cpu(cpu_msrs, 0).controls,
 243                                 sizeof(struct op_msr) * model->num_controls);
 244 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 245                         memcpy(per_cpu(cpu_msrs, cpu).multiplex,
 246                                 per_cpu(cpu_msrs, 0).multiplex,
 247                                 sizeof(struct op_msr) * model->num_virt_counters);
 248 #endif
 249                 }
 250         }
 251         on_each_cpu(nmi_cpu_setup, NULL, 1);
 252         nmi_enabled = 1;
 253         return 0;
 254 }
 255
 256 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 257
 258 static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs)
 259 {
 260         struct op_msr *multiplex = msrs->multiplex;
 261         int i;
 262
 263         for (i = 0; i < model->num_counters; ++i) {
 264                 int virt = op_x86_phys_to_virt(i);
 265                 if (multiplex[virt].addr)
 266                         rdmsrl(multiplex[virt].addr, multiplex[virt].saved);
 267         }
 268 }
 269
 270 static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
 271 {
 272         struct op_msr *multiplex = msrs->multiplex;
 273         int i;
 274
 275         for (i = 0; i < model->num_counters; ++i) {
 276                 int virt = op_x86_phys_to_virt(i);
 277                 if (multiplex[virt].addr)
 278                         wrmsrl(multiplex[virt].addr, multiplex[virt].saved);
 279         }
 280 }
 281
 282 #endif
 283
 284 static void nmi_cpu_restore_registers(struct op_msrs *msrs)
 285 {
 286         struct op_msr *counters = msrs->counters;
 287         struct op_msr *controls = msrs->controls;
 288         unsigned int i;
 289
 290         for (i = 0; i < model->num_controls; ++i) {
 291                 if (controls[i].addr)
 292                         wrmsrl(controls[i].addr, controls[i].saved);
 293         }
 294
 295         for (i = 0; i < model->num_counters; ++i) {
 296                 if (counters[i].addr)
 297                         wrmsrl(counters[i].addr, counters[i].saved);
 298         }
 299 }
 300
 301 static void nmi_cpu_shutdown(void *dummy)
 302 {
 303         unsigned int v;
 304         int cpu = smp_processor_id();
 305         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 306
 307         /* restoring APIC_LVTPC can trigger an apic error because the delivery
 308          * mode and vector nr combination can be illegal. That's by design: on
 309          * power on apic lvt contain a zero vector nr which are legal only for
 310          * NMI delivery mode. So inhibit apic err before restoring lvtpc
 311          */
 312         v = apic_read(APIC_LVTERR);
 313         apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
 314         apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
 315         apic_write(APIC_LVTERR, v);
 316         nmi_cpu_restore_registers(msrs);
 317 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 318         per_cpu(switch_index, cpu) = 0;
 319 #endif
 320 }
 321
 322 static void nmi_shutdown(void)
 323 {
 324         struct op_msrs *msrs;
 325
 326         nmi_enabled = 0;
 327         on_each_cpu(nmi_cpu_shutdown, NULL, 1);
 328         unregister_die_notifier(&profile_exceptions_nb);
 329         msrs = &get_cpu_var(cpu_msrs);
 330         model->shutdown(msrs);
 331         free_msrs();
 332         put_cpu_var(cpu_msrs);
 333 }
 334
 335 static void nmi_cpu_start(void *dummy)
 336 {
 337         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
 338         model->start(msrs);
 339 }
 340
 341 static int nmi_start(void)
 342 {
 343         on_each_cpu(nmi_cpu_start, NULL, 1);
 344         return 0;
 345 }
 346
 347 static void nmi_cpu_stop(void *dummy)
 348 {
 349         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
 350         model->stop(msrs);
 351 }
 352
 353 static void nmi_stop(void)
 354 {
 355         on_each_cpu(nmi_cpu_stop, NULL, 1);
 356 }
 357
 358 static int nmi_create_files(struct super_block *sb, struct dentry *root)
 359 {
 360         unsigned int i;
 361
 362         for (i = 0; i < model->num_virt_counters; ++i) {
 363                 struct dentry *dir;
 364                 char buf[4];
 365
 366 #ifndef CONFIG_OPROFILE_EVENT_MULTIPLEX
 367                 /* quick little hack to _not_ expose a counter if it is not
 368                  * available for use.  This should protect userspace app.
 369                  * NOTE:  assumes 1:1 mapping here (that counters are organized
 370                  *        sequentially in their struct assignment).
 371                  */
 372                 if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
 373                         continue;
 374 #endif /* CONFIG_OPROFILE_EVENT_MULTIPLEX */
 375
 376                 snprintf(buf,  sizeof(buf), "%d", i);
 377                 dir = oprofilefs_mkdir(sb, root, buf);
 378                 oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
 379                 oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
 380                 oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
 381                 oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
 382                 oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
 383                 oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
 384         }
 385
 386         return 0;
 387 }
 388
 389 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 390
 391 static void nmi_cpu_switch(void *dummy)
 392 {
 393         int cpu = smp_processor_id();
 394         int si = per_cpu(switch_index, cpu);
 395         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 396
 397         nmi_cpu_stop(NULL);
 398         nmi_cpu_save_mpx_registers(msrs);
 399
 400         /* move to next set */
 401         si += model->num_counters;
 402         if ((si > model->num_virt_counters) || (counter_config[si].count == 0))
 403                 per_cpu(switch_index, cpu) = 0;
 404         else
 405                 per_cpu(switch_index, cpu) = si;
 406
 407         model->switch_ctrl(model, msrs);
 408         nmi_cpu_restore_mpx_registers(msrs);
 409
 410         nmi_cpu_start(NULL);
 411 }
 412
 413
 414 /*
 415  * Quick check to see if multiplexing is necessary.
 416  * The check should be sufficient since counters are used
 417  * in ordre.
 418  */
 419 static int nmi_multiplex_on(void)
 420 {
 421         return counter_config[model->num_counters].count ? 0 : -EINVAL;
 422 }
 423
 424 static int nmi_switch_event(void)
 425 {
 426         if (!model->switch_ctrl)
 427                 return -ENOSYS;         /* not implemented */
 428         if (nmi_multiplex_on() < 0)
 429                 return -EINVAL;         /* not necessary */
 430
 431         on_each_cpu(nmi_cpu_switch, NULL, 1);
 432
 433         atomic_inc(&multiplex_counter);
 434
 435         return 0;
 436 }
 437
 438 #endif
 439
 440 #ifdef CONFIG_SMP
 441 static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
 442                                  void *data)
 443 {
 444         int cpu = (unsigned long)data;
 445         switch (action) {
 446         case CPU_DOWN_FAILED:
 447         case CPU_ONLINE:
 448                 smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
 449                 break;
 450         case CPU_DOWN_PREPARE:
 451                 smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
 452                 break;
 453         }
 454         return NOTIFY_DONE;
 455 }
 456
 457 static struct notifier_block oprofile_cpu_nb = {
 458         .notifier_call = oprofile_cpu_notifier
 459 };
 460 #endif
 461
 462 #ifdef CONFIG_PM
 463
 464 static int nmi_suspend(struct sys_device *dev, pm_message_t state)
 465 {
 466         /* Only one CPU left, just stop that one */
 467         if (nmi_enabled == 1)
 468                 nmi_cpu_stop(NULL);
 469         return 0;
 470 }
 471
 472 static int nmi_resume(struct sys_device *dev)
 473 {
 474         if (nmi_enabled == 1)
 475                 nmi_cpu_start(NULL);
 476         return 0;
 477 }
 478
 479 static struct sysdev_class oprofile_sysclass = {
 480         .name           = "oprofile",
 481         .resume         = nmi_resume,
 482         .suspend        = nmi_suspend,
 483 };
 484
 485 static struct sys_device device_oprofile = {
 486         .id     = 0,
 487         .cls    = &oprofile_sysclass,
 488 };
 489
 490 static int __init init_sysfs(void)
 491 {
 492         int error;
 493
 494         error = sysdev_class_register(&oprofile_sysclass);
 495         if (!error)
 496                 error = sysdev_register(&device_oprofile);
 497         return error;
 498 }
 499
 500 static void exit_sysfs(void)
 501 {
 502         sysdev_unregister(&device_oprofile);
 503         sysdev_class_unregister(&oprofile_sysclass);
 504 }
 505
 506 #else
 507 #define init_sysfs() do { } while (0)
 508 #define exit_sysfs() do { } while (0)
 509 #endif /* CONFIG_PM */
 510
 511 static int __init p4_init(char **cpu_type)
 512 {
 513         __u8 cpu_model = boot_cpu_data.x86_model;
 514
 515         if (cpu_model > 6 || cpu_model == 5)
 516                 return 0;
 517
 518 #ifndef CONFIG_SMP
 519         *cpu_type = "i386/p4";
 520         model = &op_p4_spec;
 521         return 1;
 522 #else
 523         switch (smp_num_siblings) {
 524         case 1:
 525                 *cpu_type = "i386/p4";
 526                 model = &op_p4_spec;
 527                 return 1;
 528
 529         case 2:
 530                 *cpu_type = "i386/p4-ht";
 531                 model = &op_p4_ht2_spec;
 532                 return 1;
 533         }
 534 #endif
 535
 536         printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
 537         printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
 538         return 0;
 539 }
 540
 541 static int force_arch_perfmon;
 542 static int force_cpu_type(const char *str, struct kernel_param *kp)
 543 {
 544         if (!strcmp(str, "arch_perfmon")) {
 545                 force_arch_perfmon = 1;
 546                 printk(KERN_INFO "oprofile: forcing architectural perfmon\n");
 547         }
 548
 549         return 0;
 550 }
 551 module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0);
 552
 553 static int __init ppro_init(char **cpu_type)
 554 {
 555         __u8 cpu_model = boot_cpu_data.x86_model;
 556         struct op_x86_model_spec const *spec = &op_ppro_spec;   /* default */
 557
 558         if (force_arch_perfmon && cpu_has_arch_perfmon)
 559                 return 0;
 560
 561         switch (cpu_model) {
 562         case 0 ... 2:
 563                 *cpu_type = "i386/ppro";
 564                 break;
 565         case 3 ... 5:
 566                 *cpu_type = "i386/pii";
 567                 break;
 568         case 6 ... 8:
 569         case 10 ... 11:
 570                 *cpu_type = "i386/piii";
 571                 break;
 572         case 9:
 573         case 13:
 574                 *cpu_type = "i386/p6_mobile";
 575                 break;
 576         case 14:
 577                 *cpu_type = "i386/core";
 578                 break;
 579         case 15: case 23:
 580                 *cpu_type = "i386/core_2";
 581                 break;
 582         case 26:
 583                 spec = &op_arch_perfmon_spec;
 584                 *cpu_type = "i386/core_i7";
 585                 break;
 586         case 28:
 587                 *cpu_type = "i386/atom";
 588                 break;
 589         default:
 590                 /* Unknown */
 591                 return 0;
 592         }
 593
 594         model = spec;
 595         return 1;
 596 }
 597
 598 /* in order to get sysfs right */
 599 static int using_nmi;
 600
 601 int __init op_nmi_init(struct oprofile_operations *ops)
 602 {
 603         __u8 vendor = boot_cpu_data.x86_vendor;
 604         __u8 family = boot_cpu_data.x86;
 605         char *cpu_type = NULL;
 606         int ret = 0;
 607
 608         if (!cpu_has_apic)
 609                 return -ENODEV;
 610
 611         switch (vendor) {
 612         case X86_VENDOR_AMD:
 613                 /* Needs to be at least an Athlon (or hammer in 32bit mode) */
 614
 615                 switch (family) {
 616                 case 6:
 617                         cpu_type = "i386/athlon";
 618                         break;
 619                 case 0xf:
 620                         /*
 621                          * Actually it could be i386/hammer too, but
 622                          * give user space an consistent name.
 623                          */
 624                         cpu_type = "x86-64/hammer";
 625                         break;
 626                 case 0x10:
 627                         cpu_type = "x86-64/family10";
 628                         break;
 629                 case 0x11:
 630                         cpu_type = "x86-64/family11h";
 631                         break;
 632                 default:
 633                         return -ENODEV;
 634                 }
 635                 model = &op_amd_spec;
 636                 break;
 637
 638         case X86_VENDOR_INTEL:
 639                 switch (family) {
 640                         /* Pentium IV */
 641                 case 0xf:
 642                         p4_init(&cpu_type);
 643                         break;
 644
 645                         /* A P6-class processor */
 646                 case 6:
 647                         ppro_init(&cpu_type);
 648                         break;
 649
 650                 default:
 651                         break;
 652                 }
 653
 654                 if (cpu_type)
 655                         break;
 656
 657                 if (!cpu_has_arch_perfmon)
 658                         return -ENODEV;
 659
 660                 /* use arch perfmon as fallback */
 661                 cpu_type = "i386/arch_perfmon";
 662                 model = &op_arch_perfmon_spec;
 663                 break;
 664
 665         default:
 666                 return -ENODEV;
 667         }
 668
 669 #ifdef CONFIG_SMP
 670         register_cpu_notifier(&oprofile_cpu_nb);
 671 #endif
 672         /* default values, can be overwritten by model */
 673         ops->create_files       = nmi_create_files;
 674         ops->setup              = nmi_setup;
 675         ops->shutdown           = nmi_shutdown;
 676         ops->start              = nmi_start;
 677         ops->stop               = nmi_stop;
 678         ops->cpu_type           = cpu_type;
 679 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 680         ops->switch_events      = nmi_switch_event;
 681 #endif
 682
 683         if (model->init)
 684                 ret = model->init(ops);
 685         if (ret)
 686                 return ret;
 687
 688         init_sysfs();
 689         using_nmi = 1;
 690         printk(KERN_INFO "oprofile: using NMI interrupt.\n");
 691         return 0;
 692 }
 693
 694 void op_nmi_exit(void)
 695 {
 696         if (using_nmi) {
 697                 exit_sysfs();
 698 #ifdef CONFIG_SMP
 699                 unregister_cpu_notifier(&oprofile_cpu_nb);
 700 #endif
 701         }
 702         if (model->exit)
 703                 model->exit();
 704 }