2 * Copyright 2002 Andi Kleen, SuSE Labs.
3 * Thanks to Ben LaHaise for precious feedback.
5 #include <linux/highmem.h>
6 #include <linux/bootmem.h>
7 #include <linux/module.h>
8 #include <linux/sched.h>
9 #include <linux/slab.h>
11 #include <linux/interrupt.h>
12 #include <linux/seq_file.h>
13 #include <linux/debugfs.h>
14 #include <linux/pfn.h>
15 #include <linux/percpu.h>
18 #include <asm/processor.h>
19 #include <asm/tlbflush.h>
20 #include <asm/sections.h>
21 #include <asm/setup.h>
22 #include <asm/uaccess.h>
23 #include <asm/pgalloc.h>
24 #include <asm/proto.h>
28 * The current flushing context - we pass it instead of 5 arguments:
37 unsigned force_split : 1;
43 * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings)
44 * using cpa_lock. So that we don't allow any other cpu, with stale large tlb
45 * entries change the page attribute in parallel to some other cpu
46 * splitting a large page entry along with changing the attribute.
48 static DEFINE_SPINLOCK(cpa_lock);
50 #define CPA_FLUSHTLB 1
52 #define CPA_PAGES_ARRAY 4
55 static unsigned long direct_pages_count[PG_LEVEL_NUM];
57 void update_page_count(int level, unsigned long pages)
61 /* Protect against CPA */
62 spin_lock_irqsave(&pgd_lock, flags);
63 direct_pages_count[level] += pages;
64 spin_unlock_irqrestore(&pgd_lock, flags);
67 static void split_page_count(int level)
69 direct_pages_count[level]--;
70 direct_pages_count[level - 1] += PTRS_PER_PTE;
73 void arch_report_meminfo(struct seq_file *m)
75 seq_printf(m, "DirectMap4k: %8lu kB\n",
76 direct_pages_count[PG_LEVEL_4K] << 2);
77 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
78 seq_printf(m, "DirectMap2M: %8lu kB\n",
79 direct_pages_count[PG_LEVEL_2M] << 11);
81 seq_printf(m, "DirectMap4M: %8lu kB\n",
82 direct_pages_count[PG_LEVEL_2M] << 12);
86 seq_printf(m, "DirectMap1G: %8lu kB\n",
87 direct_pages_count[PG_LEVEL_1G] << 20);
91 static inline void split_page_count(int level) { }
96 static inline unsigned long highmap_start_pfn(void)
98 return __pa(_text) >> PAGE_SHIFT;
101 static inline unsigned long highmap_end_pfn(void)
103 return __pa(roundup(_brk_end, PMD_SIZE)) >> PAGE_SHIFT;
108 #ifdef CONFIG_DEBUG_PAGEALLOC
109 # define debug_pagealloc 1
111 # define debug_pagealloc 0
115 within(unsigned long addr, unsigned long start, unsigned long end)
117 return addr >= start && addr < end;
125 * clflush_cache_range - flush a cache range with clflush
126 * @addr: virtual start address
127 * @size: number of bytes to flush
129 * clflush is an unordered instruction which needs fencing with mfence
130 * to avoid ordering issues.
132 void clflush_cache_range(void *vaddr, unsigned int size)
134 void *vend = vaddr + size - 1;
138 for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size)
141 * Flush any possible final partial cacheline:
147 EXPORT_SYMBOL_GPL(clflush_cache_range);
149 static void __cpa_flush_all(void *arg)
151 unsigned long cache = (unsigned long)arg;
154 * Flush all to work around Errata in early athlons regarding
155 * large page flushing.
159 if (cache && boot_cpu_data.x86 >= 4)
163 static void cpa_flush_all(unsigned long cache)
165 BUG_ON(irqs_disabled());
167 on_each_cpu(__cpa_flush_all, (void *) cache, 1);
170 static void __cpa_flush_range(void *arg)
173 * We could optimize that further and do individual per page
174 * tlb invalidates for a low number of pages. Caveat: we must
175 * flush the high aliases on 64bit as well.
180 static void cpa_flush_range(unsigned long start, int numpages, int cache)
182 unsigned int i, level;
185 BUG_ON(irqs_disabled());
186 WARN_ON(PAGE_ALIGN(start) != start);
188 on_each_cpu(__cpa_flush_range, NULL, 1);
194 * We only need to flush on one CPU,
195 * clflush is a MESI-coherent instruction that
196 * will cause all other CPUs to flush the same
199 for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) {
200 pte_t *pte = lookup_address(addr, &level);
203 * Only flush present addresses:
205 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
206 clflush_cache_range((void *) addr, PAGE_SIZE);
210 static void cpa_flush_array(unsigned long *start, int numpages, int cache,
211 int in_flags, struct page **pages)
213 unsigned int i, level;
214 unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */
216 BUG_ON(irqs_disabled());
218 on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1);
220 if (!cache || do_wbinvd)
224 * We only need to flush on one CPU,
225 * clflush is a MESI-coherent instruction that
226 * will cause all other CPUs to flush the same
229 for (i = 0; i < numpages; i++) {
233 if (in_flags & CPA_PAGES_ARRAY)
234 addr = (unsigned long)page_address(pages[i]);
238 pte = lookup_address(addr, &level);
241 * Only flush present addresses:
243 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
244 clflush_cache_range((void *)addr, PAGE_SIZE);
249 * Certain areas of memory on x86 require very specific protection flags,
250 * for example the BIOS area or kernel text. Callers don't always get this
251 * right (again, ioremap() on BIOS memory is not uncommon) so this function
252 * checks and fixes these known static required protection bits.
254 static inline pgprot_t static_protections(pgprot_t prot, unsigned long address,
257 pgprot_t forbidden = __pgprot(0);
260 * The BIOS area between 640k and 1Mb needs to be executable for
261 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
263 if (within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT))
264 pgprot_val(forbidden) |= _PAGE_NX;
267 * The kernel text needs to be executable for obvious reasons
268 * Does not cover __inittext since that is gone later on. On
269 * 64bit we do not enforce !NX on the low mapping
271 if (within(address, (unsigned long)_text, (unsigned long)_etext))
272 pgprot_val(forbidden) |= _PAGE_NX;
275 * The .rodata section needs to be read-only. Using the pfn
276 * catches all aliases.
278 if (within(pfn, __pa((unsigned long)__start_rodata) >> PAGE_SHIFT,
279 __pa((unsigned long)__end_rodata) >> PAGE_SHIFT))
280 pgprot_val(forbidden) |= _PAGE_RW;
282 #if defined(CONFIG_X86_64) && defined(CONFIG_DEBUG_RODATA)
284 * Kernel text mappings for the large page aligned .rodata section
285 * will be read-only. For the kernel identity mappings covering
286 * the holes caused by this alignment can be anything.
288 * This will preserve the large page mappings for kernel text/data
291 if (within(address, (unsigned long)_text,
292 (unsigned long)__end_rodata_hpage_align))
293 pgprot_val(forbidden) |= _PAGE_RW;
296 prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden));
302 * Lookup the page table entry for a virtual address. Return a pointer
303 * to the entry and the level of the mapping.
305 * Note: We return pud and pmd either when the entry is marked large
306 * or when the present bit is not set. Otherwise we would return a
307 * pointer to a nonexisting mapping.
309 pte_t *lookup_address(unsigned long address, unsigned int *level)
311 pgd_t *pgd = pgd_offset_k(address);
315 *level = PG_LEVEL_NONE;
320 pud = pud_offset(pgd, address);
324 *level = PG_LEVEL_1G;
325 if (pud_large(*pud) || !pud_present(*pud))
328 pmd = pmd_offset(pud, address);
332 *level = PG_LEVEL_2M;
333 if (pmd_large(*pmd) || !pmd_present(*pmd))
336 *level = PG_LEVEL_4K;
338 return pte_offset_kernel(pmd, address);
340 EXPORT_SYMBOL_GPL(lookup_address);
343 * Set the new pmd in all the pgds we know about:
345 static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte)
348 set_pte_atomic(kpte, pte);
350 if (!SHARED_KERNEL_PMD) {
353 list_for_each_entry(page, &pgd_list, lru) {
358 pgd = (pgd_t *)page_address(page) + pgd_index(address);
359 pud = pud_offset(pgd, address);
360 pmd = pmd_offset(pud, address);
361 set_pte_atomic((pte_t *)pmd, pte);
368 try_preserve_large_page(pte_t *kpte, unsigned long address,
369 struct cpa_data *cpa)
371 unsigned long nextpage_addr, numpages, pmask, psize, flags, addr, pfn;
372 pte_t new_pte, old_pte, *tmp;
373 pgprot_t old_prot, new_prot;
377 if (cpa->force_split)
380 spin_lock_irqsave(&pgd_lock, flags);
382 * Check for races, another CPU might have split this page
385 tmp = lookup_address(address, &level);
391 psize = PMD_PAGE_SIZE;
392 pmask = PMD_PAGE_MASK;
396 psize = PUD_PAGE_SIZE;
397 pmask = PUD_PAGE_MASK;
406 * Calculate the number of pages, which fit into this large
407 * page starting at address:
409 nextpage_addr = (address + psize) & pmask;
410 numpages = (nextpage_addr - address) >> PAGE_SHIFT;
411 if (numpages < cpa->numpages)
412 cpa->numpages = numpages;
415 * We are safe now. Check whether the new pgprot is the same:
418 old_prot = new_prot = pte_pgprot(old_pte);
420 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
421 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
424 * old_pte points to the large page base address. So we need
425 * to add the offset of the virtual address:
427 pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT);
430 new_prot = static_protections(new_prot, address, pfn);
433 * We need to check the full range, whether
434 * static_protection() requires a different pgprot for one of
435 * the pages in the range we try to preserve:
437 addr = address + PAGE_SIZE;
439 for (i = 1; i < cpa->numpages; i++, addr += PAGE_SIZE, pfn++) {
440 pgprot_t chk_prot = static_protections(new_prot, addr, pfn);
442 if (pgprot_val(chk_prot) != pgprot_val(new_prot))
447 * If there are no changes, return. maxpages has been updated
450 if (pgprot_val(new_prot) == pgprot_val(old_prot)) {
456 * We need to change the attributes. Check, whether we can
457 * change the large page in one go. We request a split, when
458 * the address is not aligned and the number of pages is
459 * smaller than the number of pages in the large page. Note
460 * that we limited the number of possible pages already to
461 * the number of pages in the large page.
463 if (address == (nextpage_addr - psize) && cpa->numpages == numpages) {
465 * The address is aligned and the number of pages
466 * covers the full page.
468 new_pte = pfn_pte(pte_pfn(old_pte), canon_pgprot(new_prot));
469 __set_pmd_pte(kpte, address, new_pte);
470 cpa->flags |= CPA_FLUSHTLB;
475 spin_unlock_irqrestore(&pgd_lock, flags);
480 static int split_large_page(pte_t *kpte, unsigned long address)
482 unsigned long flags, pfn, pfninc = 1;
483 unsigned int i, level;
488 if (!debug_pagealloc)
489 spin_unlock(&cpa_lock);
490 base = alloc_pages(GFP_KERNEL | __GFP_NOTRACK, 0);
491 if (!debug_pagealloc)
492 spin_lock(&cpa_lock);
496 spin_lock_irqsave(&pgd_lock, flags);
498 * Check for races, another CPU might have split this page
501 tmp = lookup_address(address, &level);
505 pbase = (pte_t *)page_address(base);
506 paravirt_alloc_pte(&init_mm, page_to_pfn(base));
507 ref_prot = pte_pgprot(pte_clrhuge(*kpte));
509 * If we ever want to utilize the PAT bit, we need to
510 * update this function to make sure it's converted from
511 * bit 12 to bit 7 when we cross from the 2MB level to
514 WARN_ON_ONCE(pgprot_val(ref_prot) & _PAGE_PAT_LARGE);
517 if (level == PG_LEVEL_1G) {
518 pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT;
519 pgprot_val(ref_prot) |= _PAGE_PSE;
524 * Get the target pfn from the original entry:
526 pfn = pte_pfn(*kpte);
527 for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc)
528 set_pte(&pbase[i], pfn_pte(pfn, ref_prot));
530 if (address >= (unsigned long)__va(0) &&
531 address < (unsigned long)__va(max_low_pfn_mapped << PAGE_SHIFT))
532 split_page_count(level);
535 if (address >= (unsigned long)__va(1UL<<32) &&
536 address < (unsigned long)__va(max_pfn_mapped << PAGE_SHIFT))
537 split_page_count(level);
541 * Install the new, split up pagetable.
543 * We use the standard kernel pagetable protections for the new
544 * pagetable protections, the actual ptes set above control the
545 * primary protection behavior:
547 __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE)));
550 * Intel Atom errata AAH41 workaround.
552 * The real fix should be in hw or in a microcode update, but
553 * we also probabilistically try to reduce the window of having
554 * a large TLB mixed with 4K TLBs while instruction fetches are
563 * If we dropped out via the lookup_address check under
564 * pgd_lock then stick the page back into the pool:
568 spin_unlock_irqrestore(&pgd_lock, flags);
573 static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr,
577 * Ignore all non primary paths.
583 * Ignore the NULL PTE for kernel identity mapping, as it is expected
585 * Also set numpages to '1' indicating that we processed cpa req for
586 * one virtual address page and its pfn. TBD: numpages can be set based
587 * on the initial value and the level returned by lookup_address().
589 if (within(vaddr, PAGE_OFFSET,
590 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) {
592 cpa->pfn = __pa(vaddr) >> PAGE_SHIFT;
595 WARN(1, KERN_WARNING "CPA: called for zero pte. "
596 "vaddr = %lx cpa->vaddr = %lx\n", vaddr,
603 static int __change_page_attr(struct cpa_data *cpa, int primary)
605 unsigned long address;
608 pte_t *kpte, old_pte;
610 if (cpa->flags & CPA_PAGES_ARRAY) {
611 struct page *page = cpa->pages[cpa->curpage];
612 if (unlikely(PageHighMem(page)))
614 address = (unsigned long)page_address(page);
615 } else if (cpa->flags & CPA_ARRAY)
616 address = cpa->vaddr[cpa->curpage];
618 address = *cpa->vaddr;
620 kpte = lookup_address(address, &level);
622 return __cpa_process_fault(cpa, address, primary);
625 if (!pte_val(old_pte))
626 return __cpa_process_fault(cpa, address, primary);
628 if (level == PG_LEVEL_4K) {
630 pgprot_t new_prot = pte_pgprot(old_pte);
631 unsigned long pfn = pte_pfn(old_pte);
633 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
634 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
636 new_prot = static_protections(new_prot, address, pfn);
639 * We need to keep the pfn from the existing PTE,
640 * after all we're only going to change it's attributes
641 * not the memory it points to
643 new_pte = pfn_pte(pfn, canon_pgprot(new_prot));
646 * Do we really change anything ?
648 if (pte_val(old_pte) != pte_val(new_pte)) {
649 set_pte_atomic(kpte, new_pte);
650 cpa->flags |= CPA_FLUSHTLB;
657 * Check, whether we can keep the large page intact
658 * and just change the pte:
660 do_split = try_preserve_large_page(kpte, address, cpa);
662 * When the range fits into the existing large page,
663 * return. cp->numpages and cpa->tlbflush have been updated in
670 * We have to split the large page:
672 err = split_large_page(kpte, address);
675 * Do a global flush tlb after splitting the large page
676 * and before we do the actual change page attribute in the PTE.
678 * With out this, we violate the TLB application note, that says
679 * "The TLBs may contain both ordinary and large-page
680 * translations for a 4-KByte range of linear addresses. This
681 * may occur if software modifies the paging structures so that
682 * the page size used for the address range changes. If the two
683 * translations differ with respect to page frame or attributes
684 * (e.g., permissions), processor behavior is undefined and may
685 * be implementation-specific."
687 * We do this global tlb flush inside the cpa_lock, so that we
688 * don't allow any other cpu, with stale tlb entries change the
689 * page attribute in parallel, that also falls into the
690 * just split large page entry.
699 static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias);
701 static int cpa_process_alias(struct cpa_data *cpa)
703 struct cpa_data alias_cpa;
704 unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT);
708 if (cpa->pfn >= max_pfn_mapped)
712 if (cpa->pfn >= max_low_pfn_mapped && cpa->pfn < (1UL<<(32-PAGE_SHIFT)))
716 * No need to redo, when the primary call touched the direct
719 if (cpa->flags & CPA_PAGES_ARRAY) {
720 struct page *page = cpa->pages[cpa->curpage];
721 if (unlikely(PageHighMem(page)))
723 vaddr = (unsigned long)page_address(page);
724 } else if (cpa->flags & CPA_ARRAY)
725 vaddr = cpa->vaddr[cpa->curpage];
729 if (!(within(vaddr, PAGE_OFFSET,
730 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) {
733 alias_cpa.vaddr = &laddr;
734 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
736 ret = __change_page_attr_set_clr(&alias_cpa, 0);
743 * If the primary call didn't touch the high mapping already
744 * and the physical address is inside the kernel map, we need
745 * to touch the high mapped kernel as well:
747 if (!within(vaddr, (unsigned long)_text, _brk_end) &&
748 within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) {
749 unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) +
750 __START_KERNEL_map - phys_base;
752 alias_cpa.vaddr = &temp_cpa_vaddr;
753 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
756 * The high mapping range is imprecise, so ignore the
759 __change_page_attr_set_clr(&alias_cpa, 0);
766 static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias)
768 int ret, numpages = cpa->numpages;
772 * Store the remaining nr of pages for the large page
773 * preservation check.
775 cpa->numpages = numpages;
776 /* for array changes, we can't use large page */
777 if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY))
780 if (!debug_pagealloc)
781 spin_lock(&cpa_lock);
782 ret = __change_page_attr(cpa, checkalias);
783 if (!debug_pagealloc)
784 spin_unlock(&cpa_lock);
789 ret = cpa_process_alias(cpa);
795 * Adjust the number of pages with the result of the
796 * CPA operation. Either a large page has been
797 * preserved or a single page update happened.
799 BUG_ON(cpa->numpages > numpages);
800 numpages -= cpa->numpages;
801 if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY))
804 *cpa->vaddr += cpa->numpages * PAGE_SIZE;
810 static inline int cache_attr(pgprot_t attr)
812 return pgprot_val(attr) &
813 (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD);
816 static int change_page_attr_set_clr(unsigned long *addr, int numpages,
817 pgprot_t mask_set, pgprot_t mask_clr,
818 int force_split, int in_flag,
822 int ret, cache, checkalias;
823 unsigned long baddr = 0;
826 * Check, if we are requested to change a not supported
829 mask_set = canon_pgprot(mask_set);
830 mask_clr = canon_pgprot(mask_clr);
831 if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split)
834 /* Ensure we are PAGE_SIZE aligned */
835 if (in_flag & CPA_ARRAY) {
837 for (i = 0; i < numpages; i++) {
838 if (addr[i] & ~PAGE_MASK) {
839 addr[i] &= PAGE_MASK;
843 } else if (!(in_flag & CPA_PAGES_ARRAY)) {
845 * in_flag of CPA_PAGES_ARRAY implies it is aligned.
846 * No need to cehck in that case
848 if (*addr & ~PAGE_MASK) {
851 * People should not be passing in unaligned addresses:
856 * Save address for cache flush. *addr is modified in the call
857 * to __change_page_attr_set_clr() below.
862 /* Must avoid aliasing mappings in the highmem code */
869 cpa.numpages = numpages;
870 cpa.mask_set = mask_set;
871 cpa.mask_clr = mask_clr;
874 cpa.force_split = force_split;
876 if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY))
877 cpa.flags |= in_flag;
879 /* No alias checking for _NX bit modifications */
880 checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX;
882 ret = __change_page_attr_set_clr(&cpa, checkalias);
885 * Check whether we really changed something:
887 if (!(cpa.flags & CPA_FLUSHTLB))
891 * No need to flush, when we did not set any of the caching
894 cache = cache_attr(mask_set);
897 * On success we use clflush, when the CPU supports it to
898 * avoid the wbindv. If the CPU does not support it and in the
899 * error case we fall back to cpa_flush_all (which uses
902 if (!ret && cpu_has_clflush) {
903 if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) {
904 cpa_flush_array(addr, numpages, cache,
907 cpa_flush_range(baddr, numpages, cache);
909 cpa_flush_all(cache);
915 static inline int change_page_attr_set(unsigned long *addr, int numpages,
916 pgprot_t mask, int array)
918 return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0,
919 (array ? CPA_ARRAY : 0), NULL);
922 static inline int change_page_attr_clear(unsigned long *addr, int numpages,
923 pgprot_t mask, int array)
925 return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0,
926 (array ? CPA_ARRAY : 0), NULL);
929 static inline int cpa_set_pages_array(struct page **pages, int numpages,
932 return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0,
933 CPA_PAGES_ARRAY, pages);
936 static inline int cpa_clear_pages_array(struct page **pages, int numpages,
939 return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0,
940 CPA_PAGES_ARRAY, pages);
943 int _set_memory_uc(unsigned long addr, int numpages)
946 * for now UC MINUS. see comments in ioremap_nocache()
948 return change_page_attr_set(&addr, numpages,
949 __pgprot(_PAGE_CACHE_UC_MINUS), 0);
952 int set_memory_uc(unsigned long addr, int numpages)
957 * for now UC MINUS. see comments in ioremap_nocache()
959 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
960 _PAGE_CACHE_UC_MINUS, NULL);
964 ret = _set_memory_uc(addr, numpages);
971 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
975 EXPORT_SYMBOL(set_memory_uc);
977 int set_memory_array_uc(unsigned long *addr, int addrinarray)
983 * for now UC MINUS. see comments in ioremap_nocache()
985 for (i = 0; i < addrinarray; i++) {
986 ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE,
987 _PAGE_CACHE_UC_MINUS, NULL);
992 ret = change_page_attr_set(addr, addrinarray,
993 __pgprot(_PAGE_CACHE_UC_MINUS), 1);
1000 for (j = 0; j < i; j++)
1001 free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE);
1005 EXPORT_SYMBOL(set_memory_array_uc);
1007 int _set_memory_wc(unsigned long addr, int numpages)
1010 unsigned long addr_copy = addr;
1012 ret = change_page_attr_set(&addr, numpages,
1013 __pgprot(_PAGE_CACHE_UC_MINUS), 0);
1015 ret = change_page_attr_set_clr(&addr_copy, numpages,
1016 __pgprot(_PAGE_CACHE_WC),
1017 __pgprot(_PAGE_CACHE_MASK),
1023 int set_memory_wc(unsigned long addr, int numpages)
1028 return set_memory_uc(addr, numpages);
1030 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1031 _PAGE_CACHE_WC, NULL);
1035 ret = _set_memory_wc(addr, numpages);
1042 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1046 EXPORT_SYMBOL(set_memory_wc);
1048 int _set_memory_wb(unsigned long addr, int numpages)
1050 return change_page_attr_clear(&addr, numpages,
1051 __pgprot(_PAGE_CACHE_MASK), 0);
1054 int set_memory_wb(unsigned long addr, int numpages)
1058 ret = _set_memory_wb(addr, numpages);
1062 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1065 EXPORT_SYMBOL(set_memory_wb);
1067 int set_memory_array_wb(unsigned long *addr, int addrinarray)
1072 ret = change_page_attr_clear(addr, addrinarray,
1073 __pgprot(_PAGE_CACHE_MASK), 1);
1077 for (i = 0; i < addrinarray; i++)
1078 free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE);
1082 EXPORT_SYMBOL(set_memory_array_wb);
1084 int set_memory_x(unsigned long addr, int numpages)
1086 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0);
1088 EXPORT_SYMBOL(set_memory_x);
1090 int set_memory_nx(unsigned long addr, int numpages)
1092 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0);
1094 EXPORT_SYMBOL(set_memory_nx);
1096 int set_memory_ro(unsigned long addr, int numpages)
1098 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0);
1100 EXPORT_SYMBOL_GPL(set_memory_ro);
1102 int set_memory_rw(unsigned long addr, int numpages)
1104 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0);
1106 EXPORT_SYMBOL_GPL(set_memory_rw);
1108 int set_memory_np(unsigned long addr, int numpages)
1110 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0);
1113 int set_memory_4k(unsigned long addr, int numpages)
1115 return change_page_attr_set_clr(&addr, numpages, __pgprot(0),
1116 __pgprot(0), 1, 0, NULL);
1119 int set_pages_uc(struct page *page, int numpages)
1121 unsigned long addr = (unsigned long)page_address(page);
1123 return set_memory_uc(addr, numpages);
1125 EXPORT_SYMBOL(set_pages_uc);
1127 int set_pages_array_uc(struct page **pages, int addrinarray)
1129 unsigned long start;
1134 for (i = 0; i < addrinarray; i++) {
1135 if (PageHighMem(pages[i]))
1137 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1138 end = start + PAGE_SIZE;
1139 if (reserve_memtype(start, end, _PAGE_CACHE_UC_MINUS, NULL))
1143 if (cpa_set_pages_array(pages, addrinarray,
1144 __pgprot(_PAGE_CACHE_UC_MINUS)) == 0) {
1145 return 0; /* Success */
1149 for (i = 0; i < free_idx; i++) {
1150 if (PageHighMem(pages[i]))
1152 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1153 end = start + PAGE_SIZE;
1154 free_memtype(start, end);
1158 EXPORT_SYMBOL(set_pages_array_uc);
1160 int set_pages_wb(struct page *page, int numpages)
1162 unsigned long addr = (unsigned long)page_address(page);
1164 return set_memory_wb(addr, numpages);
1166 EXPORT_SYMBOL(set_pages_wb);
1168 int set_pages_array_wb(struct page **pages, int addrinarray)
1171 unsigned long start;
1175 retval = cpa_clear_pages_array(pages, addrinarray,
1176 __pgprot(_PAGE_CACHE_MASK));
1180 for (i = 0; i < addrinarray; i++) {
1181 if (PageHighMem(pages[i]))
1183 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1184 end = start + PAGE_SIZE;
1185 free_memtype(start, end);
1190 EXPORT_SYMBOL(set_pages_array_wb);
1192 int set_pages_x(struct page *page, int numpages)
1194 unsigned long addr = (unsigned long)page_address(page);
1196 return set_memory_x(addr, numpages);
1198 EXPORT_SYMBOL(set_pages_x);
1200 int set_pages_nx(struct page *page, int numpages)
1202 unsigned long addr = (unsigned long)page_address(page);
1204 return set_memory_nx(addr, numpages);
1206 EXPORT_SYMBOL(set_pages_nx);
1208 int set_pages_ro(struct page *page, int numpages)
1210 unsigned long addr = (unsigned long)page_address(page);
1212 return set_memory_ro(addr, numpages);
1215 int set_pages_rw(struct page *page, int numpages)
1217 unsigned long addr = (unsigned long)page_address(page);
1219 return set_memory_rw(addr, numpages);
1222 #ifdef CONFIG_DEBUG_PAGEALLOC
1224 static int __set_pages_p(struct page *page, int numpages)
1226 unsigned long tempaddr = (unsigned long) page_address(page);
1227 struct cpa_data cpa = { .vaddr = &tempaddr,
1228 .numpages = numpages,
1229 .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1230 .mask_clr = __pgprot(0),
1234 * No alias checking needed for setting present flag. otherwise,
1235 * we may need to break large pages for 64-bit kernel text
1236 * mappings (this adds to complexity if we want to do this from
1237 * atomic context especially). Let's keep it simple!
1239 return __change_page_attr_set_clr(&cpa, 0);
1242 static int __set_pages_np(struct page *page, int numpages)
1244 unsigned long tempaddr = (unsigned long) page_address(page);
1245 struct cpa_data cpa = { .vaddr = &tempaddr,
1246 .numpages = numpages,
1247 .mask_set = __pgprot(0),
1248 .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1252 * No alias checking needed for setting not present flag. otherwise,
1253 * we may need to break large pages for 64-bit kernel text
1254 * mappings (this adds to complexity if we want to do this from
1255 * atomic context especially). Let's keep it simple!
1257 return __change_page_attr_set_clr(&cpa, 0);
1260 void kernel_map_pages(struct page *page, int numpages, int enable)
1262 if (PageHighMem(page))
1265 debug_check_no_locks_freed(page_address(page),
1266 numpages * PAGE_SIZE);
1270 * If page allocator is not up yet then do not call c_p_a():
1272 if (!debug_pagealloc_enabled)
1276 * The return value is ignored as the calls cannot fail.
1277 * Large pages for identity mappings are not used at boot time
1278 * and hence no memory allocations during large page split.
1281 __set_pages_p(page, numpages);
1283 __set_pages_np(page, numpages);
1286 * We should perform an IPI and flush all tlbs,
1287 * but that can deadlock->flush only current cpu:
1292 #ifdef CONFIG_HIBERNATION
1294 bool kernel_page_present(struct page *page)
1299 if (PageHighMem(page))
1302 pte = lookup_address((unsigned long)page_address(page), &level);
1303 return (pte_val(*pte) & _PAGE_PRESENT);
1306 #endif /* CONFIG_HIBERNATION */
1308 #endif /* CONFIG_DEBUG_PAGEALLOC */
1311 * The testcases use internal knowledge of the implementation that shouldn't
1312 * be exposed to the rest of the kernel. Include these directly here.
1314 #ifdef CONFIG_CPA_DEBUG
1315 #include "pageattr-test.c"