SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/mm.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27 #include <linux/moduleparam.h>
  28 #include "kvm_cache_regs.h"
  29 #include "x86.h"
  30
  31 #include <asm/io.h>
  32 #include <asm/desc.h>
  33 #include <asm/vmx.h>
  34 #include <asm/virtext.h>
  35 #include <asm/mce.h>
  36
  37 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  38
  39 MODULE_AUTHOR("Qumranet");
  40 MODULE_LICENSE("GPL");
  41
  42 static int __read_mostly bypass_guest_pf = 1;
  43 module_param(bypass_guest_pf, bool, S_IRUGO);
  44
  45 static int __read_mostly enable_vpid = 1;
  46 module_param_named(vpid, enable_vpid, bool, 0444);
  47
  48 static int __read_mostly flexpriority_enabled = 1;
  49 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  50
  51 static int __read_mostly enable_ept = 1;
  52 module_param_named(ept, enable_ept, bool, S_IRUGO);
  53
  54 static int __read_mostly enable_unrestricted_guest = 1;
  55 module_param_named(unrestricted_guest,
  56                         enable_unrestricted_guest, bool, S_IRUGO);
  57
  58 static int __read_mostly emulate_invalid_guest_state = 0;
  59 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  60
  61 struct vmcs {
  62         u32 revision_id;
  63         u32 abort;
  64         char data[0];
  65 };
  66
  67 struct vcpu_vmx {
  68         struct kvm_vcpu       vcpu;
  69         struct list_head      local_vcpus_link;
  70         unsigned long         host_rsp;
  71         int                   launched;
  72         u8                    fail;
  73         u32                   idt_vectoring_info;
  74         struct kvm_msr_entry *guest_msrs;
  75         struct kvm_msr_entry *host_msrs;
  76         int                   nmsrs;
  77         int                   save_nmsrs;
  78         int                   msr_offset_efer;
  79 #ifdef CONFIG_X86_64
  80         int                   msr_offset_kernel_gs_base;
  81 #endif
  82         struct vmcs          *vmcs;
  83         struct {
  84                 int           loaded;
  85                 u16           fs_sel, gs_sel, ldt_sel;
  86                 int           gs_ldt_reload_needed;
  87                 int           fs_reload_needed;
  88                 int           guest_efer_loaded;
  89         } host_state;
  90         struct {
  91                 int vm86_active;
  92                 u8 save_iopl;
  93                 struct kvm_save_segment {
  94                         u16 selector;
  95                         unsigned long base;
  96                         u32 limit;
  97                         u32 ar;
  98                 } tr, es, ds, fs, gs;
  99                 struct {
 100                         bool pending;
 101                         u8 vector;
 102                         unsigned rip;
 103                 } irq;
 104         } rmode;
 105         int vpid;
 106         bool emulation_required;
 107         enum emulation_result invalid_state_emulation_result;
 108
 109         /* Support for vnmi-less CPUs */
 110         int soft_vnmi_blocked;
 111         ktime_t entry_time;
 112         s64 vnmi_blocked_time;
 113         u32 exit_reason;
 114 };
 115
 116 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 117 {
 118         return container_of(vcpu, struct vcpu_vmx, vcpu);
 119 }
 120
 121 static int init_rmode(struct kvm *kvm);
 122 static u64 construct_eptp(unsigned long root_hpa);
 123
 124 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 125 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 126 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 127
 128 static unsigned long *vmx_io_bitmap_a;
 129 static unsigned long *vmx_io_bitmap_b;
 130 static unsigned long *vmx_msr_bitmap_legacy;
 131 static unsigned long *vmx_msr_bitmap_longmode;
 132
 133 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 134 static DEFINE_SPINLOCK(vmx_vpid_lock);
 135
 136 static struct vmcs_config {
 137         int size;
 138         int order;
 139         u32 revision_id;
 140         u32 pin_based_exec_ctrl;
 141         u32 cpu_based_exec_ctrl;
 142         u32 cpu_based_2nd_exec_ctrl;
 143         u32 vmexit_ctrl;
 144         u32 vmentry_ctrl;
 145 } vmcs_config;
 146
 147 static struct vmx_capability {
 148         u32 ept;
 149         u32 vpid;
 150 } vmx_capability;
 151
 152 #define VMX_SEGMENT_FIELD(seg)                                  \
 153         [VCPU_SREG_##seg] = {                                   \
 154                 .selector = GUEST_##seg##_SELECTOR,             \
 155                 .base = GUEST_##seg##_BASE,                     \
 156                 .limit = GUEST_##seg##_LIMIT,                   \
 157                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 158         }
 159
 160 static struct kvm_vmx_segment_field {
 161         unsigned selector;
 162         unsigned base;
 163         unsigned limit;
 164         unsigned ar_bytes;
 165 } kvm_vmx_segment_fields[] = {
 166         VMX_SEGMENT_FIELD(CS),
 167         VMX_SEGMENT_FIELD(DS),
 168         VMX_SEGMENT_FIELD(ES),
 169         VMX_SEGMENT_FIELD(FS),
 170         VMX_SEGMENT_FIELD(GS),
 171         VMX_SEGMENT_FIELD(SS),
 172         VMX_SEGMENT_FIELD(TR),
 173         VMX_SEGMENT_FIELD(LDTR),
 174 };
 175
 176 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 177
 178 /*
 179  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 180  * away by decrementing the array size.
 181  */
 182 static const u32 vmx_msr_index[] = {
 183 #ifdef CONFIG_X86_64
 184         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
 185 #endif
 186         MSR_EFER, MSR_K6_STAR,
 187 };
 188 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 189
 190 static void load_msrs(struct kvm_msr_entry *e, int n)
 191 {
 192         int i;
 193
 194         for (i = 0; i < n; ++i)
 195                 wrmsrl(e[i].index, e[i].data);
 196 }
 197
 198 static void save_msrs(struct kvm_msr_entry *e, int n)
 199 {
 200         int i;
 201
 202         for (i = 0; i < n; ++i)
 203                 rdmsrl(e[i].index, e[i].data);
 204 }
 205
 206 static inline int is_page_fault(u32 intr_info)
 207 {
 208         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 209                              INTR_INFO_VALID_MASK)) ==
 210                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 211 }
 212
 213 static inline int is_no_device(u32 intr_info)
 214 {
 215         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 216                              INTR_INFO_VALID_MASK)) ==
 217                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 218 }
 219
 220 static inline int is_invalid_opcode(u32 intr_info)
 221 {
 222         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 223                              INTR_INFO_VALID_MASK)) ==
 224                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 225 }
 226
 227 static inline int is_external_interrupt(u32 intr_info)
 228 {
 229         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 230                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 231 }
 232
 233 static inline int is_machine_check(u32 intr_info)
 234 {
 235         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 236                              INTR_INFO_VALID_MASK)) ==
 237                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 238 }
 239
 240 static inline int cpu_has_vmx_msr_bitmap(void)
 241 {
 242         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 243 }
 244
 245 static inline int cpu_has_vmx_tpr_shadow(void)
 246 {
 247         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 248 }
 249
 250 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 251 {
 252         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 253 }
 254
 255 static inline int cpu_has_secondary_exec_ctrls(void)
 256 {
 257         return vmcs_config.cpu_based_exec_ctrl &
 258                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 259 }
 260
 261 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 262 {
 263         return vmcs_config.cpu_based_2nd_exec_ctrl &
 264                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 265 }
 266
 267 static inline bool cpu_has_vmx_flexpriority(void)
 268 {
 269         return cpu_has_vmx_tpr_shadow() &&
 270                 cpu_has_vmx_virtualize_apic_accesses();
 271 }
 272
 273 static inline int cpu_has_vmx_invept_individual_addr(void)
 274 {
 275         return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
 276 }
 277
 278 static inline int cpu_has_vmx_invept_context(void)
 279 {
 280         return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
 281 }
 282
 283 static inline int cpu_has_vmx_invept_global(void)
 284 {
 285         return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
 286 }
 287
 288 static inline int cpu_has_vmx_ept(void)
 289 {
 290         return vmcs_config.cpu_based_2nd_exec_ctrl &
 291                 SECONDARY_EXEC_ENABLE_EPT;
 292 }
 293
 294 static inline int cpu_has_vmx_unrestricted_guest(void)
 295 {
 296         return vmcs_config.cpu_based_2nd_exec_ctrl &
 297                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 298 }
 299
 300 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 301 {
 302         return flexpriority_enabled &&
 303                 (cpu_has_vmx_virtualize_apic_accesses()) &&
 304                 (irqchip_in_kernel(kvm));
 305 }
 306
 307 static inline int cpu_has_vmx_vpid(void)
 308 {
 309         return vmcs_config.cpu_based_2nd_exec_ctrl &
 310                 SECONDARY_EXEC_ENABLE_VPID;
 311 }
 312
 313 static inline int cpu_has_virtual_nmis(void)
 314 {
 315         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 316 }
 317
 318 static inline bool report_flexpriority(void)
 319 {
 320         return flexpriority_enabled;
 321 }
 322
 323 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 324 {
 325         int i;
 326
 327         for (i = 0; i < vmx->nmsrs; ++i)
 328                 if (vmx->guest_msrs[i].index == msr)
 329                         return i;
 330         return -1;
 331 }
 332
 333 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 334 {
 335     struct {
 336         u64 vpid : 16;
 337         u64 rsvd : 48;
 338         u64 gva;
 339     } operand = { vpid, 0, gva };
 340
 341     asm volatile (__ex(ASM_VMX_INVVPID)
 342                   /* CF==1 or ZF==1 --> rc = -1 */
 343                   "; ja 1f ; ud2 ; 1:"
 344                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 345 }
 346
 347 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 348 {
 349         struct {
 350                 u64 eptp, gpa;
 351         } operand = {eptp, gpa};
 352
 353         asm volatile (__ex(ASM_VMX_INVEPT)
 354                         /* CF==1 or ZF==1 --> rc = -1 */
 355                         "; ja 1f ; ud2 ; 1:\n"
 356                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 357 }
 358
 359 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 360 {
 361         int i;
 362
 363         i = __find_msr_index(vmx, msr);
 364         if (i >= 0)
 365                 return &vmx->guest_msrs[i];
 366         return NULL;
 367 }
 368
 369 static void vmcs_clear(struct vmcs *vmcs)
 370 {
 371         u64 phys_addr = __pa(vmcs);
 372         u8 error;
 373
 374         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 375                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 376                       : "cc", "memory");
 377         if (error)
 378                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 379                        vmcs, phys_addr);
 380 }
 381
 382 static void __vcpu_clear(void *arg)
 383 {
 384         struct vcpu_vmx *vmx = arg;
 385         int cpu = raw_smp_processor_id();
 386
 387         if (vmx->vcpu.cpu == cpu)
 388                 vmcs_clear(vmx->vmcs);
 389         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 390                 per_cpu(current_vmcs, cpu) = NULL;
 391         rdtscll(vmx->vcpu.arch.host_tsc);
 392         list_del(&vmx->local_vcpus_link);
 393         vmx->vcpu.cpu = -1;
 394         vmx->launched = 0;
 395 }
 396
 397 static void vcpu_clear(struct vcpu_vmx *vmx)
 398 {
 399         if (vmx->vcpu.cpu == -1)
 400                 return;
 401         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 402 }
 403
 404 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 405 {
 406         if (vmx->vpid == 0)
 407                 return;
 408
 409         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 410 }
 411
 412 static inline void ept_sync_global(void)
 413 {
 414         if (cpu_has_vmx_invept_global())
 415                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 416 }
 417
 418 static inline void ept_sync_context(u64 eptp)
 419 {
 420         if (enable_ept) {
 421                 if (cpu_has_vmx_invept_context())
 422                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 423                 else
 424                         ept_sync_global();
 425         }
 426 }
 427
 428 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 429 {
 430         if (enable_ept) {
 431                 if (cpu_has_vmx_invept_individual_addr())
 432                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 433                                         eptp, gpa);
 434                 else
 435                         ept_sync_context(eptp);
 436         }
 437 }
 438
 439 static unsigned long vmcs_readl(unsigned long field)
 440 {
 441         unsigned long value;
 442
 443         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 444                       : "=a"(value) : "d"(field) : "cc");
 445         return value;
 446 }
 447
 448 static u16 vmcs_read16(unsigned long field)
 449 {
 450         return vmcs_readl(field);
 451 }
 452
 453 static u32 vmcs_read32(unsigned long field)
 454 {
 455         return vmcs_readl(field);
 456 }
 457
 458 static u64 vmcs_read64(unsigned long field)
 459 {
 460 #ifdef CONFIG_X86_64
 461         return vmcs_readl(field);
 462 #else
 463         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 464 #endif
 465 }
 466
 467 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 468 {
 469         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 470                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 471         dump_stack();
 472 }
 473
 474 static void vmcs_writel(unsigned long field, unsigned long value)
 475 {
 476         u8 error;
 477
 478         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 479                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 480         if (unlikely(error))
 481                 vmwrite_error(field, value);
 482 }
 483
 484 static void vmcs_write16(unsigned long field, u16 value)
 485 {
 486         vmcs_writel(field, value);
 487 }
 488
 489 static void vmcs_write32(unsigned long field, u32 value)
 490 {
 491         vmcs_writel(field, value);
 492 }
 493
 494 static void vmcs_write64(unsigned long field, u64 value)
 495 {
 496         vmcs_writel(field, value);
 497 #ifndef CONFIG_X86_64
 498         asm volatile ("");
 499         vmcs_writel(field+1, value >> 32);
 500 #endif
 501 }
 502
 503 static void vmcs_clear_bits(unsigned long field, u32 mask)
 504 {
 505         vmcs_writel(field, vmcs_readl(field) & ~mask);
 506 }
 507
 508 static void vmcs_set_bits(unsigned long field, u32 mask)
 509 {
 510         vmcs_writel(field, vmcs_readl(field) | mask);
 511 }
 512
 513 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 514 {
 515         u32 eb;
 516
 517         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
 518         if (!vcpu->fpu_active)
 519                 eb |= 1u << NM_VECTOR;
 520         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
 521                 if (vcpu->guest_debug &
 522                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
 523                         eb |= 1u << DB_VECTOR;
 524                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
 525                         eb |= 1u << BP_VECTOR;
 526         }
 527         if (to_vmx(vcpu)->rmode.vm86_active)
 528                 eb = ~0;
 529         if (enable_ept)
 530                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 531         vmcs_write32(EXCEPTION_BITMAP, eb);
 532 }
 533
 534 static void reload_tss(void)
 535 {
 536         /*
 537          * VT restores TR but not its size.  Useless.
 538          */
 539         struct descriptor_table gdt;
 540         struct desc_struct *descs;
 541
 542         kvm_get_gdt(&gdt);
 543         descs = (void *)gdt.base;
 544         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 545         load_TR_desc();
 546 }
 547
 548 static void load_transition_efer(struct vcpu_vmx *vmx)
 549 {
 550         int efer_offset = vmx->msr_offset_efer;
 551         u64 host_efer = vmx->host_msrs[efer_offset].data;
 552         u64 guest_efer = vmx->guest_msrs[efer_offset].data;
 553         u64 ignore_bits;
 554
 555         if (efer_offset < 0)
 556                 return;
 557         /*
 558          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 559          * outside long mode
 560          */
 561         ignore_bits = EFER_NX | EFER_SCE;
 562 #ifdef CONFIG_X86_64
 563         ignore_bits |= EFER_LMA | EFER_LME;
 564         /* SCE is meaningful only in long mode on Intel */
 565         if (guest_efer & EFER_LMA)
 566                 ignore_bits &= ~(u64)EFER_SCE;
 567 #endif
 568         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
 569                 return;
 570
 571         vmx->host_state.guest_efer_loaded = 1;
 572         guest_efer &= ~ignore_bits;
 573         guest_efer |= host_efer & ignore_bits;
 574         wrmsrl(MSR_EFER, guest_efer);
 575         vmx->vcpu.stat.efer_reload++;
 576 }
 577
 578 static void reload_host_efer(struct vcpu_vmx *vmx)
 579 {
 580         if (vmx->host_state.guest_efer_loaded) {
 581                 vmx->host_state.guest_efer_loaded = 0;
 582                 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
 583         }
 584 }
 585
 586 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 587 {
 588         struct vcpu_vmx *vmx = to_vmx(vcpu);
 589
 590         if (vmx->host_state.loaded)
 591                 return;
 592
 593         vmx->host_state.loaded = 1;
 594         /*
 595          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 596          * allow segment selectors with cpl > 0 or ti == 1.
 597          */
 598         vmx->host_state.ldt_sel = kvm_read_ldt();
 599         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 600         vmx->host_state.fs_sel = kvm_read_fs();
 601         if (!(vmx->host_state.fs_sel & 7)) {
 602                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 603                 vmx->host_state.fs_reload_needed = 0;
 604         } else {
 605                 vmcs_write16(HOST_FS_SELECTOR, 0);
 606                 vmx->host_state.fs_reload_needed = 1;
 607         }
 608         vmx->host_state.gs_sel = kvm_read_gs();
 609         if (!(vmx->host_state.gs_sel & 7))
 610                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 611         else {
 612                 vmcs_write16(HOST_GS_SELECTOR, 0);
 613                 vmx->host_state.gs_ldt_reload_needed = 1;
 614         }
 615
 616 #ifdef CONFIG_X86_64
 617         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 618         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 619 #else
 620         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 621         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 622 #endif
 623
 624 #ifdef CONFIG_X86_64
 625         if (is_long_mode(&vmx->vcpu))
 626                 save_msrs(vmx->host_msrs +
 627                           vmx->msr_offset_kernel_gs_base, 1);
 628
 629 #endif
 630         load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 631         load_transition_efer(vmx);
 632 }
 633
 634 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 635 {
 636         unsigned long flags;
 637
 638         if (!vmx->host_state.loaded)
 639                 return;
 640
 641         ++vmx->vcpu.stat.host_state_reload;
 642         vmx->host_state.loaded = 0;
 643         if (vmx->host_state.fs_reload_needed)
 644                 kvm_load_fs(vmx->host_state.fs_sel);
 645         if (vmx->host_state.gs_ldt_reload_needed) {
 646                 kvm_load_ldt(vmx->host_state.ldt_sel);
 647                 /*
 648                  * If we have to reload gs, we must take care to
 649                  * preserve our gs base.
 650                  */
 651                 local_irq_save(flags);
 652                 kvm_load_gs(vmx->host_state.gs_sel);
 653 #ifdef CONFIG_X86_64
 654                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 655 #endif
 656                 local_irq_restore(flags);
 657         }
 658         reload_tss();
 659         save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 660         load_msrs(vmx->host_msrs, vmx->save_nmsrs);
 661         reload_host_efer(vmx);
 662 }
 663
 664 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 665 {
 666         preempt_disable();
 667         __vmx_load_host_state(vmx);
 668         preempt_enable();
 669 }
 670
 671 /*
 672  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 673  * vcpu mutex is already taken.
 674  */
 675 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 676 {
 677         struct vcpu_vmx *vmx = to_vmx(vcpu);
 678         u64 phys_addr = __pa(vmx->vmcs);
 679         u64 tsc_this, delta, new_offset;
 680
 681         if (vcpu->cpu != cpu) {
 682                 vcpu_clear(vmx);
 683                 kvm_migrate_timers(vcpu);
 684                 vpid_sync_vcpu_all(vmx);
 685                 local_irq_disable();
 686                 list_add(&vmx->local_vcpus_link,
 687                          &per_cpu(vcpus_on_cpu, cpu));
 688                 local_irq_enable();
 689         }
 690
 691         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 692                 u8 error;
 693
 694                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 695                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 696                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 697                               : "cc");
 698                 if (error)
 699                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 700                                vmx->vmcs, phys_addr);
 701         }
 702
 703         if (vcpu->cpu != cpu) {
 704                 struct descriptor_table dt;
 705                 unsigned long sysenter_esp;
 706
 707                 vcpu->cpu = cpu;
 708                 /*
 709                  * Linux uses per-cpu TSS and GDT, so set these when switching
 710                  * processors.
 711                  */
 712                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 713                 kvm_get_gdt(&dt);
 714                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 715
 716                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 717                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 718
 719                 /*
 720                  * Make sure the time stamp counter is monotonous.
 721                  */
 722                 rdtscll(tsc_this);
 723                 if (tsc_this < vcpu->arch.host_tsc) {
 724                         delta = vcpu->arch.host_tsc - tsc_this;
 725                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 726                         vmcs_write64(TSC_OFFSET, new_offset);
 727                 }
 728         }
 729 }
 730
 731 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 732 {
 733         __vmx_load_host_state(to_vmx(vcpu));
 734 }
 735
 736 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 737 {
 738         if (vcpu->fpu_active)
 739                 return;
 740         vcpu->fpu_active = 1;
 741         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 742         if (vcpu->arch.cr0 & X86_CR0_TS)
 743                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 744         update_exception_bitmap(vcpu);
 745 }
 746
 747 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 748 {
 749         if (!vcpu->fpu_active)
 750                 return;
 751         vcpu->fpu_active = 0;
 752         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 753         update_exception_bitmap(vcpu);
 754 }
 755
 756 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 757 {
 758         return vmcs_readl(GUEST_RFLAGS);
 759 }
 760
 761 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 762 {
 763         if (to_vmx(vcpu)->rmode.vm86_active)
 764                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 765         vmcs_writel(GUEST_RFLAGS, rflags);
 766 }
 767
 768 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 769 {
 770         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 771         int ret = 0;
 772
 773         if (interruptibility & GUEST_INTR_STATE_STI)
 774                 ret |= X86_SHADOW_INT_STI;
 775         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
 776                 ret |= X86_SHADOW_INT_MOV_SS;
 777
 778         return ret & mask;
 779 }
 780
 781 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 782 {
 783         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 784         u32 interruptibility = interruptibility_old;
 785
 786         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
 787
 788         if (mask & X86_SHADOW_INT_MOV_SS)
 789                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
 790         if (mask & X86_SHADOW_INT_STI)
 791                 interruptibility |= GUEST_INTR_STATE_STI;
 792
 793         if ((interruptibility != interruptibility_old))
 794                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
 795 }
 796
 797 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 798 {
 799         unsigned long rip;
 800
 801         rip = kvm_rip_read(vcpu);
 802         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 803         kvm_rip_write(vcpu, rip);
 804
 805         /* skipping an emulated instruction also counts */
 806         vmx_set_interrupt_shadow(vcpu, 0);
 807 }
 808
 809 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 810                                 bool has_error_code, u32 error_code)
 811 {
 812         struct vcpu_vmx *vmx = to_vmx(vcpu);
 813         u32 intr_info = nr | INTR_INFO_VALID_MASK;
 814
 815         if (has_error_code) {
 816                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 817                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
 818         }
 819
 820         if (vmx->rmode.vm86_active) {
 821                 vmx->rmode.irq.pending = true;
 822                 vmx->rmode.irq.vector = nr;
 823                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
 824                 if (kvm_exception_is_soft(nr))
 825                         vmx->rmode.irq.rip +=
 826                                 vmx->vcpu.arch.event_exit_inst_len;
 827                 intr_info |= INTR_TYPE_SOFT_INTR;
 828                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 829                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
 830                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
 831                 return;
 832         }
 833
 834         if (kvm_exception_is_soft(nr)) {
 835                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
 836                              vmx->vcpu.arch.event_exit_inst_len);
 837                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
 838         } else
 839                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
 840
 841         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 842 }
 843
 844 /*
 845  * Swap MSR entry in host/guest MSR entry array.
 846  */
 847 #ifdef CONFIG_X86_64
 848 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 849 {
 850         struct kvm_msr_entry tmp;
 851
 852         tmp = vmx->guest_msrs[to];
 853         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 854         vmx->guest_msrs[from] = tmp;
 855         tmp = vmx->host_msrs[to];
 856         vmx->host_msrs[to] = vmx->host_msrs[from];
 857         vmx->host_msrs[from] = tmp;
 858 }
 859 #endif
 860
 861 /*
 862  * Set up the vmcs to automatically save and restore system
 863  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 864  * mode, as fiddling with msrs is very expensive.
 865  */
 866 static void setup_msrs(struct vcpu_vmx *vmx)
 867 {
 868         int save_nmsrs;
 869         unsigned long *msr_bitmap;
 870
 871         vmx_load_host_state(vmx);
 872         save_nmsrs = 0;
 873 #ifdef CONFIG_X86_64
 874         if (is_long_mode(&vmx->vcpu)) {
 875                 int index;
 876
 877                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 878                 if (index >= 0)
 879                         move_msr_up(vmx, index, save_nmsrs++);
 880                 index = __find_msr_index(vmx, MSR_LSTAR);
 881                 if (index >= 0)
 882                         move_msr_up(vmx, index, save_nmsrs++);
 883                 index = __find_msr_index(vmx, MSR_CSTAR);
 884                 if (index >= 0)
 885                         move_msr_up(vmx, index, save_nmsrs++);
 886                 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 887                 if (index >= 0)
 888                         move_msr_up(vmx, index, save_nmsrs++);
 889                 /*
 890                  * MSR_K6_STAR is only needed on long mode guests, and only
 891                  * if efer.sce is enabled.
 892                  */
 893                 index = __find_msr_index(vmx, MSR_K6_STAR);
 894                 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
 895                         move_msr_up(vmx, index, save_nmsrs++);
 896         }
 897 #endif
 898         vmx->save_nmsrs = save_nmsrs;
 899
 900 #ifdef CONFIG_X86_64
 901         vmx->msr_offset_kernel_gs_base =
 902                 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 903 #endif
 904         vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
 905
 906         if (cpu_has_vmx_msr_bitmap()) {
 907                 if (is_long_mode(&vmx->vcpu))
 908                         msr_bitmap = vmx_msr_bitmap_longmode;
 909                 else
 910                         msr_bitmap = vmx_msr_bitmap_legacy;
 911
 912                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
 913         }
 914 }
 915
 916 /*
 917  * reads and returns guest's timestamp counter "register"
 918  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 919  */
 920 static u64 guest_read_tsc(void)
 921 {
 922         u64 host_tsc, tsc_offset;
 923
 924         rdtscll(host_tsc);
 925         tsc_offset = vmcs_read64(TSC_OFFSET);
 926         return host_tsc + tsc_offset;
 927 }
 928
 929 /*
 930  * writes 'guest_tsc' into guest's timestamp counter "register"
 931  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 932  */
 933 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
 934 {
 935         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 936 }
 937
 938 /*
 939  * Reads an msr value (of 'msr_index') into 'pdata'.
 940  * Returns 0 on success, non-0 otherwise.
 941  * Assumes vcpu_load() was already called.
 942  */
 943 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
 944 {
 945         u64 data;
 946         struct kvm_msr_entry *msr;
 947
 948         if (!pdata) {
 949                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
 950                 return -EINVAL;
 951         }
 952
 953         switch (msr_index) {
 954 #ifdef CONFIG_X86_64
 955         case MSR_FS_BASE:
 956                 data = vmcs_readl(GUEST_FS_BASE);
 957                 break;
 958         case MSR_GS_BASE:
 959                 data = vmcs_readl(GUEST_GS_BASE);
 960                 break;
 961         case MSR_EFER:
 962                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 963 #endif
 964         case MSR_IA32_TSC:
 965                 data = guest_read_tsc();
 966                 break;
 967         case MSR_IA32_SYSENTER_CS:
 968                 data = vmcs_read32(GUEST_SYSENTER_CS);
 969                 break;
 970         case MSR_IA32_SYSENTER_EIP:
 971                 data = vmcs_readl(GUEST_SYSENTER_EIP);
 972                 break;
 973         case MSR_IA32_SYSENTER_ESP:
 974                 data = vmcs_readl(GUEST_SYSENTER_ESP);
 975                 break;
 976         default:
 977                 vmx_load_host_state(to_vmx(vcpu));
 978                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
 979                 if (msr) {
 980                         data = msr->data;
 981                         break;
 982                 }
 983                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 984         }
 985
 986         *pdata = data;
 987         return 0;
 988 }
 989
 990 /*
 991  * Writes msr value into into the appropriate "register".
 992  * Returns 0 on success, non-0 otherwise.
 993  * Assumes vcpu_load() was already called.
 994  */
 995 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
 996 {
 997         struct vcpu_vmx *vmx = to_vmx(vcpu);
 998         struct kvm_msr_entry *msr;
 999         u64 host_tsc;
1000         int ret = 0;
1001
1002         switch (msr_index) {
1003         case MSR_EFER:
1004                 vmx_load_host_state(vmx);
1005                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1006                 break;
1007 #ifdef CONFIG_X86_64
1008         case MSR_FS_BASE:
1009                 vmcs_writel(GUEST_FS_BASE, data);
1010                 break;
1011         case MSR_GS_BASE:
1012                 vmcs_writel(GUEST_GS_BASE, data);
1013                 break;
1014 #endif
1015         case MSR_IA32_SYSENTER_CS:
1016                 vmcs_write32(GUEST_SYSENTER_CS, data);
1017                 break;
1018         case MSR_IA32_SYSENTER_EIP:
1019                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1020                 break;
1021         case MSR_IA32_SYSENTER_ESP:
1022                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1023                 break;
1024         case MSR_IA32_TSC:
1025                 rdtscll(host_tsc);
1026                 guest_write_tsc(data, host_tsc);
1027                 break;
1028         case MSR_P6_PERFCTR0:
1029         case MSR_P6_PERFCTR1:
1030         case MSR_P6_EVNTSEL0:
1031         case MSR_P6_EVNTSEL1:
1032                 /*
1033                  * Just discard all writes to the performance counters; this
1034                  * should keep both older linux and windows 64-bit guests
1035                  * happy
1036                  */
1037                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
1038
1039                 break;
1040         case MSR_IA32_CR_PAT:
1041                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1042                         vmcs_write64(GUEST_IA32_PAT, data);
1043                         vcpu->arch.pat = data;
1044                         break;
1045                 }
1046                 /* Otherwise falls through to kvm_set_msr_common */
1047         default:
1048                 vmx_load_host_state(vmx);
1049                 msr = find_msr_entry(vmx, msr_index);
1050                 if (msr) {
1051                         msr->data = data;
1052                         break;
1053                 }
1054                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1055         }
1056
1057         return ret;
1058 }
1059
1060 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1061 {
1062         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1063         switch (reg) {
1064         case VCPU_REGS_RSP:
1065                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1066                 break;
1067         case VCPU_REGS_RIP:
1068                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1069                 break;
1070         case VCPU_EXREG_PDPTR:
1071                 if (enable_ept)
1072                         ept_save_pdptrs(vcpu);
1073                 break;
1074         default:
1075                 break;
1076         }
1077 }
1078
1079 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1080 {
1081         int old_debug = vcpu->guest_debug;
1082         unsigned long flags;
1083
1084         vcpu->guest_debug = dbg->control;
1085         if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
1086                 vcpu->guest_debug = 0;
1087
1088         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1089                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1090         else
1091                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1092
1093         flags = vmcs_readl(GUEST_RFLAGS);
1094         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1095                 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1096         else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1097                 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1098         vmcs_writel(GUEST_RFLAGS, flags);
1099
1100         update_exception_bitmap(vcpu);
1101
1102         return 0;
1103 }
1104
1105 static __init int cpu_has_kvm_support(void)
1106 {
1107         return cpu_has_vmx();
1108 }
1109
1110 static __init int vmx_disabled_by_bios(void)
1111 {
1112         u64 msr;
1113
1114         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1115         return (msr & (FEATURE_CONTROL_LOCKED |
1116                        FEATURE_CONTROL_VMXON_ENABLED))
1117             == FEATURE_CONTROL_LOCKED;
1118         /* locked but not enabled */
1119 }
1120
1121 static void hardware_enable(void *garbage)
1122 {
1123         int cpu = raw_smp_processor_id();
1124         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1125         u64 old;
1126
1127         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1128         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1129         if ((old & (FEATURE_CONTROL_LOCKED |
1130                     FEATURE_CONTROL_VMXON_ENABLED))
1131             != (FEATURE_CONTROL_LOCKED |
1132                 FEATURE_CONTROL_VMXON_ENABLED))
1133                 /* enable and lock */
1134                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1135                        FEATURE_CONTROL_LOCKED |
1136                        FEATURE_CONTROL_VMXON_ENABLED);
1137         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1138         asm volatile (ASM_VMX_VMXON_RAX
1139                       : : "a"(&phys_addr), "m"(phys_addr)
1140                       : "memory", "cc");
1141 }
1142
1143 static void vmclear_local_vcpus(void)
1144 {
1145         int cpu = raw_smp_processor_id();
1146         struct vcpu_vmx *vmx, *n;
1147
1148         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1149                                  local_vcpus_link)
1150                 __vcpu_clear(vmx);
1151 }
1152
1153
1154 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1155  * tricks.
1156  */
1157 static void kvm_cpu_vmxoff(void)
1158 {
1159         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1160         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1161 }
1162
1163 static void hardware_disable(void *garbage)
1164 {
1165         vmclear_local_vcpus();
1166         kvm_cpu_vmxoff();
1167 }
1168
1169 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1170                                       u32 msr, u32 *result)
1171 {
1172         u32 vmx_msr_low, vmx_msr_high;
1173         u32 ctl = ctl_min | ctl_opt;
1174
1175         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1176
1177         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1178         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1179
1180         /* Ensure minimum (required) set of control bits are supported. */
1181         if (ctl_min & ~ctl)
1182                 return -EIO;
1183
1184         *result = ctl;
1185         return 0;
1186 }
1187
1188 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1189 {
1190         u32 vmx_msr_low, vmx_msr_high;
1191         u32 min, opt, min2, opt2;
1192         u32 _pin_based_exec_control = 0;
1193         u32 _cpu_based_exec_control = 0;
1194         u32 _cpu_based_2nd_exec_control = 0;
1195         u32 _vmexit_control = 0;
1196         u32 _vmentry_control = 0;
1197
1198         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1199         opt = PIN_BASED_VIRTUAL_NMIS;
1200         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1201                                 &_pin_based_exec_control) < 0)
1202                 return -EIO;
1203
1204         min = CPU_BASED_HLT_EXITING |
1205 #ifdef CONFIG_X86_64
1206               CPU_BASED_CR8_LOAD_EXITING |
1207               CPU_BASED_CR8_STORE_EXITING |
1208 #endif
1209               CPU_BASED_CR3_LOAD_EXITING |
1210               CPU_BASED_CR3_STORE_EXITING |
1211               CPU_BASED_USE_IO_BITMAPS |
1212               CPU_BASED_MOV_DR_EXITING |
1213               CPU_BASED_USE_TSC_OFFSETING |
1214               CPU_BASED_INVLPG_EXITING;
1215         opt = CPU_BASED_TPR_SHADOW |
1216               CPU_BASED_USE_MSR_BITMAPS |
1217               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1218         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1219                                 &_cpu_based_exec_control) < 0)
1220                 return -EIO;
1221 #ifdef CONFIG_X86_64
1222         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1223                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1224                                            ~CPU_BASED_CR8_STORE_EXITING;
1225 #endif
1226         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1227                 min2 = 0;
1228                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1229                         SECONDARY_EXEC_WBINVD_EXITING |
1230                         SECONDARY_EXEC_ENABLE_VPID |
1231                         SECONDARY_EXEC_ENABLE_EPT |
1232                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
1233                 if (adjust_vmx_controls(min2, opt2,
1234                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1235                                         &_cpu_based_2nd_exec_control) < 0)
1236                         return -EIO;
1237         }
1238 #ifndef CONFIG_X86_64
1239         if (!(_cpu_based_2nd_exec_control &
1240                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1241                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1242 #endif
1243         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1244                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1245                    enabled */
1246                 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1247                          CPU_BASED_CR3_STORE_EXITING |
1248                          CPU_BASED_INVLPG_EXITING);
1249                 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1250                                         &_cpu_based_exec_control) < 0)
1251                         return -EIO;
1252                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1253                       vmx_capability.ept, vmx_capability.vpid);
1254         }
1255
1256         min = 0;
1257 #ifdef CONFIG_X86_64
1258         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1259 #endif
1260         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1261         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1262                                 &_vmexit_control) < 0)
1263                 return -EIO;
1264
1265         min = 0;
1266         opt = VM_ENTRY_LOAD_IA32_PAT;
1267         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1268                                 &_vmentry_control) < 0)
1269                 return -EIO;
1270
1271         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1272
1273         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1274         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1275                 return -EIO;
1276
1277 #ifdef CONFIG_X86_64
1278         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1279         if (vmx_msr_high & (1u<<16))
1280                 return -EIO;
1281 #endif
1282
1283         /* Require Write-Back (WB) memory type for VMCS accesses. */
1284         if (((vmx_msr_high >> 18) & 15) != 6)
1285                 return -EIO;
1286
1287         vmcs_conf->size = vmx_msr_high & 0x1fff;
1288         vmcs_conf->order = get_order(vmcs_config.size);
1289         vmcs_conf->revision_id = vmx_msr_low;
1290
1291         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1292         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1293         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1294         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1295         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1296
1297         return 0;
1298 }
1299
1300 static struct vmcs *alloc_vmcs_cpu(int cpu)
1301 {
1302         int node = cpu_to_node(cpu);
1303         struct page *pages;
1304         struct vmcs *vmcs;
1305
1306         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1307         if (!pages)
1308                 return NULL;
1309         vmcs = page_address(pages);
1310         memset(vmcs, 0, vmcs_config.size);
1311         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1312         return vmcs;
1313 }
1314
1315 static struct vmcs *alloc_vmcs(void)
1316 {
1317         return alloc_vmcs_cpu(raw_smp_processor_id());
1318 }
1319
1320 static void free_vmcs(struct vmcs *vmcs)
1321 {
1322         free_pages((unsigned long)vmcs, vmcs_config.order);
1323 }
1324
1325 static void free_kvm_area(void)
1326 {
1327         int cpu;
1328
1329         for_each_online_cpu(cpu)
1330                 free_vmcs(per_cpu(vmxarea, cpu));
1331 }
1332
1333 static __init int alloc_kvm_area(void)
1334 {
1335         int cpu;
1336
1337         for_each_online_cpu(cpu) {
1338                 struct vmcs *vmcs;
1339
1340                 vmcs = alloc_vmcs_cpu(cpu);
1341                 if (!vmcs) {
1342                         free_kvm_area();
1343                         return -ENOMEM;
1344                 }
1345
1346                 per_cpu(vmxarea, cpu) = vmcs;
1347         }
1348         return 0;
1349 }
1350
1351 static __init int hardware_setup(void)
1352 {
1353         if (setup_vmcs_config(&vmcs_config) < 0)
1354                 return -EIO;
1355
1356         if (boot_cpu_has(X86_FEATURE_NX))
1357                 kvm_enable_efer_bits(EFER_NX);
1358
1359         if (!cpu_has_vmx_vpid())
1360                 enable_vpid = 0;
1361
1362         if (!cpu_has_vmx_ept()) {
1363                 enable_ept = 0;
1364                 enable_unrestricted_guest = 0;
1365         }
1366
1367         if (!cpu_has_vmx_unrestricted_guest())
1368                 enable_unrestricted_guest = 0;
1369
1370         if (!cpu_has_vmx_flexpriority())
1371                 flexpriority_enabled = 0;
1372
1373         if (!cpu_has_vmx_tpr_shadow())
1374                 kvm_x86_ops->update_cr8_intercept = NULL;
1375
1376         return alloc_kvm_area();
1377 }
1378
1379 static __exit void hardware_unsetup(void)
1380 {
1381         free_kvm_area();
1382 }
1383
1384 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1385 {
1386         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1387
1388         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1389                 vmcs_write16(sf->selector, save->selector);
1390                 vmcs_writel(sf->base, save->base);
1391                 vmcs_write32(sf->limit, save->limit);
1392                 vmcs_write32(sf->ar_bytes, save->ar);
1393         } else {
1394                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1395                         << AR_DPL_SHIFT;
1396                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1397         }
1398 }
1399
1400 static void enter_pmode(struct kvm_vcpu *vcpu)
1401 {
1402         unsigned long flags;
1403         struct vcpu_vmx *vmx = to_vmx(vcpu);
1404
1405         vmx->emulation_required = 1;
1406         vmx->rmode.vm86_active = 0;
1407
1408         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1409         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1410         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1411
1412         flags = vmcs_readl(GUEST_RFLAGS);
1413         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1414         flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
1415         vmcs_writel(GUEST_RFLAGS, flags);
1416
1417         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1418                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1419
1420         update_exception_bitmap(vcpu);
1421
1422         if (emulate_invalid_guest_state)
1423                 return;
1424
1425         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1426         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1427         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1428         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1429
1430         vmcs_write16(GUEST_SS_SELECTOR, 0);
1431         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1432
1433         vmcs_write16(GUEST_CS_SELECTOR,
1434                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1435         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1436 }
1437
1438 static gva_t rmode_tss_base(struct kvm *kvm)
1439 {
1440         if (!kvm->arch.tss_addr) {
1441                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1442                                  kvm->memslots[0].npages - 3;
1443                 return base_gfn << PAGE_SHIFT;
1444         }
1445         return kvm->arch.tss_addr;
1446 }
1447
1448 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1449 {
1450         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1451
1452         save->selector = vmcs_read16(sf->selector);
1453         save->base = vmcs_readl(sf->base);
1454         save->limit = vmcs_read32(sf->limit);
1455         save->ar = vmcs_read32(sf->ar_bytes);
1456         vmcs_write16(sf->selector, save->base >> 4);
1457         vmcs_write32(sf->base, save->base & 0xfffff);
1458         vmcs_write32(sf->limit, 0xffff);
1459         vmcs_write32(sf->ar_bytes, 0xf3);
1460 }
1461
1462 static void enter_rmode(struct kvm_vcpu *vcpu)
1463 {
1464         unsigned long flags;
1465         struct vcpu_vmx *vmx = to_vmx(vcpu);
1466
1467         if (enable_unrestricted_guest)
1468                 return;
1469
1470         vmx->emulation_required = 1;
1471         vmx->rmode.vm86_active = 1;
1472
1473         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1474         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1475
1476         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1477         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1478
1479         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1480         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1481
1482         flags = vmcs_readl(GUEST_RFLAGS);
1483         vmx->rmode.save_iopl
1484                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1485
1486         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1487
1488         vmcs_writel(GUEST_RFLAGS, flags);
1489         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1490         update_exception_bitmap(vcpu);
1491
1492         if (emulate_invalid_guest_state)
1493                 goto continue_rmode;
1494
1495         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1496         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1497         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1498
1499         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1500         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1501         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1502                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1503         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1504
1505         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1506         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1507         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1508         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1509
1510 continue_rmode:
1511         kvm_mmu_reset_context(vcpu);
1512         init_rmode(vcpu->kvm);
1513 }
1514
1515 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1516 {
1517         struct vcpu_vmx *vmx = to_vmx(vcpu);
1518         struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1519
1520         vcpu->arch.shadow_efer = efer;
1521         if (!msr)
1522                 return;
1523         if (efer & EFER_LMA) {
1524                 vmcs_write32(VM_ENTRY_CONTROLS,
1525                              vmcs_read32(VM_ENTRY_CONTROLS) |
1526                              VM_ENTRY_IA32E_MODE);
1527                 msr->data = efer;
1528         } else {
1529                 vmcs_write32(VM_ENTRY_CONTROLS,
1530                              vmcs_read32(VM_ENTRY_CONTROLS) &
1531                              ~VM_ENTRY_IA32E_MODE);
1532
1533                 msr->data = efer & ~EFER_LME;
1534         }
1535         setup_msrs(vmx);
1536 }
1537
1538 #ifdef CONFIG_X86_64
1539
1540 static void enter_lmode(struct kvm_vcpu *vcpu)
1541 {
1542         u32 guest_tr_ar;
1543
1544         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1545         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1546                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1547                        __func__);
1548                 vmcs_write32(GUEST_TR_AR_BYTES,
1549                              (guest_tr_ar & ~AR_TYPE_MASK)
1550                              | AR_TYPE_BUSY_64_TSS);
1551         }
1552         vcpu->arch.shadow_efer |= EFER_LMA;
1553         vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
1554 }
1555
1556 static void exit_lmode(struct kvm_vcpu *vcpu)
1557 {
1558         vcpu->arch.shadow_efer &= ~EFER_LMA;
1559
1560         vmcs_write32(VM_ENTRY_CONTROLS,
1561                      vmcs_read32(VM_ENTRY_CONTROLS)
1562                      & ~VM_ENTRY_IA32E_MODE);
1563 }
1564
1565 #endif
1566
1567 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1568 {
1569         vpid_sync_vcpu_all(to_vmx(vcpu));
1570         if (enable_ept)
1571                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1572 }
1573
1574 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1575 {
1576         vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1577         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1578 }
1579
1580 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1581 {
1582         if (!test_bit(VCPU_EXREG_PDPTR,
1583                       (unsigned long *)&vcpu->arch.regs_dirty))
1584                 return;
1585
1586         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1587                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1588                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1589                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1590                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1591         }
1592 }
1593
1594 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1595 {
1596         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1597                 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1598                 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1599                 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1600                 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1601         }
1602
1603         __set_bit(VCPU_EXREG_PDPTR,
1604                   (unsigned long *)&vcpu->arch.regs_avail);
1605         __set_bit(VCPU_EXREG_PDPTR,
1606                   (unsigned long *)&vcpu->arch.regs_dirty);
1607 }
1608
1609 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1610
1611 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1612                                         unsigned long cr0,
1613                                         struct kvm_vcpu *vcpu)
1614 {
1615         if (!(cr0 & X86_CR0_PG)) {
1616                 /* From paging/starting to nonpaging */
1617                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1618                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1619                              (CPU_BASED_CR3_LOAD_EXITING |
1620                               CPU_BASED_CR3_STORE_EXITING));
1621                 vcpu->arch.cr0 = cr0;
1622                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1623                 *hw_cr0 &= ~X86_CR0_WP;
1624         } else if (!is_paging(vcpu)) {
1625                 /* From nonpaging to paging */
1626                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1627                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1628                              ~(CPU_BASED_CR3_LOAD_EXITING |
1629                                CPU_BASED_CR3_STORE_EXITING));
1630                 vcpu->arch.cr0 = cr0;
1631                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1632                 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1633                         *hw_cr0 &= ~X86_CR0_WP;
1634         }
1635 }
1636
1637 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1638                                         struct kvm_vcpu *vcpu)
1639 {
1640         if (!is_paging(vcpu)) {
1641                 *hw_cr4 &= ~X86_CR4_PAE;
1642                 *hw_cr4 |= X86_CR4_PSE;
1643         } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1644                 *hw_cr4 &= ~X86_CR4_PAE;
1645 }
1646
1647 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1648 {
1649         struct vcpu_vmx *vmx = to_vmx(vcpu);
1650         unsigned long hw_cr0;
1651
1652         if (enable_unrestricted_guest)
1653                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1654                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1655         else
1656                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1657
1658         vmx_fpu_deactivate(vcpu);
1659
1660         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1661                 enter_pmode(vcpu);
1662
1663         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1664                 enter_rmode(vcpu);
1665
1666 #ifdef CONFIG_X86_64
1667         if (vcpu->arch.shadow_efer & EFER_LME) {
1668                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1669                         enter_lmode(vcpu);
1670                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1671                         exit_lmode(vcpu);
1672         }
1673 #endif
1674
1675         if (enable_ept)
1676                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1677
1678         vmcs_writel(CR0_READ_SHADOW, cr0);
1679         vmcs_writel(GUEST_CR0, hw_cr0);
1680         vcpu->arch.cr0 = cr0;
1681
1682         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1683                 vmx_fpu_activate(vcpu);
1684 }
1685
1686 static u64 construct_eptp(unsigned long root_hpa)
1687 {
1688         u64 eptp;
1689
1690         /* TODO write the value reading from MSR */
1691         eptp = VMX_EPT_DEFAULT_MT |
1692                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1693         eptp |= (root_hpa & PAGE_MASK);
1694
1695         return eptp;
1696 }
1697
1698 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1699 {
1700         unsigned long guest_cr3;
1701         u64 eptp;
1702
1703         guest_cr3 = cr3;
1704         if (enable_ept) {
1705                 eptp = construct_eptp(cr3);
1706                 vmcs_write64(EPT_POINTER, eptp);
1707                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1708                         VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1709         }
1710
1711         vmx_flush_tlb(vcpu);
1712         vmcs_writel(GUEST_CR3, guest_cr3);
1713         if (vcpu->arch.cr0 & X86_CR0_PE)
1714                 vmx_fpu_deactivate(vcpu);
1715 }
1716
1717 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1718 {
1719         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1720                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1721
1722         vcpu->arch.cr4 = cr4;
1723         if (enable_ept)
1724                 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1725
1726         vmcs_writel(CR4_READ_SHADOW, cr4);
1727         vmcs_writel(GUEST_CR4, hw_cr4);
1728 }
1729
1730 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1731 {
1732         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1733
1734         return vmcs_readl(sf->base);
1735 }
1736
1737 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1738                             struct kvm_segment *var, int seg)
1739 {
1740         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1741         u32 ar;
1742
1743         var->base = vmcs_readl(sf->base);
1744         var->limit = vmcs_read32(sf->limit);
1745         var->selector = vmcs_read16(sf->selector);
1746         ar = vmcs_read32(sf->ar_bytes);
1747         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1748                 ar = 0;
1749         var->type = ar & 15;
1750         var->s = (ar >> 4) & 1;
1751         var->dpl = (ar >> 5) & 3;
1752         var->present = (ar >> 7) & 1;
1753         var->avl = (ar >> 12) & 1;
1754         var->l = (ar >> 13) & 1;
1755         var->db = (ar >> 14) & 1;
1756         var->g = (ar >> 15) & 1;
1757         var->unusable = (ar >> 16) & 1;
1758 }
1759
1760 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1761 {
1762         struct kvm_segment kvm_seg;
1763
1764         if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1765                 return 0;
1766
1767         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1768                 return 3;
1769
1770         vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1771         return kvm_seg.selector & 3;
1772 }
1773
1774 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1775 {
1776         u32 ar;
1777
1778         if (var->unusable)
1779                 ar = 1 << 16;
1780         else {
1781                 ar = var->type & 15;
1782                 ar |= (var->s & 1) << 4;
1783                 ar |= (var->dpl & 3) << 5;
1784                 ar |= (var->present & 1) << 7;
1785                 ar |= (var->avl & 1) << 12;
1786                 ar |= (var->l & 1) << 13;
1787                 ar |= (var->db & 1) << 14;
1788                 ar |= (var->g & 1) << 15;
1789         }
1790         if (ar == 0) /* a 0 value means unusable */
1791                 ar = AR_UNUSABLE_MASK;
1792
1793         return ar;
1794 }
1795
1796 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1797                             struct kvm_segment *var, int seg)
1798 {
1799         struct vcpu_vmx *vmx = to_vmx(vcpu);
1800         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1801         u32 ar;
1802
1803         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1804                 vmx->rmode.tr.selector = var->selector;
1805                 vmx->rmode.tr.base = var->base;
1806                 vmx->rmode.tr.limit = var->limit;
1807                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
1808                 return;
1809         }
1810         vmcs_writel(sf->base, var->base);
1811         vmcs_write32(sf->limit, var->limit);
1812         vmcs_write16(sf->selector, var->selector);
1813         if (vmx->rmode.vm86_active && var->s) {
1814                 /*
1815                  * Hack real-mode segments into vm86 compatibility.
1816                  */
1817                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1818                         vmcs_writel(sf->base, 0xf0000);
1819                 ar = 0xf3;
1820         } else
1821                 ar = vmx_segment_access_rights(var);
1822
1823         /*
1824          *   Fix the "Accessed" bit in AR field of segment registers for older
1825          * qemu binaries.
1826          *   IA32 arch specifies that at the time of processor reset the
1827          * "Accessed" bit in the AR field of segment registers is 1. And qemu
1828          * is setting it to 0 in the usedland code. This causes invalid guest
1829          * state vmexit when "unrestricted guest" mode is turned on.
1830          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
1831          * tree. Newer qemu binaries with that qemu fix would not need this
1832          * kvm hack.
1833          */
1834         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1835                 ar |= 0x1; /* Accessed */
1836
1837         vmcs_write32(sf->ar_bytes, ar);
1838 }
1839
1840 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1841 {
1842         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1843
1844         *db = (ar >> 14) & 1;
1845         *l = (ar >> 13) & 1;
1846 }
1847
1848 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1849 {
1850         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1851         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1852 }
1853
1854 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1855 {
1856         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1857         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1858 }
1859
1860 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1861 {
1862         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1863         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1864 }
1865
1866 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1867 {
1868         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1869         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1870 }
1871
1872 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1873 {
1874         struct kvm_segment var;
1875         u32 ar;
1876
1877         vmx_get_segment(vcpu, &var, seg);
1878         ar = vmx_segment_access_rights(&var);
1879
1880         if (var.base != (var.selector << 4))
1881                 return false;
1882         if (var.limit != 0xffff)
1883                 return false;
1884         if (ar != 0xf3)
1885                 return false;
1886
1887         return true;
1888 }
1889
1890 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1891 {
1892         struct kvm_segment cs;
1893         unsigned int cs_rpl;
1894
1895         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1896         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1897
1898         if (cs.unusable)
1899                 return false;
1900         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1901                 return false;
1902         if (!cs.s)
1903                 return false;
1904         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1905                 if (cs.dpl > cs_rpl)
1906                         return false;
1907         } else {
1908                 if (cs.dpl != cs_rpl)
1909                         return false;
1910         }
1911         if (!cs.present)
1912                 return false;
1913
1914         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1915         return true;
1916 }
1917
1918 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1919 {
1920         struct kvm_segment ss;
1921         unsigned int ss_rpl;
1922
1923         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1924         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1925
1926         if (ss.unusable)
1927                 return true;
1928         if (ss.type != 3 && ss.type != 7)
1929                 return false;
1930         if (!ss.s)
1931                 return false;
1932         if (ss.dpl != ss_rpl) /* DPL != RPL */
1933                 return false;
1934         if (!ss.present)
1935                 return false;
1936
1937         return true;
1938 }
1939
1940 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1941 {
1942         struct kvm_segment var;
1943         unsigned int rpl;
1944
1945         vmx_get_segment(vcpu, &var, seg);
1946         rpl = var.selector & SELECTOR_RPL_MASK;
1947
1948         if (var.unusable)
1949                 return true;
1950         if (!var.s)
1951                 return false;
1952         if (!var.present)
1953                 return false;
1954         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1955                 if (var.dpl < rpl) /* DPL < RPL */
1956                         return false;
1957         }
1958
1959         /* TODO: Add other members to kvm_segment_field to allow checking for other access
1960          * rights flags
1961          */
1962         return true;
1963 }
1964
1965 static bool tr_valid(struct kvm_vcpu *vcpu)
1966 {
1967         struct kvm_segment tr;
1968
1969         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1970
1971         if (tr.unusable)
1972                 return false;
1973         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
1974                 return false;
1975         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
1976                 return false;
1977         if (!tr.present)
1978                 return false;
1979
1980         return true;
1981 }
1982
1983 static bool ldtr_valid(struct kvm_vcpu *vcpu)
1984 {
1985         struct kvm_segment ldtr;
1986
1987         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1988
1989         if (ldtr.unusable)
1990                 return true;
1991         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
1992                 return false;
1993         if (ldtr.type != 2)
1994                 return false;
1995         if (!ldtr.present)
1996                 return false;
1997
1998         return true;
1999 }
2000
2001 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2002 {
2003         struct kvm_segment cs, ss;
2004
2005         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2006         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2007
2008         return ((cs.selector & SELECTOR_RPL_MASK) ==
2009                  (ss.selector & SELECTOR_RPL_MASK));
2010 }
2011
2012 /*
2013  * Check if guest state is valid. Returns true if valid, false if
2014  * not.
2015  * We assume that registers are always usable
2016  */
2017 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2018 {
2019         /* real mode guest state checks */
2020         if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
2021                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2022                         return false;
2023                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2024                         return false;
2025                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2026                         return false;
2027                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2028                         return false;
2029                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2030                         return false;
2031                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2032                         return false;
2033         } else {
2034         /* protected mode guest state checks */
2035                 if (!cs_ss_rpl_check(vcpu))
2036                         return false;
2037                 if (!code_segment_valid(vcpu))
2038                         return false;
2039                 if (!stack_segment_valid(vcpu))
2040                         return false;
2041                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2042                         return false;
2043                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2044                         return false;
2045                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2046                         return false;
2047                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2048                         return false;
2049                 if (!tr_valid(vcpu))
2050                         return false;
2051                 if (!ldtr_valid(vcpu))
2052                         return false;
2053         }
2054         /* TODO:
2055          * - Add checks on RIP
2056          * - Add checks on RFLAGS
2057          */
2058
2059         return true;
2060 }
2061
2062 static int init_rmode_tss(struct kvm *kvm)
2063 {
2064         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2065         u16 data = 0;
2066         int ret = 0;
2067         int r;
2068
2069         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2070         if (r < 0)
2071                 goto out;
2072         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2073         r = kvm_write_guest_page(kvm, fn++, &data,
2074                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
2075         if (r < 0)
2076                 goto out;
2077         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2078         if (r < 0)
2079                 goto out;
2080         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2081         if (r < 0)
2082                 goto out;
2083         data = ~0;
2084         r = kvm_write_guest_page(kvm, fn, &data,
2085                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2086                                  sizeof(u8));
2087         if (r < 0)
2088                 goto out;
2089
2090         ret = 1;
2091 out:
2092         return ret;
2093 }
2094
2095 static int init_rmode_identity_map(struct kvm *kvm)
2096 {
2097         int i, r, ret;
2098         pfn_t identity_map_pfn;
2099         u32 tmp;
2100
2101         if (!enable_ept)
2102                 return 1;
2103         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2104                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2105                         "haven't been allocated!\n");
2106                 return 0;
2107         }
2108         if (likely(kvm->arch.ept_identity_pagetable_done))
2109                 return 1;
2110         ret = 0;
2111         identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
2112         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2113         if (r < 0)
2114                 goto out;
2115         /* Set up identity-mapping pagetable for EPT in real mode */
2116         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2117                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2118                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2119                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2120                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2121                 if (r < 0)
2122                         goto out;
2123         }
2124         kvm->arch.ept_identity_pagetable_done = true;
2125         ret = 1;
2126 out:
2127         return ret;
2128 }
2129
2130 static void seg_setup(int seg)
2131 {
2132         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2133         unsigned int ar;
2134
2135         vmcs_write16(sf->selector, 0);
2136         vmcs_writel(sf->base, 0);
2137         vmcs_write32(sf->limit, 0xffff);
2138         if (enable_unrestricted_guest) {
2139                 ar = 0x93;
2140                 if (seg == VCPU_SREG_CS)
2141                         ar |= 0x08; /* code segment */
2142         } else
2143                 ar = 0xf3;
2144
2145         vmcs_write32(sf->ar_bytes, ar);
2146 }
2147
2148 static int alloc_apic_access_page(struct kvm *kvm)
2149 {
2150         struct kvm_userspace_memory_region kvm_userspace_mem;
2151         int r = 0;
2152
2153         down_write(&kvm->slots_lock);
2154         if (kvm->arch.apic_access_page)
2155                 goto out;
2156         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2157         kvm_userspace_mem.flags = 0;
2158         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2159         kvm_userspace_mem.memory_size = PAGE_SIZE;
2160         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2161         if (r)
2162                 goto out;
2163
2164         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2165 out:
2166         up_write(&kvm->slots_lock);
2167         return r;
2168 }
2169
2170 static int alloc_identity_pagetable(struct kvm *kvm)
2171 {
2172         struct kvm_userspace_memory_region kvm_userspace_mem;
2173         int r = 0;
2174
2175         down_write(&kvm->slots_lock);
2176         if (kvm->arch.ept_identity_pagetable)
2177                 goto out;
2178         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2179         kvm_userspace_mem.flags = 0;
2180         kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2181         kvm_userspace_mem.memory_size = PAGE_SIZE;
2182         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2183         if (r)
2184                 goto out;
2185
2186         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2187                         VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
2188 out:
2189         up_write(&kvm->slots_lock);
2190         return r;
2191 }
2192
2193 static void allocate_vpid(struct vcpu_vmx *vmx)
2194 {
2195         int vpid;
2196
2197         vmx->vpid = 0;
2198         if (!enable_vpid)
2199                 return;
2200         spin_lock(&vmx_vpid_lock);
2201         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2202         if (vpid < VMX_NR_VPIDS) {
2203                 vmx->vpid = vpid;
2204                 __set_bit(vpid, vmx_vpid_bitmap);
2205         }
2206         spin_unlock(&vmx_vpid_lock);
2207 }
2208
2209 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2210 {
2211         int f = sizeof(unsigned long);
2212
2213         if (!cpu_has_vmx_msr_bitmap())
2214                 return;
2215
2216         /*
2217          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2218          * have the write-low and read-high bitmap offsets the wrong way round.
2219          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2220          */
2221         if (msr <= 0x1fff) {
2222                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2223                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2224         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2225                 msr &= 0x1fff;
2226                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2227                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2228         }
2229 }
2230
2231 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2232 {
2233         if (!longmode_only)
2234                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2235         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2236 }
2237
2238 /*
2239  * Sets up the vmcs for emulated real mode.
2240  */
2241 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2242 {
2243         u32 host_sysenter_cs, msr_low, msr_high;
2244         u32 junk;
2245         u64 host_pat, tsc_this, tsc_base;
2246         unsigned long a;
2247         struct descriptor_table dt;
2248         int i;
2249         unsigned long kvm_vmx_return;
2250         u32 exec_control;
2251
2252         /* I/O */
2253         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2254         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2255
2256         if (cpu_has_vmx_msr_bitmap())
2257                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2258
2259         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2260
2261         /* Control */
2262         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2263                 vmcs_config.pin_based_exec_ctrl);
2264
2265         exec_control = vmcs_config.cpu_based_exec_ctrl;
2266         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2267                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2268 #ifdef CONFIG_X86_64
2269                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2270                                 CPU_BASED_CR8_LOAD_EXITING;
2271 #endif
2272         }
2273         if (!enable_ept)
2274                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2275                                 CPU_BASED_CR3_LOAD_EXITING  |
2276                                 CPU_BASED_INVLPG_EXITING;
2277         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2278
2279         if (cpu_has_secondary_exec_ctrls()) {
2280                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2281                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2282                         exec_control &=
2283                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2284                 if (vmx->vpid == 0)
2285                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2286                 if (!enable_ept)
2287                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2288                 if (!enable_unrestricted_guest)
2289                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2290                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2291         }
2292
2293         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2294         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2295         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2296
2297         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
2298         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2299         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2300
2301         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2302         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2303         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2304         vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs());    /* 22.2.4 */
2305         vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs());    /* 22.2.4 */
2306         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2307 #ifdef CONFIG_X86_64
2308         rdmsrl(MSR_FS_BASE, a);
2309         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2310         rdmsrl(MSR_GS_BASE, a);
2311         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2312 #else
2313         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2314         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2315 #endif
2316
2317         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2318
2319         kvm_get_idt(&dt);
2320         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
2321
2322         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2323         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2324         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2325         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2326         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2327
2328         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2329         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2330         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2331         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2332         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2333         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2334
2335         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2336                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2337                 host_pat = msr_low | ((u64) msr_high << 32);
2338                 vmcs_write64(HOST_IA32_PAT, host_pat);
2339         }
2340         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2341                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2342                 host_pat = msr_low | ((u64) msr_high << 32);
2343                 /* Write the default value follow host pat */
2344                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2345                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2346                 vmx->vcpu.arch.pat = host_pat;
2347         }
2348
2349         for (i = 0; i < NR_VMX_MSR; ++i) {
2350                 u32 index = vmx_msr_index[i];
2351                 u32 data_low, data_high;
2352                 u64 data;
2353                 int j = vmx->nmsrs;
2354
2355                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2356                         continue;
2357                 if (wrmsr_safe(index, data_low, data_high) < 0)
2358                         continue;
2359                 data = data_low | ((u64)data_high << 32);
2360                 vmx->host_msrs[j].index = index;
2361                 vmx->host_msrs[j].reserved = 0;
2362                 vmx->host_msrs[j].data = data;
2363                 vmx->guest_msrs[j] = vmx->host_msrs[j];
2364                 ++vmx->nmsrs;
2365         }
2366
2367         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2368
2369         /* 22.2.1, 20.8.1 */
2370         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2371
2372         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2373         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2374
2375         tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2376         rdtscll(tsc_this);
2377         if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2378                 tsc_base = tsc_this;
2379
2380         guest_write_tsc(0, tsc_base);
2381
2382         return 0;
2383 }
2384
2385 static int init_rmode(struct kvm *kvm)
2386 {
2387         if (!init_rmode_tss(kvm))
2388                 return 0;
2389         if (!init_rmode_identity_map(kvm))
2390                 return 0;
2391         return 1;
2392 }
2393
2394 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2395 {
2396         struct vcpu_vmx *vmx = to_vmx(vcpu);
2397         u64 msr;
2398         int ret;
2399
2400         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2401         down_read(&vcpu->kvm->slots_lock);
2402         if (!init_rmode(vmx->vcpu.kvm)) {
2403                 ret = -ENOMEM;
2404                 goto out;
2405         }
2406
2407         vmx->rmode.vm86_active = 0;
2408
2409         vmx->soft_vnmi_blocked = 0;
2410
2411         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2412         kvm_set_cr8(&vmx->vcpu, 0);
2413         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2414         if (vmx->vcpu.vcpu_id == 0)
2415                 msr |= MSR_IA32_APICBASE_BSP;
2416         kvm_set_apic_base(&vmx->vcpu, msr);
2417
2418         fx_init(&vmx->vcpu);
2419
2420         seg_setup(VCPU_SREG_CS);
2421         /*
2422          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2423          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2424          */
2425         if (vmx->vcpu.vcpu_id == 0) {
2426                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2427                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2428         } else {
2429                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2430                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2431         }
2432
2433         seg_setup(VCPU_SREG_DS);
2434         seg_setup(VCPU_SREG_ES);
2435         seg_setup(VCPU_SREG_FS);
2436         seg_setup(VCPU_SREG_GS);
2437         seg_setup(VCPU_SREG_SS);
2438
2439         vmcs_write16(GUEST_TR_SELECTOR, 0);
2440         vmcs_writel(GUEST_TR_BASE, 0);
2441         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2442         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2443
2444         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2445         vmcs_writel(GUEST_LDTR_BASE, 0);
2446         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2447         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2448
2449         vmcs_write32(GUEST_SYSENTER_CS, 0);
2450         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2451         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2452
2453         vmcs_writel(GUEST_RFLAGS, 0x02);
2454         if (vmx->vcpu.vcpu_id == 0)
2455                 kvm_rip_write(vcpu, 0xfff0);
2456         else
2457                 kvm_rip_write(vcpu, 0);
2458         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2459
2460         vmcs_writel(GUEST_DR7, 0x400);
2461
2462         vmcs_writel(GUEST_GDTR_BASE, 0);
2463         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2464
2465         vmcs_writel(GUEST_IDTR_BASE, 0);
2466         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2467
2468         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2469         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2470         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2471
2472         /* Special registers */
2473         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2474
2475         setup_msrs(vmx);
2476
2477         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2478
2479         if (cpu_has_vmx_tpr_shadow()) {
2480                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2481                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2482                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2483                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2484                 vmcs_write32(TPR_THRESHOLD, 0);
2485         }
2486
2487         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2488                 vmcs_write64(APIC_ACCESS_ADDR,
2489                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2490
2491         if (vmx->vpid != 0)
2492                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2493
2494         vmx->vcpu.arch.cr0 = 0x60000010;
2495         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2496         vmx_set_cr4(&vmx->vcpu, 0);
2497         vmx_set_efer(&vmx->vcpu, 0);
2498         vmx_fpu_activate(&vmx->vcpu);
2499         update_exception_bitmap(&vmx->vcpu);
2500
2501         vpid_sync_vcpu_all(vmx);
2502
2503         ret = 0;
2504
2505         /* HACK: Don't enable emulation on guest boot/reset */
2506         vmx->emulation_required = 0;
2507
2508 out:
2509         up_read(&vcpu->kvm->slots_lock);
2510         return ret;
2511 }
2512
2513 static void enable_irq_window(struct kvm_vcpu *vcpu)
2514 {
2515         u32 cpu_based_vm_exec_control;
2516
2517         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2518         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2519         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2520 }
2521
2522 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2523 {
2524         u32 cpu_based_vm_exec_control;
2525
2526         if (!cpu_has_virtual_nmis()) {
2527                 enable_irq_window(vcpu);
2528                 return;
2529         }
2530
2531         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2532         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2533         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2534 }
2535
2536 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2537 {
2538         struct vcpu_vmx *vmx = to_vmx(vcpu);
2539         uint32_t intr;
2540         int irq = vcpu->arch.interrupt.nr;
2541
2542         KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2543
2544         ++vcpu->stat.irq_injections;
2545         if (vmx->rmode.vm86_active) {
2546                 vmx->rmode.irq.pending = true;
2547                 vmx->rmode.irq.vector = irq;
2548                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2549                 if (vcpu->arch.interrupt.soft)
2550                         vmx->rmode.irq.rip +=
2551                                 vmx->vcpu.arch.event_exit_inst_len;
2552                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2553                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2554                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2555                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2556                 return;
2557         }
2558         intr = irq | INTR_INFO_VALID_MASK;
2559         if (vcpu->arch.interrupt.soft) {
2560                 intr |= INTR_TYPE_SOFT_INTR;
2561                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2562                              vmx->vcpu.arch.event_exit_inst_len);
2563         } else
2564                 intr |= INTR_TYPE_EXT_INTR;
2565         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2566 }
2567
2568 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2569 {
2570         struct vcpu_vmx *vmx = to_vmx(vcpu);
2571
2572         if (!cpu_has_virtual_nmis()) {
2573                 /*
2574                  * Tracking the NMI-blocked state in software is built upon
2575                  * finding the next open IRQ window. This, in turn, depends on
2576                  * well-behaving guests: They have to keep IRQs disabled at
2577                  * least as long as the NMI handler runs. Otherwise we may
2578                  * cause NMI nesting, maybe breaking the guest. But as this is
2579                  * highly unlikely, we can live with the residual risk.
2580                  */
2581                 vmx->soft_vnmi_blocked = 1;
2582                 vmx->vnmi_blocked_time = 0;
2583         }
2584
2585         ++vcpu->stat.nmi_injections;
2586         if (vmx->rmode.vm86_active) {
2587                 vmx->rmode.irq.pending = true;
2588                 vmx->rmode.irq.vector = NMI_VECTOR;
2589                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2590                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2591                              NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2592                              INTR_INFO_VALID_MASK);
2593                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2594                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2595                 return;
2596         }
2597         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2598                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2599 }
2600
2601 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2602 {
2603         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2604                 return 0;
2605
2606         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2607                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2608                                 GUEST_INTR_STATE_NMI));
2609 }
2610
2611 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2612 {
2613         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2614                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2615                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2616 }
2617
2618 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2619 {
2620         int ret;
2621         struct kvm_userspace_memory_region tss_mem = {
2622                 .slot = TSS_PRIVATE_MEMSLOT,
2623                 .guest_phys_addr = addr,
2624                 .memory_size = PAGE_SIZE * 3,
2625                 .flags = 0,
2626         };
2627
2628         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2629         if (ret)
2630                 return ret;
2631         kvm->arch.tss_addr = addr;
2632         return 0;
2633 }
2634
2635 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2636                                   int vec, u32 err_code)
2637 {
2638         /*
2639          * Instruction with address size override prefix opcode 0x67
2640          * Cause the #SS fault with 0 error code in VM86 mode.
2641          */
2642         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2643                 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2644                         return 1;
2645         /*
2646          * Forward all other exceptions that are valid in real mode.
2647          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2648          *        the required debugging infrastructure rework.
2649          */
2650         switch (vec) {
2651         case DB_VECTOR:
2652                 if (vcpu->guest_debug &
2653                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2654                         return 0;
2655                 kvm_queue_exception(vcpu, vec);
2656                 return 1;
2657         case BP_VECTOR:
2658                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2659                         return 0;
2660                 /* fall through */
2661         case DE_VECTOR:
2662         case OF_VECTOR:
2663         case BR_VECTOR:
2664         case UD_VECTOR:
2665         case DF_VECTOR:
2666         case SS_VECTOR:
2667         case GP_VECTOR:
2668         case MF_VECTOR:
2669                 kvm_queue_exception(vcpu, vec);
2670                 return 1;
2671         }
2672         return 0;
2673 }
2674
2675 /*
2676  * Trigger machine check on the host. We assume all the MSRs are already set up
2677  * by the CPU and that we still run on the same CPU as the MCE occurred on.
2678  * We pass a fake environment to the machine check handler because we want
2679  * the guest to be always treated like user space, no matter what context
2680  * it used internally.
2681  */
2682 static void kvm_machine_check(void)
2683 {
2684 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2685         struct pt_regs regs = {
2686                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2687                 .flags = X86_EFLAGS_IF,
2688         };
2689
2690         do_machine_check(&regs, 0);
2691 #endif
2692 }
2693
2694 static int handle_machine_check(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2695 {
2696         /* already handled by vcpu_run */
2697         return 1;
2698 }
2699
2700 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2701 {
2702         struct vcpu_vmx *vmx = to_vmx(vcpu);
2703         u32 intr_info, ex_no, error_code;
2704         unsigned long cr2, rip, dr6;
2705         u32 vect_info;
2706         enum emulation_result er;
2707
2708         vect_info = vmx->idt_vectoring_info;
2709         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2710
2711         if (is_machine_check(intr_info))
2712                 return handle_machine_check(vcpu, kvm_run);
2713
2714         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2715                                                 !is_page_fault(intr_info))
2716                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2717                        "intr info 0x%x\n", __func__, vect_info, intr_info);
2718
2719         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2720                 return 1;  /* already handled by vmx_vcpu_run() */
2721
2722         if (is_no_device(intr_info)) {
2723                 vmx_fpu_activate(vcpu);
2724                 return 1;
2725         }
2726
2727         if (is_invalid_opcode(intr_info)) {
2728                 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2729                 if (er != EMULATE_DONE)
2730                         kvm_queue_exception(vcpu, UD_VECTOR);
2731                 return 1;
2732         }
2733
2734         error_code = 0;
2735         rip = kvm_rip_read(vcpu);
2736         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2737                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2738         if (is_page_fault(intr_info)) {
2739                 /* EPT won't cause page fault directly */
2740                 if (enable_ept)
2741                         BUG();
2742                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2743                 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2744                             (u32)((u64)cr2 >> 32), handler);
2745                 if (kvm_event_needs_reinjection(vcpu))
2746                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
2747                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2748         }
2749
2750         if (vmx->rmode.vm86_active &&
2751             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2752                                                                 error_code)) {
2753                 if (vcpu->arch.halt_request) {
2754                         vcpu->arch.halt_request = 0;
2755                         return kvm_emulate_halt(vcpu);
2756                 }
2757                 return 1;
2758         }
2759
2760         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2761         switch (ex_no) {
2762         case DB_VECTOR:
2763                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2764                 if (!(vcpu->guest_debug &
2765                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2766                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2767                         kvm_queue_exception(vcpu, DB_VECTOR);
2768                         return 1;
2769                 }
2770                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2771                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2772                 /* fall through */
2773         case BP_VECTOR:
2774                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2775                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2776                 kvm_run->debug.arch.exception = ex_no;
2777                 break;
2778         default:
2779                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2780                 kvm_run->ex.exception = ex_no;
2781                 kvm_run->ex.error_code = error_code;
2782                 break;
2783         }
2784         return 0;
2785 }
2786
2787 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2788                                      struct kvm_run *kvm_run)
2789 {
2790         ++vcpu->stat.irq_exits;
2791         KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
2792         return 1;
2793 }
2794
2795 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2796 {
2797         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2798         return 0;
2799 }
2800
2801 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2802 {
2803         unsigned long exit_qualification;
2804         int size, in, string;
2805         unsigned port;
2806
2807         ++vcpu->stat.io_exits;
2808         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2809         string = (exit_qualification & 16) != 0;
2810
2811         if (string) {
2812                 if (emulate_instruction(vcpu,
2813                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2814                         return 0;
2815                 return 1;
2816         }
2817
2818         size = (exit_qualification & 7) + 1;
2819         in = (exit_qualification & 8) != 0;
2820         port = exit_qualification >> 16;
2821
2822         skip_emulated_instruction(vcpu);
2823         return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2824 }
2825
2826 static void
2827 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2828 {
2829         /*
2830          * Patch in the VMCALL instruction:
2831          */
2832         hypercall[0] = 0x0f;
2833         hypercall[1] = 0x01;
2834         hypercall[2] = 0xc1;
2835 }
2836
2837 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2838 {
2839         unsigned long exit_qualification;
2840         int cr;
2841         int reg;
2842
2843         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2844         cr = exit_qualification & 15;
2845         reg = (exit_qualification >> 8) & 15;
2846         switch ((exit_qualification >> 4) & 3) {
2847         case 0: /* mov to cr */
2848                 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2849                             (u32)kvm_register_read(vcpu, reg),
2850                             (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2851                             handler);
2852                 switch (cr) {
2853                 case 0:
2854                         kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
2855                         skip_emulated_instruction(vcpu);
2856                         return 1;
2857                 case 3:
2858                         kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
2859                         skip_emulated_instruction(vcpu);
2860                         return 1;
2861                 case 4:
2862                         kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
2863                         skip_emulated_instruction(vcpu);
2864                         return 1;
2865                 case 8: {
2866                                 u8 cr8_prev = kvm_get_cr8(vcpu);
2867                                 u8 cr8 = kvm_register_read(vcpu, reg);
2868                                 kvm_set_cr8(vcpu, cr8);
2869                                 skip_emulated_instruction(vcpu);
2870                                 if (irqchip_in_kernel(vcpu->kvm))
2871                                         return 1;
2872                                 if (cr8_prev <= cr8)
2873                                         return 1;
2874                                 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2875                                 return 0;
2876                         }
2877                 };
2878                 break;
2879         case 2: /* clts */
2880                 vmx_fpu_deactivate(vcpu);
2881                 vcpu->arch.cr0 &= ~X86_CR0_TS;
2882                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2883                 vmx_fpu_activate(vcpu);
2884                 KVMTRACE_0D(CLTS, vcpu, handler);
2885                 skip_emulated_instruction(vcpu);
2886                 return 1;
2887         case 1: /*mov from cr*/
2888                 switch (cr) {
2889                 case 3:
2890                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2891                         KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2892                                     (u32)kvm_register_read(vcpu, reg),
2893                                     (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2894                                     handler);
2895                         skip_emulated_instruction(vcpu);
2896                         return 1;
2897                 case 8:
2898                         kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2899                         KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2900                                     (u32)kvm_register_read(vcpu, reg), handler);
2901                         skip_emulated_instruction(vcpu);
2902                         return 1;
2903                 }
2904                 break;
2905         case 3: /* lmsw */
2906                 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2907
2908                 skip_emulated_instruction(vcpu);
2909                 return 1;
2910         default:
2911                 break;
2912         }
2913         kvm_run->exit_reason = 0;
2914         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2915                (int)(exit_qualification >> 4) & 3, cr);
2916         return 0;
2917 }
2918
2919 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2920 {
2921         unsigned long exit_qualification;
2922         unsigned long val;
2923         int dr, reg;
2924
2925         dr = vmcs_readl(GUEST_DR7);
2926         if (dr & DR7_GD) {
2927                 /*
2928                  * As the vm-exit takes precedence over the debug trap, we
2929                  * need to emulate the latter, either for the host or the
2930                  * guest debugging itself.
2931                  */
2932                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2933                         kvm_run->debug.arch.dr6 = vcpu->arch.dr6;
2934                         kvm_run->debug.arch.dr7 = dr;
2935                         kvm_run->debug.arch.pc =
2936                                 vmcs_readl(GUEST_CS_BASE) +
2937                                 vmcs_readl(GUEST_RIP);
2938                         kvm_run->debug.arch.exception = DB_VECTOR;
2939                         kvm_run->exit_reason = KVM_EXIT_DEBUG;
2940                         return 0;
2941                 } else {
2942                         vcpu->arch.dr7 &= ~DR7_GD;
2943                         vcpu->arch.dr6 |= DR6_BD;
2944                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2945                         kvm_queue_exception(vcpu, DB_VECTOR);
2946                         return 1;
2947                 }
2948         }
2949
2950         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2951         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2952         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2953         if (exit_qualification & TYPE_MOV_FROM_DR) {
2954                 switch (dr) {
2955                 case 0 ... 3:
2956                         val = vcpu->arch.db[dr];
2957                         break;
2958                 case 6:
2959                         val = vcpu->arch.dr6;
2960                         break;
2961                 case 7:
2962                         val = vcpu->arch.dr7;
2963                         break;
2964                 default:
2965                         val = 0;
2966                 }
2967                 kvm_register_write(vcpu, reg, val);
2968                 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
2969         } else {
2970                 val = vcpu->arch.regs[reg];
2971                 switch (dr) {
2972                 case 0 ... 3:
2973                         vcpu->arch.db[dr] = val;
2974                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2975                                 vcpu->arch.eff_db[dr] = val;
2976                         break;
2977                 case 4 ... 5:
2978                         if (vcpu->arch.cr4 & X86_CR4_DE)
2979                                 kvm_queue_exception(vcpu, UD_VECTOR);
2980                         break;
2981                 case 6:
2982                         if (val & 0xffffffff00000000ULL) {
2983                                 kvm_queue_exception(vcpu, GP_VECTOR);
2984                                 break;
2985                         }
2986                         vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
2987                         break;
2988                 case 7:
2989                         if (val & 0xffffffff00000000ULL) {
2990                                 kvm_queue_exception(vcpu, GP_VECTOR);
2991                                 break;
2992                         }
2993                         vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
2994                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
2995                                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2996                                 vcpu->arch.switch_db_regs =
2997                                         (val & DR7_BP_EN_MASK);
2998                         }
2999                         break;
3000                 }
3001                 KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)val, handler);
3002         }
3003         skip_emulated_instruction(vcpu);
3004         return 1;
3005 }
3006
3007 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3008 {
3009         kvm_emulate_cpuid(vcpu);
3010         return 1;
3011 }
3012
3013 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3014 {
3015         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3016         u64 data;
3017
3018         if (vmx_get_msr(vcpu, ecx, &data)) {
3019                 kvm_inject_gp(vcpu, 0);
3020                 return 1;
3021         }
3022
3023         KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
3024                     handler);
3025
3026         /* FIXME: handling of bits 32:63 of rax, rdx */
3027         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3028         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3029         skip_emulated_instruction(vcpu);
3030         return 1;
3031 }
3032
3033 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3034 {
3035         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3036         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3037                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3038
3039         KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
3040                     handler);
3041
3042         if (vmx_set_msr(vcpu, ecx, data) != 0) {
3043                 kvm_inject_gp(vcpu, 0);
3044                 return 1;
3045         }
3046
3047         skip_emulated_instruction(vcpu);
3048         return 1;
3049 }
3050
3051 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
3052                                       struct kvm_run *kvm_run)
3053 {
3054         return 1;
3055 }
3056
3057 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
3058                                    struct kvm_run *kvm_run)
3059 {
3060         u32 cpu_based_vm_exec_control;
3061
3062         /* clear pending irq */
3063         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3064         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3065         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3066
3067         KVMTRACE_0D(PEND_INTR, vcpu, handler);
3068         ++vcpu->stat.irq_window_exits;
3069
3070         /*
3071          * If the user space waits to inject interrupts, exit as soon as
3072          * possible
3073          */
3074         if (!irqchip_in_kernel(vcpu->kvm) &&
3075             kvm_run->request_interrupt_window &&
3076             !kvm_cpu_has_interrupt(vcpu)) {
3077                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3078                 return 0;
3079         }
3080         return 1;
3081 }
3082
3083 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3084 {
3085         skip_emulated_instruction(vcpu);
3086         return kvm_emulate_halt(vcpu);
3087 }
3088
3089 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3090 {
3091         skip_emulated_instruction(vcpu);
3092         kvm_emulate_hypercall(vcpu);
3093         return 1;
3094 }
3095
3096 static int handle_vmx_insn(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3097 {
3098         kvm_queue_exception(vcpu, UD_VECTOR);
3099         return 1;
3100 }
3101
3102 static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3103 {
3104         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3105
3106         kvm_mmu_invlpg(vcpu, exit_qualification);
3107         skip_emulated_instruction(vcpu);
3108         return 1;
3109 }
3110
3111 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3112 {
3113         skip_emulated_instruction(vcpu);
3114         /* TODO: Add support for VT-d/pass-through device */
3115         return 1;
3116 }
3117
3118 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3119 {
3120         unsigned long exit_qualification;
3121         enum emulation_result er;
3122         unsigned long offset;
3123
3124         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3125         offset = exit_qualification & 0xffful;
3126
3127         er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3128
3129         if (er !=  EMULATE_DONE) {
3130                 printk(KERN_ERR
3131                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3132                        offset);
3133                 return -ENOTSUPP;
3134         }
3135         return 1;
3136 }
3137
3138 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3139 {
3140         struct vcpu_vmx *vmx = to_vmx(vcpu);
3141         unsigned long exit_qualification;
3142         u16 tss_selector;
3143         int reason, type, idt_v;
3144
3145         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3146         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3147
3148         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3149
3150         reason = (u32)exit_qualification >> 30;
3151         if (reason == TASK_SWITCH_GATE && idt_v) {
3152                 switch (type) {
3153                 case INTR_TYPE_NMI_INTR:
3154                         vcpu->arch.nmi_injected = false;
3155                         if (cpu_has_virtual_nmis())
3156                                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3157                                               GUEST_INTR_STATE_NMI);
3158                         break;
3159                 case INTR_TYPE_EXT_INTR:
3160                 case INTR_TYPE_SOFT_INTR:
3161                         kvm_clear_interrupt_queue(vcpu);
3162                         break;
3163                 case INTR_TYPE_HARD_EXCEPTION:
3164                 case INTR_TYPE_SOFT_EXCEPTION:
3165                         kvm_clear_exception_queue(vcpu);
3166                         break;
3167                 default:
3168                         break;
3169                 }
3170         }
3171         tss_selector = exit_qualification;
3172
3173         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3174                        type != INTR_TYPE_EXT_INTR &&
3175                        type != INTR_TYPE_NMI_INTR))
3176                 skip_emulated_instruction(vcpu);
3177
3178         if (!kvm_task_switch(vcpu, tss_selector, reason))
3179                 return 0;
3180
3181         /* clear all local breakpoint enable flags */
3182         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3183
3184         /*
3185          * TODO: What about debug traps on tss switch?
3186          *       Are we supposed to inject them and update dr6?
3187          */
3188
3189         return 1;
3190 }
3191
3192 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3193 {
3194         unsigned long exit_qualification;
3195         gpa_t gpa;
3196         int gla_validity;
3197
3198         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3199
3200         if (exit_qualification & (1 << 6)) {
3201                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3202                 return -ENOTSUPP;
3203         }
3204
3205         gla_validity = (exit_qualification >> 7) & 0x3;
3206         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3207                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3208                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3209                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3210                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3211                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3212                         (long unsigned int)exit_qualification);
3213                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3214                 kvm_run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3215                 return 0;
3216         }
3217
3218         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3219         return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3220 }
3221
3222 static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3223 {
3224         u32 cpu_based_vm_exec_control;
3225
3226         /* clear pending NMI */
3227         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3228         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3229         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3230         ++vcpu->stat.nmi_window_exits;
3231
3232         return 1;
3233 }
3234
3235 static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3236                                 struct kvm_run *kvm_run)
3237 {
3238         struct vcpu_vmx *vmx = to_vmx(vcpu);
3239         enum emulation_result err = EMULATE_DONE;
3240
3241         local_irq_enable();
3242         preempt_enable();
3243
3244         while (!guest_state_valid(vcpu)) {
3245                 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3246
3247                 if (err == EMULATE_DO_MMIO)
3248                         break;
3249
3250                 if (err != EMULATE_DONE) {
3251                         kvm_report_emulation_failure(vcpu, "emulation failure");
3252                         break;
3253                 }
3254
3255                 if (signal_pending(current))
3256                         break;
3257                 if (need_resched())
3258                         schedule();
3259         }
3260
3261         preempt_disable();
3262         local_irq_disable();
3263
3264         vmx->invalid_state_emulation_result = err;
3265 }
3266
3267 /*
3268  * The exit handlers return 1 if the exit was handled fully and guest execution
3269  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3270  * to be done to userspace and return 0.
3271  */
3272 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3273                                       struct kvm_run *kvm_run) = {
3274         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3275         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3276         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3277         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3278         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3279         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3280         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3281         [EXIT_REASON_CPUID]                   = handle_cpuid,
3282         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3283         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3284         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3285         [EXIT_REASON_HLT]                     = handle_halt,
3286         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3287         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3288         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
3289         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
3290         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
3291         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
3292         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
3293         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
3294         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
3295         [EXIT_REASON_VMOFF]                   = handle_vmx_insn,
3296         [EXIT_REASON_VMON]                    = handle_vmx_insn,
3297         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3298         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3299         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3300         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3301         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3302         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
3303 };
3304
3305 static const int kvm_vmx_max_exit_handlers =
3306         ARRAY_SIZE(kvm_vmx_exit_handlers);
3307
3308 /*
3309  * The guest has exited.  See if we can fix it or if we need userspace
3310  * assistance.
3311  */
3312 static int vmx_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
3313 {
3314         struct vcpu_vmx *vmx = to_vmx(vcpu);
3315         u32 exit_reason = vmx->exit_reason;
3316         u32 vectoring_info = vmx->idt_vectoring_info;
3317
3318         KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
3319                     (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
3320
3321         /* If we need to emulate an MMIO from handle_invalid_guest_state
3322          * we just return 0 */
3323         if (vmx->emulation_required && emulate_invalid_guest_state) {
3324                 if (guest_state_valid(vcpu))
3325                         vmx->emulation_required = 0;
3326                 return vmx->invalid_state_emulation_result != EMULATE_DO_MMIO;
3327         }
3328
3329         /* Access CR3 don't cause VMExit in paging mode, so we need
3330          * to sync with guest real CR3. */
3331         if (enable_ept && is_paging(vcpu))
3332                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3333
3334         if (unlikely(vmx->fail)) {
3335                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3336                 kvm_run->fail_entry.hardware_entry_failure_reason
3337                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3338                 return 0;
3339         }
3340
3341         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3342                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3343                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3344                         exit_reason != EXIT_REASON_TASK_SWITCH))
3345                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3346                        "(0x%x) and exit reason is 0x%x\n",
3347                        __func__, vectoring_info, exit_reason);
3348
3349         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3350                 if (vmx_interrupt_allowed(vcpu)) {
3351                         vmx->soft_vnmi_blocked = 0;
3352                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3353                            vcpu->arch.nmi_pending) {
3354                         /*
3355                          * This CPU don't support us in finding the end of an
3356                          * NMI-blocked window if the guest runs with IRQs
3357                          * disabled. So we pull the trigger after 1 s of
3358                          * futile waiting, but inform the user about this.
3359                          */
3360                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3361                                "state on VCPU %d after 1 s timeout\n",
3362                                __func__, vcpu->vcpu_id);
3363                         vmx->soft_vnmi_blocked = 0;
3364                 }
3365         }
3366
3367         if (exit_reason < kvm_vmx_max_exit_handlers
3368             && kvm_vmx_exit_handlers[exit_reason])
3369                 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3370         else {
3371                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3372                 kvm_run->hw.hardware_exit_reason = exit_reason;
3373         }
3374         return 0;
3375 }
3376
3377 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3378 {
3379         if (irr == -1 || tpr < irr) {
3380                 vmcs_write32(TPR_THRESHOLD, 0);
3381                 return;
3382         }
3383
3384         vmcs_write32(TPR_THRESHOLD, irr);
3385 }
3386
3387 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3388 {
3389         u32 exit_intr_info;
3390         u32 idt_vectoring_info = vmx->idt_vectoring_info;
3391         bool unblock_nmi;
3392         u8 vector;
3393         int type;
3394         bool idtv_info_valid;
3395
3396         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3397
3398         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3399
3400         /* Handle machine checks before interrupts are enabled */
3401         if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3402             || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3403                 && is_machine_check(exit_intr_info)))
3404                 kvm_machine_check();
3405
3406         /* We need to handle NMIs before interrupts are enabled */
3407         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3408             (exit_intr_info & INTR_INFO_VALID_MASK)) {
3409                 KVMTRACE_0D(NMI, &vmx->vcpu, handler);
3410                 asm("int $2");
3411         }
3412
3413         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3414
3415         if (cpu_has_virtual_nmis()) {
3416                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3417                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3418                 /*
3419                  * SDM 3: 27.7.1.2 (September 2008)
3420                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3421                  * a guest IRET fault.
3422                  * SDM 3: 23.2.2 (September 2008)
3423                  * Bit 12 is undefined in any of the following cases:
3424                  *  If the VM exit sets the valid bit in the IDT-vectoring
3425                  *   information field.
3426                  *  If the VM exit is due to a double fault.
3427                  */
3428                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3429                     vector != DF_VECTOR && !idtv_info_valid)
3430                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3431                                       GUEST_INTR_STATE_NMI);
3432         } else if (unlikely(vmx->soft_vnmi_blocked))
3433                 vmx->vnmi_blocked_time +=
3434                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3435
3436         vmx->vcpu.arch.nmi_injected = false;
3437         kvm_clear_exception_queue(&vmx->vcpu);
3438         kvm_clear_interrupt_queue(&vmx->vcpu);
3439
3440         if (!idtv_info_valid)
3441                 return;
3442
3443         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3444         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3445
3446         switch (type) {
3447         case INTR_TYPE_NMI_INTR:
3448                 vmx->vcpu.arch.nmi_injected = true;
3449                 /*
3450                  * SDM 3: 27.7.1.2 (September 2008)
3451                  * Clear bit "block by NMI" before VM entry if a NMI
3452                  * delivery faulted.
3453                  */
3454                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3455                                 GUEST_INTR_STATE_NMI);
3456                 break;
3457         case INTR_TYPE_SOFT_EXCEPTION:
3458                 vmx->vcpu.arch.event_exit_inst_len =
3459                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3460                 /* fall through */
3461         case INTR_TYPE_HARD_EXCEPTION:
3462                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3463                         u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3464                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
3465                 } else
3466                         kvm_queue_exception(&vmx->vcpu, vector);
3467                 break;
3468         case INTR_TYPE_SOFT_INTR:
3469                 vmx->vcpu.arch.event_exit_inst_len =
3470                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3471                 /* fall through */
3472         case INTR_TYPE_EXT_INTR:
3473                 kvm_queue_interrupt(&vmx->vcpu, vector,
3474                         type == INTR_TYPE_SOFT_INTR);
3475                 break;
3476         default:
3477                 break;
3478         }
3479 }
3480
3481 /*
3482  * Failure to inject an interrupt should give us the information
3483  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3484  * when fetching the interrupt redirection bitmap in the real-mode
3485  * tss, this doesn't happen.  So we do it ourselves.
3486  */
3487 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3488 {
3489         vmx->rmode.irq.pending = 0;
3490         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3491                 return;
3492         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3493         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3494                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3495                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3496                 return;
3497         }
3498         vmx->idt_vectoring_info =
3499                 VECTORING_INFO_VALID_MASK
3500                 | INTR_TYPE_EXT_INTR
3501                 | vmx->rmode.irq.vector;
3502 }
3503
3504 #ifdef CONFIG_X86_64
3505 #define R "r"
3506 #define Q "q"
3507 #else
3508 #define R "e"
3509 #define Q "l"
3510 #endif
3511
3512 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3513 {
3514         struct vcpu_vmx *vmx = to_vmx(vcpu);
3515
3516         if (enable_ept && is_paging(vcpu)) {
3517                 vmcs_writel(GUEST_CR3, vcpu->arch.cr3);
3518                 ept_load_pdptrs(vcpu);
3519         }
3520         /* Record the guest's net vcpu time for enforced NMI injections. */
3521         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3522                 vmx->entry_time = ktime_get();
3523
3524         /* Handle invalid guest state instead of entering VMX */
3525         if (vmx->emulation_required && emulate_invalid_guest_state) {
3526                 handle_invalid_guest_state(vcpu, kvm_run);
3527                 return;
3528         }
3529
3530         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3531                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3532         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3533                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3534
3535         /* When single-stepping over STI and MOV SS, we must clear the
3536          * corresponding interruptibility bits in the guest state. Otherwise
3537          * vmentry fails as it then expects bit 14 (BS) in pending debug
3538          * exceptions being set, but that's not correct for the guest debugging
3539          * case. */
3540         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3541                 vmx_set_interrupt_shadow(vcpu, 0);
3542
3543         /*
3544          * Loading guest fpu may have cleared host cr0.ts
3545          */
3546         vmcs_writel(HOST_CR0, read_cr0());
3547
3548         set_debugreg(vcpu->arch.dr6, 6);
3549
3550         asm(
3551                 /* Store host registers */
3552                 "push %%"R"dx; push %%"R"bp;"
3553                 "push %%"R"cx \n\t"
3554                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3555                 "je 1f \n\t"
3556                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3557                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3558                 "1: \n\t"
3559                 /* Check if vmlaunch of vmresume is needed */
3560                 "cmpl $0, %c[launched](%0) \n\t"
3561                 /* Load guest registers.  Don't clobber flags. */
3562                 "mov %c[cr2](%0), %%"R"ax \n\t"
3563                 "mov %%"R"ax, %%cr2 \n\t"
3564                 "mov %c[rax](%0), %%"R"ax \n\t"
3565                 "mov %c[rbx](%0), %%"R"bx \n\t"
3566                 "mov %c[rdx](%0), %%"R"dx \n\t"
3567                 "mov %c[rsi](%0), %%"R"si \n\t"
3568                 "mov %c[rdi](%0), %%"R"di \n\t"
3569                 "mov %c[rbp](%0), %%"R"bp \n\t"
3570 #ifdef CONFIG_X86_64
3571                 "mov %c[r8](%0),  %%r8  \n\t"
3572                 "mov %c[r9](%0),  %%r9  \n\t"
3573                 "mov %c[r10](%0), %%r10 \n\t"
3574                 "mov %c[r11](%0), %%r11 \n\t"
3575                 "mov %c[r12](%0), %%r12 \n\t"
3576                 "mov %c[r13](%0), %%r13 \n\t"
3577                 "mov %c[r14](%0), %%r14 \n\t"
3578                 "mov %c[r15](%0), %%r15 \n\t"
3579 #endif
3580                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3581
3582                 /* Enter guest mode */
3583                 "jne .Llaunched \n\t"
3584                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3585                 "jmp .Lkvm_vmx_return \n\t"
3586                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3587                 ".Lkvm_vmx_return: "
3588                 /* Save guest registers, load host registers, keep flags */
3589                 "xchg %0,     (%%"R"sp) \n\t"
3590                 "mov %%"R"ax, %c[rax](%0) \n\t"
3591                 "mov %%"R"bx, %c[rbx](%0) \n\t"
3592                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3593                 "mov %%"R"dx, %c[rdx](%0) \n\t"
3594                 "mov %%"R"si, %c[rsi](%0) \n\t"
3595                 "mov %%"R"di, %c[rdi](%0) \n\t"
3596                 "mov %%"R"bp, %c[rbp](%0) \n\t"
3597 #ifdef CONFIG_X86_64
3598                 "mov %%r8,  %c[r8](%0) \n\t"
3599                 "mov %%r9,  %c[r9](%0) \n\t"
3600                 "mov %%r10, %c[r10](%0) \n\t"
3601                 "mov %%r11, %c[r11](%0) \n\t"
3602                 "mov %%r12, %c[r12](%0) \n\t"
3603                 "mov %%r13, %c[r13](%0) \n\t"
3604                 "mov %%r14, %c[r14](%0) \n\t"
3605                 "mov %%r15, %c[r15](%0) \n\t"
3606 #endif
3607                 "mov %%cr2, %%"R"ax   \n\t"
3608                 "mov %%"R"ax, %c[cr2](%0) \n\t"
3609
3610                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
3611                 "setbe %c[fail](%0) \n\t"
3612               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3613                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3614                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3615                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3616                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3617                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3618                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3619                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3620                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3621                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3622                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3623 #ifdef CONFIG_X86_64
3624                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3625                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3626                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3627                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3628                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3629                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3630                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3631                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3632 #endif
3633                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3634               : "cc", "memory"
3635                 , R"bx", R"di", R"si"
3636 #ifdef CONFIG_X86_64
3637                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3638 #endif
3639               );
3640
3641         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3642                                   | (1 << VCPU_EXREG_PDPTR));
3643         vcpu->arch.regs_dirty = 0;
3644
3645         get_debugreg(vcpu->arch.dr6, 6);
3646
3647         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3648         if (vmx->rmode.irq.pending)
3649                 fixup_rmode_irq(vmx);
3650
3651         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3652         vmx->launched = 1;
3653
3654         vmx_complete_interrupts(vmx);
3655 }
3656
3657 #undef R
3658 #undef Q
3659
3660 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3661 {
3662         struct vcpu_vmx *vmx = to_vmx(vcpu);
3663
3664         if (vmx->vmcs) {
3665                 vcpu_clear(vmx);
3666                 free_vmcs(vmx->vmcs);
3667                 vmx->vmcs = NULL;
3668         }
3669 }
3670
3671 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3672 {
3673         struct vcpu_vmx *vmx = to_vmx(vcpu);
3674
3675         spin_lock(&vmx_vpid_lock);
3676         if (vmx->vpid != 0)
3677                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3678         spin_unlock(&vmx_vpid_lock);
3679         vmx_free_vmcs(vcpu);
3680         kfree(vmx->host_msrs);
3681         kfree(vmx->guest_msrs);
3682         kvm_vcpu_uninit(vcpu);
3683         kmem_cache_free(kvm_vcpu_cache, vmx);
3684 }
3685
3686 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3687 {
3688         int err;
3689         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3690         int cpu;
3691
3692         if (!vmx)
3693                 return ERR_PTR(-ENOMEM);
3694
3695         allocate_vpid(vmx);
3696
3697         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3698         if (err)
3699                 goto free_vcpu;
3700
3701         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3702         if (!vmx->guest_msrs) {
3703                 err = -ENOMEM;
3704                 goto uninit_vcpu;
3705         }
3706
3707         vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3708         if (!vmx->host_msrs)
3709                 goto free_guest_msrs;
3710
3711         vmx->vmcs = alloc_vmcs();
3712         if (!vmx->vmcs)
3713                 goto free_msrs;
3714
3715         vmcs_clear(vmx->vmcs);
3716
3717         cpu = get_cpu();
3718         vmx_vcpu_load(&vmx->vcpu, cpu);
3719         err = vmx_vcpu_setup(vmx);
3720         vmx_vcpu_put(&vmx->vcpu);
3721         put_cpu();
3722         if (err)
3723                 goto free_vmcs;
3724         if (vm_need_virtualize_apic_accesses(kvm))
3725                 if (alloc_apic_access_page(kvm) != 0)
3726                         goto free_vmcs;
3727
3728         if (enable_ept)
3729                 if (alloc_identity_pagetable(kvm) != 0)
3730                         goto free_vmcs;
3731
3732         return &vmx->vcpu;
3733
3734 free_vmcs:
3735         free_vmcs(vmx->vmcs);
3736 free_msrs:
3737         kfree(vmx->host_msrs);
3738 free_guest_msrs:
3739         kfree(vmx->guest_msrs);
3740 uninit_vcpu:
3741         kvm_vcpu_uninit(&vmx->vcpu);
3742 free_vcpu:
3743         kmem_cache_free(kvm_vcpu_cache, vmx);
3744         return ERR_PTR(err);
3745 }
3746
3747 static void __init vmx_check_processor_compat(void *rtn)
3748 {
3749         struct vmcs_config vmcs_conf;
3750
3751         *(int *)rtn = 0;
3752         if (setup_vmcs_config(&vmcs_conf) < 0)
3753                 *(int *)rtn = -EIO;
3754         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3755                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3756                                 smp_processor_id());
3757                 *(int *)rtn = -EIO;
3758         }
3759 }
3760
3761 static int get_ept_level(void)
3762 {
3763         return VMX_EPT_DEFAULT_GAW + 1;
3764 }
3765
3766 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3767 {
3768         u64 ret;
3769
3770         /* For VT-d and EPT combination
3771          * 1. MMIO: always map as UC
3772          * 2. EPT with VT-d:
3773          *   a. VT-d without snooping control feature: can't guarantee the
3774          *      result, try to trust guest.
3775          *   b. VT-d with snooping control feature: snooping control feature of
3776          *      VT-d engine can guarantee the cache correctness. Just set it
3777          *      to WB to keep consistent with host. So the same as item 3.
3778          * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3779          *    consistent with host MTRR
3780          */
3781         if (is_mmio)
3782                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
3783         else if (vcpu->kvm->arch.iommu_domain &&
3784                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3785                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3786                       VMX_EPT_MT_EPTE_SHIFT;
3787         else
3788                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3789                         | VMX_EPT_IGMT_BIT;
3790
3791         return ret;
3792 }
3793
3794 static struct kvm_x86_ops vmx_x86_ops = {
3795         .cpu_has_kvm_support = cpu_has_kvm_support,
3796         .disabled_by_bios = vmx_disabled_by_bios,
3797         .hardware_setup = hardware_setup,
3798         .hardware_unsetup = hardware_unsetup,
3799         .check_processor_compatibility = vmx_check_processor_compat,
3800         .hardware_enable = hardware_enable,
3801         .hardware_disable = hardware_disable,
3802         .cpu_has_accelerated_tpr = report_flexpriority,
3803
3804         .vcpu_create = vmx_create_vcpu,
3805         .vcpu_free = vmx_free_vcpu,
3806         .vcpu_reset = vmx_vcpu_reset,
3807
3808         .prepare_guest_switch = vmx_save_host_state,
3809         .vcpu_load = vmx_vcpu_load,
3810         .vcpu_put = vmx_vcpu_put,
3811
3812         .set_guest_debug = set_guest_debug,
3813         .get_msr = vmx_get_msr,
3814         .set_msr = vmx_set_msr,
3815         .get_segment_base = vmx_get_segment_base,
3816         .get_segment = vmx_get_segment,
3817         .set_segment = vmx_set_segment,
3818         .get_cpl = vmx_get_cpl,
3819         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3820         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3821         .set_cr0 = vmx_set_cr0,
3822         .set_cr3 = vmx_set_cr3,
3823         .set_cr4 = vmx_set_cr4,
3824         .set_efer = vmx_set_efer,
3825         .get_idt = vmx_get_idt,
3826         .set_idt = vmx_set_idt,
3827         .get_gdt = vmx_get_gdt,
3828         .set_gdt = vmx_set_gdt,
3829         .cache_reg = vmx_cache_reg,
3830         .get_rflags = vmx_get_rflags,
3831         .set_rflags = vmx_set_rflags,
3832
3833         .tlb_flush = vmx_flush_tlb,
3834
3835         .run = vmx_vcpu_run,
3836         .handle_exit = vmx_handle_exit,
3837         .skip_emulated_instruction = skip_emulated_instruction,
3838         .set_interrupt_shadow = vmx_set_interrupt_shadow,
3839         .get_interrupt_shadow = vmx_get_interrupt_shadow,
3840         .patch_hypercall = vmx_patch_hypercall,
3841         .set_irq = vmx_inject_irq,
3842         .set_nmi = vmx_inject_nmi,
3843         .queue_exception = vmx_queue_exception,
3844         .interrupt_allowed = vmx_interrupt_allowed,
3845         .nmi_allowed = vmx_nmi_allowed,
3846         .enable_nmi_window = enable_nmi_window,
3847         .enable_irq_window = enable_irq_window,
3848         .update_cr8_intercept = update_cr8_intercept,
3849
3850         .set_tss_addr = vmx_set_tss_addr,
3851         .get_tdp_level = get_ept_level,
3852         .get_mt_mask = vmx_get_mt_mask,
3853 };
3854
3855 static int __init vmx_init(void)
3856 {
3857         int r;
3858
3859         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
3860         if (!vmx_io_bitmap_a)
3861                 return -ENOMEM;
3862
3863         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
3864         if (!vmx_io_bitmap_b) {
3865                 r = -ENOMEM;
3866                 goto out;
3867         }
3868
3869         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
3870         if (!vmx_msr_bitmap_legacy) {
3871                 r = -ENOMEM;
3872                 goto out1;
3873         }
3874
3875         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
3876         if (!vmx_msr_bitmap_longmode) {
3877                 r = -ENOMEM;
3878                 goto out2;
3879         }
3880
3881         /*
3882          * Allow direct access to the PC debug port (it is often used for I/O
3883          * delays, but the vmexits simply slow things down).
3884          */
3885         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
3886         clear_bit(0x80, vmx_io_bitmap_a);
3887
3888         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
3889
3890         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
3891         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
3892
3893         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3894
3895         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
3896         if (r)
3897                 goto out3;
3898
3899         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
3900         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
3901         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
3902         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
3903         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
3904         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
3905
3906         if (enable_ept) {
3907                 bypass_guest_pf = 0;
3908                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3909                         VMX_EPT_WRITABLE_MASK);
3910                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
3911                                 VMX_EPT_EXECUTABLE_MASK);
3912                 kvm_enable_tdp();
3913         } else
3914                 kvm_disable_tdp();
3915
3916         if (bypass_guest_pf)
3917                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3918
3919         ept_sync_global();
3920
3921         return 0;
3922
3923 out3:
3924         free_page((unsigned long)vmx_msr_bitmap_longmode);
3925 out2:
3926         free_page((unsigned long)vmx_msr_bitmap_legacy);
3927 out1:
3928         free_page((unsigned long)vmx_io_bitmap_b);
3929 out:
3930         free_page((unsigned long)vmx_io_bitmap_a);
3931         return r;
3932 }
3933
3934 static void __exit vmx_exit(void)
3935 {
3936         free_page((unsigned long)vmx_msr_bitmap_legacy);
3937         free_page((unsigned long)vmx_msr_bitmap_longmode);
3938         free_page((unsigned long)vmx_io_bitmap_b);
3939         free_page((unsigned long)vmx_io_bitmap_a);
3940
3941         kvm_exit();
3942 }
3943
3944 module_init(vmx_init)
3945 module_exit(vmx_exit)