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   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/mm.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/ftrace_event.h>
  29 #include <linux/slab.h>
  30 #include "kvm_cache_regs.h"
  31 #include "x86.h"
  32
  33 #include <asm/io.h>
  34 #include <asm/desc.h>
  35 #include <asm/vmx.h>
  36 #include <asm/virtext.h>
  37 #include <asm/mce.h>
  38
  39 #include "trace.h"
  40
  41 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  42
  43 MODULE_AUTHOR("Qumranet");
  44 MODULE_LICENSE("GPL");
  45
  46 static int __read_mostly bypass_guest_pf = 1;
  47 module_param(bypass_guest_pf, bool, S_IRUGO);
  48
  49 static int __read_mostly enable_vpid = 1;
  50 module_param_named(vpid, enable_vpid, bool, 0444);
  51
  52 static int __read_mostly flexpriority_enabled = 1;
  53 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  54
  55 static int __read_mostly enable_ept = 1;
  56 module_param_named(ept, enable_ept, bool, S_IRUGO);
  57
  58 static int __read_mostly enable_unrestricted_guest = 1;
  59 module_param_named(unrestricted_guest,
  60                         enable_unrestricted_guest, bool, S_IRUGO);
  61
  62 static int __read_mostly emulate_invalid_guest_state = 0;
  63 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  64
  65 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  66         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  67 #define KVM_GUEST_CR0_MASK                                              \
  68         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  69 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  70         (X86_CR0_WP | X86_CR0_NE)
  71 #define KVM_VM_CR0_ALWAYS_ON                                            \
  72         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  73 #define KVM_CR4_GUEST_OWNED_BITS                                      \
  74         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
  75          | X86_CR4_OSXMMEXCPT)
  76
  77 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
  78 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
  79
  80 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
  81
  82 /*
  83  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
  84  * ple_gap:    upper bound on the amount of time between two successive
  85  *             executions of PAUSE in a loop. Also indicate if ple enabled.
  86  *             According to test, this time is usually small than 41 cycles.
  87  * ple_window: upper bound on the amount of time a guest is allowed to execute
  88  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
  89  *             less than 2^12 cycles
  90  * Time is measured based on a counter that runs at the same rate as the TSC,
  91  * refer SDM volume 3b section 21.6.13 & 22.1.3.
  92  */
  93 #define KVM_VMX_DEFAULT_PLE_GAP    41
  94 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
  95 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
  96 module_param(ple_gap, int, S_IRUGO);
  97
  98 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
  99 module_param(ple_window, int, S_IRUGO);
 100
 101 struct vmcs {
 102         u32 revision_id;
 103         u32 abort;
 104         char data[0];
 105 };
 106
 107 struct shared_msr_entry {
 108         unsigned index;
 109         u64 data;
 110         u64 mask;
 111 };
 112
 113 struct vcpu_vmx {
 114         struct kvm_vcpu       vcpu;
 115         struct list_head      local_vcpus_link;
 116         unsigned long         host_rsp;
 117         int                   launched;
 118         u8                    fail;
 119         u32                   idt_vectoring_info;
 120         struct shared_msr_entry *guest_msrs;
 121         int                   nmsrs;
 122         int                   save_nmsrs;
 123 #ifdef CONFIG_X86_64
 124         u64                   msr_host_kernel_gs_base;
 125         u64                   msr_guest_kernel_gs_base;
 126 #endif
 127         struct vmcs          *vmcs;
 128         struct {
 129                 int           loaded;
 130                 u16           fs_sel, gs_sel, ldt_sel;
 131                 int           gs_ldt_reload_needed;
 132                 int           fs_reload_needed;
 133         } host_state;
 134         struct {
 135                 int vm86_active;
 136                 ulong save_rflags;
 137                 struct kvm_save_segment {
 138                         u16 selector;
 139                         unsigned long base;
 140                         u32 limit;
 141                         u32 ar;
 142                 } tr, es, ds, fs, gs;
 143                 struct {
 144                         bool pending;
 145                         u8 vector;
 146                         unsigned rip;
 147                 } irq;
 148         } rmode;
 149         int vpid;
 150         bool emulation_required;
 151
 152         /* Support for vnmi-less CPUs */
 153         int soft_vnmi_blocked;
 154         ktime_t entry_time;
 155         s64 vnmi_blocked_time;
 156         u32 exit_reason;
 157
 158         bool rdtscp_enabled;
 159 };
 160
 161 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 162 {
 163         return container_of(vcpu, struct vcpu_vmx, vcpu);
 164 }
 165
 166 static int init_rmode(struct kvm *kvm);
 167 static u64 construct_eptp(unsigned long root_hpa);
 168
 169 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 170 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 171 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 172
 173 static unsigned long *vmx_io_bitmap_a;
 174 static unsigned long *vmx_io_bitmap_b;
 175 static unsigned long *vmx_msr_bitmap_legacy;
 176 static unsigned long *vmx_msr_bitmap_longmode;
 177
 178 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 179 static DEFINE_SPINLOCK(vmx_vpid_lock);
 180
 181 static struct vmcs_config {
 182         int size;
 183         int order;
 184         u32 revision_id;
 185         u32 pin_based_exec_ctrl;
 186         u32 cpu_based_exec_ctrl;
 187         u32 cpu_based_2nd_exec_ctrl;
 188         u32 vmexit_ctrl;
 189         u32 vmentry_ctrl;
 190 } vmcs_config;
 191
 192 static struct vmx_capability {
 193         u32 ept;
 194         u32 vpid;
 195 } vmx_capability;
 196
 197 #define VMX_SEGMENT_FIELD(seg)                                  \
 198         [VCPU_SREG_##seg] = {                                   \
 199                 .selector = GUEST_##seg##_SELECTOR,             \
 200                 .base = GUEST_##seg##_BASE,                     \
 201                 .limit = GUEST_##seg##_LIMIT,                   \
 202                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 203         }
 204
 205 static struct kvm_vmx_segment_field {
 206         unsigned selector;
 207         unsigned base;
 208         unsigned limit;
 209         unsigned ar_bytes;
 210 } kvm_vmx_segment_fields[] = {
 211         VMX_SEGMENT_FIELD(CS),
 212         VMX_SEGMENT_FIELD(DS),
 213         VMX_SEGMENT_FIELD(ES),
 214         VMX_SEGMENT_FIELD(FS),
 215         VMX_SEGMENT_FIELD(GS),
 216         VMX_SEGMENT_FIELD(SS),
 217         VMX_SEGMENT_FIELD(TR),
 218         VMX_SEGMENT_FIELD(LDTR),
 219 };
 220
 221 static u64 host_efer;
 222
 223 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 224
 225 /*
 226  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 227  * away by decrementing the array size.
 228  */
 229 static const u32 vmx_msr_index[] = {
 230 #ifdef CONFIG_X86_64
 231         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 232 #endif
 233         MSR_EFER, MSR_TSC_AUX, MSR_K6_STAR,
 234 };
 235 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 236
 237 static inline bool is_page_fault(u32 intr_info)
 238 {
 239         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 240                              INTR_INFO_VALID_MASK)) ==
 241                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 242 }
 243
 244 static inline bool is_no_device(u32 intr_info)
 245 {
 246         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 247                              INTR_INFO_VALID_MASK)) ==
 248                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 249 }
 250
 251 static inline bool is_invalid_opcode(u32 intr_info)
 252 {
 253         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 254                              INTR_INFO_VALID_MASK)) ==
 255                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 256 }
 257
 258 static inline bool is_external_interrupt(u32 intr_info)
 259 {
 260         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 261                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 262 }
 263
 264 static inline bool is_machine_check(u32 intr_info)
 265 {
 266         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 267                              INTR_INFO_VALID_MASK)) ==
 268                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 269 }
 270
 271 static inline bool cpu_has_vmx_msr_bitmap(void)
 272 {
 273         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 274 }
 275
 276 static inline bool cpu_has_vmx_tpr_shadow(void)
 277 {
 278         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 279 }
 280
 281 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 282 {
 283         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 284 }
 285
 286 static inline bool cpu_has_secondary_exec_ctrls(void)
 287 {
 288         return vmcs_config.cpu_based_exec_ctrl &
 289                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 290 }
 291
 292 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 293 {
 294         return vmcs_config.cpu_based_2nd_exec_ctrl &
 295                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 296 }
 297
 298 static inline bool cpu_has_vmx_flexpriority(void)
 299 {
 300         return cpu_has_vmx_tpr_shadow() &&
 301                 cpu_has_vmx_virtualize_apic_accesses();
 302 }
 303
 304 static inline bool cpu_has_vmx_ept_execute_only(void)
 305 {
 306         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 307 }
 308
 309 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 310 {
 311         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 312 }
 313
 314 static inline bool cpu_has_vmx_eptp_writeback(void)
 315 {
 316         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 317 }
 318
 319 static inline bool cpu_has_vmx_ept_2m_page(void)
 320 {
 321         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 322 }
 323
 324 static inline bool cpu_has_vmx_ept_1g_page(void)
 325 {
 326         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 327 }
 328
 329 static inline bool cpu_has_vmx_invept_individual_addr(void)
 330 {
 331         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 332 }
 333
 334 static inline bool cpu_has_vmx_invept_context(void)
 335 {
 336         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 337 }
 338
 339 static inline bool cpu_has_vmx_invept_global(void)
 340 {
 341         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 342 }
 343
 344 static inline bool cpu_has_vmx_ept(void)
 345 {
 346         return vmcs_config.cpu_based_2nd_exec_ctrl &
 347                 SECONDARY_EXEC_ENABLE_EPT;
 348 }
 349
 350 static inline bool cpu_has_vmx_unrestricted_guest(void)
 351 {
 352         return vmcs_config.cpu_based_2nd_exec_ctrl &
 353                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 354 }
 355
 356 static inline bool cpu_has_vmx_ple(void)
 357 {
 358         return vmcs_config.cpu_based_2nd_exec_ctrl &
 359                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 360 }
 361
 362 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 363 {
 364         return flexpriority_enabled && irqchip_in_kernel(kvm);
 365 }
 366
 367 static inline bool cpu_has_vmx_vpid(void)
 368 {
 369         return vmcs_config.cpu_based_2nd_exec_ctrl &
 370                 SECONDARY_EXEC_ENABLE_VPID;
 371 }
 372
 373 static inline bool cpu_has_vmx_rdtscp(void)
 374 {
 375         return vmcs_config.cpu_based_2nd_exec_ctrl &
 376                 SECONDARY_EXEC_RDTSCP;
 377 }
 378
 379 static inline bool cpu_has_virtual_nmis(void)
 380 {
 381         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 382 }
 383
 384 static inline bool report_flexpriority(void)
 385 {
 386         return flexpriority_enabled;
 387 }
 388
 389 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 390 {
 391         int i;
 392
 393         for (i = 0; i < vmx->nmsrs; ++i)
 394                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 395                         return i;
 396         return -1;
 397 }
 398
 399 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 400 {
 401     struct {
 402         u64 vpid : 16;
 403         u64 rsvd : 48;
 404         u64 gva;
 405     } operand = { vpid, 0, gva };
 406
 407     asm volatile (__ex(ASM_VMX_INVVPID)
 408                   /* CF==1 or ZF==1 --> rc = -1 */
 409                   "; ja 1f ; ud2 ; 1:"
 410                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 411 }
 412
 413 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 414 {
 415         struct {
 416                 u64 eptp, gpa;
 417         } operand = {eptp, gpa};
 418
 419         asm volatile (__ex(ASM_VMX_INVEPT)
 420                         /* CF==1 or ZF==1 --> rc = -1 */
 421                         "; ja 1f ; ud2 ; 1:\n"
 422                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 423 }
 424
 425 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 426 {
 427         int i;
 428
 429         i = __find_msr_index(vmx, msr);
 430         if (i >= 0)
 431                 return &vmx->guest_msrs[i];
 432         return NULL;
 433 }
 434
 435 static void vmcs_clear(struct vmcs *vmcs)
 436 {
 437         u64 phys_addr = __pa(vmcs);
 438         u8 error;
 439
 440         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 441                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 442                       : "cc", "memory");
 443         if (error)
 444                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 445                        vmcs, phys_addr);
 446 }
 447
 448 static void __vcpu_clear(void *arg)
 449 {
 450         struct vcpu_vmx *vmx = arg;
 451         int cpu = raw_smp_processor_id();
 452
 453         if (vmx->vcpu.cpu == cpu)
 454                 vmcs_clear(vmx->vmcs);
 455         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 456                 per_cpu(current_vmcs, cpu) = NULL;
 457         rdtscll(vmx->vcpu.arch.host_tsc);
 458         list_del(&vmx->local_vcpus_link);
 459         vmx->vcpu.cpu = -1;
 460         vmx->launched = 0;
 461 }
 462
 463 static void vcpu_clear(struct vcpu_vmx *vmx)
 464 {
 465         if (vmx->vcpu.cpu == -1)
 466                 return;
 467         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 468 }
 469
 470 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 471 {
 472         if (vmx->vpid == 0)
 473                 return;
 474
 475         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 476 }
 477
 478 static inline void ept_sync_global(void)
 479 {
 480         if (cpu_has_vmx_invept_global())
 481                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 482 }
 483
 484 static inline void ept_sync_context(u64 eptp)
 485 {
 486         if (enable_ept) {
 487                 if (cpu_has_vmx_invept_context())
 488                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 489                 else
 490                         ept_sync_global();
 491         }
 492 }
 493
 494 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 495 {
 496         if (enable_ept) {
 497                 if (cpu_has_vmx_invept_individual_addr())
 498                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 499                                         eptp, gpa);
 500                 else
 501                         ept_sync_context(eptp);
 502         }
 503 }
 504
 505 static unsigned long vmcs_readl(unsigned long field)
 506 {
 507         unsigned long value;
 508
 509         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 510                       : "=a"(value) : "d"(field) : "cc");
 511         return value;
 512 }
 513
 514 static u16 vmcs_read16(unsigned long field)
 515 {
 516         return vmcs_readl(field);
 517 }
 518
 519 static u32 vmcs_read32(unsigned long field)
 520 {
 521         return vmcs_readl(field);
 522 }
 523
 524 static u64 vmcs_read64(unsigned long field)
 525 {
 526 #ifdef CONFIG_X86_64
 527         return vmcs_readl(field);
 528 #else
 529         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 530 #endif
 531 }
 532
 533 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 534 {
 535         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 536                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 537         dump_stack();
 538 }
 539
 540 static void vmcs_writel(unsigned long field, unsigned long value)
 541 {
 542         u8 error;
 543
 544         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 545                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 546         if (unlikely(error))
 547                 vmwrite_error(field, value);
 548 }
 549
 550 static void vmcs_write16(unsigned long field, u16 value)
 551 {
 552         vmcs_writel(field, value);
 553 }
 554
 555 static void vmcs_write32(unsigned long field, u32 value)
 556 {
 557         vmcs_writel(field, value);
 558 }
 559
 560 static void vmcs_write64(unsigned long field, u64 value)
 561 {
 562         vmcs_writel(field, value);
 563 #ifndef CONFIG_X86_64
 564         asm volatile ("");
 565         vmcs_writel(field+1, value >> 32);
 566 #endif
 567 }
 568
 569 static void vmcs_clear_bits(unsigned long field, u32 mask)
 570 {
 571         vmcs_writel(field, vmcs_readl(field) & ~mask);
 572 }
 573
 574 static void vmcs_set_bits(unsigned long field, u32 mask)
 575 {
 576         vmcs_writel(field, vmcs_readl(field) | mask);
 577 }
 578
 579 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 580 {
 581         u32 eb;
 582
 583         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 584              (1u << NM_VECTOR) | (1u << DB_VECTOR);
 585         if ((vcpu->guest_debug &
 586              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 587             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 588                 eb |= 1u << BP_VECTOR;
 589         if (to_vmx(vcpu)->rmode.vm86_active)
 590                 eb = ~0;
 591         if (enable_ept)
 592                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 593         if (vcpu->fpu_active)
 594                 eb &= ~(1u << NM_VECTOR);
 595         vmcs_write32(EXCEPTION_BITMAP, eb);
 596 }
 597
 598 static void reload_tss(void)
 599 {
 600         /*
 601          * VT restores TR but not its size.  Useless.
 602          */
 603         struct desc_ptr gdt;
 604         struct desc_struct *descs;
 605
 606         native_store_gdt(&gdt);
 607         descs = (void *)gdt.address;
 608         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 609         load_TR_desc();
 610 }
 611
 612 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 613 {
 614         u64 guest_efer;
 615         u64 ignore_bits;
 616
 617         guest_efer = vmx->vcpu.arch.efer;
 618
 619         /*
 620          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 621          * outside long mode
 622          */
 623         ignore_bits = EFER_NX | EFER_SCE;
 624 #ifdef CONFIG_X86_64
 625         ignore_bits |= EFER_LMA | EFER_LME;
 626         /* SCE is meaningful only in long mode on Intel */
 627         if (guest_efer & EFER_LMA)
 628                 ignore_bits &= ~(u64)EFER_SCE;
 629 #endif
 630         guest_efer &= ~ignore_bits;
 631         guest_efer |= host_efer & ignore_bits;
 632         vmx->guest_msrs[efer_offset].data = guest_efer;
 633         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
 634         return true;
 635 }
 636
 637 static unsigned long segment_base(u16 selector)
 638 {
 639         struct desc_ptr gdt;
 640         struct desc_struct *d;
 641         unsigned long table_base;
 642         unsigned long v;
 643
 644         if (!(selector & ~3))
 645                 return 0;
 646
 647         native_store_gdt(&gdt);
 648         table_base = gdt.address;
 649
 650         if (selector & 4) {           /* from ldt */
 651                 u16 ldt_selector = kvm_read_ldt();
 652
 653                 if (!(ldt_selector & ~3))
 654                         return 0;
 655
 656                 table_base = segment_base(ldt_selector);
 657         }
 658         d = (struct desc_struct *)(table_base + (selector & ~7));
 659         v = get_desc_base(d);
 660 #ifdef CONFIG_X86_64
 661        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
 662                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
 663 #endif
 664         return v;
 665 }
 666
 667 static inline unsigned long kvm_read_tr_base(void)
 668 {
 669         u16 tr;
 670         asm("str %0" : "=g"(tr));
 671         return segment_base(tr);
 672 }
 673
 674 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 675 {
 676         struct vcpu_vmx *vmx = to_vmx(vcpu);
 677         int i;
 678
 679         if (vmx->host_state.loaded)
 680                 return;
 681
 682         vmx->host_state.loaded = 1;
 683         /*
 684          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 685          * allow segment selectors with cpl > 0 or ti == 1.
 686          */
 687         vmx->host_state.ldt_sel = kvm_read_ldt();
 688         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 689         vmx->host_state.fs_sel = kvm_read_fs();
 690         if (!(vmx->host_state.fs_sel & 7)) {
 691                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 692                 vmx->host_state.fs_reload_needed = 0;
 693         } else {
 694                 vmcs_write16(HOST_FS_SELECTOR, 0);
 695                 vmx->host_state.fs_reload_needed = 1;
 696         }
 697         vmx->host_state.gs_sel = kvm_read_gs();
 698         if (!(vmx->host_state.gs_sel & 7))
 699                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 700         else {
 701                 vmcs_write16(HOST_GS_SELECTOR, 0);
 702                 vmx->host_state.gs_ldt_reload_needed = 1;
 703         }
 704
 705 #ifdef CONFIG_X86_64
 706         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 707         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 708 #else
 709         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 710         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 711 #endif
 712
 713 #ifdef CONFIG_X86_64
 714         if (is_long_mode(&vmx->vcpu)) {
 715                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 716                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 717         }
 718 #endif
 719         for (i = 0; i < vmx->save_nmsrs; ++i)
 720                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
 721                                    vmx->guest_msrs[i].data,
 722                                    vmx->guest_msrs[i].mask);
 723 }
 724
 725 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 726 {
 727         unsigned long flags;
 728
 729         if (!vmx->host_state.loaded)
 730                 return;
 731
 732         ++vmx->vcpu.stat.host_state_reload;
 733         vmx->host_state.loaded = 0;
 734         if (vmx->host_state.fs_reload_needed)
 735                 kvm_load_fs(vmx->host_state.fs_sel);
 736         if (vmx->host_state.gs_ldt_reload_needed) {
 737                 kvm_load_ldt(vmx->host_state.ldt_sel);
 738                 /*
 739                  * If we have to reload gs, we must take care to
 740                  * preserve our gs base.
 741                  */
 742                 local_irq_save(flags);
 743                 kvm_load_gs(vmx->host_state.gs_sel);
 744 #ifdef CONFIG_X86_64
 745                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 746 #endif
 747                 local_irq_restore(flags);
 748         }
 749         reload_tss();
 750 #ifdef CONFIG_X86_64
 751         if (is_long_mode(&vmx->vcpu)) {
 752                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 753                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 754         }
 755 #endif
 756 }
 757
 758 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 759 {
 760         preempt_disable();
 761         __vmx_load_host_state(vmx);
 762         preempt_enable();
 763 }
 764
 765 /*
 766  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 767  * vcpu mutex is already taken.
 768  */
 769 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 770 {
 771         struct vcpu_vmx *vmx = to_vmx(vcpu);
 772         u64 phys_addr = __pa(vmx->vmcs);
 773         u64 tsc_this, delta, new_offset;
 774
 775         if (vcpu->cpu != cpu) {
 776                 vcpu_clear(vmx);
 777                 kvm_migrate_timers(vcpu);
 778                 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
 779                 local_irq_disable();
 780                 list_add(&vmx->local_vcpus_link,
 781                          &per_cpu(vcpus_on_cpu, cpu));
 782                 local_irq_enable();
 783         }
 784
 785         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 786                 u8 error;
 787
 788                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 789                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 790                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 791                               : "cc");
 792                 if (error)
 793                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 794                                vmx->vmcs, phys_addr);
 795         }
 796
 797         if (vcpu->cpu != cpu) {
 798                 struct desc_ptr dt;
 799                 unsigned long sysenter_esp;
 800
 801                 vcpu->cpu = cpu;
 802                 /*
 803                  * Linux uses per-cpu TSS and GDT, so set these when switching
 804                  * processors.
 805                  */
 806                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 807                 native_store_gdt(&dt);
 808                 vmcs_writel(HOST_GDTR_BASE, dt.address);   /* 22.2.4 */
 809
 810                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 811                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 812
 813                 /*
 814                  * Make sure the time stamp counter is monotonous.
 815                  */
 816                 rdtscll(tsc_this);
 817                 if (tsc_this < vcpu->arch.host_tsc) {
 818                         delta = vcpu->arch.host_tsc - tsc_this;
 819                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 820                         vmcs_write64(TSC_OFFSET, new_offset);
 821                 }
 822         }
 823 }
 824
 825 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 826 {
 827         __vmx_load_host_state(to_vmx(vcpu));
 828 }
 829
 830 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 831 {
 832         ulong cr0;
 833
 834         if (vcpu->fpu_active)
 835                 return;
 836         vcpu->fpu_active = 1;
 837         cr0 = vmcs_readl(GUEST_CR0);
 838         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
 839         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
 840         vmcs_writel(GUEST_CR0, cr0);
 841         update_exception_bitmap(vcpu);
 842         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
 843         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 844 }
 845
 846 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
 847
 848 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 849 {
 850         vmx_decache_cr0_guest_bits(vcpu);
 851         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
 852         update_exception_bitmap(vcpu);
 853         vcpu->arch.cr0_guest_owned_bits = 0;
 854         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 855         vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
 856 }
 857
 858 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 859 {
 860         unsigned long rflags, save_rflags;
 861
 862         rflags = vmcs_readl(GUEST_RFLAGS);
 863         if (to_vmx(vcpu)->rmode.vm86_active) {
 864                 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
 865                 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
 866                 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
 867         }
 868         return rflags;
 869 }
 870
 871 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 872 {
 873         if (to_vmx(vcpu)->rmode.vm86_active) {
 874                 to_vmx(vcpu)->rmode.save_rflags = rflags;
 875                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 876         }
 877         vmcs_writel(GUEST_RFLAGS, rflags);
 878 }
 879
 880 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 881 {
 882         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 883         int ret = 0;
 884
 885         if (interruptibility & GUEST_INTR_STATE_STI)
 886                 ret |= KVM_X86_SHADOW_INT_STI;
 887         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
 888                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
 889
 890         return ret & mask;
 891 }
 892
 893 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 894 {
 895         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 896         u32 interruptibility = interruptibility_old;
 897
 898         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
 899
 900         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
 901                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
 902         else if (mask & KVM_X86_SHADOW_INT_STI)
 903                 interruptibility |= GUEST_INTR_STATE_STI;
 904
 905         if ((interruptibility != interruptibility_old))
 906                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
 907 }
 908
 909 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 910 {
 911         unsigned long rip;
 912
 913         rip = kvm_rip_read(vcpu);
 914         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 915         kvm_rip_write(vcpu, rip);
 916
 917         /* skipping an emulated instruction also counts */
 918         vmx_set_interrupt_shadow(vcpu, 0);
 919 }
 920
 921 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 922                                 bool has_error_code, u32 error_code)
 923 {
 924         struct vcpu_vmx *vmx = to_vmx(vcpu);
 925         u32 intr_info = nr | INTR_INFO_VALID_MASK;
 926
 927         if (has_error_code) {
 928                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 929                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
 930         }
 931
 932         if (vmx->rmode.vm86_active) {
 933                 vmx->rmode.irq.pending = true;
 934                 vmx->rmode.irq.vector = nr;
 935                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
 936                 if (kvm_exception_is_soft(nr))
 937                         vmx->rmode.irq.rip +=
 938                                 vmx->vcpu.arch.event_exit_inst_len;
 939                 intr_info |= INTR_TYPE_SOFT_INTR;
 940                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 941                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
 942                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
 943                 return;
 944         }
 945
 946         if (kvm_exception_is_soft(nr)) {
 947                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
 948                              vmx->vcpu.arch.event_exit_inst_len);
 949                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
 950         } else
 951                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
 952
 953         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 954 }
 955
 956 static bool vmx_rdtscp_supported(void)
 957 {
 958         return cpu_has_vmx_rdtscp();
 959 }
 960
 961 /*
 962  * Swap MSR entry in host/guest MSR entry array.
 963  */
 964 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 965 {
 966         struct shared_msr_entry tmp;
 967
 968         tmp = vmx->guest_msrs[to];
 969         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 970         vmx->guest_msrs[from] = tmp;
 971 }
 972
 973 /*
 974  * Set up the vmcs to automatically save and restore system
 975  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 976  * mode, as fiddling with msrs is very expensive.
 977  */
 978 static void setup_msrs(struct vcpu_vmx *vmx)
 979 {
 980         int save_nmsrs, index;
 981         unsigned long *msr_bitmap;
 982
 983         vmx_load_host_state(vmx);
 984         save_nmsrs = 0;
 985 #ifdef CONFIG_X86_64
 986         if (is_long_mode(&vmx->vcpu)) {
 987                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 988                 if (index >= 0)
 989                         move_msr_up(vmx, index, save_nmsrs++);
 990                 index = __find_msr_index(vmx, MSR_LSTAR);
 991                 if (index >= 0)
 992                         move_msr_up(vmx, index, save_nmsrs++);
 993                 index = __find_msr_index(vmx, MSR_CSTAR);
 994                 if (index >= 0)
 995                         move_msr_up(vmx, index, save_nmsrs++);
 996                 index = __find_msr_index(vmx, MSR_TSC_AUX);
 997                 if (index >= 0 && vmx->rdtscp_enabled)
 998                         move_msr_up(vmx, index, save_nmsrs++);
 999                 /*
1000                  * MSR_K6_STAR is only needed on long mode guests, and only
1001                  * if efer.sce is enabled.
1002                  */
1003                 index = __find_msr_index(vmx, MSR_K6_STAR);
1004                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1005                         move_msr_up(vmx, index, save_nmsrs++);
1006         }
1007 #endif
1008         index = __find_msr_index(vmx, MSR_EFER);
1009         if (index >= 0 && update_transition_efer(vmx, index))
1010                 move_msr_up(vmx, index, save_nmsrs++);
1011
1012         vmx->save_nmsrs = save_nmsrs;
1013
1014         if (cpu_has_vmx_msr_bitmap()) {
1015                 if (is_long_mode(&vmx->vcpu))
1016                         msr_bitmap = vmx_msr_bitmap_longmode;
1017                 else
1018                         msr_bitmap = vmx_msr_bitmap_legacy;
1019
1020                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1021         }
1022 }
1023
1024 /*
1025  * reads and returns guest's timestamp counter "register"
1026  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1027  */
1028 static u64 guest_read_tsc(void)
1029 {
1030         u64 host_tsc, tsc_offset;
1031
1032         rdtscll(host_tsc);
1033         tsc_offset = vmcs_read64(TSC_OFFSET);
1034         return host_tsc + tsc_offset;
1035 }
1036
1037 /*
1038  * writes 'guest_tsc' into guest's timestamp counter "register"
1039  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
1040  */
1041 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
1042 {
1043         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
1044 }
1045
1046 /*
1047  * Reads an msr value (of 'msr_index') into 'pdata'.
1048  * Returns 0 on success, non-0 otherwise.
1049  * Assumes vcpu_load() was already called.
1050  */
1051 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1052 {
1053         u64 data;
1054         struct shared_msr_entry *msr;
1055
1056         if (!pdata) {
1057                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1058                 return -EINVAL;
1059         }
1060
1061         switch (msr_index) {
1062 #ifdef CONFIG_X86_64
1063         case MSR_FS_BASE:
1064                 data = vmcs_readl(GUEST_FS_BASE);
1065                 break;
1066         case MSR_GS_BASE:
1067                 data = vmcs_readl(GUEST_GS_BASE);
1068                 break;
1069         case MSR_KERNEL_GS_BASE:
1070                 vmx_load_host_state(to_vmx(vcpu));
1071                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1072                 break;
1073 #endif
1074         case MSR_EFER:
1075                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1076         case MSR_IA32_TSC:
1077                 data = guest_read_tsc();
1078                 break;
1079         case MSR_IA32_SYSENTER_CS:
1080                 data = vmcs_read32(GUEST_SYSENTER_CS);
1081                 break;
1082         case MSR_IA32_SYSENTER_EIP:
1083                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1084                 break;
1085         case MSR_IA32_SYSENTER_ESP:
1086                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1087                 break;
1088         case MSR_TSC_AUX:
1089                 if (!to_vmx(vcpu)->rdtscp_enabled)
1090                         return 1;
1091                 /* Otherwise falls through */
1092         default:
1093                 vmx_load_host_state(to_vmx(vcpu));
1094                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1095                 if (msr) {
1096                         vmx_load_host_state(to_vmx(vcpu));
1097                         data = msr->data;
1098                         break;
1099                 }
1100                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1101         }
1102
1103         *pdata = data;
1104         return 0;
1105 }
1106
1107 /*
1108  * Writes msr value into into the appropriate "register".
1109  * Returns 0 on success, non-0 otherwise.
1110  * Assumes vcpu_load() was already called.
1111  */
1112 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1113 {
1114         struct vcpu_vmx *vmx = to_vmx(vcpu);
1115         struct shared_msr_entry *msr;
1116         u64 host_tsc;
1117         int ret = 0;
1118
1119         switch (msr_index) {
1120         case MSR_EFER:
1121                 vmx_load_host_state(vmx);
1122                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1123                 break;
1124 #ifdef CONFIG_X86_64
1125         case MSR_FS_BASE:
1126                 vmcs_writel(GUEST_FS_BASE, data);
1127                 break;
1128         case MSR_GS_BASE:
1129                 vmcs_writel(GUEST_GS_BASE, data);
1130                 break;
1131         case MSR_KERNEL_GS_BASE:
1132                 vmx_load_host_state(vmx);
1133                 vmx->msr_guest_kernel_gs_base = data;
1134                 break;
1135 #endif
1136         case MSR_IA32_SYSENTER_CS:
1137                 vmcs_write32(GUEST_SYSENTER_CS, data);
1138                 break;
1139         case MSR_IA32_SYSENTER_EIP:
1140                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1141                 break;
1142         case MSR_IA32_SYSENTER_ESP:
1143                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1144                 break;
1145         case MSR_IA32_TSC:
1146                 rdtscll(host_tsc);
1147                 guest_write_tsc(data, host_tsc);
1148                 break;
1149         case MSR_IA32_CR_PAT:
1150                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1151                         vmcs_write64(GUEST_IA32_PAT, data);
1152                         vcpu->arch.pat = data;
1153                         break;
1154                 }
1155                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1156                 break;
1157         case MSR_TSC_AUX:
1158                 if (!vmx->rdtscp_enabled)
1159                         return 1;
1160                 /* Check reserved bit, higher 32 bits should be zero */
1161                 if ((data >> 32) != 0)
1162                         return 1;
1163                 /* Otherwise falls through */
1164         default:
1165                 msr = find_msr_entry(vmx, msr_index);
1166                 if (msr) {
1167                         vmx_load_host_state(vmx);
1168                         msr->data = data;
1169                         break;
1170                 }
1171                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1172         }
1173
1174         return ret;
1175 }
1176
1177 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1178 {
1179         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1180         switch (reg) {
1181         case VCPU_REGS_RSP:
1182                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1183                 break;
1184         case VCPU_REGS_RIP:
1185                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1186                 break;
1187         case VCPU_EXREG_PDPTR:
1188                 if (enable_ept)
1189                         ept_save_pdptrs(vcpu);
1190                 break;
1191         default:
1192                 break;
1193         }
1194 }
1195
1196 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1197 {
1198         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1199                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1200         else
1201                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1202
1203         update_exception_bitmap(vcpu);
1204 }
1205
1206 static __init int cpu_has_kvm_support(void)
1207 {
1208         return cpu_has_vmx();
1209 }
1210
1211 static __init int vmx_disabled_by_bios(void)
1212 {
1213         u64 msr;
1214
1215         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1216         return (msr & (FEATURE_CONTROL_LOCKED |
1217                        FEATURE_CONTROL_VMXON_ENABLED))
1218             == FEATURE_CONTROL_LOCKED;
1219         /* locked but not enabled */
1220 }
1221
1222 static int hardware_enable(void *garbage)
1223 {
1224         int cpu = raw_smp_processor_id();
1225         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1226         u64 old;
1227
1228         if (read_cr4() & X86_CR4_VMXE)
1229                 return -EBUSY;
1230
1231         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1232         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1233         if ((old & (FEATURE_CONTROL_LOCKED |
1234                     FEATURE_CONTROL_VMXON_ENABLED))
1235             != (FEATURE_CONTROL_LOCKED |
1236                 FEATURE_CONTROL_VMXON_ENABLED))
1237                 /* enable and lock */
1238                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1239                        FEATURE_CONTROL_LOCKED |
1240                        FEATURE_CONTROL_VMXON_ENABLED);
1241         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1242         asm volatile (ASM_VMX_VMXON_RAX
1243                       : : "a"(&phys_addr), "m"(phys_addr)
1244                       : "memory", "cc");
1245
1246         ept_sync_global();
1247
1248         return 0;
1249 }
1250
1251 static void vmclear_local_vcpus(void)
1252 {
1253         int cpu = raw_smp_processor_id();
1254         struct vcpu_vmx *vmx, *n;
1255
1256         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1257                                  local_vcpus_link)
1258                 __vcpu_clear(vmx);
1259 }
1260
1261
1262 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1263  * tricks.
1264  */
1265 static void kvm_cpu_vmxoff(void)
1266 {
1267         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1268         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1269 }
1270
1271 static void hardware_disable(void *garbage)
1272 {
1273         vmclear_local_vcpus();
1274         kvm_cpu_vmxoff();
1275 }
1276
1277 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1278                                       u32 msr, u32 *result)
1279 {
1280         u32 vmx_msr_low, vmx_msr_high;
1281         u32 ctl = ctl_min | ctl_opt;
1282
1283         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1284
1285         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1286         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1287
1288         /* Ensure minimum (required) set of control bits are supported. */
1289         if (ctl_min & ~ctl)
1290                 return -EIO;
1291
1292         *result = ctl;
1293         return 0;
1294 }
1295
1296 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1297 {
1298         u32 vmx_msr_low, vmx_msr_high;
1299         u32 min, opt, min2, opt2;
1300         u32 _pin_based_exec_control = 0;
1301         u32 _cpu_based_exec_control = 0;
1302         u32 _cpu_based_2nd_exec_control = 0;
1303         u32 _vmexit_control = 0;
1304         u32 _vmentry_control = 0;
1305
1306         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1307         opt = PIN_BASED_VIRTUAL_NMIS;
1308         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1309                                 &_pin_based_exec_control) < 0)
1310                 return -EIO;
1311
1312         min = CPU_BASED_HLT_EXITING |
1313 #ifdef CONFIG_X86_64
1314               CPU_BASED_CR8_LOAD_EXITING |
1315               CPU_BASED_CR8_STORE_EXITING |
1316 #endif
1317               CPU_BASED_CR3_LOAD_EXITING |
1318               CPU_BASED_CR3_STORE_EXITING |
1319               CPU_BASED_USE_IO_BITMAPS |
1320               CPU_BASED_MOV_DR_EXITING |
1321               CPU_BASED_USE_TSC_OFFSETING |
1322               CPU_BASED_MWAIT_EXITING |
1323               CPU_BASED_MONITOR_EXITING |
1324               CPU_BASED_INVLPG_EXITING;
1325         opt = CPU_BASED_TPR_SHADOW |
1326               CPU_BASED_USE_MSR_BITMAPS |
1327               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1328         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1329                                 &_cpu_based_exec_control) < 0)
1330                 return -EIO;
1331 #ifdef CONFIG_X86_64
1332         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1333                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1334                                            ~CPU_BASED_CR8_STORE_EXITING;
1335 #endif
1336         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1337                 min2 = 0;
1338                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1339                         SECONDARY_EXEC_WBINVD_EXITING |
1340                         SECONDARY_EXEC_ENABLE_VPID |
1341                         SECONDARY_EXEC_ENABLE_EPT |
1342                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
1343                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1344                         SECONDARY_EXEC_RDTSCP;
1345                 if (adjust_vmx_controls(min2, opt2,
1346                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1347                                         &_cpu_based_2nd_exec_control) < 0)
1348                         return -EIO;
1349         }
1350 #ifndef CONFIG_X86_64
1351         if (!(_cpu_based_2nd_exec_control &
1352                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1353                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1354 #endif
1355         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1356                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1357                    enabled */
1358                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1359                                              CPU_BASED_CR3_STORE_EXITING |
1360                                              CPU_BASED_INVLPG_EXITING);
1361                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1362                       vmx_capability.ept, vmx_capability.vpid);
1363         }
1364
1365         min = 0;
1366 #ifdef CONFIG_X86_64
1367         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1368 #endif
1369         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1370         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1371                                 &_vmexit_control) < 0)
1372                 return -EIO;
1373
1374         min = 0;
1375         opt = VM_ENTRY_LOAD_IA32_PAT;
1376         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1377                                 &_vmentry_control) < 0)
1378                 return -EIO;
1379
1380         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1381
1382         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1383         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1384                 return -EIO;
1385
1386 #ifdef CONFIG_X86_64
1387         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1388         if (vmx_msr_high & (1u<<16))
1389                 return -EIO;
1390 #endif
1391
1392         /* Require Write-Back (WB) memory type for VMCS accesses. */
1393         if (((vmx_msr_high >> 18) & 15) != 6)
1394                 return -EIO;
1395
1396         vmcs_conf->size = vmx_msr_high & 0x1fff;
1397         vmcs_conf->order = get_order(vmcs_config.size);
1398         vmcs_conf->revision_id = vmx_msr_low;
1399
1400         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1401         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1402         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1403         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1404         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1405
1406         return 0;
1407 }
1408
1409 static struct vmcs *alloc_vmcs_cpu(int cpu)
1410 {
1411         int node = cpu_to_node(cpu);
1412         struct page *pages;
1413         struct vmcs *vmcs;
1414
1415         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1416         if (!pages)
1417                 return NULL;
1418         vmcs = page_address(pages);
1419         memset(vmcs, 0, vmcs_config.size);
1420         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1421         return vmcs;
1422 }
1423
1424 static struct vmcs *alloc_vmcs(void)
1425 {
1426         return alloc_vmcs_cpu(raw_smp_processor_id());
1427 }
1428
1429 static void free_vmcs(struct vmcs *vmcs)
1430 {
1431         free_pages((unsigned long)vmcs, vmcs_config.order);
1432 }
1433
1434 static void free_kvm_area(void)
1435 {
1436         int cpu;
1437
1438         for_each_possible_cpu(cpu) {
1439                 free_vmcs(per_cpu(vmxarea, cpu));
1440                 per_cpu(vmxarea, cpu) = NULL;
1441         }
1442 }
1443
1444 static __init int alloc_kvm_area(void)
1445 {
1446         int cpu;
1447
1448         for_each_possible_cpu(cpu) {
1449                 struct vmcs *vmcs;
1450
1451                 vmcs = alloc_vmcs_cpu(cpu);
1452                 if (!vmcs) {
1453                         free_kvm_area();
1454                         return -ENOMEM;
1455                 }
1456
1457                 per_cpu(vmxarea, cpu) = vmcs;
1458         }
1459         return 0;
1460 }
1461
1462 static __init int hardware_setup(void)
1463 {
1464         if (setup_vmcs_config(&vmcs_config) < 0)
1465                 return -EIO;
1466
1467         if (boot_cpu_has(X86_FEATURE_NX))
1468                 kvm_enable_efer_bits(EFER_NX);
1469
1470         if (!cpu_has_vmx_vpid())
1471                 enable_vpid = 0;
1472
1473         if (!cpu_has_vmx_ept()) {
1474                 enable_ept = 0;
1475                 enable_unrestricted_guest = 0;
1476         }
1477
1478         if (!cpu_has_vmx_unrestricted_guest())
1479                 enable_unrestricted_guest = 0;
1480
1481         if (!cpu_has_vmx_flexpriority())
1482                 flexpriority_enabled = 0;
1483
1484         if (!cpu_has_vmx_tpr_shadow())
1485                 kvm_x86_ops->update_cr8_intercept = NULL;
1486
1487         if (enable_ept && !cpu_has_vmx_ept_2m_page())
1488                 kvm_disable_largepages();
1489
1490         if (!cpu_has_vmx_ple())
1491                 ple_gap = 0;
1492
1493         return alloc_kvm_area();
1494 }
1495
1496 static __exit void hardware_unsetup(void)
1497 {
1498         free_kvm_area();
1499 }
1500
1501 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1502 {
1503         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1504
1505         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1506                 vmcs_write16(sf->selector, save->selector);
1507                 vmcs_writel(sf->base, save->base);
1508                 vmcs_write32(sf->limit, save->limit);
1509                 vmcs_write32(sf->ar_bytes, save->ar);
1510         } else {
1511                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1512                         << AR_DPL_SHIFT;
1513                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1514         }
1515 }
1516
1517 static void enter_pmode(struct kvm_vcpu *vcpu)
1518 {
1519         unsigned long flags;
1520         struct vcpu_vmx *vmx = to_vmx(vcpu);
1521
1522         vmx->emulation_required = 1;
1523         vmx->rmode.vm86_active = 0;
1524
1525         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1526         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1527         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1528
1529         flags = vmcs_readl(GUEST_RFLAGS);
1530         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1531         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1532         vmcs_writel(GUEST_RFLAGS, flags);
1533
1534         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1535                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1536
1537         update_exception_bitmap(vcpu);
1538
1539         if (emulate_invalid_guest_state)
1540                 return;
1541
1542         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1543         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1544         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1545         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1546
1547         vmcs_write16(GUEST_SS_SELECTOR, 0);
1548         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1549
1550         vmcs_write16(GUEST_CS_SELECTOR,
1551                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1552         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1553 }
1554
1555 static gva_t rmode_tss_base(struct kvm *kvm)
1556 {
1557         if (!kvm->arch.tss_addr) {
1558                 struct kvm_memslots *slots;
1559                 gfn_t base_gfn;
1560
1561                 slots = rcu_dereference(kvm->memslots);
1562                 base_gfn = kvm->memslots->memslots[0].base_gfn +
1563                                  kvm->memslots->memslots[0].npages - 3;
1564                 return base_gfn << PAGE_SHIFT;
1565         }
1566         return kvm->arch.tss_addr;
1567 }
1568
1569 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1570 {
1571         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1572
1573         save->selector = vmcs_read16(sf->selector);
1574         save->base = vmcs_readl(sf->base);
1575         save->limit = vmcs_read32(sf->limit);
1576         save->ar = vmcs_read32(sf->ar_bytes);
1577         vmcs_write16(sf->selector, save->base >> 4);
1578         vmcs_write32(sf->base, save->base & 0xfffff);
1579         vmcs_write32(sf->limit, 0xffff);
1580         vmcs_write32(sf->ar_bytes, 0xf3);
1581 }
1582
1583 static void enter_rmode(struct kvm_vcpu *vcpu)
1584 {
1585         unsigned long flags;
1586         struct vcpu_vmx *vmx = to_vmx(vcpu);
1587
1588         if (enable_unrestricted_guest)
1589                 return;
1590
1591         vmx->emulation_required = 1;
1592         vmx->rmode.vm86_active = 1;
1593
1594         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1595         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1596
1597         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1598         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1599
1600         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1601         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1602
1603         flags = vmcs_readl(GUEST_RFLAGS);
1604         vmx->rmode.save_rflags = flags;
1605
1606         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1607
1608         vmcs_writel(GUEST_RFLAGS, flags);
1609         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1610         update_exception_bitmap(vcpu);
1611
1612         if (emulate_invalid_guest_state)
1613                 goto continue_rmode;
1614
1615         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1616         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1617         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1618
1619         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1620         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1621         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1622                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1623         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1624
1625         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1626         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1627         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1628         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1629
1630 continue_rmode:
1631         kvm_mmu_reset_context(vcpu);
1632         init_rmode(vcpu->kvm);
1633 }
1634
1635 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1636 {
1637         struct vcpu_vmx *vmx = to_vmx(vcpu);
1638         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1639
1640         if (!msr)
1641                 return;
1642
1643         /*
1644          * Force kernel_gs_base reloading before EFER changes, as control
1645          * of this msr depends on is_long_mode().
1646          */
1647         vmx_load_host_state(to_vmx(vcpu));
1648         vcpu->arch.efer = efer;
1649         if (efer & EFER_LMA) {
1650                 vmcs_write32(VM_ENTRY_CONTROLS,
1651                              vmcs_read32(VM_ENTRY_CONTROLS) |
1652                              VM_ENTRY_IA32E_MODE);
1653                 msr->data = efer;
1654         } else {
1655                 vmcs_write32(VM_ENTRY_CONTROLS,
1656                              vmcs_read32(VM_ENTRY_CONTROLS) &
1657                              ~VM_ENTRY_IA32E_MODE);
1658
1659                 msr->data = efer & ~EFER_LME;
1660         }
1661         setup_msrs(vmx);
1662 }
1663
1664 #ifdef CONFIG_X86_64
1665
1666 static void enter_lmode(struct kvm_vcpu *vcpu)
1667 {
1668         u32 guest_tr_ar;
1669
1670         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1671         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1672                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1673                        __func__);
1674                 vmcs_write32(GUEST_TR_AR_BYTES,
1675                              (guest_tr_ar & ~AR_TYPE_MASK)
1676                              | AR_TYPE_BUSY_64_TSS);
1677         }
1678         vcpu->arch.efer |= EFER_LMA;
1679         vmx_set_efer(vcpu, vcpu->arch.efer);
1680 }
1681
1682 static void exit_lmode(struct kvm_vcpu *vcpu)
1683 {
1684         vcpu->arch.efer &= ~EFER_LMA;
1685
1686         vmcs_write32(VM_ENTRY_CONTROLS,
1687                      vmcs_read32(VM_ENTRY_CONTROLS)
1688                      & ~VM_ENTRY_IA32E_MODE);
1689 }
1690
1691 #endif
1692
1693 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1694 {
1695         vpid_sync_vcpu_all(to_vmx(vcpu));
1696         if (enable_ept)
1697                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1698 }
1699
1700 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1701 {
1702         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1703
1704         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1705         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1706 }
1707
1708 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1709 {
1710         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1711
1712         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1713         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1714 }
1715
1716 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1717 {
1718         if (!test_bit(VCPU_EXREG_PDPTR,
1719                       (unsigned long *)&vcpu->arch.regs_dirty))
1720                 return;
1721
1722         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1723                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1724                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1725                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1726                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1727         }
1728 }
1729
1730 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1731 {
1732         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1733                 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1734                 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1735                 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1736                 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1737         }
1738
1739         __set_bit(VCPU_EXREG_PDPTR,
1740                   (unsigned long *)&vcpu->arch.regs_avail);
1741         __set_bit(VCPU_EXREG_PDPTR,
1742                   (unsigned long *)&vcpu->arch.regs_dirty);
1743 }
1744
1745 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1746
1747 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1748                                         unsigned long cr0,
1749                                         struct kvm_vcpu *vcpu)
1750 {
1751         if (!(cr0 & X86_CR0_PG)) {
1752                 /* From paging/starting to nonpaging */
1753                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1754                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1755                              (CPU_BASED_CR3_LOAD_EXITING |
1756                               CPU_BASED_CR3_STORE_EXITING));
1757                 vcpu->arch.cr0 = cr0;
1758                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1759         } else if (!is_paging(vcpu)) {
1760                 /* From nonpaging to paging */
1761                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1762                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1763                              ~(CPU_BASED_CR3_LOAD_EXITING |
1764                                CPU_BASED_CR3_STORE_EXITING));
1765                 vcpu->arch.cr0 = cr0;
1766                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1767         }
1768
1769         if (!(cr0 & X86_CR0_WP))
1770                 *hw_cr0 &= ~X86_CR0_WP;
1771 }
1772
1773 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1774 {
1775         struct vcpu_vmx *vmx = to_vmx(vcpu);
1776         unsigned long hw_cr0;
1777
1778         if (enable_unrestricted_guest)
1779                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1780                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1781         else
1782                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1783
1784         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1785                 enter_pmode(vcpu);
1786
1787         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1788                 enter_rmode(vcpu);
1789
1790 #ifdef CONFIG_X86_64
1791         if (vcpu->arch.efer & EFER_LME) {
1792                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1793                         enter_lmode(vcpu);
1794                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1795                         exit_lmode(vcpu);
1796         }
1797 #endif
1798
1799         if (enable_ept)
1800                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1801
1802         if (!vcpu->fpu_active)
1803                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
1804
1805         vmcs_writel(CR0_READ_SHADOW, cr0);
1806         vmcs_writel(GUEST_CR0, hw_cr0);
1807         vcpu->arch.cr0 = cr0;
1808 }
1809
1810 static u64 construct_eptp(unsigned long root_hpa)
1811 {
1812         u64 eptp;
1813
1814         /* TODO write the value reading from MSR */
1815         eptp = VMX_EPT_DEFAULT_MT |
1816                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1817         eptp |= (root_hpa & PAGE_MASK);
1818
1819         return eptp;
1820 }
1821
1822 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1823 {
1824         unsigned long guest_cr3;
1825         u64 eptp;
1826
1827         guest_cr3 = cr3;
1828         if (enable_ept) {
1829                 eptp = construct_eptp(cr3);
1830                 vmcs_write64(EPT_POINTER, eptp);
1831                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1832                         vcpu->kvm->arch.ept_identity_map_addr;
1833                 ept_load_pdptrs(vcpu);
1834         }
1835
1836         vmx_flush_tlb(vcpu);
1837         vmcs_writel(GUEST_CR3, guest_cr3);
1838 }
1839
1840 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1841 {
1842         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1843                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1844
1845         vcpu->arch.cr4 = cr4;
1846         if (enable_ept) {
1847                 if (!is_paging(vcpu)) {
1848                         hw_cr4 &= ~X86_CR4_PAE;
1849                         hw_cr4 |= X86_CR4_PSE;
1850                 } else if (!(cr4 & X86_CR4_PAE)) {
1851                         hw_cr4 &= ~X86_CR4_PAE;
1852                 }
1853         }
1854
1855         vmcs_writel(CR4_READ_SHADOW, cr4);
1856         vmcs_writel(GUEST_CR4, hw_cr4);
1857 }
1858
1859 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1860 {
1861         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1862
1863         return vmcs_readl(sf->base);
1864 }
1865
1866 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1867                             struct kvm_segment *var, int seg)
1868 {
1869         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1870         u32 ar;
1871
1872         var->base = vmcs_readl(sf->base);
1873         var->limit = vmcs_read32(sf->limit);
1874         var->selector = vmcs_read16(sf->selector);
1875         ar = vmcs_read32(sf->ar_bytes);
1876         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1877                 ar = 0;
1878         var->type = ar & 15;
1879         var->s = (ar >> 4) & 1;
1880         var->dpl = (ar >> 5) & 3;
1881         var->present = (ar >> 7) & 1;
1882         var->avl = (ar >> 12) & 1;
1883         var->l = (ar >> 13) & 1;
1884         var->db = (ar >> 14) & 1;
1885         var->g = (ar >> 15) & 1;
1886         var->unusable = (ar >> 16) & 1;
1887 }
1888
1889 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1890 {
1891         if (!is_protmode(vcpu))
1892                 return 0;
1893
1894         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1895                 return 3;
1896
1897         return vmcs_read16(GUEST_CS_SELECTOR) & 3;
1898 }
1899
1900 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1901 {
1902         u32 ar;
1903
1904         if (var->unusable)
1905                 ar = 1 << 16;
1906         else {
1907                 ar = var->type & 15;
1908                 ar |= (var->s & 1) << 4;
1909                 ar |= (var->dpl & 3) << 5;
1910                 ar |= (var->present & 1) << 7;
1911                 ar |= (var->avl & 1) << 12;
1912                 ar |= (var->l & 1) << 13;
1913                 ar |= (var->db & 1) << 14;
1914                 ar |= (var->g & 1) << 15;
1915         }
1916         if (ar == 0) /* a 0 value means unusable */
1917                 ar = AR_UNUSABLE_MASK;
1918
1919         return ar;
1920 }
1921
1922 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1923                             struct kvm_segment *var, int seg)
1924 {
1925         struct vcpu_vmx *vmx = to_vmx(vcpu);
1926         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1927         u32 ar;
1928
1929         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1930                 vmx->rmode.tr.selector = var->selector;
1931                 vmx->rmode.tr.base = var->base;
1932                 vmx->rmode.tr.limit = var->limit;
1933                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
1934                 return;
1935         }
1936         vmcs_writel(sf->base, var->base);
1937         vmcs_write32(sf->limit, var->limit);
1938         vmcs_write16(sf->selector, var->selector);
1939         if (vmx->rmode.vm86_active && var->s) {
1940                 /*
1941                  * Hack real-mode segments into vm86 compatibility.
1942                  */
1943                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1944                         vmcs_writel(sf->base, 0xf0000);
1945                 ar = 0xf3;
1946         } else
1947                 ar = vmx_segment_access_rights(var);
1948
1949         /*
1950          *   Fix the "Accessed" bit in AR field of segment registers for older
1951          * qemu binaries.
1952          *   IA32 arch specifies that at the time of processor reset the
1953          * "Accessed" bit in the AR field of segment registers is 1. And qemu
1954          * is setting it to 0 in the usedland code. This causes invalid guest
1955          * state vmexit when "unrestricted guest" mode is turned on.
1956          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
1957          * tree. Newer qemu binaries with that qemu fix would not need this
1958          * kvm hack.
1959          */
1960         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1961                 ar |= 0x1; /* Accessed */
1962
1963         vmcs_write32(sf->ar_bytes, ar);
1964 }
1965
1966 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1967 {
1968         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1969
1970         *db = (ar >> 14) & 1;
1971         *l = (ar >> 13) & 1;
1972 }
1973
1974 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1975 {
1976         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
1977         dt->address = vmcs_readl(GUEST_IDTR_BASE);
1978 }
1979
1980 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1981 {
1982         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
1983         vmcs_writel(GUEST_IDTR_BASE, dt->address);
1984 }
1985
1986 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1987 {
1988         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
1989         dt->address = vmcs_readl(GUEST_GDTR_BASE);
1990 }
1991
1992 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1993 {
1994         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
1995         vmcs_writel(GUEST_GDTR_BASE, dt->address);
1996 }
1997
1998 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1999 {
2000         struct kvm_segment var;
2001         u32 ar;
2002
2003         vmx_get_segment(vcpu, &var, seg);
2004         ar = vmx_segment_access_rights(&var);
2005
2006         if (var.base != (var.selector << 4))
2007                 return false;
2008         if (var.limit != 0xffff)
2009                 return false;
2010         if (ar != 0xf3)
2011                 return false;
2012
2013         return true;
2014 }
2015
2016 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2017 {
2018         struct kvm_segment cs;
2019         unsigned int cs_rpl;
2020
2021         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2022         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2023
2024         if (cs.unusable)
2025                 return false;
2026         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2027                 return false;
2028         if (!cs.s)
2029                 return false;
2030         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2031                 if (cs.dpl > cs_rpl)
2032                         return false;
2033         } else {
2034                 if (cs.dpl != cs_rpl)
2035                         return false;
2036         }
2037         if (!cs.present)
2038                 return false;
2039
2040         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2041         return true;
2042 }
2043
2044 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2045 {
2046         struct kvm_segment ss;
2047         unsigned int ss_rpl;
2048
2049         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2050         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2051
2052         if (ss.unusable)
2053                 return true;
2054         if (ss.type != 3 && ss.type != 7)
2055                 return false;
2056         if (!ss.s)
2057                 return false;
2058         if (ss.dpl != ss_rpl) /* DPL != RPL */
2059                 return false;
2060         if (!ss.present)
2061                 return false;
2062
2063         return true;
2064 }
2065
2066 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2067 {
2068         struct kvm_segment var;
2069         unsigned int rpl;
2070
2071         vmx_get_segment(vcpu, &var, seg);
2072         rpl = var.selector & SELECTOR_RPL_MASK;
2073
2074         if (var.unusable)
2075                 return true;
2076         if (!var.s)
2077                 return false;
2078         if (!var.present)
2079                 return false;
2080         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2081                 if (var.dpl < rpl) /* DPL < RPL */
2082                         return false;
2083         }
2084
2085         /* TODO: Add other members to kvm_segment_field to allow checking for other access
2086          * rights flags
2087          */
2088         return true;
2089 }
2090
2091 static bool tr_valid(struct kvm_vcpu *vcpu)
2092 {
2093         struct kvm_segment tr;
2094
2095         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2096
2097         if (tr.unusable)
2098                 return false;
2099         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
2100                 return false;
2101         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2102                 return false;
2103         if (!tr.present)
2104                 return false;
2105
2106         return true;
2107 }
2108
2109 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2110 {
2111         struct kvm_segment ldtr;
2112
2113         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2114
2115         if (ldtr.unusable)
2116                 return true;
2117         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
2118                 return false;
2119         if (ldtr.type != 2)
2120                 return false;
2121         if (!ldtr.present)
2122                 return false;
2123
2124         return true;
2125 }
2126
2127 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2128 {
2129         struct kvm_segment cs, ss;
2130
2131         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2132         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2133
2134         return ((cs.selector & SELECTOR_RPL_MASK) ==
2135                  (ss.selector & SELECTOR_RPL_MASK));
2136 }
2137
2138 /*
2139  * Check if guest state is valid. Returns true if valid, false if
2140  * not.
2141  * We assume that registers are always usable
2142  */
2143 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2144 {
2145         /* real mode guest state checks */
2146         if (!is_protmode(vcpu)) {
2147                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2148                         return false;
2149                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2150                         return false;
2151                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2152                         return false;
2153                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2154                         return false;
2155                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2156                         return false;
2157                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2158                         return false;
2159         } else {
2160         /* protected mode guest state checks */
2161                 if (!cs_ss_rpl_check(vcpu))
2162                         return false;
2163                 if (!code_segment_valid(vcpu))
2164                         return false;
2165                 if (!stack_segment_valid(vcpu))
2166                         return false;
2167                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2168                         return false;
2169                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2170                         return false;
2171                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2172                         return false;
2173                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2174                         return false;
2175                 if (!tr_valid(vcpu))
2176                         return false;
2177                 if (!ldtr_valid(vcpu))
2178                         return false;
2179         }
2180         /* TODO:
2181          * - Add checks on RIP
2182          * - Add checks on RFLAGS
2183          */
2184
2185         return true;
2186 }
2187
2188 static int init_rmode_tss(struct kvm *kvm)
2189 {
2190         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2191         u16 data = 0;
2192         int ret = 0;
2193         int r;
2194
2195         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2196         if (r < 0)
2197                 goto out;
2198         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2199         r = kvm_write_guest_page(kvm, fn++, &data,
2200                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
2201         if (r < 0)
2202                 goto out;
2203         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2204         if (r < 0)
2205                 goto out;
2206         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2207         if (r < 0)
2208                 goto out;
2209         data = ~0;
2210         r = kvm_write_guest_page(kvm, fn, &data,
2211                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2212                                  sizeof(u8));
2213         if (r < 0)
2214                 goto out;
2215
2216         ret = 1;
2217 out:
2218         return ret;
2219 }
2220
2221 static int init_rmode_identity_map(struct kvm *kvm)
2222 {
2223         int i, r, ret;
2224         pfn_t identity_map_pfn;
2225         u32 tmp;
2226
2227         if (!enable_ept)
2228                 return 1;
2229         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2230                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2231                         "haven't been allocated!\n");
2232                 return 0;
2233         }
2234         if (likely(kvm->arch.ept_identity_pagetable_done))
2235                 return 1;
2236         ret = 0;
2237         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2238         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2239         if (r < 0)
2240                 goto out;
2241         /* Set up identity-mapping pagetable for EPT in real mode */
2242         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2243                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2244                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2245                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2246                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2247                 if (r < 0)
2248                         goto out;
2249         }
2250         kvm->arch.ept_identity_pagetable_done = true;
2251         ret = 1;
2252 out:
2253         return ret;
2254 }
2255
2256 static void seg_setup(int seg)
2257 {
2258         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2259         unsigned int ar;
2260
2261         vmcs_write16(sf->selector, 0);
2262         vmcs_writel(sf->base, 0);
2263         vmcs_write32(sf->limit, 0xffff);
2264         if (enable_unrestricted_guest) {
2265                 ar = 0x93;
2266                 if (seg == VCPU_SREG_CS)
2267                         ar |= 0x08; /* code segment */
2268         } else
2269                 ar = 0xf3;
2270
2271         vmcs_write32(sf->ar_bytes, ar);
2272 }
2273
2274 static int alloc_apic_access_page(struct kvm *kvm)
2275 {
2276         struct kvm_userspace_memory_region kvm_userspace_mem;
2277         int r = 0;
2278
2279         mutex_lock(&kvm->slots_lock);
2280         if (kvm->arch.apic_access_page)
2281                 goto out;
2282         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2283         kvm_userspace_mem.flags = 0;
2284         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2285         kvm_userspace_mem.memory_size = PAGE_SIZE;
2286         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2287         if (r)
2288                 goto out;
2289
2290         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2291 out:
2292         mutex_unlock(&kvm->slots_lock);
2293         return r;
2294 }
2295
2296 static int alloc_identity_pagetable(struct kvm *kvm)
2297 {
2298         struct kvm_userspace_memory_region kvm_userspace_mem;
2299         int r = 0;
2300
2301         mutex_lock(&kvm->slots_lock);
2302         if (kvm->arch.ept_identity_pagetable)
2303                 goto out;
2304         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2305         kvm_userspace_mem.flags = 0;
2306         kvm_userspace_mem.guest_phys_addr =
2307                 kvm->arch.ept_identity_map_addr;
2308         kvm_userspace_mem.memory_size = PAGE_SIZE;
2309         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2310         if (r)
2311                 goto out;
2312
2313         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2314                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2315 out:
2316         mutex_unlock(&kvm->slots_lock);
2317         return r;
2318 }
2319
2320 static void allocate_vpid(struct vcpu_vmx *vmx)
2321 {
2322         int vpid;
2323
2324         vmx->vpid = 0;
2325         if (!enable_vpid)
2326                 return;
2327         spin_lock(&vmx_vpid_lock);
2328         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2329         if (vpid < VMX_NR_VPIDS) {
2330                 vmx->vpid = vpid;
2331                 __set_bit(vpid, vmx_vpid_bitmap);
2332         }
2333         spin_unlock(&vmx_vpid_lock);
2334 }
2335
2336 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2337 {
2338         int f = sizeof(unsigned long);
2339
2340         if (!cpu_has_vmx_msr_bitmap())
2341                 return;
2342
2343         /*
2344          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2345          * have the write-low and read-high bitmap offsets the wrong way round.
2346          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2347          */
2348         if (msr <= 0x1fff) {
2349                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2350                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2351         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2352                 msr &= 0x1fff;
2353                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2354                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2355         }
2356 }
2357
2358 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2359 {
2360         if (!longmode_only)
2361                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2362         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2363 }
2364
2365 /*
2366  * Sets up the vmcs for emulated real mode.
2367  */
2368 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2369 {
2370         u32 host_sysenter_cs, msr_low, msr_high;
2371         u32 junk;
2372         u64 host_pat, tsc_this, tsc_base;
2373         unsigned long a;
2374         struct desc_ptr dt;
2375         int i;
2376         unsigned long kvm_vmx_return;
2377         u32 exec_control;
2378
2379         /* I/O */
2380         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2381         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2382
2383         if (cpu_has_vmx_msr_bitmap())
2384                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2385
2386         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2387
2388         /* Control */
2389         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2390                 vmcs_config.pin_based_exec_ctrl);
2391
2392         exec_control = vmcs_config.cpu_based_exec_ctrl;
2393         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2394                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2395 #ifdef CONFIG_X86_64
2396                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2397                                 CPU_BASED_CR8_LOAD_EXITING;
2398 #endif
2399         }
2400         if (!enable_ept)
2401                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2402                                 CPU_BASED_CR3_LOAD_EXITING  |
2403                                 CPU_BASED_INVLPG_EXITING;
2404         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2405
2406         if (cpu_has_secondary_exec_ctrls()) {
2407                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2408                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2409                         exec_control &=
2410                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2411                 if (vmx->vpid == 0)
2412                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2413                 if (!enable_ept) {
2414                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2415                         enable_unrestricted_guest = 0;
2416                 }
2417                 if (!enable_unrestricted_guest)
2418                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2419                 if (!ple_gap)
2420                         exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2421                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2422         }
2423
2424         if (ple_gap) {
2425                 vmcs_write32(PLE_GAP, ple_gap);
2426                 vmcs_write32(PLE_WINDOW, ple_window);
2427         }
2428
2429         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2430         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2431         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2432
2433         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
2434         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2435         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2436
2437         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2438         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2439         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2440         vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs());    /* 22.2.4 */
2441         vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs());    /* 22.2.4 */
2442         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2443 #ifdef CONFIG_X86_64
2444         rdmsrl(MSR_FS_BASE, a);
2445         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2446         rdmsrl(MSR_GS_BASE, a);
2447         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2448 #else
2449         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2450         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2451 #endif
2452
2453         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2454
2455         native_store_idt(&dt);
2456         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
2457
2458         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2459         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2460         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2461         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2462         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2463
2464         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2465         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2466         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2467         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2468         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2469         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2470
2471         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2472                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2473                 host_pat = msr_low | ((u64) msr_high << 32);
2474                 vmcs_write64(HOST_IA32_PAT, host_pat);
2475         }
2476         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2477                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2478                 host_pat = msr_low | ((u64) msr_high << 32);
2479                 /* Write the default value follow host pat */
2480                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2481                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2482                 vmx->vcpu.arch.pat = host_pat;
2483         }
2484
2485         for (i = 0; i < NR_VMX_MSR; ++i) {
2486                 u32 index = vmx_msr_index[i];
2487                 u32 data_low, data_high;
2488                 int j = vmx->nmsrs;
2489
2490                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2491                         continue;
2492                 if (wrmsr_safe(index, data_low, data_high) < 0)
2493                         continue;
2494                 vmx->guest_msrs[j].index = i;
2495                 vmx->guest_msrs[j].data = 0;
2496                 vmx->guest_msrs[j].mask = -1ull;
2497                 ++vmx->nmsrs;
2498         }
2499
2500         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2501
2502         /* 22.2.1, 20.8.1 */
2503         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2504
2505         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2506         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2507         if (enable_ept)
2508                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2509         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2510
2511         tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2512         rdtscll(tsc_this);
2513         if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2514                 tsc_base = tsc_this;
2515
2516         guest_write_tsc(0, tsc_base);
2517
2518         return 0;
2519 }
2520
2521 static int init_rmode(struct kvm *kvm)
2522 {
2523         if (!init_rmode_tss(kvm))
2524                 return 0;
2525         if (!init_rmode_identity_map(kvm))
2526                 return 0;
2527         return 1;
2528 }
2529
2530 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2531 {
2532         struct vcpu_vmx *vmx = to_vmx(vcpu);
2533         u64 msr;
2534         int ret, idx;
2535
2536         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2537         idx = srcu_read_lock(&vcpu->kvm->srcu);
2538         if (!init_rmode(vmx->vcpu.kvm)) {
2539                 ret = -ENOMEM;
2540                 goto out;
2541         }
2542
2543         vmx->rmode.vm86_active = 0;
2544
2545         vmx->soft_vnmi_blocked = 0;
2546
2547         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2548         kvm_set_cr8(&vmx->vcpu, 0);
2549         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2550         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2551                 msr |= MSR_IA32_APICBASE_BSP;
2552         kvm_set_apic_base(&vmx->vcpu, msr);
2553
2554         fx_init(&vmx->vcpu);
2555
2556         seg_setup(VCPU_SREG_CS);
2557         /*
2558          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2559          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2560          */
2561         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2562                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2563                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2564         } else {
2565                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2566                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2567         }
2568
2569         seg_setup(VCPU_SREG_DS);
2570         seg_setup(VCPU_SREG_ES);
2571         seg_setup(VCPU_SREG_FS);
2572         seg_setup(VCPU_SREG_GS);
2573         seg_setup(VCPU_SREG_SS);
2574
2575         vmcs_write16(GUEST_TR_SELECTOR, 0);
2576         vmcs_writel(GUEST_TR_BASE, 0);
2577         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2578         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2579
2580         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2581         vmcs_writel(GUEST_LDTR_BASE, 0);
2582         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2583         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2584
2585         vmcs_write32(GUEST_SYSENTER_CS, 0);
2586         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2587         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2588
2589         vmcs_writel(GUEST_RFLAGS, 0x02);
2590         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2591                 kvm_rip_write(vcpu, 0xfff0);
2592         else
2593                 kvm_rip_write(vcpu, 0);
2594         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2595
2596         vmcs_writel(GUEST_DR7, 0x400);
2597
2598         vmcs_writel(GUEST_GDTR_BASE, 0);
2599         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2600
2601         vmcs_writel(GUEST_IDTR_BASE, 0);
2602         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2603
2604         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2605         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2606         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2607
2608         /* Special registers */
2609         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2610
2611         setup_msrs(vmx);
2612
2613         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2614
2615         if (cpu_has_vmx_tpr_shadow()) {
2616                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2617                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2618                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2619                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2620                 vmcs_write32(TPR_THRESHOLD, 0);
2621         }
2622
2623         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2624                 vmcs_write64(APIC_ACCESS_ADDR,
2625                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2626
2627         if (vmx->vpid != 0)
2628                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2629
2630         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2631         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2632         vmx_set_cr4(&vmx->vcpu, 0);
2633         vmx_set_efer(&vmx->vcpu, 0);
2634         vmx_fpu_activate(&vmx->vcpu);
2635         update_exception_bitmap(&vmx->vcpu);
2636
2637         vpid_sync_vcpu_all(vmx);
2638
2639         ret = 0;
2640
2641         /* HACK: Don't enable emulation on guest boot/reset */
2642         vmx->emulation_required = 0;
2643
2644 out:
2645         srcu_read_unlock(&vcpu->kvm->srcu, idx);
2646         return ret;
2647 }
2648
2649 static void enable_irq_window(struct kvm_vcpu *vcpu)
2650 {
2651         u32 cpu_based_vm_exec_control;
2652
2653         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2654         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2655         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2656 }
2657
2658 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2659 {
2660         u32 cpu_based_vm_exec_control;
2661
2662         if (!cpu_has_virtual_nmis()) {
2663                 enable_irq_window(vcpu);
2664                 return;
2665         }
2666
2667         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2668         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2669         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2670 }
2671
2672 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2673 {
2674         struct vcpu_vmx *vmx = to_vmx(vcpu);
2675         uint32_t intr;
2676         int irq = vcpu->arch.interrupt.nr;
2677
2678         trace_kvm_inj_virq(irq);
2679
2680         ++vcpu->stat.irq_injections;
2681         if (vmx->rmode.vm86_active) {
2682                 vmx->rmode.irq.pending = true;
2683                 vmx->rmode.irq.vector = irq;
2684                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2685                 if (vcpu->arch.interrupt.soft)
2686                         vmx->rmode.irq.rip +=
2687                                 vmx->vcpu.arch.event_exit_inst_len;
2688                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2689                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2690                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2691                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2692                 return;
2693         }
2694         intr = irq | INTR_INFO_VALID_MASK;
2695         if (vcpu->arch.interrupt.soft) {
2696                 intr |= INTR_TYPE_SOFT_INTR;
2697                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2698                              vmx->vcpu.arch.event_exit_inst_len);
2699         } else
2700                 intr |= INTR_TYPE_EXT_INTR;
2701         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2702 }
2703
2704 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2705 {
2706         struct vcpu_vmx *vmx = to_vmx(vcpu);
2707
2708         if (!cpu_has_virtual_nmis()) {
2709                 /*
2710                  * Tracking the NMI-blocked state in software is built upon
2711                  * finding the next open IRQ window. This, in turn, depends on
2712                  * well-behaving guests: They have to keep IRQs disabled at
2713                  * least as long as the NMI handler runs. Otherwise we may
2714                  * cause NMI nesting, maybe breaking the guest. But as this is
2715                  * highly unlikely, we can live with the residual risk.
2716                  */
2717                 vmx->soft_vnmi_blocked = 1;
2718                 vmx->vnmi_blocked_time = 0;
2719         }
2720
2721         ++vcpu->stat.nmi_injections;
2722         if (vmx->rmode.vm86_active) {
2723                 vmx->rmode.irq.pending = true;
2724                 vmx->rmode.irq.vector = NMI_VECTOR;
2725                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2726                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2727                              NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2728                              INTR_INFO_VALID_MASK);
2729                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2730                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2731                 return;
2732         }
2733         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2734                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2735 }
2736
2737 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2738 {
2739         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2740                 return 0;
2741
2742         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2743                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2744                                 GUEST_INTR_STATE_NMI));
2745 }
2746
2747 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2748 {
2749         if (!cpu_has_virtual_nmis())
2750                 return to_vmx(vcpu)->soft_vnmi_blocked;
2751         else
2752                 return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2753                           GUEST_INTR_STATE_NMI);
2754 }
2755
2756 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2757 {
2758         struct vcpu_vmx *vmx = to_vmx(vcpu);
2759
2760         if (!cpu_has_virtual_nmis()) {
2761                 if (vmx->soft_vnmi_blocked != masked) {
2762                         vmx->soft_vnmi_blocked = masked;
2763                         vmx->vnmi_blocked_time = 0;
2764                 }
2765         } else {
2766                 if (masked)
2767                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2768                                       GUEST_INTR_STATE_NMI);
2769                 else
2770                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2771                                         GUEST_INTR_STATE_NMI);
2772         }
2773 }
2774
2775 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2776 {
2777         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2778                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2779                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2780 }
2781
2782 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2783 {
2784         int ret;
2785         struct kvm_userspace_memory_region tss_mem = {
2786                 .slot = TSS_PRIVATE_MEMSLOT,
2787                 .guest_phys_addr = addr,
2788                 .memory_size = PAGE_SIZE * 3,
2789                 .flags = 0,
2790         };
2791
2792         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2793         if (ret)
2794                 return ret;
2795         kvm->arch.tss_addr = addr;
2796         return 0;
2797 }
2798
2799 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2800                                   int vec, u32 err_code)
2801 {
2802         /*
2803          * Instruction with address size override prefix opcode 0x67
2804          * Cause the #SS fault with 0 error code in VM86 mode.
2805          */
2806         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2807                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2808                         return 1;
2809         /*
2810          * Forward all other exceptions that are valid in real mode.
2811          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2812          *        the required debugging infrastructure rework.
2813          */
2814         switch (vec) {
2815         case DB_VECTOR:
2816                 if (vcpu->guest_debug &
2817                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2818                         return 0;
2819                 kvm_queue_exception(vcpu, vec);
2820                 return 1;
2821         case BP_VECTOR:
2822                 /*
2823                  * Update instruction length as we may reinject the exception
2824                  * from user space while in guest debugging mode.
2825                  */
2826                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2827                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2828                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2829                         return 0;
2830                 /* fall through */
2831         case DE_VECTOR:
2832         case OF_VECTOR:
2833         case BR_VECTOR:
2834         case UD_VECTOR:
2835         case DF_VECTOR:
2836         case SS_VECTOR:
2837         case GP_VECTOR:
2838         case MF_VECTOR:
2839                 kvm_queue_exception(vcpu, vec);
2840                 return 1;
2841         }
2842         return 0;
2843 }
2844
2845 /*
2846  * Trigger machine check on the host. We assume all the MSRs are already set up
2847  * by the CPU and that we still run on the same CPU as the MCE occurred on.
2848  * We pass a fake environment to the machine check handler because we want
2849  * the guest to be always treated like user space, no matter what context
2850  * it used internally.
2851  */
2852 static void kvm_machine_check(void)
2853 {
2854 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2855         struct pt_regs regs = {
2856                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2857                 .flags = X86_EFLAGS_IF,
2858         };
2859
2860         do_machine_check(&regs, 0);
2861 #endif
2862 }
2863
2864 static int handle_machine_check(struct kvm_vcpu *vcpu)
2865 {
2866         /* already handled by vcpu_run */
2867         return 1;
2868 }
2869
2870 static int handle_exception(struct kvm_vcpu *vcpu)
2871 {
2872         struct vcpu_vmx *vmx = to_vmx(vcpu);
2873         struct kvm_run *kvm_run = vcpu->run;
2874         u32 intr_info, ex_no, error_code;
2875         unsigned long cr2, rip, dr6;
2876         u32 vect_info;
2877         enum emulation_result er;
2878
2879         vect_info = vmx->idt_vectoring_info;
2880         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2881
2882         if (is_machine_check(intr_info))
2883                 return handle_machine_check(vcpu);
2884
2885         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2886             !is_page_fault(intr_info)) {
2887                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2888                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2889                 vcpu->run->internal.ndata = 2;
2890                 vcpu->run->internal.data[0] = vect_info;
2891                 vcpu->run->internal.data[1] = intr_info;
2892                 return 0;
2893         }
2894
2895         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2896                 return 1;  /* already handled by vmx_vcpu_run() */
2897
2898         if (is_no_device(intr_info)) {
2899                 vmx_fpu_activate(vcpu);
2900                 return 1;
2901         }
2902
2903         if (is_invalid_opcode(intr_info)) {
2904                 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
2905                 if (er != EMULATE_DONE)
2906                         kvm_queue_exception(vcpu, UD_VECTOR);
2907                 return 1;
2908         }
2909
2910         error_code = 0;
2911         rip = kvm_rip_read(vcpu);
2912         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2913                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2914         if (is_page_fault(intr_info)) {
2915                 /* EPT won't cause page fault directly */
2916                 if (enable_ept)
2917                         BUG();
2918                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2919                 trace_kvm_page_fault(cr2, error_code);
2920
2921                 if (kvm_event_needs_reinjection(vcpu))
2922                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
2923                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2924         }
2925
2926         if (vmx->rmode.vm86_active &&
2927             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2928                                                                 error_code)) {
2929                 if (vcpu->arch.halt_request) {
2930                         vcpu->arch.halt_request = 0;
2931                         return kvm_emulate_halt(vcpu);
2932                 }
2933                 return 1;
2934         }
2935
2936         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2937         switch (ex_no) {
2938         case DB_VECTOR:
2939                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2940                 if (!(vcpu->guest_debug &
2941                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2942                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2943                         kvm_queue_exception(vcpu, DB_VECTOR);
2944                         return 1;
2945                 }
2946                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2947                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2948                 /* fall through */
2949         case BP_VECTOR:
2950                 /*
2951                  * Update instruction length as we may reinject #BP from
2952                  * user space while in guest debugging mode. Reading it for
2953                  * #DB as well causes no harm, it is not used in that case.
2954                  */
2955                 vmx->vcpu.arch.event_exit_inst_len =
2956                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2957                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2958                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2959                 kvm_run->debug.arch.exception = ex_no;
2960                 break;
2961         default:
2962                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2963                 kvm_run->ex.exception = ex_no;
2964                 kvm_run->ex.error_code = error_code;
2965                 break;
2966         }
2967         return 0;
2968 }
2969
2970 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
2971 {
2972         ++vcpu->stat.irq_exits;
2973         return 1;
2974 }
2975
2976 static int handle_triple_fault(struct kvm_vcpu *vcpu)
2977 {
2978         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
2979         return 0;
2980 }
2981
2982 static int handle_io(struct kvm_vcpu *vcpu)
2983 {
2984         unsigned long exit_qualification;
2985         int size, in, string;
2986         unsigned port;
2987
2988         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2989         string = (exit_qualification & 16) != 0;
2990         in = (exit_qualification & 8) != 0;
2991
2992         ++vcpu->stat.io_exits;
2993
2994         if (string || in)
2995                 return !(emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO);
2996
2997         port = exit_qualification >> 16;
2998         size = (exit_qualification & 7) + 1;
2999         skip_emulated_instruction(vcpu);
3000
3001         return kvm_fast_pio_out(vcpu, size, port);
3002 }
3003
3004 static void
3005 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3006 {
3007         /*
3008          * Patch in the VMCALL instruction:
3009          */
3010         hypercall[0] = 0x0f;
3011         hypercall[1] = 0x01;
3012         hypercall[2] = 0xc1;
3013 }
3014
3015 static int handle_cr(struct kvm_vcpu *vcpu)
3016 {
3017         unsigned long exit_qualification, val;
3018         int cr;
3019         int reg;
3020
3021         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3022         cr = exit_qualification & 15;
3023         reg = (exit_qualification >> 8) & 15;
3024         switch ((exit_qualification >> 4) & 3) {
3025         case 0: /* mov to cr */
3026                 val = kvm_register_read(vcpu, reg);
3027                 trace_kvm_cr_write(cr, val);
3028                 switch (cr) {
3029                 case 0:
3030                         kvm_set_cr0(vcpu, val);
3031                         skip_emulated_instruction(vcpu);
3032                         return 1;
3033                 case 3:
3034                         kvm_set_cr3(vcpu, val);
3035                         skip_emulated_instruction(vcpu);
3036                         return 1;
3037                 case 4:
3038                         kvm_set_cr4(vcpu, val);
3039                         skip_emulated_instruction(vcpu);
3040                         return 1;
3041                 case 8: {
3042                                 u8 cr8_prev = kvm_get_cr8(vcpu);
3043                                 u8 cr8 = kvm_register_read(vcpu, reg);
3044                                 kvm_set_cr8(vcpu, cr8);
3045                                 skip_emulated_instruction(vcpu);
3046                                 if (irqchip_in_kernel(vcpu->kvm))
3047                                         return 1;
3048                                 if (cr8_prev <= cr8)
3049                                         return 1;
3050                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3051                                 return 0;
3052                         }
3053                 };
3054                 break;
3055         case 2: /* clts */
3056                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3057                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3058                 skip_emulated_instruction(vcpu);
3059                 vmx_fpu_activate(vcpu);
3060                 return 1;
3061         case 1: /*mov from cr*/
3062                 switch (cr) {
3063                 case 3:
3064                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
3065                         trace_kvm_cr_read(cr, vcpu->arch.cr3);
3066                         skip_emulated_instruction(vcpu);
3067                         return 1;
3068                 case 8:
3069                         val = kvm_get_cr8(vcpu);
3070                         kvm_register_write(vcpu, reg, val);
3071                         trace_kvm_cr_read(cr, val);
3072                         skip_emulated_instruction(vcpu);
3073                         return 1;
3074                 }
3075                 break;
3076         case 3: /* lmsw */
3077                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3078                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3079                 kvm_lmsw(vcpu, val);
3080
3081                 skip_emulated_instruction(vcpu);
3082                 return 1;
3083         default:
3084                 break;
3085         }
3086         vcpu->run->exit_reason = 0;
3087         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3088                (int)(exit_qualification >> 4) & 3, cr);
3089         return 0;
3090 }
3091
3092 static int handle_dr(struct kvm_vcpu *vcpu)
3093 {
3094         unsigned long exit_qualification;
3095         int dr, reg;
3096
3097         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3098         if (!kvm_require_cpl(vcpu, 0))
3099                 return 1;
3100         dr = vmcs_readl(GUEST_DR7);
3101         if (dr & DR7_GD) {
3102                 /*
3103                  * As the vm-exit takes precedence over the debug trap, we
3104                  * need to emulate the latter, either for the host or the
3105                  * guest debugging itself.
3106                  */
3107                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3108                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3109                         vcpu->run->debug.arch.dr7 = dr;
3110                         vcpu->run->debug.arch.pc =
3111                                 vmcs_readl(GUEST_CS_BASE) +
3112                                 vmcs_readl(GUEST_RIP);
3113                         vcpu->run->debug.arch.exception = DB_VECTOR;
3114                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3115                         return 0;
3116                 } else {
3117                         vcpu->arch.dr7 &= ~DR7_GD;
3118                         vcpu->arch.dr6 |= DR6_BD;
3119                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3120                         kvm_queue_exception(vcpu, DB_VECTOR);
3121                         return 1;
3122                 }
3123         }
3124
3125         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3126         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3127         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3128         if (exit_qualification & TYPE_MOV_FROM_DR) {
3129                 unsigned long val;
3130                 if (!kvm_get_dr(vcpu, dr, &val))
3131                         kvm_register_write(vcpu, reg, val);
3132         } else
3133                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3134         skip_emulated_instruction(vcpu);
3135         return 1;
3136 }
3137
3138 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3139 {
3140         vmcs_writel(GUEST_DR7, val);
3141 }
3142
3143 static int handle_cpuid(struct kvm_vcpu *vcpu)
3144 {
3145         kvm_emulate_cpuid(vcpu);
3146         return 1;
3147 }
3148
3149 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3150 {
3151         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3152         u64 data;
3153
3154         if (vmx_get_msr(vcpu, ecx, &data)) {
3155                 trace_kvm_msr_read_ex(ecx);
3156                 kvm_inject_gp(vcpu, 0);
3157                 return 1;
3158         }
3159
3160         trace_kvm_msr_read(ecx, data);
3161
3162         /* FIXME: handling of bits 32:63 of rax, rdx */
3163         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3164         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3165         skip_emulated_instruction(vcpu);
3166         return 1;
3167 }
3168
3169 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3170 {
3171         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3172         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3173                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3174
3175         if (vmx_set_msr(vcpu, ecx, data) != 0) {
3176                 trace_kvm_msr_write_ex(ecx, data);
3177                 kvm_inject_gp(vcpu, 0);
3178                 return 1;
3179         }
3180
3181         trace_kvm_msr_write(ecx, data);
3182         skip_emulated_instruction(vcpu);
3183         return 1;
3184 }
3185
3186 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3187 {
3188         return 1;
3189 }
3190
3191 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3192 {
3193         u32 cpu_based_vm_exec_control;
3194
3195         /* clear pending irq */
3196         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3197         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3198         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3199
3200         ++vcpu->stat.irq_window_exits;
3201
3202         /*
3203          * If the user space waits to inject interrupts, exit as soon as
3204          * possible
3205          */
3206         if (!irqchip_in_kernel(vcpu->kvm) &&
3207             vcpu->run->request_interrupt_window &&
3208             !kvm_cpu_has_interrupt(vcpu)) {
3209                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3210                 return 0;
3211         }
3212         return 1;
3213 }
3214
3215 static int handle_halt(struct kvm_vcpu *vcpu)
3216 {
3217         skip_emulated_instruction(vcpu);
3218         return kvm_emulate_halt(vcpu);
3219 }
3220
3221 static int handle_vmcall(struct kvm_vcpu *vcpu)
3222 {
3223         skip_emulated_instruction(vcpu);
3224         kvm_emulate_hypercall(vcpu);
3225         return 1;
3226 }
3227
3228 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3229 {
3230         kvm_queue_exception(vcpu, UD_VECTOR);
3231         return 1;
3232 }
3233
3234 static int handle_invlpg(struct kvm_vcpu *vcpu)
3235 {
3236         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3237
3238         kvm_mmu_invlpg(vcpu, exit_qualification);
3239         skip_emulated_instruction(vcpu);
3240         return 1;
3241 }
3242
3243 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3244 {
3245         skip_emulated_instruction(vcpu);
3246         /* TODO: Add support for VT-d/pass-through device */
3247         return 1;
3248 }
3249
3250 static int handle_apic_access(struct kvm_vcpu *vcpu)
3251 {
3252         unsigned long exit_qualification;
3253         enum emulation_result er;
3254         unsigned long offset;
3255
3256         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3257         offset = exit_qualification & 0xffful;
3258
3259         er = emulate_instruction(vcpu, 0, 0, 0);
3260
3261         if (er !=  EMULATE_DONE) {
3262                 printk(KERN_ERR
3263                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3264                        offset);
3265                 return -ENOEXEC;
3266         }
3267         return 1;
3268 }
3269
3270 static int handle_task_switch(struct kvm_vcpu *vcpu)
3271 {
3272         struct vcpu_vmx *vmx = to_vmx(vcpu);
3273         unsigned long exit_qualification;
3274         u16 tss_selector;
3275         int reason, type, idt_v;
3276
3277         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3278         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3279
3280         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3281
3282         reason = (u32)exit_qualification >> 30;
3283         if (reason == TASK_SWITCH_GATE && idt_v) {
3284                 switch (type) {
3285                 case INTR_TYPE_NMI_INTR:
3286                         vcpu->arch.nmi_injected = false;
3287                         if (cpu_has_virtual_nmis())
3288                                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3289                                               GUEST_INTR_STATE_NMI);
3290                         break;
3291                 case INTR_TYPE_EXT_INTR:
3292                 case INTR_TYPE_SOFT_INTR:
3293                         kvm_clear_interrupt_queue(vcpu);
3294                         break;
3295                 case INTR_TYPE_HARD_EXCEPTION:
3296                 case INTR_TYPE_SOFT_EXCEPTION:
3297                         kvm_clear_exception_queue(vcpu);
3298                         break;
3299                 default:
3300                         break;
3301                 }
3302         }
3303         tss_selector = exit_qualification;
3304
3305         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3306                        type != INTR_TYPE_EXT_INTR &&
3307                        type != INTR_TYPE_NMI_INTR))
3308                 skip_emulated_instruction(vcpu);
3309
3310         if (!kvm_task_switch(vcpu, tss_selector, reason))
3311                 return 0;
3312
3313         /* clear all local breakpoint enable flags */
3314         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3315
3316         /*
3317          * TODO: What about debug traps on tss switch?
3318          *       Are we supposed to inject them and update dr6?
3319          */
3320
3321         return 1;
3322 }
3323
3324 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3325 {
3326         unsigned long exit_qualification;
3327         gpa_t gpa;
3328         int gla_validity;
3329
3330         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3331
3332         if (exit_qualification & (1 << 6)) {
3333                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3334                 return -EINVAL;
3335         }
3336
3337         gla_validity = (exit_qualification >> 7) & 0x3;
3338         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3339                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3340                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3341                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3342                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3343                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3344                         (long unsigned int)exit_qualification);
3345                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3346                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3347                 return 0;
3348         }
3349
3350         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3351         trace_kvm_page_fault(gpa, exit_qualification);
3352         return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3353 }
3354
3355 static u64 ept_rsvd_mask(u64 spte, int level)
3356 {
3357         int i;
3358         u64 mask = 0;
3359
3360         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3361                 mask |= (1ULL << i);
3362
3363         if (level > 2)
3364                 /* bits 7:3 reserved */
3365                 mask |= 0xf8;
3366         else if (level == 2) {
3367                 if (spte & (1ULL << 7))
3368                         /* 2MB ref, bits 20:12 reserved */
3369                         mask |= 0x1ff000;
3370                 else
3371                         /* bits 6:3 reserved */
3372                         mask |= 0x78;
3373         }
3374
3375         return mask;
3376 }
3377
3378 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3379                                        int level)
3380 {
3381         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3382
3383         /* 010b (write-only) */
3384         WARN_ON((spte & 0x7) == 0x2);
3385
3386         /* 110b (write/execute) */
3387         WARN_ON((spte & 0x7) == 0x6);
3388
3389         /* 100b (execute-only) and value not supported by logical processor */
3390         if (!cpu_has_vmx_ept_execute_only())
3391                 WARN_ON((spte & 0x7) == 0x4);
3392
3393         /* not 000b */
3394         if ((spte & 0x7)) {
3395                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3396
3397                 if (rsvd_bits != 0) {
3398                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3399                                          __func__, rsvd_bits);
3400                         WARN_ON(1);
3401                 }
3402
3403                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3404                         u64 ept_mem_type = (spte & 0x38) >> 3;
3405
3406                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
3407                             ept_mem_type == 7) {
3408                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3409                                                 __func__, ept_mem_type);
3410                                 WARN_ON(1);
3411                         }
3412                 }
3413         }
3414 }
3415
3416 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3417 {
3418         u64 sptes[4];
3419         int nr_sptes, i;
3420         gpa_t gpa;
3421
3422         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3423
3424         printk(KERN_ERR "EPT: Misconfiguration.\n");
3425         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3426
3427         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3428
3429         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3430                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3431
3432         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3433         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3434
3435         return 0;
3436 }
3437
3438 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3439 {
3440         u32 cpu_based_vm_exec_control;
3441
3442         /* clear pending NMI */
3443         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3444         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3445         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3446         ++vcpu->stat.nmi_window_exits;
3447
3448         return 1;
3449 }
3450
3451 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3452 {
3453         struct vcpu_vmx *vmx = to_vmx(vcpu);
3454         enum emulation_result err = EMULATE_DONE;
3455         int ret = 1;
3456
3457         while (!guest_state_valid(vcpu)) {
3458                 err = emulate_instruction(vcpu, 0, 0, 0);
3459
3460                 if (err == EMULATE_DO_MMIO) {
3461                         ret = 0;
3462                         goto out;
3463                 }
3464
3465                 if (err != EMULATE_DONE) {
3466                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3467                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3468                         vcpu->run->internal.ndata = 0;
3469                         ret = 0;
3470                         goto out;
3471                 }
3472
3473                 if (signal_pending(current))
3474                         goto out;
3475                 if (need_resched())
3476                         schedule();
3477         }
3478
3479         vmx->emulation_required = 0;
3480 out:
3481         return ret;
3482 }
3483
3484 /*
3485  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3486  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3487  */
3488 static int handle_pause(struct kvm_vcpu *vcpu)
3489 {
3490         skip_emulated_instruction(vcpu);
3491         kvm_vcpu_on_spin(vcpu);
3492
3493         return 1;
3494 }
3495
3496 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3497 {
3498         kvm_queue_exception(vcpu, UD_VECTOR);
3499         return 1;
3500 }
3501
3502 /*
3503  * The exit handlers return 1 if the exit was handled fully and guest execution
3504  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3505  * to be done to userspace and return 0.
3506  */
3507 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3508         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3509         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3510         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3511         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3512         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3513         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3514         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3515         [EXIT_REASON_CPUID]                   = handle_cpuid,
3516         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3517         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3518         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3519         [EXIT_REASON_HLT]                     = handle_halt,
3520         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3521         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3522         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
3523         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
3524         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
3525         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
3526         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
3527         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
3528         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
3529         [EXIT_REASON_VMOFF]                   = handle_vmx_insn,
3530         [EXIT_REASON_VMON]                    = handle_vmx_insn,
3531         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3532         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3533         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3534         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3535         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
3536         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3537         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
3538         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
3539         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
3540         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
3541 };
3542
3543 static const int kvm_vmx_max_exit_handlers =
3544         ARRAY_SIZE(kvm_vmx_exit_handlers);
3545
3546 /*
3547  * The guest has exited.  See if we can fix it or if we need userspace
3548  * assistance.
3549  */
3550 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3551 {
3552         struct vcpu_vmx *vmx = to_vmx(vcpu);
3553         u32 exit_reason = vmx->exit_reason;
3554         u32 vectoring_info = vmx->idt_vectoring_info;
3555
3556         trace_kvm_exit(exit_reason, vcpu);
3557
3558         /* If guest state is invalid, start emulating */
3559         if (vmx->emulation_required && emulate_invalid_guest_state)
3560                 return handle_invalid_guest_state(vcpu);
3561
3562         /* Access CR3 don't cause VMExit in paging mode, so we need
3563          * to sync with guest real CR3. */
3564         if (enable_ept && is_paging(vcpu))
3565                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3566
3567         if (unlikely(vmx->fail)) {
3568                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3569                 vcpu->run->fail_entry.hardware_entry_failure_reason
3570                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3571                 return 0;
3572         }
3573
3574         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3575                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3576                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3577                         exit_reason != EXIT_REASON_TASK_SWITCH))
3578                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3579                        "(0x%x) and exit reason is 0x%x\n",
3580                        __func__, vectoring_info, exit_reason);
3581
3582         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3583                 if (vmx_interrupt_allowed(vcpu)) {
3584                         vmx->soft_vnmi_blocked = 0;
3585                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3586                            vcpu->arch.nmi_pending) {
3587                         /*
3588                          * This CPU don't support us in finding the end of an
3589                          * NMI-blocked window if the guest runs with IRQs
3590                          * disabled. So we pull the trigger after 1 s of
3591                          * futile waiting, but inform the user about this.
3592                          */
3593                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3594                                "state on VCPU %d after 1 s timeout\n",
3595                                __func__, vcpu->vcpu_id);
3596                         vmx->soft_vnmi_blocked = 0;
3597                 }
3598         }
3599
3600         if (exit_reason < kvm_vmx_max_exit_handlers
3601             && kvm_vmx_exit_handlers[exit_reason])
3602                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3603         else {
3604                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3605                 vcpu->run->hw.hardware_exit_reason = exit_reason;
3606         }
3607         return 0;
3608 }
3609
3610 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3611 {
3612         if (irr == -1 || tpr < irr) {
3613                 vmcs_write32(TPR_THRESHOLD, 0);
3614                 return;
3615         }
3616
3617         vmcs_write32(TPR_THRESHOLD, irr);
3618 }
3619
3620 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3621 {
3622         u32 exit_intr_info;
3623         u32 idt_vectoring_info = vmx->idt_vectoring_info;
3624         bool unblock_nmi;
3625         u8 vector;
3626         int type;
3627         bool idtv_info_valid;
3628
3629         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3630
3631         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3632
3633         /* Handle machine checks before interrupts are enabled */
3634         if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3635             || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3636                 && is_machine_check(exit_intr_info)))
3637                 kvm_machine_check();
3638
3639         /* We need to handle NMIs before interrupts are enabled */
3640         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3641             (exit_intr_info & INTR_INFO_VALID_MASK))
3642                 asm("int $2");
3643
3644         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3645
3646         if (cpu_has_virtual_nmis()) {
3647                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3648                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3649                 /*
3650                  * SDM 3: 27.7.1.2 (September 2008)
3651                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3652                  * a guest IRET fault.
3653                  * SDM 3: 23.2.2 (September 2008)
3654                  * Bit 12 is undefined in any of the following cases:
3655                  *  If the VM exit sets the valid bit in the IDT-vectoring
3656                  *   information field.
3657                  *  If the VM exit is due to a double fault.
3658                  */
3659                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3660                     vector != DF_VECTOR && !idtv_info_valid)
3661                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3662                                       GUEST_INTR_STATE_NMI);
3663         } else if (unlikely(vmx->soft_vnmi_blocked))
3664                 vmx->vnmi_blocked_time +=
3665                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3666
3667         vmx->vcpu.arch.nmi_injected = false;
3668         kvm_clear_exception_queue(&vmx->vcpu);
3669         kvm_clear_interrupt_queue(&vmx->vcpu);
3670
3671         if (!idtv_info_valid)
3672                 return;
3673
3674         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3675         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3676
3677         switch (type) {
3678         case INTR_TYPE_NMI_INTR:
3679                 vmx->vcpu.arch.nmi_injected = true;
3680                 /*
3681                  * SDM 3: 27.7.1.2 (September 2008)
3682                  * Clear bit "block by NMI" before VM entry if a NMI
3683                  * delivery faulted.
3684                  */
3685                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3686                                 GUEST_INTR_STATE_NMI);
3687                 break;
3688         case INTR_TYPE_SOFT_EXCEPTION:
3689                 vmx->vcpu.arch.event_exit_inst_len =
3690                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3691                 /* fall through */
3692         case INTR_TYPE_HARD_EXCEPTION:
3693                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3694                         u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3695                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
3696                 } else
3697                         kvm_queue_exception(&vmx->vcpu, vector);
3698                 break;
3699         case INTR_TYPE_SOFT_INTR:
3700                 vmx->vcpu.arch.event_exit_inst_len =
3701                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3702                 /* fall through */
3703         case INTR_TYPE_EXT_INTR:
3704                 kvm_queue_interrupt(&vmx->vcpu, vector,
3705                         type == INTR_TYPE_SOFT_INTR);
3706                 break;
3707         default:
3708                 break;
3709         }
3710 }
3711
3712 /*
3713  * Failure to inject an interrupt should give us the information
3714  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3715  * when fetching the interrupt redirection bitmap in the real-mode
3716  * tss, this doesn't happen.  So we do it ourselves.
3717  */
3718 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3719 {
3720         vmx->rmode.irq.pending = 0;
3721         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3722                 return;
3723         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3724         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3725                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3726                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3727                 return;
3728         }
3729         vmx->idt_vectoring_info =
3730                 VECTORING_INFO_VALID_MASK
3731                 | INTR_TYPE_EXT_INTR
3732                 | vmx->rmode.irq.vector;
3733 }
3734
3735 #ifdef CONFIG_X86_64
3736 #define R "r"
3737 #define Q "q"
3738 #else
3739 #define R "e"
3740 #define Q "l"
3741 #endif
3742
3743 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3744 {
3745         struct vcpu_vmx *vmx = to_vmx(vcpu);
3746
3747         /* Record the guest's net vcpu time for enforced NMI injections. */
3748         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3749                 vmx->entry_time = ktime_get();
3750
3751         /* Don't enter VMX if guest state is invalid, let the exit handler
3752            start emulation until we arrive back to a valid state */
3753         if (vmx->emulation_required && emulate_invalid_guest_state)
3754                 return;
3755
3756         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3757                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3758         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3759                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3760
3761         /* When single-stepping over STI and MOV SS, we must clear the
3762          * corresponding interruptibility bits in the guest state. Otherwise
3763          * vmentry fails as it then expects bit 14 (BS) in pending debug
3764          * exceptions being set, but that's not correct for the guest debugging
3765          * case. */
3766         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3767                 vmx_set_interrupt_shadow(vcpu, 0);
3768
3769         /*
3770          * Loading guest fpu may have cleared host cr0.ts
3771          */
3772         vmcs_writel(HOST_CR0, read_cr0());
3773
3774         asm(
3775                 /* Store host registers */
3776                 "push %%"R"dx; push %%"R"bp;"
3777                 "push %%"R"cx \n\t"
3778                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3779                 "je 1f \n\t"
3780                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3781                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3782                 "1: \n\t"
3783                 /* Reload cr2 if changed */
3784                 "mov %c[cr2](%0), %%"R"ax \n\t"
3785                 "mov %%cr2, %%"R"dx \n\t"
3786                 "cmp %%"R"ax, %%"R"dx \n\t"
3787                 "je 2f \n\t"
3788                 "mov %%"R"ax, %%cr2 \n\t"
3789                 "2: \n\t"
3790                 /* Check if vmlaunch of vmresume is needed */
3791                 "cmpl $0, %c[launched](%0) \n\t"
3792                 /* Load guest registers.  Don't clobber flags. */
3793                 "mov %c[rax](%0), %%"R"ax \n\t"
3794                 "mov %c[rbx](%0), %%"R"bx \n\t"
3795                 "mov %c[rdx](%0), %%"R"dx \n\t"
3796                 "mov %c[rsi](%0), %%"R"si \n\t"
3797                 "mov %c[rdi](%0), %%"R"di \n\t"
3798                 "mov %c[rbp](%0), %%"R"bp \n\t"
3799 #ifdef CONFIG_X86_64
3800                 "mov %c[r8](%0),  %%r8  \n\t"
3801                 "mov %c[r9](%0),  %%r9  \n\t"
3802                 "mov %c[r10](%0), %%r10 \n\t"
3803                 "mov %c[r11](%0), %%r11 \n\t"
3804                 "mov %c[r12](%0), %%r12 \n\t"
3805                 "mov %c[r13](%0), %%r13 \n\t"
3806                 "mov %c[r14](%0), %%r14 \n\t"
3807                 "mov %c[r15](%0), %%r15 \n\t"
3808 #endif
3809                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3810
3811                 /* Enter guest mode */
3812                 "jne .Llaunched \n\t"
3813                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3814                 "jmp .Lkvm_vmx_return \n\t"
3815                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3816                 ".Lkvm_vmx_return: "
3817                 /* Save guest registers, load host registers, keep flags */
3818                 "xchg %0,     (%%"R"sp) \n\t"
3819                 "mov %%"R"ax, %c[rax](%0) \n\t"
3820                 "mov %%"R"bx, %c[rbx](%0) \n\t"
3821                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3822                 "mov %%"R"dx, %c[rdx](%0) \n\t"
3823                 "mov %%"R"si, %c[rsi](%0) \n\t"
3824                 "mov %%"R"di, %c[rdi](%0) \n\t"
3825                 "mov %%"R"bp, %c[rbp](%0) \n\t"
3826 #ifdef CONFIG_X86_64
3827                 "mov %%r8,  %c[r8](%0) \n\t"
3828                 "mov %%r9,  %c[r9](%0) \n\t"
3829                 "mov %%r10, %c[r10](%0) \n\t"
3830                 "mov %%r11, %c[r11](%0) \n\t"
3831                 "mov %%r12, %c[r12](%0) \n\t"
3832                 "mov %%r13, %c[r13](%0) \n\t"
3833                 "mov %%r14, %c[r14](%0) \n\t"
3834                 "mov %%r15, %c[r15](%0) \n\t"
3835 #endif
3836                 "mov %%cr2, %%"R"ax   \n\t"
3837                 "mov %%"R"ax, %c[cr2](%0) \n\t"
3838
3839                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
3840                 "setbe %c[fail](%0) \n\t"
3841               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3842                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3843                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3844                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3845                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3846                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3847                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3848                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3849                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3850                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3851                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3852 #ifdef CONFIG_X86_64
3853                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3854                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3855                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3856                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3857                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3858                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3859                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3860                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3861 #endif
3862                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3863               : "cc", "memory"
3864                 , R"bx", R"di", R"si"
3865 #ifdef CONFIG_X86_64
3866                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3867 #endif
3868               );
3869
3870         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3871                                   | (1 << VCPU_EXREG_PDPTR));
3872         vcpu->arch.regs_dirty = 0;
3873
3874         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3875         if (vmx->rmode.irq.pending)
3876                 fixup_rmode_irq(vmx);
3877
3878         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3879         vmx->launched = 1;
3880
3881         vmx_complete_interrupts(vmx);
3882 }
3883
3884 #undef R
3885 #undef Q
3886
3887 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3888 {
3889         struct vcpu_vmx *vmx = to_vmx(vcpu);
3890
3891         if (vmx->vmcs) {
3892                 vcpu_clear(vmx);
3893                 free_vmcs(vmx->vmcs);
3894                 vmx->vmcs = NULL;
3895         }
3896 }
3897
3898 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3899 {
3900         struct vcpu_vmx *vmx = to_vmx(vcpu);
3901
3902         spin_lock(&vmx_vpid_lock);
3903         if (vmx->vpid != 0)
3904                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3905         spin_unlock(&vmx_vpid_lock);
3906         vmx_free_vmcs(vcpu);
3907         kfree(vmx->guest_msrs);
3908         kvm_vcpu_uninit(vcpu);
3909         kmem_cache_free(kvm_vcpu_cache, vmx);
3910 }
3911
3912 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3913 {
3914         int err;
3915         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3916         int cpu;
3917
3918         if (!vmx)
3919                 return ERR_PTR(-ENOMEM);
3920
3921         allocate_vpid(vmx);
3922
3923         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3924         if (err)
3925                 goto free_vcpu;
3926
3927         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3928         if (!vmx->guest_msrs) {
3929                 err = -ENOMEM;
3930                 goto uninit_vcpu;
3931         }
3932
3933         vmx->vmcs = alloc_vmcs();
3934         if (!vmx->vmcs)
3935                 goto free_msrs;
3936
3937         vmcs_clear(vmx->vmcs);
3938
3939         cpu = get_cpu();
3940         vmx_vcpu_load(&vmx->vcpu, cpu);
3941         err = vmx_vcpu_setup(vmx);
3942         vmx_vcpu_put(&vmx->vcpu);
3943         put_cpu();
3944         if (err)
3945                 goto free_vmcs;
3946         if (vm_need_virtualize_apic_accesses(kvm))
3947                 if (alloc_apic_access_page(kvm) != 0)
3948                         goto free_vmcs;
3949
3950         if (enable_ept) {
3951                 if (!kvm->arch.ept_identity_map_addr)
3952                         kvm->arch.ept_identity_map_addr =
3953                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3954                 if (alloc_identity_pagetable(kvm) != 0)
3955                         goto free_vmcs;
3956         }
3957
3958         return &vmx->vcpu;
3959
3960 free_vmcs:
3961         free_vmcs(vmx->vmcs);
3962 free_msrs:
3963         kfree(vmx->guest_msrs);
3964 uninit_vcpu:
3965         kvm_vcpu_uninit(&vmx->vcpu);
3966 free_vcpu:
3967         kmem_cache_free(kvm_vcpu_cache, vmx);
3968         return ERR_PTR(err);
3969 }
3970
3971 static void __init vmx_check_processor_compat(void *rtn)
3972 {
3973         struct vmcs_config vmcs_conf;
3974
3975         *(int *)rtn = 0;
3976         if (setup_vmcs_config(&vmcs_conf) < 0)
3977                 *(int *)rtn = -EIO;
3978         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3979                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3980                                 smp_processor_id());
3981                 *(int *)rtn = -EIO;
3982         }
3983 }
3984
3985 static int get_ept_level(void)
3986 {
3987         return VMX_EPT_DEFAULT_GAW + 1;
3988 }
3989
3990 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3991 {
3992         u64 ret;
3993
3994         /* For VT-d and EPT combination
3995          * 1. MMIO: always map as UC
3996          * 2. EPT with VT-d:
3997          *   a. VT-d without snooping control feature: can't guarantee the
3998          *      result, try to trust guest.
3999          *   b. VT-d with snooping control feature: snooping control feature of
4000          *      VT-d engine can guarantee the cache correctness. Just set it
4001          *      to WB to keep consistent with host. So the same as item 3.
4002          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4003          *    consistent with host MTRR
4004          */
4005         if (is_mmio)
4006                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4007         else if (vcpu->kvm->arch.iommu_domain &&
4008                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4009                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4010                       VMX_EPT_MT_EPTE_SHIFT;
4011         else
4012                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4013                         | VMX_EPT_IPAT_BIT;
4014
4015         return ret;
4016 }
4017
4018 #define _ER(x) { EXIT_REASON_##x, #x }
4019
4020 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4021         _ER(EXCEPTION_NMI),
4022         _ER(EXTERNAL_INTERRUPT),
4023         _ER(TRIPLE_FAULT),
4024         _ER(PENDING_INTERRUPT),
4025         _ER(NMI_WINDOW),
4026         _ER(TASK_SWITCH),
4027         _ER(CPUID),
4028         _ER(HLT),
4029         _ER(INVLPG),
4030         _ER(RDPMC),
4031         _ER(RDTSC),
4032         _ER(VMCALL),
4033         _ER(VMCLEAR),
4034         _ER(VMLAUNCH),
4035         _ER(VMPTRLD),
4036         _ER(VMPTRST),
4037         _ER(VMREAD),
4038         _ER(VMRESUME),
4039         _ER(VMWRITE),
4040         _ER(VMOFF),
4041         _ER(VMON),
4042         _ER(CR_ACCESS),
4043         _ER(DR_ACCESS),
4044         _ER(IO_INSTRUCTION),
4045         _ER(MSR_READ),
4046         _ER(MSR_WRITE),
4047         _ER(MWAIT_INSTRUCTION),
4048         _ER(MONITOR_INSTRUCTION),
4049         _ER(PAUSE_INSTRUCTION),
4050         _ER(MCE_DURING_VMENTRY),
4051         _ER(TPR_BELOW_THRESHOLD),
4052         _ER(APIC_ACCESS),
4053         _ER(EPT_VIOLATION),
4054         _ER(EPT_MISCONFIG),
4055         _ER(WBINVD),
4056         { -1, NULL }
4057 };
4058
4059 #undef _ER
4060
4061 static int vmx_get_lpage_level(void)
4062 {
4063         if (enable_ept && !cpu_has_vmx_ept_1g_page())
4064                 return PT_DIRECTORY_LEVEL;
4065         else
4066                 /* For shadow and EPT supported 1GB page */
4067                 return PT_PDPE_LEVEL;
4068 }
4069
4070 static inline u32 bit(int bitno)
4071 {
4072         return 1 << (bitno & 31);
4073 }
4074
4075 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4076 {
4077         struct kvm_cpuid_entry2 *best;
4078         struct vcpu_vmx *vmx = to_vmx(vcpu);
4079         u32 exec_control;
4080
4081         vmx->rdtscp_enabled = false;
4082         if (vmx_rdtscp_supported()) {
4083                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4084                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4085                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4086                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4087                                 vmx->rdtscp_enabled = true;
4088                         else {
4089                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4090                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4091                                                 exec_control);
4092                         }
4093                 }
4094         }
4095 }
4096
4097 static struct kvm_x86_ops vmx_x86_ops = {
4098         .cpu_has_kvm_support = cpu_has_kvm_support,
4099         .disabled_by_bios = vmx_disabled_by_bios,
4100         .hardware_setup = hardware_setup,
4101         .hardware_unsetup = hardware_unsetup,
4102         .check_processor_compatibility = vmx_check_processor_compat,
4103         .hardware_enable = hardware_enable,
4104         .hardware_disable = hardware_disable,
4105         .cpu_has_accelerated_tpr = report_flexpriority,
4106
4107         .vcpu_create = vmx_create_vcpu,
4108         .vcpu_free = vmx_free_vcpu,
4109         .vcpu_reset = vmx_vcpu_reset,
4110
4111         .prepare_guest_switch = vmx_save_host_state,
4112         .vcpu_load = vmx_vcpu_load,
4113         .vcpu_put = vmx_vcpu_put,
4114
4115         .set_guest_debug = set_guest_debug,
4116         .get_msr = vmx_get_msr,
4117         .set_msr = vmx_set_msr,
4118         .get_segment_base = vmx_get_segment_base,
4119         .get_segment = vmx_get_segment,
4120         .set_segment = vmx_set_segment,
4121         .get_cpl = vmx_get_cpl,
4122         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4123         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4124         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4125         .set_cr0 = vmx_set_cr0,
4126         .set_cr3 = vmx_set_cr3,
4127         .set_cr4 = vmx_set_cr4,
4128         .set_efer = vmx_set_efer,
4129         .get_idt = vmx_get_idt,
4130         .set_idt = vmx_set_idt,
4131         .get_gdt = vmx_get_gdt,
4132         .set_gdt = vmx_set_gdt,
4133         .set_dr7 = vmx_set_dr7,
4134         .cache_reg = vmx_cache_reg,
4135         .get_rflags = vmx_get_rflags,
4136         .set_rflags = vmx_set_rflags,
4137         .fpu_activate = vmx_fpu_activate,
4138         .fpu_deactivate = vmx_fpu_deactivate,
4139
4140         .tlb_flush = vmx_flush_tlb,
4141
4142         .run = vmx_vcpu_run,
4143         .handle_exit = vmx_handle_exit,
4144         .skip_emulated_instruction = skip_emulated_instruction,
4145         .set_interrupt_shadow = vmx_set_interrupt_shadow,
4146         .get_interrupt_shadow = vmx_get_interrupt_shadow,
4147         .patch_hypercall = vmx_patch_hypercall,
4148         .set_irq = vmx_inject_irq,
4149         .set_nmi = vmx_inject_nmi,
4150         .queue_exception = vmx_queue_exception,
4151         .interrupt_allowed = vmx_interrupt_allowed,
4152         .nmi_allowed = vmx_nmi_allowed,
4153         .get_nmi_mask = vmx_get_nmi_mask,
4154         .set_nmi_mask = vmx_set_nmi_mask,
4155         .enable_nmi_window = enable_nmi_window,
4156         .enable_irq_window = enable_irq_window,
4157         .update_cr8_intercept = update_cr8_intercept,
4158
4159         .set_tss_addr = vmx_set_tss_addr,
4160         .get_tdp_level = get_ept_level,
4161         .get_mt_mask = vmx_get_mt_mask,
4162
4163         .exit_reasons_str = vmx_exit_reasons_str,
4164         .get_lpage_level = vmx_get_lpage_level,
4165
4166         .cpuid_update = vmx_cpuid_update,
4167
4168         .rdtscp_supported = vmx_rdtscp_supported,
4169 };
4170
4171 static int __init vmx_init(void)
4172 {
4173         int r, i;
4174
4175         rdmsrl_safe(MSR_EFER, &host_efer);
4176
4177         for (i = 0; i < NR_VMX_MSR; ++i)
4178                 kvm_define_shared_msr(i, vmx_msr_index[i]);
4179
4180         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4181         if (!vmx_io_bitmap_a)
4182                 return -ENOMEM;
4183
4184         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4185         if (!vmx_io_bitmap_b) {
4186                 r = -ENOMEM;
4187                 goto out;
4188         }
4189
4190         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4191         if (!vmx_msr_bitmap_legacy) {
4192                 r = -ENOMEM;
4193                 goto out1;
4194         }
4195
4196         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4197         if (!vmx_msr_bitmap_longmode) {
4198                 r = -ENOMEM;
4199                 goto out2;
4200         }
4201
4202         /*
4203          * Allow direct access to the PC debug port (it is often used for I/O
4204          * delays, but the vmexits simply slow things down).
4205          */
4206         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4207         clear_bit(0x80, vmx_io_bitmap_a);
4208
4209         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4210
4211         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4212         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4213
4214         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4215
4216         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
4217         if (r)
4218                 goto out3;
4219
4220         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4221         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4222         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4223         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4224         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4225         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4226
4227         if (enable_ept) {
4228                 bypass_guest_pf = 0;
4229                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4230                         VMX_EPT_WRITABLE_MASK);
4231                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4232                                 VMX_EPT_EXECUTABLE_MASK);
4233                 kvm_enable_tdp();
4234         } else
4235                 kvm_disable_tdp();
4236
4237         if (bypass_guest_pf)
4238                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4239
4240         return 0;
4241
4242 out3:
4243         free_page((unsigned long)vmx_msr_bitmap_longmode);
4244 out2:
4245         free_page((unsigned long)vmx_msr_bitmap_legacy);
4246 out1:
4247         free_page((unsigned long)vmx_io_bitmap_b);
4248 out:
4249         free_page((unsigned long)vmx_io_bitmap_a);
4250         return r;
4251 }
4252
4253 static void __exit vmx_exit(void)
4254 {
4255         free_page((unsigned long)vmx_msr_bitmap_legacy);
4256         free_page((unsigned long)vmx_msr_bitmap_longmode);
4257         free_page((unsigned long)vmx_io_bitmap_b);
4258         free_page((unsigned long)vmx_io_bitmap_a);
4259
4260         kvm_exit();
4261 }
4262
4263 module_init(vmx_init)
4264 module_exit(vmx_exit)