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   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/mm.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/ftrace_event.h>
  29 #include "kvm_cache_regs.h"
  30 #include "x86.h"
  31
  32 #include <asm/io.h>
  33 #include <asm/desc.h>
  34 #include <asm/vmx.h>
  35 #include <asm/virtext.h>
  36 #include <asm/mce.h>
  37
  38 #include "trace.h"
  39
  40 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  41
  42 MODULE_AUTHOR("Qumranet");
  43 MODULE_LICENSE("GPL");
  44
  45 static int __read_mostly bypass_guest_pf = 1;
  46 module_param(bypass_guest_pf, bool, S_IRUGO);
  47
  48 static int __read_mostly enable_vpid = 1;
  49 module_param_named(vpid, enable_vpid, bool, 0444);
  50
  51 static int __read_mostly flexpriority_enabled = 1;
  52 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  53
  54 static int __read_mostly enable_ept = 1;
  55 module_param_named(ept, enable_ept, bool, S_IRUGO);
  56
  57 static int __read_mostly enable_unrestricted_guest = 1;
  58 module_param_named(unrestricted_guest,
  59                         enable_unrestricted_guest, bool, S_IRUGO);
  60
  61 static int __read_mostly emulate_invalid_guest_state = 0;
  62 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  63
  64 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  65         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  66 #define KVM_GUEST_CR0_MASK                                              \
  67         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  68 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  69         (X86_CR0_WP | X86_CR0_NE | X86_CR0_MP)
  70 #define KVM_VM_CR0_ALWAYS_ON                                            \
  71         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  72 #define KVM_CR4_GUEST_OWNED_BITS                                      \
  73         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
  74          | X86_CR4_OSXMMEXCPT)
  75
  76 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
  77 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
  78
  79 /*
  80  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
  81  * ple_gap:    upper bound on the amount of time between two successive
  82  *             executions of PAUSE in a loop. Also indicate if ple enabled.
  83  *             According to test, this time is usually small than 41 cycles.
  84  * ple_window: upper bound on the amount of time a guest is allowed to execute
  85  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
  86  *             less than 2^12 cycles
  87  * Time is measured based on a counter that runs at the same rate as the TSC,
  88  * refer SDM volume 3b section 21.6.13 & 22.1.3.
  89  */
  90 #define KVM_VMX_DEFAULT_PLE_GAP    41
  91 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
  92 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
  93 module_param(ple_gap, int, S_IRUGO);
  94
  95 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
  96 module_param(ple_window, int, S_IRUGO);
  97
  98 struct vmcs {
  99         u32 revision_id;
 100         u32 abort;
 101         char data[0];
 102 };
 103
 104 struct shared_msr_entry {
 105         unsigned index;
 106         u64 data;
 107         u64 mask;
 108 };
 109
 110 struct vcpu_vmx {
 111         struct kvm_vcpu       vcpu;
 112         struct list_head      local_vcpus_link;
 113         unsigned long         host_rsp;
 114         int                   launched;
 115         u8                    fail;
 116         u32                   idt_vectoring_info;
 117         struct shared_msr_entry *guest_msrs;
 118         int                   nmsrs;
 119         int                   save_nmsrs;
 120 #ifdef CONFIG_X86_64
 121         u64                   msr_host_kernel_gs_base;
 122         u64                   msr_guest_kernel_gs_base;
 123 #endif
 124         struct vmcs          *vmcs;
 125         struct {
 126                 int           loaded;
 127                 u16           fs_sel, gs_sel, ldt_sel;
 128                 int           gs_ldt_reload_needed;
 129                 int           fs_reload_needed;
 130         } host_state;
 131         struct {
 132                 int vm86_active;
 133                 u8 save_iopl;
 134                 struct kvm_save_segment {
 135                         u16 selector;
 136                         unsigned long base;
 137                         u32 limit;
 138                         u32 ar;
 139                 } tr, es, ds, fs, gs;
 140                 struct {
 141                         bool pending;
 142                         u8 vector;
 143                         unsigned rip;
 144                 } irq;
 145         } rmode;
 146         int vpid;
 147         bool emulation_required;
 148
 149         /* Support for vnmi-less CPUs */
 150         int soft_vnmi_blocked;
 151         ktime_t entry_time;
 152         s64 vnmi_blocked_time;
 153         u32 exit_reason;
 154
 155         bool rdtscp_enabled;
 156 };
 157
 158 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 159 {
 160         return container_of(vcpu, struct vcpu_vmx, vcpu);
 161 }
 162
 163 static int init_rmode(struct kvm *kvm);
 164 static u64 construct_eptp(unsigned long root_hpa);
 165
 166 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 167 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 168 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 169
 170 static unsigned long *vmx_io_bitmap_a;
 171 static unsigned long *vmx_io_bitmap_b;
 172 static unsigned long *vmx_msr_bitmap_legacy;
 173 static unsigned long *vmx_msr_bitmap_longmode;
 174
 175 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 176 static DEFINE_SPINLOCK(vmx_vpid_lock);
 177
 178 static struct vmcs_config {
 179         int size;
 180         int order;
 181         u32 revision_id;
 182         u32 pin_based_exec_ctrl;
 183         u32 cpu_based_exec_ctrl;
 184         u32 cpu_based_2nd_exec_ctrl;
 185         u32 vmexit_ctrl;
 186         u32 vmentry_ctrl;
 187 } vmcs_config;
 188
 189 static struct vmx_capability {
 190         u32 ept;
 191         u32 vpid;
 192 } vmx_capability;
 193
 194 #define VMX_SEGMENT_FIELD(seg)                                  \
 195         [VCPU_SREG_##seg] = {                                   \
 196                 .selector = GUEST_##seg##_SELECTOR,             \
 197                 .base = GUEST_##seg##_BASE,                     \
 198                 .limit = GUEST_##seg##_LIMIT,                   \
 199                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 200         }
 201
 202 static struct kvm_vmx_segment_field {
 203         unsigned selector;
 204         unsigned base;
 205         unsigned limit;
 206         unsigned ar_bytes;
 207 } kvm_vmx_segment_fields[] = {
 208         VMX_SEGMENT_FIELD(CS),
 209         VMX_SEGMENT_FIELD(DS),
 210         VMX_SEGMENT_FIELD(ES),
 211         VMX_SEGMENT_FIELD(FS),
 212         VMX_SEGMENT_FIELD(GS),
 213         VMX_SEGMENT_FIELD(SS),
 214         VMX_SEGMENT_FIELD(TR),
 215         VMX_SEGMENT_FIELD(LDTR),
 216 };
 217
 218 static u64 host_efer;
 219
 220 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 221
 222 /*
 223  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 224  * away by decrementing the array size.
 225  */
 226 static const u32 vmx_msr_index[] = {
 227 #ifdef CONFIG_X86_64
 228         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 229 #endif
 230         MSR_EFER, MSR_TSC_AUX, MSR_K6_STAR,
 231 };
 232 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 233
 234 static inline int is_page_fault(u32 intr_info)
 235 {
 236         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 237                              INTR_INFO_VALID_MASK)) ==
 238                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 239 }
 240
 241 static inline int is_no_device(u32 intr_info)
 242 {
 243         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 244                              INTR_INFO_VALID_MASK)) ==
 245                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 246 }
 247
 248 static inline int is_invalid_opcode(u32 intr_info)
 249 {
 250         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 251                              INTR_INFO_VALID_MASK)) ==
 252                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 253 }
 254
 255 static inline int is_external_interrupt(u32 intr_info)
 256 {
 257         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 258                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 259 }
 260
 261 static inline int is_machine_check(u32 intr_info)
 262 {
 263         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 264                              INTR_INFO_VALID_MASK)) ==
 265                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 266 }
 267
 268 static inline int cpu_has_vmx_msr_bitmap(void)
 269 {
 270         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 271 }
 272
 273 static inline int cpu_has_vmx_tpr_shadow(void)
 274 {
 275         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 276 }
 277
 278 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 279 {
 280         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 281 }
 282
 283 static inline int cpu_has_secondary_exec_ctrls(void)
 284 {
 285         return vmcs_config.cpu_based_exec_ctrl &
 286                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 287 }
 288
 289 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 290 {
 291         return vmcs_config.cpu_based_2nd_exec_ctrl &
 292                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 293 }
 294
 295 static inline bool cpu_has_vmx_flexpriority(void)
 296 {
 297         return cpu_has_vmx_tpr_shadow() &&
 298                 cpu_has_vmx_virtualize_apic_accesses();
 299 }
 300
 301 static inline bool cpu_has_vmx_ept_execute_only(void)
 302 {
 303         return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
 304 }
 305
 306 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 307 {
 308         return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
 309 }
 310
 311 static inline bool cpu_has_vmx_eptp_writeback(void)
 312 {
 313         return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
 314 }
 315
 316 static inline bool cpu_has_vmx_ept_2m_page(void)
 317 {
 318         return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
 319 }
 320
 321 static inline bool cpu_has_vmx_ept_1g_page(void)
 322 {
 323         return !!(vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT);
 324 }
 325
 326 static inline int cpu_has_vmx_invept_individual_addr(void)
 327 {
 328         return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
 329 }
 330
 331 static inline int cpu_has_vmx_invept_context(void)
 332 {
 333         return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
 334 }
 335
 336 static inline int cpu_has_vmx_invept_global(void)
 337 {
 338         return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
 339 }
 340
 341 static inline int cpu_has_vmx_ept(void)
 342 {
 343         return vmcs_config.cpu_based_2nd_exec_ctrl &
 344                 SECONDARY_EXEC_ENABLE_EPT;
 345 }
 346
 347 static inline int cpu_has_vmx_unrestricted_guest(void)
 348 {
 349         return vmcs_config.cpu_based_2nd_exec_ctrl &
 350                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 351 }
 352
 353 static inline int cpu_has_vmx_ple(void)
 354 {
 355         return vmcs_config.cpu_based_2nd_exec_ctrl &
 356                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 357 }
 358
 359 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 360 {
 361         return flexpriority_enabled &&
 362                 (cpu_has_vmx_virtualize_apic_accesses()) &&
 363                 (irqchip_in_kernel(kvm));
 364 }
 365
 366 static inline int cpu_has_vmx_vpid(void)
 367 {
 368         return vmcs_config.cpu_based_2nd_exec_ctrl &
 369                 SECONDARY_EXEC_ENABLE_VPID;
 370 }
 371
 372 static inline int cpu_has_vmx_rdtscp(void)
 373 {
 374         return vmcs_config.cpu_based_2nd_exec_ctrl &
 375                 SECONDARY_EXEC_RDTSCP;
 376 }
 377
 378 static inline int cpu_has_virtual_nmis(void)
 379 {
 380         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 381 }
 382
 383 static inline bool report_flexpriority(void)
 384 {
 385         return flexpriority_enabled;
 386 }
 387
 388 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 389 {
 390         int i;
 391
 392         for (i = 0; i < vmx->nmsrs; ++i)
 393                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 394                         return i;
 395         return -1;
 396 }
 397
 398 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 399 {
 400     struct {
 401         u64 vpid : 16;
 402         u64 rsvd : 48;
 403         u64 gva;
 404     } operand = { vpid, 0, gva };
 405
 406     asm volatile (__ex(ASM_VMX_INVVPID)
 407                   /* CF==1 or ZF==1 --> rc = -1 */
 408                   "; ja 1f ; ud2 ; 1:"
 409                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 410 }
 411
 412 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 413 {
 414         struct {
 415                 u64 eptp, gpa;
 416         } operand = {eptp, gpa};
 417
 418         asm volatile (__ex(ASM_VMX_INVEPT)
 419                         /* CF==1 or ZF==1 --> rc = -1 */
 420                         "; ja 1f ; ud2 ; 1:\n"
 421                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 422 }
 423
 424 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 425 {
 426         int i;
 427
 428         i = __find_msr_index(vmx, msr);
 429         if (i >= 0)
 430                 return &vmx->guest_msrs[i];
 431         return NULL;
 432 }
 433
 434 static void vmcs_clear(struct vmcs *vmcs)
 435 {
 436         u64 phys_addr = __pa(vmcs);
 437         u8 error;
 438
 439         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 440                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 441                       : "cc", "memory");
 442         if (error)
 443                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 444                        vmcs, phys_addr);
 445 }
 446
 447 static void __vcpu_clear(void *arg)
 448 {
 449         struct vcpu_vmx *vmx = arg;
 450         int cpu = raw_smp_processor_id();
 451
 452         if (vmx->vcpu.cpu == cpu)
 453                 vmcs_clear(vmx->vmcs);
 454         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 455                 per_cpu(current_vmcs, cpu) = NULL;
 456         rdtscll(vmx->vcpu.arch.host_tsc);
 457         list_del(&vmx->local_vcpus_link);
 458         vmx->vcpu.cpu = -1;
 459         vmx->launched = 0;
 460 }
 461
 462 static void vcpu_clear(struct vcpu_vmx *vmx)
 463 {
 464         if (vmx->vcpu.cpu == -1)
 465                 return;
 466         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 467 }
 468
 469 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 470 {
 471         if (vmx->vpid == 0)
 472                 return;
 473
 474         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 475 }
 476
 477 static inline void ept_sync_global(void)
 478 {
 479         if (cpu_has_vmx_invept_global())
 480                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 481 }
 482
 483 static inline void ept_sync_context(u64 eptp)
 484 {
 485         if (enable_ept) {
 486                 if (cpu_has_vmx_invept_context())
 487                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 488                 else
 489                         ept_sync_global();
 490         }
 491 }
 492
 493 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 494 {
 495         if (enable_ept) {
 496                 if (cpu_has_vmx_invept_individual_addr())
 497                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 498                                         eptp, gpa);
 499                 else
 500                         ept_sync_context(eptp);
 501         }
 502 }
 503
 504 static unsigned long vmcs_readl(unsigned long field)
 505 {
 506         unsigned long value;
 507
 508         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 509                       : "=a"(value) : "d"(field) : "cc");
 510         return value;
 511 }
 512
 513 static u16 vmcs_read16(unsigned long field)
 514 {
 515         return vmcs_readl(field);
 516 }
 517
 518 static u32 vmcs_read32(unsigned long field)
 519 {
 520         return vmcs_readl(field);
 521 }
 522
 523 static u64 vmcs_read64(unsigned long field)
 524 {
 525 #ifdef CONFIG_X86_64
 526         return vmcs_readl(field);
 527 #else
 528         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 529 #endif
 530 }
 531
 532 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 533 {
 534         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 535                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 536         dump_stack();
 537 }
 538
 539 static void vmcs_writel(unsigned long field, unsigned long value)
 540 {
 541         u8 error;
 542
 543         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 544                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 545         if (unlikely(error))
 546                 vmwrite_error(field, value);
 547 }
 548
 549 static void vmcs_write16(unsigned long field, u16 value)
 550 {
 551         vmcs_writel(field, value);
 552 }
 553
 554 static void vmcs_write32(unsigned long field, u32 value)
 555 {
 556         vmcs_writel(field, value);
 557 }
 558
 559 static void vmcs_write64(unsigned long field, u64 value)
 560 {
 561         vmcs_writel(field, value);
 562 #ifndef CONFIG_X86_64
 563         asm volatile ("");
 564         vmcs_writel(field+1, value >> 32);
 565 #endif
 566 }
 567
 568 static void vmcs_clear_bits(unsigned long field, u32 mask)
 569 {
 570         vmcs_writel(field, vmcs_readl(field) & ~mask);
 571 }
 572
 573 static void vmcs_set_bits(unsigned long field, u32 mask)
 574 {
 575         vmcs_writel(field, vmcs_readl(field) | mask);
 576 }
 577
 578 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 579 {
 580         u32 eb;
 581
 582         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 583              (1u << NM_VECTOR) | (1u << DB_VECTOR);
 584         if ((vcpu->guest_debug &
 585              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 586             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 587                 eb |= 1u << BP_VECTOR;
 588         if (to_vmx(vcpu)->rmode.vm86_active)
 589                 eb = ~0;
 590         if (enable_ept)
 591                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 592         if (vcpu->fpu_active)
 593                 eb &= ~(1u << NM_VECTOR);
 594         vmcs_write32(EXCEPTION_BITMAP, eb);
 595 }
 596
 597 static void reload_tss(void)
 598 {
 599         /*
 600          * VT restores TR but not its size.  Useless.
 601          */
 602         struct descriptor_table gdt;
 603         struct desc_struct *descs;
 604
 605         kvm_get_gdt(&gdt);
 606         descs = (void *)gdt.base;
 607         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 608         load_TR_desc();
 609 }
 610
 611 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 612 {
 613         u64 guest_efer;
 614         u64 ignore_bits;
 615
 616         guest_efer = vmx->vcpu.arch.shadow_efer;
 617
 618         /*
 619          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 620          * outside long mode
 621          */
 622         ignore_bits = EFER_NX | EFER_SCE;
 623 #ifdef CONFIG_X86_64
 624         ignore_bits |= EFER_LMA | EFER_LME;
 625         /* SCE is meaningful only in long mode on Intel */
 626         if (guest_efer & EFER_LMA)
 627                 ignore_bits &= ~(u64)EFER_SCE;
 628 #endif
 629         guest_efer &= ~ignore_bits;
 630         guest_efer |= host_efer & ignore_bits;
 631         vmx->guest_msrs[efer_offset].data = guest_efer;
 632         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
 633         return true;
 634 }
 635
 636 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 637 {
 638         struct vcpu_vmx *vmx = to_vmx(vcpu);
 639         int i;
 640
 641         if (vmx->host_state.loaded)
 642                 return;
 643
 644         vmx->host_state.loaded = 1;
 645         /*
 646          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 647          * allow segment selectors with cpl > 0 or ti == 1.
 648          */
 649         vmx->host_state.ldt_sel = kvm_read_ldt();
 650         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 651         vmx->host_state.fs_sel = kvm_read_fs();
 652         if (!(vmx->host_state.fs_sel & 7)) {
 653                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 654                 vmx->host_state.fs_reload_needed = 0;
 655         } else {
 656                 vmcs_write16(HOST_FS_SELECTOR, 0);
 657                 vmx->host_state.fs_reload_needed = 1;
 658         }
 659         vmx->host_state.gs_sel = kvm_read_gs();
 660         if (!(vmx->host_state.gs_sel & 7))
 661                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 662         else {
 663                 vmcs_write16(HOST_GS_SELECTOR, 0);
 664                 vmx->host_state.gs_ldt_reload_needed = 1;
 665         }
 666
 667 #ifdef CONFIG_X86_64
 668         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 669         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 670 #else
 671         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 672         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 673 #endif
 674
 675 #ifdef CONFIG_X86_64
 676         if (is_long_mode(&vmx->vcpu)) {
 677                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 678                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 679         }
 680 #endif
 681         for (i = 0; i < vmx->save_nmsrs; ++i)
 682                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
 683                                    vmx->guest_msrs[i].data,
 684                                    vmx->guest_msrs[i].mask);
 685 }
 686
 687 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 688 {
 689         unsigned long flags;
 690
 691         if (!vmx->host_state.loaded)
 692                 return;
 693
 694         ++vmx->vcpu.stat.host_state_reload;
 695         vmx->host_state.loaded = 0;
 696         if (vmx->host_state.fs_reload_needed)
 697                 kvm_load_fs(vmx->host_state.fs_sel);
 698         if (vmx->host_state.gs_ldt_reload_needed) {
 699                 kvm_load_ldt(vmx->host_state.ldt_sel);
 700                 /*
 701                  * If we have to reload gs, we must take care to
 702                  * preserve our gs base.
 703                  */
 704                 local_irq_save(flags);
 705                 kvm_load_gs(vmx->host_state.gs_sel);
 706 #ifdef CONFIG_X86_64
 707                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 708 #endif
 709                 local_irq_restore(flags);
 710         }
 711         reload_tss();
 712 #ifdef CONFIG_X86_64
 713         if (is_long_mode(&vmx->vcpu)) {
 714                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 715                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 716         }
 717 #endif
 718 }
 719
 720 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 721 {
 722         preempt_disable();
 723         __vmx_load_host_state(vmx);
 724         preempt_enable();
 725 }
 726
 727 /*
 728  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 729  * vcpu mutex is already taken.
 730  */
 731 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 732 {
 733         struct vcpu_vmx *vmx = to_vmx(vcpu);
 734         u64 phys_addr = __pa(vmx->vmcs);
 735         u64 tsc_this, delta, new_offset;
 736
 737         if (vcpu->cpu != cpu) {
 738                 vcpu_clear(vmx);
 739                 kvm_migrate_timers(vcpu);
 740                 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
 741                 local_irq_disable();
 742                 list_add(&vmx->local_vcpus_link,
 743                          &per_cpu(vcpus_on_cpu, cpu));
 744                 local_irq_enable();
 745         }
 746
 747         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 748                 u8 error;
 749
 750                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 751                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 752                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 753                               : "cc");
 754                 if (error)
 755                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 756                                vmx->vmcs, phys_addr);
 757         }
 758
 759         if (vcpu->cpu != cpu) {
 760                 struct descriptor_table dt;
 761                 unsigned long sysenter_esp;
 762
 763                 vcpu->cpu = cpu;
 764                 /*
 765                  * Linux uses per-cpu TSS and GDT, so set these when switching
 766                  * processors.
 767                  */
 768                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 769                 kvm_get_gdt(&dt);
 770                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 771
 772                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 773                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 774
 775                 /*
 776                  * Make sure the time stamp counter is monotonous.
 777                  */
 778                 rdtscll(tsc_this);
 779                 if (tsc_this < vcpu->arch.host_tsc) {
 780                         delta = vcpu->arch.host_tsc - tsc_this;
 781                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 782                         vmcs_write64(TSC_OFFSET, new_offset);
 783                 }
 784         }
 785 }
 786
 787 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 788 {
 789         __vmx_load_host_state(to_vmx(vcpu));
 790 }
 791
 792 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 793 {
 794         if (vcpu->fpu_active)
 795                 return;
 796         vcpu->fpu_active = 1;
 797         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 798         if (kvm_read_cr0_bits(vcpu, X86_CR0_TS))
 799                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 800         update_exception_bitmap(vcpu);
 801         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
 802         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 803 }
 804
 805 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
 806
 807 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 808 {
 809         vmx_decache_cr0_guest_bits(vcpu);
 810         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 811         update_exception_bitmap(vcpu);
 812         vcpu->arch.cr0_guest_owned_bits = 0;
 813         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 814         vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
 815 }
 816
 817 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 818 {
 819         unsigned long rflags;
 820
 821         rflags = vmcs_readl(GUEST_RFLAGS);
 822         if (to_vmx(vcpu)->rmode.vm86_active)
 823                 rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
 824         return rflags;
 825 }
 826
 827 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 828 {
 829         if (to_vmx(vcpu)->rmode.vm86_active)
 830                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 831         vmcs_writel(GUEST_RFLAGS, rflags);
 832 }
 833
 834 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 835 {
 836         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 837         int ret = 0;
 838
 839         if (interruptibility & GUEST_INTR_STATE_STI)
 840                 ret |= X86_SHADOW_INT_STI;
 841         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
 842                 ret |= X86_SHADOW_INT_MOV_SS;
 843
 844         return ret & mask;
 845 }
 846
 847 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 848 {
 849         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 850         u32 interruptibility = interruptibility_old;
 851
 852         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
 853
 854         if (mask & X86_SHADOW_INT_MOV_SS)
 855                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
 856         if (mask & X86_SHADOW_INT_STI)
 857                 interruptibility |= GUEST_INTR_STATE_STI;
 858
 859         if ((interruptibility != interruptibility_old))
 860                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
 861 }
 862
 863 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 864 {
 865         unsigned long rip;
 866
 867         rip = kvm_rip_read(vcpu);
 868         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 869         kvm_rip_write(vcpu, rip);
 870
 871         /* skipping an emulated instruction also counts */
 872         vmx_set_interrupt_shadow(vcpu, 0);
 873 }
 874
 875 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 876                                 bool has_error_code, u32 error_code)
 877 {
 878         struct vcpu_vmx *vmx = to_vmx(vcpu);
 879         u32 intr_info = nr | INTR_INFO_VALID_MASK;
 880
 881         if (has_error_code) {
 882                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 883                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
 884         }
 885
 886         if (vmx->rmode.vm86_active) {
 887                 vmx->rmode.irq.pending = true;
 888                 vmx->rmode.irq.vector = nr;
 889                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
 890                 if (kvm_exception_is_soft(nr))
 891                         vmx->rmode.irq.rip +=
 892                                 vmx->vcpu.arch.event_exit_inst_len;
 893                 intr_info |= INTR_TYPE_SOFT_INTR;
 894                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 895                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
 896                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
 897                 return;
 898         }
 899
 900         if (kvm_exception_is_soft(nr)) {
 901                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
 902                              vmx->vcpu.arch.event_exit_inst_len);
 903                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
 904         } else
 905                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
 906
 907         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 908 }
 909
 910 static bool vmx_rdtscp_supported(void)
 911 {
 912         return cpu_has_vmx_rdtscp();
 913 }
 914
 915 /*
 916  * Swap MSR entry in host/guest MSR entry array.
 917  */
 918 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 919 {
 920         struct shared_msr_entry tmp;
 921
 922         tmp = vmx->guest_msrs[to];
 923         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 924         vmx->guest_msrs[from] = tmp;
 925 }
 926
 927 /*
 928  * Set up the vmcs to automatically save and restore system
 929  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 930  * mode, as fiddling with msrs is very expensive.
 931  */
 932 static void setup_msrs(struct vcpu_vmx *vmx)
 933 {
 934         int save_nmsrs, index;
 935         unsigned long *msr_bitmap;
 936
 937         vmx_load_host_state(vmx);
 938         save_nmsrs = 0;
 939 #ifdef CONFIG_X86_64
 940         if (is_long_mode(&vmx->vcpu)) {
 941                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 942                 if (index >= 0)
 943                         move_msr_up(vmx, index, save_nmsrs++);
 944                 index = __find_msr_index(vmx, MSR_LSTAR);
 945                 if (index >= 0)
 946                         move_msr_up(vmx, index, save_nmsrs++);
 947                 index = __find_msr_index(vmx, MSR_CSTAR);
 948                 if (index >= 0)
 949                         move_msr_up(vmx, index, save_nmsrs++);
 950                 index = __find_msr_index(vmx, MSR_TSC_AUX);
 951                 if (index >= 0 && vmx->rdtscp_enabled)
 952                         move_msr_up(vmx, index, save_nmsrs++);
 953                 /*
 954                  * MSR_K6_STAR is only needed on long mode guests, and only
 955                  * if efer.sce is enabled.
 956                  */
 957                 index = __find_msr_index(vmx, MSR_K6_STAR);
 958                 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
 959                         move_msr_up(vmx, index, save_nmsrs++);
 960         }
 961 #endif
 962         index = __find_msr_index(vmx, MSR_EFER);
 963         if (index >= 0 && update_transition_efer(vmx, index))
 964                 move_msr_up(vmx, index, save_nmsrs++);
 965
 966         vmx->save_nmsrs = save_nmsrs;
 967
 968         if (cpu_has_vmx_msr_bitmap()) {
 969                 if (is_long_mode(&vmx->vcpu))
 970                         msr_bitmap = vmx_msr_bitmap_longmode;
 971                 else
 972                         msr_bitmap = vmx_msr_bitmap_legacy;
 973
 974                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
 975         }
 976 }
 977
 978 /*
 979  * reads and returns guest's timestamp counter "register"
 980  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 981  */
 982 static u64 guest_read_tsc(void)
 983 {
 984         u64 host_tsc, tsc_offset;
 985
 986         rdtscll(host_tsc);
 987         tsc_offset = vmcs_read64(TSC_OFFSET);
 988         return host_tsc + tsc_offset;
 989 }
 990
 991 /*
 992  * writes 'guest_tsc' into guest's timestamp counter "register"
 993  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 994  */
 995 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
 996 {
 997         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 998 }
 999
1000 /*
1001  * Reads an msr value (of 'msr_index') into 'pdata'.
1002  * Returns 0 on success, non-0 otherwise.
1003  * Assumes vcpu_load() was already called.
1004  */
1005 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1006 {
1007         u64 data;
1008         struct shared_msr_entry *msr;
1009
1010         if (!pdata) {
1011                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1012                 return -EINVAL;
1013         }
1014
1015         switch (msr_index) {
1016 #ifdef CONFIG_X86_64
1017         case MSR_FS_BASE:
1018                 data = vmcs_readl(GUEST_FS_BASE);
1019                 break;
1020         case MSR_GS_BASE:
1021                 data = vmcs_readl(GUEST_GS_BASE);
1022                 break;
1023         case MSR_KERNEL_GS_BASE:
1024                 vmx_load_host_state(to_vmx(vcpu));
1025                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1026                 break;
1027 #endif
1028         case MSR_EFER:
1029                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1030         case MSR_IA32_TSC:
1031                 data = guest_read_tsc();
1032                 break;
1033         case MSR_IA32_SYSENTER_CS:
1034                 data = vmcs_read32(GUEST_SYSENTER_CS);
1035                 break;
1036         case MSR_IA32_SYSENTER_EIP:
1037                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1038                 break;
1039         case MSR_IA32_SYSENTER_ESP:
1040                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1041                 break;
1042         case MSR_TSC_AUX:
1043                 if (!to_vmx(vcpu)->rdtscp_enabled)
1044                         return 1;
1045                 /* Otherwise falls through */
1046         default:
1047                 vmx_load_host_state(to_vmx(vcpu));
1048                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1049                 if (msr) {
1050                         vmx_load_host_state(to_vmx(vcpu));
1051                         data = msr->data;
1052                         break;
1053                 }
1054                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1055         }
1056
1057         *pdata = data;
1058         return 0;
1059 }
1060
1061 /*
1062  * Writes msr value into into the appropriate "register".
1063  * Returns 0 on success, non-0 otherwise.
1064  * Assumes vcpu_load() was already called.
1065  */
1066 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1067 {
1068         struct vcpu_vmx *vmx = to_vmx(vcpu);
1069         struct shared_msr_entry *msr;
1070         u64 host_tsc;
1071         int ret = 0;
1072
1073         switch (msr_index) {
1074         case MSR_EFER:
1075                 vmx_load_host_state(vmx);
1076                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1077                 break;
1078 #ifdef CONFIG_X86_64
1079         case MSR_FS_BASE:
1080                 vmcs_writel(GUEST_FS_BASE, data);
1081                 break;
1082         case MSR_GS_BASE:
1083                 vmcs_writel(GUEST_GS_BASE, data);
1084                 break;
1085         case MSR_KERNEL_GS_BASE:
1086                 vmx_load_host_state(vmx);
1087                 vmx->msr_guest_kernel_gs_base = data;
1088                 break;
1089 #endif
1090         case MSR_IA32_SYSENTER_CS:
1091                 vmcs_write32(GUEST_SYSENTER_CS, data);
1092                 break;
1093         case MSR_IA32_SYSENTER_EIP:
1094                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1095                 break;
1096         case MSR_IA32_SYSENTER_ESP:
1097                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1098                 break;
1099         case MSR_IA32_TSC:
1100                 rdtscll(host_tsc);
1101                 guest_write_tsc(data, host_tsc);
1102                 break;
1103         case MSR_IA32_CR_PAT:
1104                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1105                         vmcs_write64(GUEST_IA32_PAT, data);
1106                         vcpu->arch.pat = data;
1107                         break;
1108                 }
1109                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1110                 break;
1111         case MSR_TSC_AUX:
1112                 if (!vmx->rdtscp_enabled)
1113                         return 1;
1114                 /* Check reserved bit, higher 32 bits should be zero */
1115                 if ((data >> 32) != 0)
1116                         return 1;
1117                 /* Otherwise falls through */
1118         default:
1119                 msr = find_msr_entry(vmx, msr_index);
1120                 if (msr) {
1121                         vmx_load_host_state(vmx);
1122                         msr->data = data;
1123                         break;
1124                 }
1125                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1126         }
1127
1128         return ret;
1129 }
1130
1131 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1132 {
1133         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1134         switch (reg) {
1135         case VCPU_REGS_RSP:
1136                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1137                 break;
1138         case VCPU_REGS_RIP:
1139                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1140                 break;
1141         case VCPU_EXREG_PDPTR:
1142                 if (enable_ept)
1143                         ept_save_pdptrs(vcpu);
1144                 break;
1145         default:
1146                 break;
1147         }
1148 }
1149
1150 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1151 {
1152         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1153                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1154         else
1155                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1156
1157         update_exception_bitmap(vcpu);
1158 }
1159
1160 static __init int cpu_has_kvm_support(void)
1161 {
1162         return cpu_has_vmx();
1163 }
1164
1165 static __init int vmx_disabled_by_bios(void)
1166 {
1167         u64 msr;
1168
1169         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1170         return (msr & (FEATURE_CONTROL_LOCKED |
1171                        FEATURE_CONTROL_VMXON_ENABLED))
1172             == FEATURE_CONTROL_LOCKED;
1173         /* locked but not enabled */
1174 }
1175
1176 static int hardware_enable(void *garbage)
1177 {
1178         int cpu = raw_smp_processor_id();
1179         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1180         u64 old;
1181
1182         if (read_cr4() & X86_CR4_VMXE)
1183                 return -EBUSY;
1184
1185         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1186         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1187         if ((old & (FEATURE_CONTROL_LOCKED |
1188                     FEATURE_CONTROL_VMXON_ENABLED))
1189             != (FEATURE_CONTROL_LOCKED |
1190                 FEATURE_CONTROL_VMXON_ENABLED))
1191                 /* enable and lock */
1192                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1193                        FEATURE_CONTROL_LOCKED |
1194                        FEATURE_CONTROL_VMXON_ENABLED);
1195         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1196         asm volatile (ASM_VMX_VMXON_RAX
1197                       : : "a"(&phys_addr), "m"(phys_addr)
1198                       : "memory", "cc");
1199
1200         ept_sync_global();
1201
1202         return 0;
1203 }
1204
1205 static void vmclear_local_vcpus(void)
1206 {
1207         int cpu = raw_smp_processor_id();
1208         struct vcpu_vmx *vmx, *n;
1209
1210         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1211                                  local_vcpus_link)
1212                 __vcpu_clear(vmx);
1213 }
1214
1215
1216 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1217  * tricks.
1218  */
1219 static void kvm_cpu_vmxoff(void)
1220 {
1221         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1222         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1223 }
1224
1225 static void hardware_disable(void *garbage)
1226 {
1227         vmclear_local_vcpus();
1228         kvm_cpu_vmxoff();
1229 }
1230
1231 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1232                                       u32 msr, u32 *result)
1233 {
1234         u32 vmx_msr_low, vmx_msr_high;
1235         u32 ctl = ctl_min | ctl_opt;
1236
1237         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1238
1239         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1240         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1241
1242         /* Ensure minimum (required) set of control bits are supported. */
1243         if (ctl_min & ~ctl)
1244                 return -EIO;
1245
1246         *result = ctl;
1247         return 0;
1248 }
1249
1250 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1251 {
1252         u32 vmx_msr_low, vmx_msr_high;
1253         u32 min, opt, min2, opt2;
1254         u32 _pin_based_exec_control = 0;
1255         u32 _cpu_based_exec_control = 0;
1256         u32 _cpu_based_2nd_exec_control = 0;
1257         u32 _vmexit_control = 0;
1258         u32 _vmentry_control = 0;
1259
1260         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1261         opt = PIN_BASED_VIRTUAL_NMIS;
1262         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1263                                 &_pin_based_exec_control) < 0)
1264                 return -EIO;
1265
1266         min = CPU_BASED_HLT_EXITING |
1267 #ifdef CONFIG_X86_64
1268               CPU_BASED_CR8_LOAD_EXITING |
1269               CPU_BASED_CR8_STORE_EXITING |
1270 #endif
1271               CPU_BASED_CR3_LOAD_EXITING |
1272               CPU_BASED_CR3_STORE_EXITING |
1273               CPU_BASED_USE_IO_BITMAPS |
1274               CPU_BASED_MOV_DR_EXITING |
1275               CPU_BASED_USE_TSC_OFFSETING |
1276               CPU_BASED_MWAIT_EXITING |
1277               CPU_BASED_MONITOR_EXITING |
1278               CPU_BASED_INVLPG_EXITING;
1279         opt = CPU_BASED_TPR_SHADOW |
1280               CPU_BASED_USE_MSR_BITMAPS |
1281               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1282         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1283                                 &_cpu_based_exec_control) < 0)
1284                 return -EIO;
1285 #ifdef CONFIG_X86_64
1286         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1287                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1288                                            ~CPU_BASED_CR8_STORE_EXITING;
1289 #endif
1290         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1291                 min2 = 0;
1292                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1293                         SECONDARY_EXEC_WBINVD_EXITING |
1294                         SECONDARY_EXEC_ENABLE_VPID |
1295                         SECONDARY_EXEC_ENABLE_EPT |
1296                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
1297                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1298                         SECONDARY_EXEC_RDTSCP;
1299                 if (adjust_vmx_controls(min2, opt2,
1300                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1301                                         &_cpu_based_2nd_exec_control) < 0)
1302                         return -EIO;
1303         }
1304 #ifndef CONFIG_X86_64
1305         if (!(_cpu_based_2nd_exec_control &
1306                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1307                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1308 #endif
1309         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1310                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1311                    enabled */
1312                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1313                                              CPU_BASED_CR3_STORE_EXITING |
1314                                              CPU_BASED_INVLPG_EXITING);
1315                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1316                       vmx_capability.ept, vmx_capability.vpid);
1317         }
1318
1319         min = 0;
1320 #ifdef CONFIG_X86_64
1321         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1322 #endif
1323         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1324         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1325                                 &_vmexit_control) < 0)
1326                 return -EIO;
1327
1328         min = 0;
1329         opt = VM_ENTRY_LOAD_IA32_PAT;
1330         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1331                                 &_vmentry_control) < 0)
1332                 return -EIO;
1333
1334         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1335
1336         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1337         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1338                 return -EIO;
1339
1340 #ifdef CONFIG_X86_64
1341         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1342         if (vmx_msr_high & (1u<<16))
1343                 return -EIO;
1344 #endif
1345
1346         /* Require Write-Back (WB) memory type for VMCS accesses. */
1347         if (((vmx_msr_high >> 18) & 15) != 6)
1348                 return -EIO;
1349
1350         vmcs_conf->size = vmx_msr_high & 0x1fff;
1351         vmcs_conf->order = get_order(vmcs_config.size);
1352         vmcs_conf->revision_id = vmx_msr_low;
1353
1354         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1355         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1356         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1357         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1358         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1359
1360         return 0;
1361 }
1362
1363 static struct vmcs *alloc_vmcs_cpu(int cpu)
1364 {
1365         int node = cpu_to_node(cpu);
1366         struct page *pages;
1367         struct vmcs *vmcs;
1368
1369         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1370         if (!pages)
1371                 return NULL;
1372         vmcs = page_address(pages);
1373         memset(vmcs, 0, vmcs_config.size);
1374         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1375         return vmcs;
1376 }
1377
1378 static struct vmcs *alloc_vmcs(void)
1379 {
1380         return alloc_vmcs_cpu(raw_smp_processor_id());
1381 }
1382
1383 static void free_vmcs(struct vmcs *vmcs)
1384 {
1385         free_pages((unsigned long)vmcs, vmcs_config.order);
1386 }
1387
1388 static void free_kvm_area(void)
1389 {
1390         int cpu;
1391
1392         for_each_possible_cpu(cpu) {
1393                 free_vmcs(per_cpu(vmxarea, cpu));
1394                 per_cpu(vmxarea, cpu) = NULL;
1395         }
1396 }
1397
1398 static __init int alloc_kvm_area(void)
1399 {
1400         int cpu;
1401
1402         for_each_possible_cpu(cpu) {
1403                 struct vmcs *vmcs;
1404
1405                 vmcs = alloc_vmcs_cpu(cpu);
1406                 if (!vmcs) {
1407                         free_kvm_area();
1408                         return -ENOMEM;
1409                 }
1410
1411                 per_cpu(vmxarea, cpu) = vmcs;
1412         }
1413         return 0;
1414 }
1415
1416 static __init int hardware_setup(void)
1417 {
1418         if (setup_vmcs_config(&vmcs_config) < 0)
1419                 return -EIO;
1420
1421         if (boot_cpu_has(X86_FEATURE_NX))
1422                 kvm_enable_efer_bits(EFER_NX);
1423
1424         if (!cpu_has_vmx_vpid())
1425                 enable_vpid = 0;
1426
1427         if (!cpu_has_vmx_ept()) {
1428                 enable_ept = 0;
1429                 enable_unrestricted_guest = 0;
1430         }
1431
1432         if (!cpu_has_vmx_unrestricted_guest())
1433                 enable_unrestricted_guest = 0;
1434
1435         if (!cpu_has_vmx_flexpriority())
1436                 flexpriority_enabled = 0;
1437
1438         if (!cpu_has_vmx_tpr_shadow())
1439                 kvm_x86_ops->update_cr8_intercept = NULL;
1440
1441         if (enable_ept && !cpu_has_vmx_ept_2m_page())
1442                 kvm_disable_largepages();
1443
1444         if (!cpu_has_vmx_ple())
1445                 ple_gap = 0;
1446
1447         return alloc_kvm_area();
1448 }
1449
1450 static __exit void hardware_unsetup(void)
1451 {
1452         free_kvm_area();
1453 }
1454
1455 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1456 {
1457         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1458
1459         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1460                 vmcs_write16(sf->selector, save->selector);
1461                 vmcs_writel(sf->base, save->base);
1462                 vmcs_write32(sf->limit, save->limit);
1463                 vmcs_write32(sf->ar_bytes, save->ar);
1464         } else {
1465                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1466                         << AR_DPL_SHIFT;
1467                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1468         }
1469 }
1470
1471 static void enter_pmode(struct kvm_vcpu *vcpu)
1472 {
1473         unsigned long flags;
1474         struct vcpu_vmx *vmx = to_vmx(vcpu);
1475
1476         vmx->emulation_required = 1;
1477         vmx->rmode.vm86_active = 0;
1478
1479         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1480         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1481         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1482
1483         flags = vmcs_readl(GUEST_RFLAGS);
1484         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1485         flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
1486         vmcs_writel(GUEST_RFLAGS, flags);
1487
1488         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1489                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1490
1491         update_exception_bitmap(vcpu);
1492
1493         if (emulate_invalid_guest_state)
1494                 return;
1495
1496         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1497         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1498         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1499         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1500
1501         vmcs_write16(GUEST_SS_SELECTOR, 0);
1502         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1503
1504         vmcs_write16(GUEST_CS_SELECTOR,
1505                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1506         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1507 }
1508
1509 static gva_t rmode_tss_base(struct kvm *kvm)
1510 {
1511         if (!kvm->arch.tss_addr) {
1512                 struct kvm_memslots *slots;
1513                 gfn_t base_gfn;
1514
1515                 slots = rcu_dereference(kvm->memslots);
1516                 base_gfn = kvm->memslots->memslots[0].base_gfn +
1517                                  kvm->memslots->memslots[0].npages - 3;
1518                 return base_gfn << PAGE_SHIFT;
1519         }
1520         return kvm->arch.tss_addr;
1521 }
1522
1523 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1524 {
1525         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1526
1527         save->selector = vmcs_read16(sf->selector);
1528         save->base = vmcs_readl(sf->base);
1529         save->limit = vmcs_read32(sf->limit);
1530         save->ar = vmcs_read32(sf->ar_bytes);
1531         vmcs_write16(sf->selector, save->base >> 4);
1532         vmcs_write32(sf->base, save->base & 0xfffff);
1533         vmcs_write32(sf->limit, 0xffff);
1534         vmcs_write32(sf->ar_bytes, 0xf3);
1535 }
1536
1537 static void enter_rmode(struct kvm_vcpu *vcpu)
1538 {
1539         unsigned long flags;
1540         struct vcpu_vmx *vmx = to_vmx(vcpu);
1541
1542         if (enable_unrestricted_guest)
1543                 return;
1544
1545         vmx->emulation_required = 1;
1546         vmx->rmode.vm86_active = 1;
1547
1548         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1549         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1550
1551         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1552         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1553
1554         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1555         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1556
1557         flags = vmcs_readl(GUEST_RFLAGS);
1558         vmx->rmode.save_iopl
1559                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1560
1561         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1562
1563         vmcs_writel(GUEST_RFLAGS, flags);
1564         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1565         update_exception_bitmap(vcpu);
1566
1567         if (emulate_invalid_guest_state)
1568                 goto continue_rmode;
1569
1570         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1571         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1572         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1573
1574         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1575         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1576         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1577                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1578         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1579
1580         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1581         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1582         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1583         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1584
1585 continue_rmode:
1586         kvm_mmu_reset_context(vcpu);
1587         init_rmode(vcpu->kvm);
1588 }
1589
1590 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1591 {
1592         struct vcpu_vmx *vmx = to_vmx(vcpu);
1593         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1594
1595         if (!msr)
1596                 return;
1597
1598         /*
1599          * Force kernel_gs_base reloading before EFER changes, as control
1600          * of this msr depends on is_long_mode().
1601          */
1602         vmx_load_host_state(to_vmx(vcpu));
1603         vcpu->arch.shadow_efer = efer;
1604         if (!msr)
1605                 return;
1606         if (efer & EFER_LMA) {
1607                 vmcs_write32(VM_ENTRY_CONTROLS,
1608                              vmcs_read32(VM_ENTRY_CONTROLS) |
1609                              VM_ENTRY_IA32E_MODE);
1610                 msr->data = efer;
1611         } else {
1612                 vmcs_write32(VM_ENTRY_CONTROLS,
1613                              vmcs_read32(VM_ENTRY_CONTROLS) &
1614                              ~VM_ENTRY_IA32E_MODE);
1615
1616                 msr->data = efer & ~EFER_LME;
1617         }
1618         setup_msrs(vmx);
1619 }
1620
1621 #ifdef CONFIG_X86_64
1622
1623 static void enter_lmode(struct kvm_vcpu *vcpu)
1624 {
1625         u32 guest_tr_ar;
1626
1627         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1628         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1629                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1630                        __func__);
1631                 vmcs_write32(GUEST_TR_AR_BYTES,
1632                              (guest_tr_ar & ~AR_TYPE_MASK)
1633                              | AR_TYPE_BUSY_64_TSS);
1634         }
1635         vcpu->arch.shadow_efer |= EFER_LMA;
1636         vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
1637 }
1638
1639 static void exit_lmode(struct kvm_vcpu *vcpu)
1640 {
1641         vcpu->arch.shadow_efer &= ~EFER_LMA;
1642
1643         vmcs_write32(VM_ENTRY_CONTROLS,
1644                      vmcs_read32(VM_ENTRY_CONTROLS)
1645                      & ~VM_ENTRY_IA32E_MODE);
1646 }
1647
1648 #endif
1649
1650 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1651 {
1652         vpid_sync_vcpu_all(to_vmx(vcpu));
1653         if (enable_ept)
1654                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1655 }
1656
1657 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1658 {
1659         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1660
1661         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1662         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1663 }
1664
1665 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1666 {
1667         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1668
1669         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1670         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1671 }
1672
1673 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1674 {
1675         if (!test_bit(VCPU_EXREG_PDPTR,
1676                       (unsigned long *)&vcpu->arch.regs_dirty))
1677                 return;
1678
1679         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1680                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1681                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1682                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1683                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1684         }
1685 }
1686
1687 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1688 {
1689         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1690                 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1691                 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1692                 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1693                 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1694         }
1695
1696         __set_bit(VCPU_EXREG_PDPTR,
1697                   (unsigned long *)&vcpu->arch.regs_avail);
1698         __set_bit(VCPU_EXREG_PDPTR,
1699                   (unsigned long *)&vcpu->arch.regs_dirty);
1700 }
1701
1702 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1703
1704 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1705                                         unsigned long cr0,
1706                                         struct kvm_vcpu *vcpu)
1707 {
1708         if (!(cr0 & X86_CR0_PG)) {
1709                 /* From paging/starting to nonpaging */
1710                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1711                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1712                              (CPU_BASED_CR3_LOAD_EXITING |
1713                               CPU_BASED_CR3_STORE_EXITING));
1714                 vcpu->arch.cr0 = cr0;
1715                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1716         } else if (!is_paging(vcpu)) {
1717                 /* From nonpaging to paging */
1718                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1719                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1720                              ~(CPU_BASED_CR3_LOAD_EXITING |
1721                                CPU_BASED_CR3_STORE_EXITING));
1722                 vcpu->arch.cr0 = cr0;
1723                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1724         }
1725
1726         if (!(cr0 & X86_CR0_WP))
1727                 *hw_cr0 &= ~X86_CR0_WP;
1728 }
1729
1730 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1731 {
1732         struct vcpu_vmx *vmx = to_vmx(vcpu);
1733         unsigned long hw_cr0;
1734
1735         if (enable_unrestricted_guest)
1736                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1737                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1738         else
1739                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1740
1741         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1742                 enter_pmode(vcpu);
1743
1744         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1745                 enter_rmode(vcpu);
1746
1747 #ifdef CONFIG_X86_64
1748         if (vcpu->arch.shadow_efer & EFER_LME) {
1749                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1750                         enter_lmode(vcpu);
1751                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1752                         exit_lmode(vcpu);
1753         }
1754 #endif
1755
1756         if (enable_ept)
1757                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1758
1759         if (!vcpu->fpu_active)
1760                 hw_cr0 |= X86_CR0_TS;
1761
1762         vmcs_writel(CR0_READ_SHADOW, cr0);
1763         vmcs_writel(GUEST_CR0, hw_cr0);
1764         vcpu->arch.cr0 = cr0;
1765 }
1766
1767 static u64 construct_eptp(unsigned long root_hpa)
1768 {
1769         u64 eptp;
1770
1771         /* TODO write the value reading from MSR */
1772         eptp = VMX_EPT_DEFAULT_MT |
1773                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1774         eptp |= (root_hpa & PAGE_MASK);
1775
1776         return eptp;
1777 }
1778
1779 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1780 {
1781         unsigned long guest_cr3;
1782         u64 eptp;
1783
1784         guest_cr3 = cr3;
1785         if (enable_ept) {
1786                 eptp = construct_eptp(cr3);
1787                 vmcs_write64(EPT_POINTER, eptp);
1788                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1789                         vcpu->kvm->arch.ept_identity_map_addr;
1790                 ept_load_pdptrs(vcpu);
1791         }
1792
1793         vmx_flush_tlb(vcpu);
1794         vmcs_writel(GUEST_CR3, guest_cr3);
1795 }
1796
1797 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1798 {
1799         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1800                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1801
1802         vcpu->arch.cr4 = cr4;
1803         if (enable_ept) {
1804                 if (!is_paging(vcpu)) {
1805                         hw_cr4 &= ~X86_CR4_PAE;
1806                         hw_cr4 |= X86_CR4_PSE;
1807                 } else if (!(cr4 & X86_CR4_PAE)) {
1808                         hw_cr4 &= ~X86_CR4_PAE;
1809                 }
1810         }
1811
1812         vmcs_writel(CR4_READ_SHADOW, cr4);
1813         vmcs_writel(GUEST_CR4, hw_cr4);
1814 }
1815
1816 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1817 {
1818         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1819
1820         return vmcs_readl(sf->base);
1821 }
1822
1823 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1824                             struct kvm_segment *var, int seg)
1825 {
1826         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1827         u32 ar;
1828
1829         var->base = vmcs_readl(sf->base);
1830         var->limit = vmcs_read32(sf->limit);
1831         var->selector = vmcs_read16(sf->selector);
1832         ar = vmcs_read32(sf->ar_bytes);
1833         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1834                 ar = 0;
1835         var->type = ar & 15;
1836         var->s = (ar >> 4) & 1;
1837         var->dpl = (ar >> 5) & 3;
1838         var->present = (ar >> 7) & 1;
1839         var->avl = (ar >> 12) & 1;
1840         var->l = (ar >> 13) & 1;
1841         var->db = (ar >> 14) & 1;
1842         var->g = (ar >> 15) & 1;
1843         var->unusable = (ar >> 16) & 1;
1844 }
1845
1846 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1847 {
1848         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) /* if real mode */
1849                 return 0;
1850
1851         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1852                 return 3;
1853
1854         return vmcs_read16(GUEST_CS_SELECTOR) & 3;
1855 }
1856
1857 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1858 {
1859         u32 ar;
1860
1861         if (var->unusable)
1862                 ar = 1 << 16;
1863         else {
1864                 ar = var->type & 15;
1865                 ar |= (var->s & 1) << 4;
1866                 ar |= (var->dpl & 3) << 5;
1867                 ar |= (var->present & 1) << 7;
1868                 ar |= (var->avl & 1) << 12;
1869                 ar |= (var->l & 1) << 13;
1870                 ar |= (var->db & 1) << 14;
1871                 ar |= (var->g & 1) << 15;
1872         }
1873         if (ar == 0) /* a 0 value means unusable */
1874                 ar = AR_UNUSABLE_MASK;
1875
1876         return ar;
1877 }
1878
1879 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1880                             struct kvm_segment *var, int seg)
1881 {
1882         struct vcpu_vmx *vmx = to_vmx(vcpu);
1883         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1884         u32 ar;
1885
1886         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1887                 vmx->rmode.tr.selector = var->selector;
1888                 vmx->rmode.tr.base = var->base;
1889                 vmx->rmode.tr.limit = var->limit;
1890                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
1891                 return;
1892         }
1893         vmcs_writel(sf->base, var->base);
1894         vmcs_write32(sf->limit, var->limit);
1895         vmcs_write16(sf->selector, var->selector);
1896         if (vmx->rmode.vm86_active && var->s) {
1897                 /*
1898                  * Hack real-mode segments into vm86 compatibility.
1899                  */
1900                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1901                         vmcs_writel(sf->base, 0xf0000);
1902                 ar = 0xf3;
1903         } else
1904                 ar = vmx_segment_access_rights(var);
1905
1906         /*
1907          *   Fix the "Accessed" bit in AR field of segment registers for older
1908          * qemu binaries.
1909          *   IA32 arch specifies that at the time of processor reset the
1910          * "Accessed" bit in the AR field of segment registers is 1. And qemu
1911          * is setting it to 0 in the usedland code. This causes invalid guest
1912          * state vmexit when "unrestricted guest" mode is turned on.
1913          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
1914          * tree. Newer qemu binaries with that qemu fix would not need this
1915          * kvm hack.
1916          */
1917         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1918                 ar |= 0x1; /* Accessed */
1919
1920         vmcs_write32(sf->ar_bytes, ar);
1921 }
1922
1923 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1924 {
1925         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1926
1927         *db = (ar >> 14) & 1;
1928         *l = (ar >> 13) & 1;
1929 }
1930
1931 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1932 {
1933         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1934         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1935 }
1936
1937 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1938 {
1939         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1940         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1941 }
1942
1943 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1944 {
1945         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1946         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1947 }
1948
1949 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1950 {
1951         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1952         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1953 }
1954
1955 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1956 {
1957         struct kvm_segment var;
1958         u32 ar;
1959
1960         vmx_get_segment(vcpu, &var, seg);
1961         ar = vmx_segment_access_rights(&var);
1962
1963         if (var.base != (var.selector << 4))
1964                 return false;
1965         if (var.limit != 0xffff)
1966                 return false;
1967         if (ar != 0xf3)
1968                 return false;
1969
1970         return true;
1971 }
1972
1973 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1974 {
1975         struct kvm_segment cs;
1976         unsigned int cs_rpl;
1977
1978         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1979         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1980
1981         if (cs.unusable)
1982                 return false;
1983         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1984                 return false;
1985         if (!cs.s)
1986                 return false;
1987         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1988                 if (cs.dpl > cs_rpl)
1989                         return false;
1990         } else {
1991                 if (cs.dpl != cs_rpl)
1992                         return false;
1993         }
1994         if (!cs.present)
1995                 return false;
1996
1997         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1998         return true;
1999 }
2000
2001 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2002 {
2003         struct kvm_segment ss;
2004         unsigned int ss_rpl;
2005
2006         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2007         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2008
2009         if (ss.unusable)
2010                 return true;
2011         if (ss.type != 3 && ss.type != 7)
2012                 return false;
2013         if (!ss.s)
2014                 return false;
2015         if (ss.dpl != ss_rpl) /* DPL != RPL */
2016                 return false;
2017         if (!ss.present)
2018                 return false;
2019
2020         return true;
2021 }
2022
2023 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2024 {
2025         struct kvm_segment var;
2026         unsigned int rpl;
2027
2028         vmx_get_segment(vcpu, &var, seg);
2029         rpl = var.selector & SELECTOR_RPL_MASK;
2030
2031         if (var.unusable)
2032                 return true;
2033         if (!var.s)
2034                 return false;
2035         if (!var.present)
2036                 return false;
2037         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2038                 if (var.dpl < rpl) /* DPL < RPL */
2039                         return false;
2040         }
2041
2042         /* TODO: Add other members to kvm_segment_field to allow checking for other access
2043          * rights flags
2044          */
2045         return true;
2046 }
2047
2048 static bool tr_valid(struct kvm_vcpu *vcpu)
2049 {
2050         struct kvm_segment tr;
2051
2052         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2053
2054         if (tr.unusable)
2055                 return false;
2056         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
2057                 return false;
2058         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2059                 return false;
2060         if (!tr.present)
2061                 return false;
2062
2063         return true;
2064 }
2065
2066 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2067 {
2068         struct kvm_segment ldtr;
2069
2070         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2071
2072         if (ldtr.unusable)
2073                 return true;
2074         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
2075                 return false;
2076         if (ldtr.type != 2)
2077                 return false;
2078         if (!ldtr.present)
2079                 return false;
2080
2081         return true;
2082 }
2083
2084 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2085 {
2086         struct kvm_segment cs, ss;
2087
2088         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2089         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2090
2091         return ((cs.selector & SELECTOR_RPL_MASK) ==
2092                  (ss.selector & SELECTOR_RPL_MASK));
2093 }
2094
2095 /*
2096  * Check if guest state is valid. Returns true if valid, false if
2097  * not.
2098  * We assume that registers are always usable
2099  */
2100 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2101 {
2102         /* real mode guest state checks */
2103         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
2104                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2105                         return false;
2106                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2107                         return false;
2108                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2109                         return false;
2110                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2111                         return false;
2112                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2113                         return false;
2114                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2115                         return false;
2116         } else {
2117         /* protected mode guest state checks */
2118                 if (!cs_ss_rpl_check(vcpu))
2119                         return false;
2120                 if (!code_segment_valid(vcpu))
2121                         return false;
2122                 if (!stack_segment_valid(vcpu))
2123                         return false;
2124                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2125                         return false;
2126                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2127                         return false;
2128                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2129                         return false;
2130                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2131                         return false;
2132                 if (!tr_valid(vcpu))
2133                         return false;
2134                 if (!ldtr_valid(vcpu))
2135                         return false;
2136         }
2137         /* TODO:
2138          * - Add checks on RIP
2139          * - Add checks on RFLAGS
2140          */
2141
2142         return true;
2143 }
2144
2145 static int init_rmode_tss(struct kvm *kvm)
2146 {
2147         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2148         u16 data = 0;
2149         int ret = 0;
2150         int r;
2151
2152         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2153         if (r < 0)
2154                 goto out;
2155         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2156         r = kvm_write_guest_page(kvm, fn++, &data,
2157                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
2158         if (r < 0)
2159                 goto out;
2160         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2161         if (r < 0)
2162                 goto out;
2163         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2164         if (r < 0)
2165                 goto out;
2166         data = ~0;
2167         r = kvm_write_guest_page(kvm, fn, &data,
2168                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2169                                  sizeof(u8));
2170         if (r < 0)
2171                 goto out;
2172
2173         ret = 1;
2174 out:
2175         return ret;
2176 }
2177
2178 static int init_rmode_identity_map(struct kvm *kvm)
2179 {
2180         int i, r, ret;
2181         pfn_t identity_map_pfn;
2182         u32 tmp;
2183
2184         if (!enable_ept)
2185                 return 1;
2186         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2187                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2188                         "haven't been allocated!\n");
2189                 return 0;
2190         }
2191         if (likely(kvm->arch.ept_identity_pagetable_done))
2192                 return 1;
2193         ret = 0;
2194         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2195         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2196         if (r < 0)
2197                 goto out;
2198         /* Set up identity-mapping pagetable for EPT in real mode */
2199         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2200                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2201                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2202                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2203                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2204                 if (r < 0)
2205                         goto out;
2206         }
2207         kvm->arch.ept_identity_pagetable_done = true;
2208         ret = 1;
2209 out:
2210         return ret;
2211 }
2212
2213 static void seg_setup(int seg)
2214 {
2215         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2216         unsigned int ar;
2217
2218         vmcs_write16(sf->selector, 0);
2219         vmcs_writel(sf->base, 0);
2220         vmcs_write32(sf->limit, 0xffff);
2221         if (enable_unrestricted_guest) {
2222                 ar = 0x93;
2223                 if (seg == VCPU_SREG_CS)
2224                         ar |= 0x08; /* code segment */
2225         } else
2226                 ar = 0xf3;
2227
2228         vmcs_write32(sf->ar_bytes, ar);
2229 }
2230
2231 static int alloc_apic_access_page(struct kvm *kvm)
2232 {
2233         struct kvm_userspace_memory_region kvm_userspace_mem;
2234         int r = 0;
2235
2236         mutex_lock(&kvm->slots_lock);
2237         if (kvm->arch.apic_access_page)
2238                 goto out;
2239         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2240         kvm_userspace_mem.flags = 0;
2241         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2242         kvm_userspace_mem.memory_size = PAGE_SIZE;
2243         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2244         if (r)
2245                 goto out;
2246
2247         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2248 out:
2249         mutex_unlock(&kvm->slots_lock);
2250         return r;
2251 }
2252
2253 static int alloc_identity_pagetable(struct kvm *kvm)
2254 {
2255         struct kvm_userspace_memory_region kvm_userspace_mem;
2256         int r = 0;
2257
2258         mutex_lock(&kvm->slots_lock);
2259         if (kvm->arch.ept_identity_pagetable)
2260                 goto out;
2261         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2262         kvm_userspace_mem.flags = 0;
2263         kvm_userspace_mem.guest_phys_addr =
2264                 kvm->arch.ept_identity_map_addr;
2265         kvm_userspace_mem.memory_size = PAGE_SIZE;
2266         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2267         if (r)
2268                 goto out;
2269
2270         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2271                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2272 out:
2273         mutex_unlock(&kvm->slots_lock);
2274         return r;
2275 }
2276
2277 static void allocate_vpid(struct vcpu_vmx *vmx)
2278 {
2279         int vpid;
2280
2281         vmx->vpid = 0;
2282         if (!enable_vpid)
2283                 return;
2284         spin_lock(&vmx_vpid_lock);
2285         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2286         if (vpid < VMX_NR_VPIDS) {
2287                 vmx->vpid = vpid;
2288                 __set_bit(vpid, vmx_vpid_bitmap);
2289         }
2290         spin_unlock(&vmx_vpid_lock);
2291 }
2292
2293 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2294 {
2295         int f = sizeof(unsigned long);
2296
2297         if (!cpu_has_vmx_msr_bitmap())
2298                 return;
2299
2300         /*
2301          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2302          * have the write-low and read-high bitmap offsets the wrong way round.
2303          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2304          */
2305         if (msr <= 0x1fff) {
2306                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2307                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2308         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2309                 msr &= 0x1fff;
2310                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2311                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2312         }
2313 }
2314
2315 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2316 {
2317         if (!longmode_only)
2318                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2319         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2320 }
2321
2322 /*
2323  * Sets up the vmcs for emulated real mode.
2324  */
2325 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2326 {
2327         u32 host_sysenter_cs, msr_low, msr_high;
2328         u32 junk;
2329         u64 host_pat, tsc_this, tsc_base;
2330         unsigned long a;
2331         struct descriptor_table dt;
2332         int i;
2333         unsigned long kvm_vmx_return;
2334         u32 exec_control;
2335
2336         /* I/O */
2337         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2338         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2339
2340         if (cpu_has_vmx_msr_bitmap())
2341                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2342
2343         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2344
2345         /* Control */
2346         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2347                 vmcs_config.pin_based_exec_ctrl);
2348
2349         exec_control = vmcs_config.cpu_based_exec_ctrl;
2350         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2351                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2352 #ifdef CONFIG_X86_64
2353                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2354                                 CPU_BASED_CR8_LOAD_EXITING;
2355 #endif
2356         }
2357         if (!enable_ept)
2358                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2359                                 CPU_BASED_CR3_LOAD_EXITING  |
2360                                 CPU_BASED_INVLPG_EXITING;
2361         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2362
2363         if (cpu_has_secondary_exec_ctrls()) {
2364                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2365                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2366                         exec_control &=
2367                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2368                 if (vmx->vpid == 0)
2369                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2370                 if (!enable_ept) {
2371                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2372                         enable_unrestricted_guest = 0;
2373                 }
2374                 if (!enable_unrestricted_guest)
2375                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2376                 if (!ple_gap)
2377                         exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2378                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2379         }
2380
2381         if (ple_gap) {
2382                 vmcs_write32(PLE_GAP, ple_gap);
2383                 vmcs_write32(PLE_WINDOW, ple_window);
2384         }
2385
2386         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2387         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2388         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2389
2390         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
2391         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2392         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2393
2394         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2395         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2396         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2397         vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs());    /* 22.2.4 */
2398         vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs());    /* 22.2.4 */
2399         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2400 #ifdef CONFIG_X86_64
2401         rdmsrl(MSR_FS_BASE, a);
2402         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2403         rdmsrl(MSR_GS_BASE, a);
2404         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2405 #else
2406         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2407         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2408 #endif
2409
2410         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2411
2412         kvm_get_idt(&dt);
2413         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
2414
2415         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2416         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2417         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2418         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2419         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2420
2421         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2422         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2423         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2424         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2425         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2426         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2427
2428         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2429                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2430                 host_pat = msr_low | ((u64) msr_high << 32);
2431                 vmcs_write64(HOST_IA32_PAT, host_pat);
2432         }
2433         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2434                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2435                 host_pat = msr_low | ((u64) msr_high << 32);
2436                 /* Write the default value follow host pat */
2437                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2438                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2439                 vmx->vcpu.arch.pat = host_pat;
2440         }
2441
2442         for (i = 0; i < NR_VMX_MSR; ++i) {
2443                 u32 index = vmx_msr_index[i];
2444                 u32 data_low, data_high;
2445                 int j = vmx->nmsrs;
2446
2447                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2448                         continue;
2449                 if (wrmsr_safe(index, data_low, data_high) < 0)
2450                         continue;
2451                 vmx->guest_msrs[j].index = i;
2452                 vmx->guest_msrs[j].data = 0;
2453                 vmx->guest_msrs[j].mask = -1ull;
2454                 ++vmx->nmsrs;
2455         }
2456
2457         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2458
2459         /* 22.2.1, 20.8.1 */
2460         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2461
2462         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2463         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2464         if (enable_ept)
2465                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2466         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2467
2468         tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2469         rdtscll(tsc_this);
2470         if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2471                 tsc_base = tsc_this;
2472
2473         guest_write_tsc(0, tsc_base);
2474
2475         return 0;
2476 }
2477
2478 static int init_rmode(struct kvm *kvm)
2479 {
2480         if (!init_rmode_tss(kvm))
2481                 return 0;
2482         if (!init_rmode_identity_map(kvm))
2483                 return 0;
2484         return 1;
2485 }
2486
2487 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2488 {
2489         struct vcpu_vmx *vmx = to_vmx(vcpu);
2490         u64 msr;
2491         int ret, idx;
2492
2493         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2494         idx = srcu_read_lock(&vcpu->kvm->srcu);
2495         if (!init_rmode(vmx->vcpu.kvm)) {
2496                 ret = -ENOMEM;
2497                 goto out;
2498         }
2499
2500         vmx->rmode.vm86_active = 0;
2501
2502         vmx->soft_vnmi_blocked = 0;
2503
2504         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2505         kvm_set_cr8(&vmx->vcpu, 0);
2506         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2507         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2508                 msr |= MSR_IA32_APICBASE_BSP;
2509         kvm_set_apic_base(&vmx->vcpu, msr);
2510
2511         fx_init(&vmx->vcpu);
2512
2513         seg_setup(VCPU_SREG_CS);
2514         /*
2515          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2516          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2517          */
2518         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2519                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2520                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2521         } else {
2522                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2523                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2524         }
2525
2526         seg_setup(VCPU_SREG_DS);
2527         seg_setup(VCPU_SREG_ES);
2528         seg_setup(VCPU_SREG_FS);
2529         seg_setup(VCPU_SREG_GS);
2530         seg_setup(VCPU_SREG_SS);
2531
2532         vmcs_write16(GUEST_TR_SELECTOR, 0);
2533         vmcs_writel(GUEST_TR_BASE, 0);
2534         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2535         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2536
2537         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2538         vmcs_writel(GUEST_LDTR_BASE, 0);
2539         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2540         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2541
2542         vmcs_write32(GUEST_SYSENTER_CS, 0);
2543         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2544         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2545
2546         vmcs_writel(GUEST_RFLAGS, 0x02);
2547         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2548                 kvm_rip_write(vcpu, 0xfff0);
2549         else
2550                 kvm_rip_write(vcpu, 0);
2551         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2552
2553         vmcs_writel(GUEST_DR7, 0x400);
2554
2555         vmcs_writel(GUEST_GDTR_BASE, 0);
2556         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2557
2558         vmcs_writel(GUEST_IDTR_BASE, 0);
2559         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2560
2561         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2562         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2563         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2564
2565         /* Special registers */
2566         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2567
2568         setup_msrs(vmx);
2569
2570         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2571
2572         if (cpu_has_vmx_tpr_shadow()) {
2573                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2574                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2575                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2576                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2577                 vmcs_write32(TPR_THRESHOLD, 0);
2578         }
2579
2580         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2581                 vmcs_write64(APIC_ACCESS_ADDR,
2582                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2583
2584         if (vmx->vpid != 0)
2585                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2586
2587         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2588         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2589         vmx_set_cr4(&vmx->vcpu, 0);
2590         vmx_set_efer(&vmx->vcpu, 0);
2591         vmx_fpu_activate(&vmx->vcpu);
2592         update_exception_bitmap(&vmx->vcpu);
2593
2594         vpid_sync_vcpu_all(vmx);
2595
2596         ret = 0;
2597
2598         /* HACK: Don't enable emulation on guest boot/reset */
2599         vmx->emulation_required = 0;
2600
2601 out:
2602         srcu_read_unlock(&vcpu->kvm->srcu, idx);
2603         return ret;
2604 }
2605
2606 static void enable_irq_window(struct kvm_vcpu *vcpu)
2607 {
2608         u32 cpu_based_vm_exec_control;
2609
2610         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2611         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2612         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2613 }
2614
2615 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2616 {
2617         u32 cpu_based_vm_exec_control;
2618
2619         if (!cpu_has_virtual_nmis()) {
2620                 enable_irq_window(vcpu);
2621                 return;
2622         }
2623
2624         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2625         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2626         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2627 }
2628
2629 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2630 {
2631         struct vcpu_vmx *vmx = to_vmx(vcpu);
2632         uint32_t intr;
2633         int irq = vcpu->arch.interrupt.nr;
2634
2635         trace_kvm_inj_virq(irq);
2636
2637         ++vcpu->stat.irq_injections;
2638         if (vmx->rmode.vm86_active) {
2639                 vmx->rmode.irq.pending = true;
2640                 vmx->rmode.irq.vector = irq;
2641                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2642                 if (vcpu->arch.interrupt.soft)
2643                         vmx->rmode.irq.rip +=
2644                                 vmx->vcpu.arch.event_exit_inst_len;
2645                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2646                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2647                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2648                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2649                 return;
2650         }
2651         intr = irq | INTR_INFO_VALID_MASK;
2652         if (vcpu->arch.interrupt.soft) {
2653                 intr |= INTR_TYPE_SOFT_INTR;
2654                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2655                              vmx->vcpu.arch.event_exit_inst_len);
2656         } else
2657                 intr |= INTR_TYPE_EXT_INTR;
2658         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2659 }
2660
2661 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2662 {
2663         struct vcpu_vmx *vmx = to_vmx(vcpu);
2664
2665         if (!cpu_has_virtual_nmis()) {
2666                 /*
2667                  * Tracking the NMI-blocked state in software is built upon
2668                  * finding the next open IRQ window. This, in turn, depends on
2669                  * well-behaving guests: They have to keep IRQs disabled at
2670                  * least as long as the NMI handler runs. Otherwise we may
2671                  * cause NMI nesting, maybe breaking the guest. But as this is
2672                  * highly unlikely, we can live with the residual risk.
2673                  */
2674                 vmx->soft_vnmi_blocked = 1;
2675                 vmx->vnmi_blocked_time = 0;
2676         }
2677
2678         ++vcpu->stat.nmi_injections;
2679         if (vmx->rmode.vm86_active) {
2680                 vmx->rmode.irq.pending = true;
2681                 vmx->rmode.irq.vector = NMI_VECTOR;
2682                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2683                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2684                              NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2685                              INTR_INFO_VALID_MASK);
2686                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2687                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2688                 return;
2689         }
2690         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2691                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2692 }
2693
2694 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2695 {
2696         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2697                 return 0;
2698
2699         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2700                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2701                                 GUEST_INTR_STATE_NMI));
2702 }
2703
2704 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2705 {
2706         if (!cpu_has_virtual_nmis())
2707                 return to_vmx(vcpu)->soft_vnmi_blocked;
2708         else
2709                 return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2710                           GUEST_INTR_STATE_NMI);
2711 }
2712
2713 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2714 {
2715         struct vcpu_vmx *vmx = to_vmx(vcpu);
2716
2717         if (!cpu_has_virtual_nmis()) {
2718                 if (vmx->soft_vnmi_blocked != masked) {
2719                         vmx->soft_vnmi_blocked = masked;
2720                         vmx->vnmi_blocked_time = 0;
2721                 }
2722         } else {
2723                 if (masked)
2724                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2725                                       GUEST_INTR_STATE_NMI);
2726                 else
2727                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2728                                         GUEST_INTR_STATE_NMI);
2729         }
2730 }
2731
2732 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2733 {
2734         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2735                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2736                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2737 }
2738
2739 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2740 {
2741         int ret;
2742         struct kvm_userspace_memory_region tss_mem = {
2743                 .slot = TSS_PRIVATE_MEMSLOT,
2744                 .guest_phys_addr = addr,
2745                 .memory_size = PAGE_SIZE * 3,
2746                 .flags = 0,
2747         };
2748
2749         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2750         if (ret)
2751                 return ret;
2752         kvm->arch.tss_addr = addr;
2753         return 0;
2754 }
2755
2756 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2757                                   int vec, u32 err_code)
2758 {
2759         /*
2760          * Instruction with address size override prefix opcode 0x67
2761          * Cause the #SS fault with 0 error code in VM86 mode.
2762          */
2763         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2764                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2765                         return 1;
2766         /*
2767          * Forward all other exceptions that are valid in real mode.
2768          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2769          *        the required debugging infrastructure rework.
2770          */
2771         switch (vec) {
2772         case DB_VECTOR:
2773                 if (vcpu->guest_debug &
2774                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2775                         return 0;
2776                 kvm_queue_exception(vcpu, vec);
2777                 return 1;
2778         case BP_VECTOR:
2779                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2780                         return 0;
2781                 /* fall through */
2782         case DE_VECTOR:
2783         case OF_VECTOR:
2784         case BR_VECTOR:
2785         case UD_VECTOR:
2786         case DF_VECTOR:
2787         case SS_VECTOR:
2788         case GP_VECTOR:
2789         case MF_VECTOR:
2790                 kvm_queue_exception(vcpu, vec);
2791                 return 1;
2792         }
2793         return 0;
2794 }
2795
2796 /*
2797  * Trigger machine check on the host. We assume all the MSRs are already set up
2798  * by the CPU and that we still run on the same CPU as the MCE occurred on.
2799  * We pass a fake environment to the machine check handler because we want
2800  * the guest to be always treated like user space, no matter what context
2801  * it used internally.
2802  */
2803 static void kvm_machine_check(void)
2804 {
2805 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2806         struct pt_regs regs = {
2807                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2808                 .flags = X86_EFLAGS_IF,
2809         };
2810
2811         do_machine_check(&regs, 0);
2812 #endif
2813 }
2814
2815 static int handle_machine_check(struct kvm_vcpu *vcpu)
2816 {
2817         /* already handled by vcpu_run */
2818         return 1;
2819 }
2820
2821 static int handle_exception(struct kvm_vcpu *vcpu)
2822 {
2823         struct vcpu_vmx *vmx = to_vmx(vcpu);
2824         struct kvm_run *kvm_run = vcpu->run;
2825         u32 intr_info, ex_no, error_code;
2826         unsigned long cr2, rip, dr6;
2827         u32 vect_info;
2828         enum emulation_result er;
2829
2830         vect_info = vmx->idt_vectoring_info;
2831         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2832
2833         if (is_machine_check(intr_info))
2834                 return handle_machine_check(vcpu);
2835
2836         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2837             !is_page_fault(intr_info)) {
2838                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2839                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2840                 vcpu->run->internal.ndata = 2;
2841                 vcpu->run->internal.data[0] = vect_info;
2842                 vcpu->run->internal.data[1] = intr_info;
2843                 return 0;
2844         }
2845
2846         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2847                 return 1;  /* already handled by vmx_vcpu_run() */
2848
2849         if (is_no_device(intr_info)) {
2850                 vmx_fpu_activate(vcpu);
2851                 return 1;
2852         }
2853
2854         if (is_invalid_opcode(intr_info)) {
2855                 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
2856                 if (er != EMULATE_DONE)
2857                         kvm_queue_exception(vcpu, UD_VECTOR);
2858                 return 1;
2859         }
2860
2861         error_code = 0;
2862         rip = kvm_rip_read(vcpu);
2863         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2864                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2865         if (is_page_fault(intr_info)) {
2866                 /* EPT won't cause page fault directly */
2867                 if (enable_ept)
2868                         BUG();
2869                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2870                 trace_kvm_page_fault(cr2, error_code);
2871
2872                 if (kvm_event_needs_reinjection(vcpu))
2873                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
2874                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2875         }
2876
2877         if (vmx->rmode.vm86_active &&
2878             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2879                                                                 error_code)) {
2880                 if (vcpu->arch.halt_request) {
2881                         vcpu->arch.halt_request = 0;
2882                         return kvm_emulate_halt(vcpu);
2883                 }
2884                 return 1;
2885         }
2886
2887         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2888         switch (ex_no) {
2889         case DB_VECTOR:
2890                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2891                 if (!(vcpu->guest_debug &
2892                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2893                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2894                         kvm_queue_exception(vcpu, DB_VECTOR);
2895                         return 1;
2896                 }
2897                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2898                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2899                 /* fall through */
2900         case BP_VECTOR:
2901                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2902                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2903                 kvm_run->debug.arch.exception = ex_no;
2904                 break;
2905         default:
2906                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2907                 kvm_run->ex.exception = ex_no;
2908                 kvm_run->ex.error_code = error_code;
2909                 break;
2910         }
2911         return 0;
2912 }
2913
2914 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
2915 {
2916         ++vcpu->stat.irq_exits;
2917         return 1;
2918 }
2919
2920 static int handle_triple_fault(struct kvm_vcpu *vcpu)
2921 {
2922         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
2923         return 0;
2924 }
2925
2926 static int handle_io(struct kvm_vcpu *vcpu)
2927 {
2928         unsigned long exit_qualification;
2929         int size, in, string;
2930         unsigned port;
2931
2932         ++vcpu->stat.io_exits;
2933         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2934         string = (exit_qualification & 16) != 0;
2935
2936         if (string) {
2937                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO)
2938                         return 0;
2939                 return 1;
2940         }
2941
2942         size = (exit_qualification & 7) + 1;
2943         in = (exit_qualification & 8) != 0;
2944         port = exit_qualification >> 16;
2945
2946         skip_emulated_instruction(vcpu);
2947         return kvm_emulate_pio(vcpu, in, size, port);
2948 }
2949
2950 static void
2951 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2952 {
2953         /*
2954          * Patch in the VMCALL instruction:
2955          */
2956         hypercall[0] = 0x0f;
2957         hypercall[1] = 0x01;
2958         hypercall[2] = 0xc1;
2959 }
2960
2961 static int handle_cr(struct kvm_vcpu *vcpu)
2962 {
2963         unsigned long exit_qualification, val;
2964         int cr;
2965         int reg;
2966
2967         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2968         cr = exit_qualification & 15;
2969         reg = (exit_qualification >> 8) & 15;
2970         switch ((exit_qualification >> 4) & 3) {
2971         case 0: /* mov to cr */
2972                 val = kvm_register_read(vcpu, reg);
2973                 trace_kvm_cr_write(cr, val);
2974                 switch (cr) {
2975                 case 0:
2976                         kvm_set_cr0(vcpu, val);
2977                         skip_emulated_instruction(vcpu);
2978                         return 1;
2979                 case 3:
2980                         kvm_set_cr3(vcpu, val);
2981                         skip_emulated_instruction(vcpu);
2982                         return 1;
2983                 case 4:
2984                         kvm_set_cr4(vcpu, val);
2985                         skip_emulated_instruction(vcpu);
2986                         return 1;
2987                 case 8: {
2988                                 u8 cr8_prev = kvm_get_cr8(vcpu);
2989                                 u8 cr8 = kvm_register_read(vcpu, reg);
2990                                 kvm_set_cr8(vcpu, cr8);
2991                                 skip_emulated_instruction(vcpu);
2992                                 if (irqchip_in_kernel(vcpu->kvm))
2993                                         return 1;
2994                                 if (cr8_prev <= cr8)
2995                                         return 1;
2996                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
2997                                 return 0;
2998                         }
2999                 };
3000                 break;
3001         case 2: /* clts */
3002                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3003                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3004                 skip_emulated_instruction(vcpu);
3005                 vmx_fpu_activate(vcpu);
3006                 return 1;
3007         case 1: /*mov from cr*/
3008                 switch (cr) {
3009                 case 3:
3010                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
3011                         trace_kvm_cr_read(cr, vcpu->arch.cr3);
3012                         skip_emulated_instruction(vcpu);
3013                         return 1;
3014                 case 8:
3015                         val = kvm_get_cr8(vcpu);
3016                         kvm_register_write(vcpu, reg, val);
3017                         trace_kvm_cr_read(cr, val);
3018                         skip_emulated_instruction(vcpu);
3019                         return 1;
3020                 }
3021                 break;
3022         case 3: /* lmsw */
3023                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3024                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3025                 kvm_lmsw(vcpu, val);
3026
3027                 skip_emulated_instruction(vcpu);
3028                 return 1;
3029         default:
3030                 break;
3031         }
3032         vcpu->run->exit_reason = 0;
3033         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3034                (int)(exit_qualification >> 4) & 3, cr);
3035         return 0;
3036 }
3037
3038 static int check_dr_alias(struct kvm_vcpu *vcpu)
3039 {
3040         if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
3041                 kvm_queue_exception(vcpu, UD_VECTOR);
3042                 return -1;
3043         }
3044         return 0;
3045 }
3046
3047 static int handle_dr(struct kvm_vcpu *vcpu)
3048 {
3049         unsigned long exit_qualification;
3050         unsigned long val;
3051         int dr, reg;
3052
3053         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3054         if (!kvm_require_cpl(vcpu, 0))
3055                 return 1;
3056         dr = vmcs_readl(GUEST_DR7);
3057         if (dr & DR7_GD) {
3058                 /*
3059                  * As the vm-exit takes precedence over the debug trap, we
3060                  * need to emulate the latter, either for the host or the
3061                  * guest debugging itself.
3062                  */
3063                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3064                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3065                         vcpu->run->debug.arch.dr7 = dr;
3066                         vcpu->run->debug.arch.pc =
3067                                 vmcs_readl(GUEST_CS_BASE) +
3068                                 vmcs_readl(GUEST_RIP);
3069                         vcpu->run->debug.arch.exception = DB_VECTOR;
3070                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3071                         return 0;
3072                 } else {
3073                         vcpu->arch.dr7 &= ~DR7_GD;
3074                         vcpu->arch.dr6 |= DR6_BD;
3075                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3076                         kvm_queue_exception(vcpu, DB_VECTOR);
3077                         return 1;
3078                 }
3079         }
3080
3081         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3082         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3083         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3084         if (exit_qualification & TYPE_MOV_FROM_DR) {
3085                 switch (dr) {
3086                 case 0 ... 3:
3087                         val = vcpu->arch.db[dr];
3088                         break;
3089                 case 4:
3090                         if (check_dr_alias(vcpu) < 0)
3091                                 return 1;
3092                         /* fall through */
3093                 case 6:
3094                         val = vcpu->arch.dr6;
3095                         break;
3096                 case 5:
3097                         if (check_dr_alias(vcpu) < 0)
3098                                 return 1;
3099                         /* fall through */
3100                 default: /* 7 */
3101                         val = vcpu->arch.dr7;
3102                         break;
3103                 }
3104                 kvm_register_write(vcpu, reg, val);
3105         } else {
3106                 val = vcpu->arch.regs[reg];
3107                 switch (dr) {
3108                 case 0 ... 3:
3109                         vcpu->arch.db[dr] = val;
3110                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
3111                                 vcpu->arch.eff_db[dr] = val;
3112                         break;
3113                 case 4:
3114                         if (check_dr_alias(vcpu) < 0)
3115                                 return 1;
3116                         /* fall through */
3117                 case 6:
3118                         if (val & 0xffffffff00000000ULL) {
3119                                 kvm_inject_gp(vcpu, 0);
3120                                 return 1;
3121                         }
3122                         vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
3123                         break;
3124                 case 5:
3125                         if (check_dr_alias(vcpu) < 0)
3126                                 return 1;
3127                         /* fall through */
3128                 default: /* 7 */
3129                         if (val & 0xffffffff00000000ULL) {
3130                                 kvm_inject_gp(vcpu, 0);
3131                                 return 1;
3132                         }
3133                         vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3134                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3135                                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3136                                 vcpu->arch.switch_db_regs =
3137                                         (val & DR7_BP_EN_MASK);
3138                         }
3139                         break;
3140                 }
3141         }
3142         skip_emulated_instruction(vcpu);
3143         return 1;
3144 }
3145
3146 static int handle_cpuid(struct kvm_vcpu *vcpu)
3147 {
3148         kvm_emulate_cpuid(vcpu);
3149         return 1;
3150 }
3151
3152 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3153 {
3154         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3155         u64 data;
3156
3157         if (vmx_get_msr(vcpu, ecx, &data)) {
3158                 kvm_inject_gp(vcpu, 0);
3159                 return 1;
3160         }
3161
3162         trace_kvm_msr_read(ecx, data);
3163
3164         /* FIXME: handling of bits 32:63 of rax, rdx */
3165         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3166         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3167         skip_emulated_instruction(vcpu);
3168         return 1;
3169 }
3170
3171 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3172 {
3173         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3174         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3175                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3176
3177         trace_kvm_msr_write(ecx, data);
3178
3179         if (vmx_set_msr(vcpu, ecx, data) != 0) {
3180                 kvm_inject_gp(vcpu, 0);
3181                 return 1;
3182         }
3183
3184         skip_emulated_instruction(vcpu);
3185         return 1;
3186 }
3187
3188 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3189 {
3190         return 1;
3191 }
3192
3193 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3194 {
3195         u32 cpu_based_vm_exec_control;
3196
3197         /* clear pending irq */
3198         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3199         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3200         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3201
3202         ++vcpu->stat.irq_window_exits;
3203
3204         /*
3205          * If the user space waits to inject interrupts, exit as soon as
3206          * possible
3207          */
3208         if (!irqchip_in_kernel(vcpu->kvm) &&
3209             vcpu->run->request_interrupt_window &&
3210             !kvm_cpu_has_interrupt(vcpu)) {
3211                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3212                 return 0;
3213         }
3214         return 1;
3215 }
3216
3217 static int handle_halt(struct kvm_vcpu *vcpu)
3218 {
3219         skip_emulated_instruction(vcpu);
3220         return kvm_emulate_halt(vcpu);
3221 }
3222
3223 static int handle_vmcall(struct kvm_vcpu *vcpu)
3224 {
3225         skip_emulated_instruction(vcpu);
3226         kvm_emulate_hypercall(vcpu);
3227         return 1;
3228 }
3229
3230 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3231 {
3232         kvm_queue_exception(vcpu, UD_VECTOR);
3233         return 1;
3234 }
3235
3236 static int handle_invlpg(struct kvm_vcpu *vcpu)
3237 {
3238         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3239
3240         kvm_mmu_invlpg(vcpu, exit_qualification);
3241         skip_emulated_instruction(vcpu);
3242         return 1;
3243 }
3244
3245 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3246 {
3247         skip_emulated_instruction(vcpu);
3248         /* TODO: Add support for VT-d/pass-through device */
3249         return 1;
3250 }
3251
3252 static int handle_apic_access(struct kvm_vcpu *vcpu)
3253 {
3254         unsigned long exit_qualification;
3255         enum emulation_result er;
3256         unsigned long offset;
3257
3258         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3259         offset = exit_qualification & 0xffful;
3260
3261         er = emulate_instruction(vcpu, 0, 0, 0);
3262
3263         if (er !=  EMULATE_DONE) {
3264                 printk(KERN_ERR
3265                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3266                        offset);
3267                 return -ENOEXEC;
3268         }
3269         return 1;
3270 }
3271
3272 static int handle_task_switch(struct kvm_vcpu *vcpu)
3273 {
3274         struct vcpu_vmx *vmx = to_vmx(vcpu);
3275         unsigned long exit_qualification;
3276         u16 tss_selector;
3277         int reason, type, idt_v;
3278
3279         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3280         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3281
3282         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3283
3284         reason = (u32)exit_qualification >> 30;
3285         if (reason == TASK_SWITCH_GATE && idt_v) {
3286                 switch (type) {
3287                 case INTR_TYPE_NMI_INTR:
3288                         vcpu->arch.nmi_injected = false;
3289                         if (cpu_has_virtual_nmis())
3290                                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3291                                               GUEST_INTR_STATE_NMI);
3292                         break;
3293                 case INTR_TYPE_EXT_INTR:
3294                 case INTR_TYPE_SOFT_INTR:
3295                         kvm_clear_interrupt_queue(vcpu);
3296                         break;
3297                 case INTR_TYPE_HARD_EXCEPTION:
3298                 case INTR_TYPE_SOFT_EXCEPTION:
3299                         kvm_clear_exception_queue(vcpu);
3300                         break;
3301                 default:
3302                         break;
3303                 }
3304         }
3305         tss_selector = exit_qualification;
3306
3307         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3308                        type != INTR_TYPE_EXT_INTR &&
3309                        type != INTR_TYPE_NMI_INTR))
3310                 skip_emulated_instruction(vcpu);
3311
3312         if (!kvm_task_switch(vcpu, tss_selector, reason))
3313                 return 0;
3314
3315         /* clear all local breakpoint enable flags */
3316         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3317
3318         /*
3319          * TODO: What about debug traps on tss switch?
3320          *       Are we supposed to inject them and update dr6?
3321          */
3322
3323         return 1;
3324 }
3325
3326 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3327 {
3328         unsigned long exit_qualification;
3329         gpa_t gpa;
3330         int gla_validity;
3331
3332         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3333
3334         if (exit_qualification & (1 << 6)) {
3335                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3336                 return -EINVAL;
3337         }
3338
3339         gla_validity = (exit_qualification >> 7) & 0x3;
3340         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3341                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3342                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3343                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3344                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3345                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3346                         (long unsigned int)exit_qualification);
3347                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3348                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3349                 return 0;
3350         }
3351
3352         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3353         trace_kvm_page_fault(gpa, exit_qualification);
3354         return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3355 }
3356
3357 static u64 ept_rsvd_mask(u64 spte, int level)
3358 {
3359         int i;
3360         u64 mask = 0;
3361
3362         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3363                 mask |= (1ULL << i);
3364
3365         if (level > 2)
3366                 /* bits 7:3 reserved */
3367                 mask |= 0xf8;
3368         else if (level == 2) {
3369                 if (spte & (1ULL << 7))
3370                         /* 2MB ref, bits 20:12 reserved */
3371                         mask |= 0x1ff000;
3372                 else
3373                         /* bits 6:3 reserved */
3374                         mask |= 0x78;
3375         }
3376
3377         return mask;
3378 }
3379
3380 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3381                                        int level)
3382 {
3383         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3384
3385         /* 010b (write-only) */
3386         WARN_ON((spte & 0x7) == 0x2);
3387
3388         /* 110b (write/execute) */
3389         WARN_ON((spte & 0x7) == 0x6);
3390
3391         /* 100b (execute-only) and value not supported by logical processor */
3392         if (!cpu_has_vmx_ept_execute_only())
3393                 WARN_ON((spte & 0x7) == 0x4);
3394
3395         /* not 000b */
3396         if ((spte & 0x7)) {
3397                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3398
3399                 if (rsvd_bits != 0) {
3400                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3401                                          __func__, rsvd_bits);
3402                         WARN_ON(1);
3403                 }
3404
3405                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3406                         u64 ept_mem_type = (spte & 0x38) >> 3;
3407
3408                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
3409                             ept_mem_type == 7) {
3410                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3411                                                 __func__, ept_mem_type);
3412                                 WARN_ON(1);
3413                         }
3414                 }
3415         }
3416 }
3417
3418 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3419 {
3420         u64 sptes[4];
3421         int nr_sptes, i;
3422         gpa_t gpa;
3423
3424         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3425
3426         printk(KERN_ERR "EPT: Misconfiguration.\n");
3427         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3428
3429         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3430
3431         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3432                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3433
3434         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3435         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3436
3437         return 0;
3438 }
3439
3440 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3441 {
3442         u32 cpu_based_vm_exec_control;
3443
3444         /* clear pending NMI */
3445         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3446         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3447         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3448         ++vcpu->stat.nmi_window_exits;
3449
3450         return 1;
3451 }
3452
3453 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3454 {
3455         struct vcpu_vmx *vmx = to_vmx(vcpu);
3456         enum emulation_result err = EMULATE_DONE;
3457         int ret = 1;
3458
3459         while (!guest_state_valid(vcpu)) {
3460                 err = emulate_instruction(vcpu, 0, 0, 0);
3461
3462                 if (err == EMULATE_DO_MMIO) {
3463                         ret = 0;
3464                         goto out;
3465                 }
3466
3467                 if (err != EMULATE_DONE) {
3468                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3469                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3470                         vcpu->run->internal.ndata = 0;
3471                         ret = 0;
3472                         goto out;
3473                 }
3474
3475                 if (signal_pending(current))
3476                         goto out;
3477                 if (need_resched())
3478                         schedule();
3479         }
3480
3481         vmx->emulation_required = 0;
3482 out:
3483         return ret;
3484 }
3485
3486 /*
3487  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3488  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3489  */
3490 static int handle_pause(struct kvm_vcpu *vcpu)
3491 {
3492         skip_emulated_instruction(vcpu);
3493         kvm_vcpu_on_spin(vcpu);
3494
3495         return 1;
3496 }
3497
3498 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3499 {
3500         kvm_queue_exception(vcpu, UD_VECTOR);
3501         return 1;
3502 }
3503
3504 /*
3505  * The exit handlers return 1 if the exit was handled fully and guest execution
3506  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3507  * to be done to userspace and return 0.
3508  */
3509 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3510         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3511         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3512         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3513         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3514         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3515         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3516         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3517         [EXIT_REASON_CPUID]                   = handle_cpuid,
3518         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3519         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3520         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3521         [EXIT_REASON_HLT]                     = handle_halt,
3522         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3523         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3524         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
3525         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
3526         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
3527         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
3528         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
3529         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
3530         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
3531         [EXIT_REASON_VMOFF]                   = handle_vmx_insn,
3532         [EXIT_REASON_VMON]                    = handle_vmx_insn,
3533         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3534         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3535         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3536         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3537         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
3538         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3539         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
3540         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
3541         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
3542         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
3543 };
3544
3545 static const int kvm_vmx_max_exit_handlers =
3546         ARRAY_SIZE(kvm_vmx_exit_handlers);
3547
3548 /*
3549  * The guest has exited.  See if we can fix it or if we need userspace
3550  * assistance.
3551  */
3552 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3553 {
3554         struct vcpu_vmx *vmx = to_vmx(vcpu);
3555         u32 exit_reason = vmx->exit_reason;
3556         u32 vectoring_info = vmx->idt_vectoring_info;
3557
3558         trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
3559
3560         /* If guest state is invalid, start emulating */
3561         if (vmx->emulation_required && emulate_invalid_guest_state)
3562                 return handle_invalid_guest_state(vcpu);
3563
3564         /* Access CR3 don't cause VMExit in paging mode, so we need
3565          * to sync with guest real CR3. */
3566         if (enable_ept && is_paging(vcpu))
3567                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3568
3569         if (unlikely(vmx->fail)) {
3570                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3571                 vcpu->run->fail_entry.hardware_entry_failure_reason
3572                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3573                 return 0;
3574         }
3575
3576         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3577                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3578                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3579                         exit_reason != EXIT_REASON_TASK_SWITCH))
3580                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3581                        "(0x%x) and exit reason is 0x%x\n",
3582                        __func__, vectoring_info, exit_reason);
3583
3584         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3585                 if (vmx_interrupt_allowed(vcpu)) {
3586                         vmx->soft_vnmi_blocked = 0;
3587                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3588                            vcpu->arch.nmi_pending) {
3589                         /*
3590                          * This CPU don't support us in finding the end of an
3591                          * NMI-blocked window if the guest runs with IRQs
3592                          * disabled. So we pull the trigger after 1 s of
3593                          * futile waiting, but inform the user about this.
3594                          */
3595                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3596                                "state on VCPU %d after 1 s timeout\n",
3597                                __func__, vcpu->vcpu_id);
3598                         vmx->soft_vnmi_blocked = 0;
3599                 }
3600         }
3601
3602         if (exit_reason < kvm_vmx_max_exit_handlers
3603             && kvm_vmx_exit_handlers[exit_reason])
3604                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3605         else {
3606                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3607                 vcpu->run->hw.hardware_exit_reason = exit_reason;
3608         }
3609         return 0;
3610 }
3611
3612 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3613 {
3614         if (irr == -1 || tpr < irr) {
3615                 vmcs_write32(TPR_THRESHOLD, 0);
3616                 return;
3617         }
3618
3619         vmcs_write32(TPR_THRESHOLD, irr);
3620 }
3621
3622 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3623 {
3624         u32 exit_intr_info;
3625         u32 idt_vectoring_info = vmx->idt_vectoring_info;
3626         bool unblock_nmi;
3627         u8 vector;
3628         int type;
3629         bool idtv_info_valid;
3630
3631         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3632
3633         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3634
3635         /* Handle machine checks before interrupts are enabled */
3636         if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3637             || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3638                 && is_machine_check(exit_intr_info)))
3639                 kvm_machine_check();
3640
3641         /* We need to handle NMIs before interrupts are enabled */
3642         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3643             (exit_intr_info & INTR_INFO_VALID_MASK))
3644                 asm("int $2");
3645
3646         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3647
3648         if (cpu_has_virtual_nmis()) {
3649                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3650                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3651                 /*
3652                  * SDM 3: 27.7.1.2 (September 2008)
3653                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3654                  * a guest IRET fault.
3655                  * SDM 3: 23.2.2 (September 2008)
3656                  * Bit 12 is undefined in any of the following cases:
3657                  *  If the VM exit sets the valid bit in the IDT-vectoring
3658                  *   information field.
3659                  *  If the VM exit is due to a double fault.
3660                  */
3661                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3662                     vector != DF_VECTOR && !idtv_info_valid)
3663                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3664                                       GUEST_INTR_STATE_NMI);
3665         } else if (unlikely(vmx->soft_vnmi_blocked))
3666                 vmx->vnmi_blocked_time +=
3667                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3668
3669         vmx->vcpu.arch.nmi_injected = false;
3670         kvm_clear_exception_queue(&vmx->vcpu);
3671         kvm_clear_interrupt_queue(&vmx->vcpu);
3672
3673         if (!idtv_info_valid)
3674                 return;
3675
3676         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3677         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3678
3679         switch (type) {
3680         case INTR_TYPE_NMI_INTR:
3681                 vmx->vcpu.arch.nmi_injected = true;
3682                 /*
3683                  * SDM 3: 27.7.1.2 (September 2008)
3684                  * Clear bit "block by NMI" before VM entry if a NMI
3685                  * delivery faulted.
3686                  */
3687                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3688                                 GUEST_INTR_STATE_NMI);
3689                 break;
3690         case INTR_TYPE_SOFT_EXCEPTION:
3691                 vmx->vcpu.arch.event_exit_inst_len =
3692                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3693                 /* fall through */
3694         case INTR_TYPE_HARD_EXCEPTION:
3695                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3696                         u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3697                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
3698                 } else
3699                         kvm_queue_exception(&vmx->vcpu, vector);
3700                 break;
3701         case INTR_TYPE_SOFT_INTR:
3702                 vmx->vcpu.arch.event_exit_inst_len =
3703                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3704                 /* fall through */
3705         case INTR_TYPE_EXT_INTR:
3706                 kvm_queue_interrupt(&vmx->vcpu, vector,
3707                         type == INTR_TYPE_SOFT_INTR);
3708                 break;
3709         default:
3710                 break;
3711         }
3712 }
3713
3714 /*
3715  * Failure to inject an interrupt should give us the information
3716  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3717  * when fetching the interrupt redirection bitmap in the real-mode
3718  * tss, this doesn't happen.  So we do it ourselves.
3719  */
3720 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3721 {
3722         vmx->rmode.irq.pending = 0;
3723         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3724                 return;
3725         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3726         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3727                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3728                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3729                 return;
3730         }
3731         vmx->idt_vectoring_info =
3732                 VECTORING_INFO_VALID_MASK
3733                 | INTR_TYPE_EXT_INTR
3734                 | vmx->rmode.irq.vector;
3735 }
3736
3737 #ifdef CONFIG_X86_64
3738 #define R "r"
3739 #define Q "q"
3740 #else
3741 #define R "e"
3742 #define Q "l"
3743 #endif
3744
3745 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3746 {
3747         struct vcpu_vmx *vmx = to_vmx(vcpu);
3748
3749         /* Record the guest's net vcpu time for enforced NMI injections. */
3750         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3751                 vmx->entry_time = ktime_get();
3752
3753         /* Don't enter VMX if guest state is invalid, let the exit handler
3754            start emulation until we arrive back to a valid state */
3755         if (vmx->emulation_required && emulate_invalid_guest_state)
3756                 return;
3757
3758         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3759                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3760         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3761                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3762
3763         /* When single-stepping over STI and MOV SS, we must clear the
3764          * corresponding interruptibility bits in the guest state. Otherwise
3765          * vmentry fails as it then expects bit 14 (BS) in pending debug
3766          * exceptions being set, but that's not correct for the guest debugging
3767          * case. */
3768         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3769                 vmx_set_interrupt_shadow(vcpu, 0);
3770
3771         /*
3772          * Loading guest fpu may have cleared host cr0.ts
3773          */
3774         vmcs_writel(HOST_CR0, read_cr0());
3775
3776         asm(
3777                 /* Store host registers */
3778                 "push %%"R"dx; push %%"R"bp;"
3779                 "push %%"R"cx \n\t"
3780                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3781                 "je 1f \n\t"
3782                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3783                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3784                 "1: \n\t"
3785                 /* Reload cr2 if changed */
3786                 "mov %c[cr2](%0), %%"R"ax \n\t"
3787                 "mov %%cr2, %%"R"dx \n\t"
3788                 "cmp %%"R"ax, %%"R"dx \n\t"
3789                 "je 2f \n\t"
3790                 "mov %%"R"ax, %%cr2 \n\t"
3791                 "2: \n\t"
3792                 /* Check if vmlaunch of vmresume is needed */
3793                 "cmpl $0, %c[launched](%0) \n\t"
3794                 /* Load guest registers.  Don't clobber flags. */
3795                 "mov %c[rax](%0), %%"R"ax \n\t"
3796                 "mov %c[rbx](%0), %%"R"bx \n\t"
3797                 "mov %c[rdx](%0), %%"R"dx \n\t"
3798                 "mov %c[rsi](%0), %%"R"si \n\t"
3799                 "mov %c[rdi](%0), %%"R"di \n\t"
3800                 "mov %c[rbp](%0), %%"R"bp \n\t"
3801 #ifdef CONFIG_X86_64
3802                 "mov %c[r8](%0),  %%r8  \n\t"
3803                 "mov %c[r9](%0),  %%r9  \n\t"
3804                 "mov %c[r10](%0), %%r10 \n\t"
3805                 "mov %c[r11](%0), %%r11 \n\t"
3806                 "mov %c[r12](%0), %%r12 \n\t"
3807                 "mov %c[r13](%0), %%r13 \n\t"
3808                 "mov %c[r14](%0), %%r14 \n\t"
3809                 "mov %c[r15](%0), %%r15 \n\t"
3810 #endif
3811                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3812
3813                 /* Enter guest mode */
3814                 "jne .Llaunched \n\t"
3815                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3816                 "jmp .Lkvm_vmx_return \n\t"
3817                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3818                 ".Lkvm_vmx_return: "
3819                 /* Save guest registers, load host registers, keep flags */
3820                 "xchg %0,     (%%"R"sp) \n\t"
3821                 "mov %%"R"ax, %c[rax](%0) \n\t"
3822                 "mov %%"R"bx, %c[rbx](%0) \n\t"
3823                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3824                 "mov %%"R"dx, %c[rdx](%0) \n\t"
3825                 "mov %%"R"si, %c[rsi](%0) \n\t"
3826                 "mov %%"R"di, %c[rdi](%0) \n\t"
3827                 "mov %%"R"bp, %c[rbp](%0) \n\t"
3828 #ifdef CONFIG_X86_64
3829                 "mov %%r8,  %c[r8](%0) \n\t"
3830                 "mov %%r9,  %c[r9](%0) \n\t"
3831                 "mov %%r10, %c[r10](%0) \n\t"
3832                 "mov %%r11, %c[r11](%0) \n\t"
3833                 "mov %%r12, %c[r12](%0) \n\t"
3834                 "mov %%r13, %c[r13](%0) \n\t"
3835                 "mov %%r14, %c[r14](%0) \n\t"
3836                 "mov %%r15, %c[r15](%0) \n\t"
3837 #endif
3838                 "mov %%cr2, %%"R"ax   \n\t"
3839                 "mov %%"R"ax, %c[cr2](%0) \n\t"
3840
3841                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
3842                 "setbe %c[fail](%0) \n\t"
3843               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3844                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3845                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3846                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3847                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3848                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3849                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3850                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3851                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3852                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3853                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3854 #ifdef CONFIG_X86_64
3855                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3856                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3857                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3858                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3859                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3860                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3861                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3862                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3863 #endif
3864                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3865               : "cc", "memory"
3866                 , R"bx", R"di", R"si"
3867 #ifdef CONFIG_X86_64
3868                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3869 #endif
3870               );
3871
3872         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3873                                   | (1 << VCPU_EXREG_PDPTR));
3874         vcpu->arch.regs_dirty = 0;
3875
3876         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3877         if (vmx->rmode.irq.pending)
3878                 fixup_rmode_irq(vmx);
3879
3880         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3881         vmx->launched = 1;
3882
3883         vmx_complete_interrupts(vmx);
3884 }
3885
3886 #undef R
3887 #undef Q
3888
3889 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3890 {
3891         struct vcpu_vmx *vmx = to_vmx(vcpu);
3892
3893         if (vmx->vmcs) {
3894                 vcpu_clear(vmx);
3895                 free_vmcs(vmx->vmcs);
3896                 vmx->vmcs = NULL;
3897         }
3898 }
3899
3900 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3901 {
3902         struct vcpu_vmx *vmx = to_vmx(vcpu);
3903
3904         spin_lock(&vmx_vpid_lock);
3905         if (vmx->vpid != 0)
3906                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3907         spin_unlock(&vmx_vpid_lock);
3908         vmx_free_vmcs(vcpu);
3909         kfree(vmx->guest_msrs);
3910         kvm_vcpu_uninit(vcpu);
3911         kmem_cache_free(kvm_vcpu_cache, vmx);
3912 }
3913
3914 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3915 {
3916         int err;
3917         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3918         int cpu;
3919
3920         if (!vmx)
3921                 return ERR_PTR(-ENOMEM);
3922
3923         allocate_vpid(vmx);
3924
3925         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3926         if (err)
3927                 goto free_vcpu;
3928
3929         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3930         if (!vmx->guest_msrs) {
3931                 err = -ENOMEM;
3932                 goto uninit_vcpu;
3933         }
3934
3935         vmx->vmcs = alloc_vmcs();
3936         if (!vmx->vmcs)
3937                 goto free_msrs;
3938
3939         vmcs_clear(vmx->vmcs);
3940
3941         cpu = get_cpu();
3942         vmx_vcpu_load(&vmx->vcpu, cpu);
3943         err = vmx_vcpu_setup(vmx);
3944         vmx_vcpu_put(&vmx->vcpu);
3945         put_cpu();
3946         if (err)
3947                 goto free_vmcs;
3948         if (vm_need_virtualize_apic_accesses(kvm))
3949                 if (alloc_apic_access_page(kvm) != 0)
3950                         goto free_vmcs;
3951
3952         if (enable_ept) {
3953                 if (!kvm->arch.ept_identity_map_addr)
3954                         kvm->arch.ept_identity_map_addr =
3955                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3956                 if (alloc_identity_pagetable(kvm) != 0)
3957                         goto free_vmcs;
3958         }
3959
3960         return &vmx->vcpu;
3961
3962 free_vmcs:
3963         free_vmcs(vmx->vmcs);
3964 free_msrs:
3965         kfree(vmx->guest_msrs);
3966 uninit_vcpu:
3967         kvm_vcpu_uninit(&vmx->vcpu);
3968 free_vcpu:
3969         kmem_cache_free(kvm_vcpu_cache, vmx);
3970         return ERR_PTR(err);
3971 }
3972
3973 static void __init vmx_check_processor_compat(void *rtn)
3974 {
3975         struct vmcs_config vmcs_conf;
3976
3977         *(int *)rtn = 0;
3978         if (setup_vmcs_config(&vmcs_conf) < 0)
3979                 *(int *)rtn = -EIO;
3980         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3981                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3982                                 smp_processor_id());
3983                 *(int *)rtn = -EIO;
3984         }
3985 }
3986
3987 static int get_ept_level(void)
3988 {
3989         return VMX_EPT_DEFAULT_GAW + 1;
3990 }
3991
3992 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3993 {
3994         u64 ret;
3995
3996         /* For VT-d and EPT combination
3997          * 1. MMIO: always map as UC
3998          * 2. EPT with VT-d:
3999          *   a. VT-d without snooping control feature: can't guarantee the
4000          *      result, try to trust guest.
4001          *   b. VT-d with snooping control feature: snooping control feature of
4002          *      VT-d engine can guarantee the cache correctness. Just set it
4003          *      to WB to keep consistent with host. So the same as item 3.
4004          * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
4005          *    consistent with host MTRR
4006          */
4007         if (is_mmio)
4008                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4009         else if (vcpu->kvm->arch.iommu_domain &&
4010                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4011                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4012                       VMX_EPT_MT_EPTE_SHIFT;
4013         else
4014                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4015                         | VMX_EPT_IGMT_BIT;
4016
4017         return ret;
4018 }
4019
4020 #define _ER(x) { EXIT_REASON_##x, #x }
4021
4022 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4023         _ER(EXCEPTION_NMI),
4024         _ER(EXTERNAL_INTERRUPT),
4025         _ER(TRIPLE_FAULT),
4026         _ER(PENDING_INTERRUPT),
4027         _ER(NMI_WINDOW),
4028         _ER(TASK_SWITCH),
4029         _ER(CPUID),
4030         _ER(HLT),
4031         _ER(INVLPG),
4032         _ER(RDPMC),
4033         _ER(RDTSC),
4034         _ER(VMCALL),
4035         _ER(VMCLEAR),
4036         _ER(VMLAUNCH),
4037         _ER(VMPTRLD),
4038         _ER(VMPTRST),
4039         _ER(VMREAD),
4040         _ER(VMRESUME),
4041         _ER(VMWRITE),
4042         _ER(VMOFF),
4043         _ER(VMON),
4044         _ER(CR_ACCESS),
4045         _ER(DR_ACCESS),
4046         _ER(IO_INSTRUCTION),
4047         _ER(MSR_READ),
4048         _ER(MSR_WRITE),
4049         _ER(MWAIT_INSTRUCTION),
4050         _ER(MONITOR_INSTRUCTION),
4051         _ER(PAUSE_INSTRUCTION),
4052         _ER(MCE_DURING_VMENTRY),
4053         _ER(TPR_BELOW_THRESHOLD),
4054         _ER(APIC_ACCESS),
4055         _ER(EPT_VIOLATION),
4056         _ER(EPT_MISCONFIG),
4057         _ER(WBINVD),
4058         { -1, NULL }
4059 };
4060
4061 #undef _ER
4062
4063 static int vmx_get_lpage_level(void)
4064 {
4065         if (enable_ept && !cpu_has_vmx_ept_1g_page())
4066                 return PT_DIRECTORY_LEVEL;
4067         else
4068                 /* For shadow and EPT supported 1GB page */
4069                 return PT_PDPE_LEVEL;
4070 }
4071
4072 static inline u32 bit(int bitno)
4073 {
4074         return 1 << (bitno & 31);
4075 }
4076
4077 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4078 {
4079         struct kvm_cpuid_entry2 *best;
4080         struct vcpu_vmx *vmx = to_vmx(vcpu);
4081         u32 exec_control;
4082
4083         vmx->rdtscp_enabled = false;
4084         if (vmx_rdtscp_supported()) {
4085                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4086                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4087                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4088                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4089                                 vmx->rdtscp_enabled = true;
4090                         else {
4091                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4092                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4093                                                 exec_control);
4094                         }
4095                 }
4096         }
4097 }
4098
4099 static struct kvm_x86_ops vmx_x86_ops = {
4100         .cpu_has_kvm_support = cpu_has_kvm_support,
4101         .disabled_by_bios = vmx_disabled_by_bios,
4102         .hardware_setup = hardware_setup,
4103         .hardware_unsetup = hardware_unsetup,
4104         .check_processor_compatibility = vmx_check_processor_compat,
4105         .hardware_enable = hardware_enable,
4106         .hardware_disable = hardware_disable,
4107         .cpu_has_accelerated_tpr = report_flexpriority,
4108
4109         .vcpu_create = vmx_create_vcpu,
4110         .vcpu_free = vmx_free_vcpu,
4111         .vcpu_reset = vmx_vcpu_reset,
4112
4113         .prepare_guest_switch = vmx_save_host_state,
4114         .vcpu_load = vmx_vcpu_load,
4115         .vcpu_put = vmx_vcpu_put,
4116
4117         .set_guest_debug = set_guest_debug,
4118         .get_msr = vmx_get_msr,
4119         .set_msr = vmx_set_msr,
4120         .get_segment_base = vmx_get_segment_base,
4121         .get_segment = vmx_get_segment,
4122         .set_segment = vmx_set_segment,
4123         .get_cpl = vmx_get_cpl,
4124         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4125         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4126         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4127         .set_cr0 = vmx_set_cr0,
4128         .set_cr3 = vmx_set_cr3,
4129         .set_cr4 = vmx_set_cr4,
4130         .set_efer = vmx_set_efer,
4131         .get_idt = vmx_get_idt,
4132         .set_idt = vmx_set_idt,
4133         .get_gdt = vmx_get_gdt,
4134         .set_gdt = vmx_set_gdt,
4135         .cache_reg = vmx_cache_reg,
4136         .get_rflags = vmx_get_rflags,
4137         .set_rflags = vmx_set_rflags,
4138         .fpu_deactivate = vmx_fpu_deactivate,
4139
4140         .tlb_flush = vmx_flush_tlb,
4141
4142         .run = vmx_vcpu_run,
4143         .handle_exit = vmx_handle_exit,
4144         .skip_emulated_instruction = skip_emulated_instruction,
4145         .set_interrupt_shadow = vmx_set_interrupt_shadow,
4146         .get_interrupt_shadow = vmx_get_interrupt_shadow,
4147         .patch_hypercall = vmx_patch_hypercall,
4148         .set_irq = vmx_inject_irq,
4149         .set_nmi = vmx_inject_nmi,
4150         .queue_exception = vmx_queue_exception,
4151         .interrupt_allowed = vmx_interrupt_allowed,
4152         .nmi_allowed = vmx_nmi_allowed,
4153         .get_nmi_mask = vmx_get_nmi_mask,
4154         .set_nmi_mask = vmx_set_nmi_mask,
4155         .enable_nmi_window = enable_nmi_window,
4156         .enable_irq_window = enable_irq_window,
4157         .update_cr8_intercept = update_cr8_intercept,
4158
4159         .set_tss_addr = vmx_set_tss_addr,
4160         .get_tdp_level = get_ept_level,
4161         .get_mt_mask = vmx_get_mt_mask,
4162
4163         .exit_reasons_str = vmx_exit_reasons_str,
4164         .get_lpage_level = vmx_get_lpage_level,
4165
4166         .cpuid_update = vmx_cpuid_update,
4167
4168         .rdtscp_supported = vmx_rdtscp_supported,
4169 };
4170
4171 static int __init vmx_init(void)
4172 {
4173         int r, i;
4174
4175         rdmsrl_safe(MSR_EFER, &host_efer);
4176
4177         for (i = 0; i < NR_VMX_MSR; ++i)
4178                 kvm_define_shared_msr(i, vmx_msr_index[i]);
4179
4180         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4181         if (!vmx_io_bitmap_a)
4182                 return -ENOMEM;
4183
4184         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4185         if (!vmx_io_bitmap_b) {
4186                 r = -ENOMEM;
4187                 goto out;
4188         }
4189
4190         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4191         if (!vmx_msr_bitmap_legacy) {
4192                 r = -ENOMEM;
4193                 goto out1;
4194         }
4195
4196         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4197         if (!vmx_msr_bitmap_longmode) {
4198                 r = -ENOMEM;
4199                 goto out2;
4200         }
4201
4202         /*
4203          * Allow direct access to the PC debug port (it is often used for I/O
4204          * delays, but the vmexits simply slow things down).
4205          */
4206         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4207         clear_bit(0x80, vmx_io_bitmap_a);
4208
4209         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4210
4211         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4212         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4213
4214         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4215
4216         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
4217         if (r)
4218                 goto out3;
4219
4220         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4221         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4222         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4223         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4224         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4225         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4226
4227         if (enable_ept) {
4228                 bypass_guest_pf = 0;
4229                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4230                         VMX_EPT_WRITABLE_MASK);
4231                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4232                                 VMX_EPT_EXECUTABLE_MASK);
4233                 kvm_enable_tdp();
4234         } else
4235                 kvm_disable_tdp();
4236
4237         if (bypass_guest_pf)
4238                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4239
4240         return 0;
4241
4242 out3:
4243         free_page((unsigned long)vmx_msr_bitmap_longmode);
4244 out2:
4245         free_page((unsigned long)vmx_msr_bitmap_legacy);
4246 out1:
4247         free_page((unsigned long)vmx_io_bitmap_b);
4248 out:
4249         free_page((unsigned long)vmx_io_bitmap_a);
4250         return r;
4251 }
4252
4253 static void __exit vmx_exit(void)
4254 {
4255         free_page((unsigned long)vmx_msr_bitmap_legacy);
4256         free_page((unsigned long)vmx_msr_bitmap_longmode);
4257         free_page((unsigned long)vmx_io_bitmap_b);
4258         free_page((unsigned long)vmx_io_bitmap_a);
4259
4260         kvm_exit();
4261 }
4262
4263 module_init(vmx_init)
4264 module_exit(vmx_exit)