SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/mm.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27 #include <linux/moduleparam.h>
  28 #include "kvm_cache_regs.h"
  29 #include "x86.h"
  30
  31 #include <asm/io.h>
  32 #include <asm/desc.h>
  33 #include <asm/vmx.h>
  34 #include <asm/virtext.h>
  35
  36 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  37
  38 MODULE_AUTHOR("Qumranet");
  39 MODULE_LICENSE("GPL");
  40
  41 static int bypass_guest_pf = 1;
  42 module_param(bypass_guest_pf, bool, 0);
  43
  44 static int enable_vpid = 1;
  45 module_param(enable_vpid, bool, 0);
  46
  47 static int flexpriority_enabled = 1;
  48 module_param(flexpriority_enabled, bool, 0);
  49
  50 static int enable_ept = 1;
  51 module_param(enable_ept, bool, 0);
  52
  53 static int emulate_invalid_guest_state = 0;
  54 module_param(emulate_invalid_guest_state, bool, 0);
  55
  56 struct vmcs {
  57         u32 revision_id;
  58         u32 abort;
  59         char data[0];
  60 };
  61
  62 struct vcpu_vmx {
  63         struct kvm_vcpu       vcpu;
  64         struct list_head      local_vcpus_link;
  65         unsigned long         host_rsp;
  66         int                   launched;
  67         u8                    fail;
  68         u32                   idt_vectoring_info;
  69         struct kvm_msr_entry *guest_msrs;
  70         struct kvm_msr_entry *host_msrs;
  71         int                   nmsrs;
  72         int                   save_nmsrs;
  73         int                   msr_offset_efer;
  74 #ifdef CONFIG_X86_64
  75         int                   msr_offset_kernel_gs_base;
  76 #endif
  77         struct vmcs          *vmcs;
  78         struct {
  79                 int           loaded;
  80                 u16           fs_sel, gs_sel, ldt_sel;
  81                 int           gs_ldt_reload_needed;
  82                 int           fs_reload_needed;
  83                 int           guest_efer_loaded;
  84         } host_state;
  85         struct {
  86                 struct {
  87                         bool pending;
  88                         u8 vector;
  89                         unsigned rip;
  90                 } irq;
  91         } rmode;
  92         int vpid;
  93         bool emulation_required;
  94
  95         /* Support for vnmi-less CPUs */
  96         int soft_vnmi_blocked;
  97         ktime_t entry_time;
  98         s64 vnmi_blocked_time;
  99 };
 100
 101 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 102 {
 103         return container_of(vcpu, struct vcpu_vmx, vcpu);
 104 }
 105
 106 static int init_rmode(struct kvm *kvm);
 107 static u64 construct_eptp(unsigned long root_hpa);
 108
 109 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 110 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 111 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 112
 113 static struct page *vmx_io_bitmap_a;
 114 static struct page *vmx_io_bitmap_b;
 115 static struct page *vmx_msr_bitmap;
 116
 117 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 118 static DEFINE_SPINLOCK(vmx_vpid_lock);
 119
 120 static struct vmcs_config {
 121         int size;
 122         int order;
 123         u32 revision_id;
 124         u32 pin_based_exec_ctrl;
 125         u32 cpu_based_exec_ctrl;
 126         u32 cpu_based_2nd_exec_ctrl;
 127         u32 vmexit_ctrl;
 128         u32 vmentry_ctrl;
 129 } vmcs_config;
 130
 131 static struct vmx_capability {
 132         u32 ept;
 133         u32 vpid;
 134 } vmx_capability;
 135
 136 #define VMX_SEGMENT_FIELD(seg)                                  \
 137         [VCPU_SREG_##seg] = {                                   \
 138                 .selector = GUEST_##seg##_SELECTOR,             \
 139                 .base = GUEST_##seg##_BASE,                     \
 140                 .limit = GUEST_##seg##_LIMIT,                   \
 141                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 142         }
 143
 144 static struct kvm_vmx_segment_field {
 145         unsigned selector;
 146         unsigned base;
 147         unsigned limit;
 148         unsigned ar_bytes;
 149 } kvm_vmx_segment_fields[] = {
 150         VMX_SEGMENT_FIELD(CS),
 151         VMX_SEGMENT_FIELD(DS),
 152         VMX_SEGMENT_FIELD(ES),
 153         VMX_SEGMENT_FIELD(FS),
 154         VMX_SEGMENT_FIELD(GS),
 155         VMX_SEGMENT_FIELD(SS),
 156         VMX_SEGMENT_FIELD(TR),
 157         VMX_SEGMENT_FIELD(LDTR),
 158 };
 159
 160 /*
 161  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 162  * away by decrementing the array size.
 163  */
 164 static const u32 vmx_msr_index[] = {
 165 #ifdef CONFIG_X86_64
 166         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
 167 #endif
 168         MSR_EFER, MSR_K6_STAR,
 169 };
 170 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 171
 172 static void load_msrs(struct kvm_msr_entry *e, int n)
 173 {
 174         int i;
 175
 176         for (i = 0; i < n; ++i)
 177                 wrmsrl(e[i].index, e[i].data);
 178 }
 179
 180 static void save_msrs(struct kvm_msr_entry *e, int n)
 181 {
 182         int i;
 183
 184         for (i = 0; i < n; ++i)
 185                 rdmsrl(e[i].index, e[i].data);
 186 }
 187
 188 static inline int is_page_fault(u32 intr_info)
 189 {
 190         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 191                              INTR_INFO_VALID_MASK)) ==
 192                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 193 }
 194
 195 static inline int is_no_device(u32 intr_info)
 196 {
 197         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 198                              INTR_INFO_VALID_MASK)) ==
 199                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 200 }
 201
 202 static inline int is_invalid_opcode(u32 intr_info)
 203 {
 204         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 205                              INTR_INFO_VALID_MASK)) ==
 206                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 207 }
 208
 209 static inline int is_external_interrupt(u32 intr_info)
 210 {
 211         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 212                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 213 }
 214
 215 static inline int cpu_has_vmx_msr_bitmap(void)
 216 {
 217         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
 218 }
 219
 220 static inline int cpu_has_vmx_tpr_shadow(void)
 221 {
 222         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
 223 }
 224
 225 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 226 {
 227         return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
 228 }
 229
 230 static inline int cpu_has_secondary_exec_ctrls(void)
 231 {
 232         return (vmcs_config.cpu_based_exec_ctrl &
 233                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
 234 }
 235
 236 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 237 {
 238         return flexpriority_enabled
 239                 && (vmcs_config.cpu_based_2nd_exec_ctrl &
 240                     SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
 241 }
 242
 243 static inline int cpu_has_vmx_invept_individual_addr(void)
 244 {
 245         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
 246 }
 247
 248 static inline int cpu_has_vmx_invept_context(void)
 249 {
 250         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
 251 }
 252
 253 static inline int cpu_has_vmx_invept_global(void)
 254 {
 255         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
 256 }
 257
 258 static inline int cpu_has_vmx_ept(void)
 259 {
 260         return (vmcs_config.cpu_based_2nd_exec_ctrl &
 261                 SECONDARY_EXEC_ENABLE_EPT);
 262 }
 263
 264 static inline int vm_need_ept(void)
 265 {
 266         return (cpu_has_vmx_ept() && enable_ept);
 267 }
 268
 269 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 270 {
 271         return ((cpu_has_vmx_virtualize_apic_accesses()) &&
 272                 (irqchip_in_kernel(kvm)));
 273 }
 274
 275 static inline int cpu_has_vmx_vpid(void)
 276 {
 277         return (vmcs_config.cpu_based_2nd_exec_ctrl &
 278                 SECONDARY_EXEC_ENABLE_VPID);
 279 }
 280
 281 static inline int cpu_has_virtual_nmis(void)
 282 {
 283         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 284 }
 285
 286 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 287 {
 288         int i;
 289
 290         for (i = 0; i < vmx->nmsrs; ++i)
 291                 if (vmx->guest_msrs[i].index == msr)
 292                         return i;
 293         return -1;
 294 }
 295
 296 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 297 {
 298     struct {
 299         u64 vpid : 16;
 300         u64 rsvd : 48;
 301         u64 gva;
 302     } operand = { vpid, 0, gva };
 303
 304     asm volatile (__ex(ASM_VMX_INVVPID)
 305                   /* CF==1 or ZF==1 --> rc = -1 */
 306                   "; ja 1f ; ud2 ; 1:"
 307                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 308 }
 309
 310 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 311 {
 312         struct {
 313                 u64 eptp, gpa;
 314         } operand = {eptp, gpa};
 315
 316         asm volatile (__ex(ASM_VMX_INVEPT)
 317                         /* CF==1 or ZF==1 --> rc = -1 */
 318                         "; ja 1f ; ud2 ; 1:\n"
 319                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 320 }
 321
 322 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 323 {
 324         int i;
 325
 326         i = __find_msr_index(vmx, msr);
 327         if (i >= 0)
 328                 return &vmx->guest_msrs[i];
 329         return NULL;
 330 }
 331
 332 static void vmcs_clear(struct vmcs *vmcs)
 333 {
 334         u64 phys_addr = __pa(vmcs);
 335         u8 error;
 336
 337         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 338                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 339                       : "cc", "memory");
 340         if (error)
 341                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 342                        vmcs, phys_addr);
 343 }
 344
 345 static void __vcpu_clear(void *arg)
 346 {
 347         struct vcpu_vmx *vmx = arg;
 348         int cpu = raw_smp_processor_id();
 349
 350         if (vmx->vcpu.cpu == cpu)
 351                 vmcs_clear(vmx->vmcs);
 352         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 353                 per_cpu(current_vmcs, cpu) = NULL;
 354         rdtscll(vmx->vcpu.arch.host_tsc);
 355         list_del(&vmx->local_vcpus_link);
 356         vmx->vcpu.cpu = -1;
 357         vmx->launched = 0;
 358 }
 359
 360 static void vcpu_clear(struct vcpu_vmx *vmx)
 361 {
 362         if (vmx->vcpu.cpu == -1)
 363                 return;
 364         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 365 }
 366
 367 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 368 {
 369         if (vmx->vpid == 0)
 370                 return;
 371
 372         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 373 }
 374
 375 static inline void ept_sync_global(void)
 376 {
 377         if (cpu_has_vmx_invept_global())
 378                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 379 }
 380
 381 static inline void ept_sync_context(u64 eptp)
 382 {
 383         if (vm_need_ept()) {
 384                 if (cpu_has_vmx_invept_context())
 385                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 386                 else
 387                         ept_sync_global();
 388         }
 389 }
 390
 391 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 392 {
 393         if (vm_need_ept()) {
 394                 if (cpu_has_vmx_invept_individual_addr())
 395                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 396                                         eptp, gpa);
 397                 else
 398                         ept_sync_context(eptp);
 399         }
 400 }
 401
 402 static unsigned long vmcs_readl(unsigned long field)
 403 {
 404         unsigned long value;
 405
 406         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 407                       : "=a"(value) : "d"(field) : "cc");
 408         return value;
 409 }
 410
 411 static u16 vmcs_read16(unsigned long field)
 412 {
 413         return vmcs_readl(field);
 414 }
 415
 416 static u32 vmcs_read32(unsigned long field)
 417 {
 418         return vmcs_readl(field);
 419 }
 420
 421 static u64 vmcs_read64(unsigned long field)
 422 {
 423 #ifdef CONFIG_X86_64
 424         return vmcs_readl(field);
 425 #else
 426         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 427 #endif
 428 }
 429
 430 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 431 {
 432         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 433                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 434         dump_stack();
 435 }
 436
 437 static void vmcs_writel(unsigned long field, unsigned long value)
 438 {
 439         u8 error;
 440
 441         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 442                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 443         if (unlikely(error))
 444                 vmwrite_error(field, value);
 445 }
 446
 447 static void vmcs_write16(unsigned long field, u16 value)
 448 {
 449         vmcs_writel(field, value);
 450 }
 451
 452 static void vmcs_write32(unsigned long field, u32 value)
 453 {
 454         vmcs_writel(field, value);
 455 }
 456
 457 static void vmcs_write64(unsigned long field, u64 value)
 458 {
 459         vmcs_writel(field, value);
 460 #ifndef CONFIG_X86_64
 461         asm volatile ("");
 462         vmcs_writel(field+1, value >> 32);
 463 #endif
 464 }
 465
 466 static void vmcs_clear_bits(unsigned long field, u32 mask)
 467 {
 468         vmcs_writel(field, vmcs_readl(field) & ~mask);
 469 }
 470
 471 static void vmcs_set_bits(unsigned long field, u32 mask)
 472 {
 473         vmcs_writel(field, vmcs_readl(field) | mask);
 474 }
 475
 476 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 477 {
 478         u32 eb;
 479
 480         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
 481         if (!vcpu->fpu_active)
 482                 eb |= 1u << NM_VECTOR;
 483         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
 484                 if (vcpu->guest_debug &
 485                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
 486                         eb |= 1u << DB_VECTOR;
 487                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
 488                         eb |= 1u << BP_VECTOR;
 489         }
 490         if (vcpu->arch.rmode.active)
 491                 eb = ~0;
 492         if (vm_need_ept())
 493                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 494         vmcs_write32(EXCEPTION_BITMAP, eb);
 495 }
 496
 497 static void reload_tss(void)
 498 {
 499         /*
 500          * VT restores TR but not its size.  Useless.
 501          */
 502         struct descriptor_table gdt;
 503         struct desc_struct *descs;
 504
 505         kvm_get_gdt(&gdt);
 506         descs = (void *)gdt.base;
 507         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 508         load_TR_desc();
 509 }
 510
 511 static void load_transition_efer(struct vcpu_vmx *vmx)
 512 {
 513         int efer_offset = vmx->msr_offset_efer;
 514         u64 host_efer = vmx->host_msrs[efer_offset].data;
 515         u64 guest_efer = vmx->guest_msrs[efer_offset].data;
 516         u64 ignore_bits;
 517
 518         if (efer_offset < 0)
 519                 return;
 520         /*
 521          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 522          * outside long mode
 523          */
 524         ignore_bits = EFER_NX | EFER_SCE;
 525 #ifdef CONFIG_X86_64
 526         ignore_bits |= EFER_LMA | EFER_LME;
 527         /* SCE is meaningful only in long mode on Intel */
 528         if (guest_efer & EFER_LMA)
 529                 ignore_bits &= ~(u64)EFER_SCE;
 530 #endif
 531         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
 532                 return;
 533
 534         vmx->host_state.guest_efer_loaded = 1;
 535         guest_efer &= ~ignore_bits;
 536         guest_efer |= host_efer & ignore_bits;
 537         wrmsrl(MSR_EFER, guest_efer);
 538         vmx->vcpu.stat.efer_reload++;
 539 }
 540
 541 static void reload_host_efer(struct vcpu_vmx *vmx)
 542 {
 543         if (vmx->host_state.guest_efer_loaded) {
 544                 vmx->host_state.guest_efer_loaded = 0;
 545                 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
 546         }
 547 }
 548
 549 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 550 {
 551         struct vcpu_vmx *vmx = to_vmx(vcpu);
 552
 553         if (vmx->host_state.loaded)
 554                 return;
 555
 556         vmx->host_state.loaded = 1;
 557         /*
 558          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 559          * allow segment selectors with cpl > 0 or ti == 1.
 560          */
 561         vmx->host_state.ldt_sel = kvm_read_ldt();
 562         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 563         vmx->host_state.fs_sel = kvm_read_fs();
 564         if (!(vmx->host_state.fs_sel & 7)) {
 565                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 566                 vmx->host_state.fs_reload_needed = 0;
 567         } else {
 568                 vmcs_write16(HOST_FS_SELECTOR, 0);
 569                 vmx->host_state.fs_reload_needed = 1;
 570         }
 571         vmx->host_state.gs_sel = kvm_read_gs();
 572         if (!(vmx->host_state.gs_sel & 7))
 573                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 574         else {
 575                 vmcs_write16(HOST_GS_SELECTOR, 0);
 576                 vmx->host_state.gs_ldt_reload_needed = 1;
 577         }
 578
 579 #ifdef CONFIG_X86_64
 580         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 581         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 582 #else
 583         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 584         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 585 #endif
 586
 587 #ifdef CONFIG_X86_64
 588         if (is_long_mode(&vmx->vcpu))
 589                 save_msrs(vmx->host_msrs +
 590                           vmx->msr_offset_kernel_gs_base, 1);
 591
 592 #endif
 593         load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 594         load_transition_efer(vmx);
 595 }
 596
 597 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 598 {
 599         unsigned long flags;
 600
 601         if (!vmx->host_state.loaded)
 602                 return;
 603
 604         ++vmx->vcpu.stat.host_state_reload;
 605         vmx->host_state.loaded = 0;
 606         if (vmx->host_state.fs_reload_needed)
 607                 kvm_load_fs(vmx->host_state.fs_sel);
 608         if (vmx->host_state.gs_ldt_reload_needed) {
 609                 kvm_load_ldt(vmx->host_state.ldt_sel);
 610                 /*
 611                  * If we have to reload gs, we must take care to
 612                  * preserve our gs base.
 613                  */
 614                 local_irq_save(flags);
 615                 kvm_load_gs(vmx->host_state.gs_sel);
 616 #ifdef CONFIG_X86_64
 617                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 618 #endif
 619                 local_irq_restore(flags);
 620         }
 621         reload_tss();
 622         save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 623         load_msrs(vmx->host_msrs, vmx->save_nmsrs);
 624         reload_host_efer(vmx);
 625 }
 626
 627 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 628 {
 629         preempt_disable();
 630         __vmx_load_host_state(vmx);
 631         preempt_enable();
 632 }
 633
 634 /*
 635  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 636  * vcpu mutex is already taken.
 637  */
 638 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 639 {
 640         struct vcpu_vmx *vmx = to_vmx(vcpu);
 641         u64 phys_addr = __pa(vmx->vmcs);
 642         u64 tsc_this, delta, new_offset;
 643
 644         if (vcpu->cpu != cpu) {
 645                 vcpu_clear(vmx);
 646                 kvm_migrate_timers(vcpu);
 647                 vpid_sync_vcpu_all(vmx);
 648                 local_irq_disable();
 649                 list_add(&vmx->local_vcpus_link,
 650                          &per_cpu(vcpus_on_cpu, cpu));
 651                 local_irq_enable();
 652         }
 653
 654         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 655                 u8 error;
 656
 657                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 658                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 659                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 660                               : "cc");
 661                 if (error)
 662                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 663                                vmx->vmcs, phys_addr);
 664         }
 665
 666         if (vcpu->cpu != cpu) {
 667                 struct descriptor_table dt;
 668                 unsigned long sysenter_esp;
 669
 670                 vcpu->cpu = cpu;
 671                 /*
 672                  * Linux uses per-cpu TSS and GDT, so set these when switching
 673                  * processors.
 674                  */
 675                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 676                 kvm_get_gdt(&dt);
 677                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 678
 679                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 680                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 681
 682                 /*
 683                  * Make sure the time stamp counter is monotonous.
 684                  */
 685                 rdtscll(tsc_this);
 686                 if (tsc_this < vcpu->arch.host_tsc) {
 687                         delta = vcpu->arch.host_tsc - tsc_this;
 688                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 689                         vmcs_write64(TSC_OFFSET, new_offset);
 690                 }
 691         }
 692 }
 693
 694 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 695 {
 696         __vmx_load_host_state(to_vmx(vcpu));
 697 }
 698
 699 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 700 {
 701         if (vcpu->fpu_active)
 702                 return;
 703         vcpu->fpu_active = 1;
 704         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 705         if (vcpu->arch.cr0 & X86_CR0_TS)
 706                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 707         update_exception_bitmap(vcpu);
 708 }
 709
 710 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 711 {
 712         if (!vcpu->fpu_active)
 713                 return;
 714         vcpu->fpu_active = 0;
 715         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 716         update_exception_bitmap(vcpu);
 717 }
 718
 719 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 720 {
 721         return vmcs_readl(GUEST_RFLAGS);
 722 }
 723
 724 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 725 {
 726         if (vcpu->arch.rmode.active)
 727                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 728         vmcs_writel(GUEST_RFLAGS, rflags);
 729 }
 730
 731 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 732 {
 733         unsigned long rip;
 734         u32 interruptibility;
 735
 736         rip = kvm_rip_read(vcpu);
 737         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 738         kvm_rip_write(vcpu, rip);
 739
 740         /*
 741          * We emulated an instruction, so temporary interrupt blocking
 742          * should be removed, if set.
 743          */
 744         interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 745         if (interruptibility & 3)
 746                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
 747                              interruptibility & ~3);
 748         vcpu->arch.interrupt_window_open = 1;
 749 }
 750
 751 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 752                                 bool has_error_code, u32 error_code)
 753 {
 754         struct vcpu_vmx *vmx = to_vmx(vcpu);
 755         u32 intr_info = nr | INTR_INFO_VALID_MASK;
 756
 757         if (has_error_code) {
 758                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 759                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
 760         }
 761
 762         if (vcpu->arch.rmode.active) {
 763                 vmx->rmode.irq.pending = true;
 764                 vmx->rmode.irq.vector = nr;
 765                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
 766                 if (nr == BP_VECTOR || nr == OF_VECTOR)
 767                         vmx->rmode.irq.rip++;
 768                 intr_info |= INTR_TYPE_SOFT_INTR;
 769                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 770                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
 771                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
 772                 return;
 773         }
 774
 775         if (nr == BP_VECTOR || nr == OF_VECTOR) {
 776                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
 777                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
 778         } else
 779                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
 780
 781         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 782 }
 783
 784 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
 785 {
 786         return false;
 787 }
 788
 789 /*
 790  * Swap MSR entry in host/guest MSR entry array.
 791  */
 792 #ifdef CONFIG_X86_64
 793 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 794 {
 795         struct kvm_msr_entry tmp;
 796
 797         tmp = vmx->guest_msrs[to];
 798         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 799         vmx->guest_msrs[from] = tmp;
 800         tmp = vmx->host_msrs[to];
 801         vmx->host_msrs[to] = vmx->host_msrs[from];
 802         vmx->host_msrs[from] = tmp;
 803 }
 804 #endif
 805
 806 /*
 807  * Set up the vmcs to automatically save and restore system
 808  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 809  * mode, as fiddling with msrs is very expensive.
 810  */
 811 static void setup_msrs(struct vcpu_vmx *vmx)
 812 {
 813         int save_nmsrs;
 814
 815         vmx_load_host_state(vmx);
 816         save_nmsrs = 0;
 817 #ifdef CONFIG_X86_64
 818         if (is_long_mode(&vmx->vcpu)) {
 819                 int index;
 820
 821                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 822                 if (index >= 0)
 823                         move_msr_up(vmx, index, save_nmsrs++);
 824                 index = __find_msr_index(vmx, MSR_LSTAR);
 825                 if (index >= 0)
 826                         move_msr_up(vmx, index, save_nmsrs++);
 827                 index = __find_msr_index(vmx, MSR_CSTAR);
 828                 if (index >= 0)
 829                         move_msr_up(vmx, index, save_nmsrs++);
 830                 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 831                 if (index >= 0)
 832                         move_msr_up(vmx, index, save_nmsrs++);
 833                 /*
 834                  * MSR_K6_STAR is only needed on long mode guests, and only
 835                  * if efer.sce is enabled.
 836                  */
 837                 index = __find_msr_index(vmx, MSR_K6_STAR);
 838                 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
 839                         move_msr_up(vmx, index, save_nmsrs++);
 840         }
 841 #endif
 842         vmx->save_nmsrs = save_nmsrs;
 843
 844 #ifdef CONFIG_X86_64
 845         vmx->msr_offset_kernel_gs_base =
 846                 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 847 #endif
 848         vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
 849 }
 850
 851 /*
 852  * reads and returns guest's timestamp counter "register"
 853  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 854  */
 855 static u64 guest_read_tsc(void)
 856 {
 857         u64 host_tsc, tsc_offset;
 858
 859         rdtscll(host_tsc);
 860         tsc_offset = vmcs_read64(TSC_OFFSET);
 861         return host_tsc + tsc_offset;
 862 }
 863
 864 /*
 865  * writes 'guest_tsc' into guest's timestamp counter "register"
 866  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 867  */
 868 static void guest_write_tsc(u64 guest_tsc)
 869 {
 870         u64 host_tsc;
 871
 872         rdtscll(host_tsc);
 873         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 874 }
 875
 876 /*
 877  * Reads an msr value (of 'msr_index') into 'pdata'.
 878  * Returns 0 on success, non-0 otherwise.
 879  * Assumes vcpu_load() was already called.
 880  */
 881 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
 882 {
 883         u64 data;
 884         struct kvm_msr_entry *msr;
 885
 886         if (!pdata) {
 887                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
 888                 return -EINVAL;
 889         }
 890
 891         switch (msr_index) {
 892 #ifdef CONFIG_X86_64
 893         case MSR_FS_BASE:
 894                 data = vmcs_readl(GUEST_FS_BASE);
 895                 break;
 896         case MSR_GS_BASE:
 897                 data = vmcs_readl(GUEST_GS_BASE);
 898                 break;
 899         case MSR_EFER:
 900                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 901 #endif
 902         case MSR_IA32_TIME_STAMP_COUNTER:
 903                 data = guest_read_tsc();
 904                 break;
 905         case MSR_IA32_SYSENTER_CS:
 906                 data = vmcs_read32(GUEST_SYSENTER_CS);
 907                 break;
 908         case MSR_IA32_SYSENTER_EIP:
 909                 data = vmcs_readl(GUEST_SYSENTER_EIP);
 910                 break;
 911         case MSR_IA32_SYSENTER_ESP:
 912                 data = vmcs_readl(GUEST_SYSENTER_ESP);
 913                 break;
 914         default:
 915                 vmx_load_host_state(to_vmx(vcpu));
 916                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
 917                 if (msr) {
 918                         data = msr->data;
 919                         break;
 920                 }
 921                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 922         }
 923
 924         *pdata = data;
 925         return 0;
 926 }
 927
 928 /*
 929  * Writes msr value into into the appropriate "register".
 930  * Returns 0 on success, non-0 otherwise.
 931  * Assumes vcpu_load() was already called.
 932  */
 933 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
 934 {
 935         struct vcpu_vmx *vmx = to_vmx(vcpu);
 936         struct kvm_msr_entry *msr;
 937         int ret = 0;
 938
 939         switch (msr_index) {
 940 #ifdef CONFIG_X86_64
 941         case MSR_EFER:
 942                 vmx_load_host_state(vmx);
 943                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 944                 break;
 945         case MSR_FS_BASE:
 946                 vmcs_writel(GUEST_FS_BASE, data);
 947                 break;
 948         case MSR_GS_BASE:
 949                 vmcs_writel(GUEST_GS_BASE, data);
 950                 break;
 951 #endif
 952         case MSR_IA32_SYSENTER_CS:
 953                 vmcs_write32(GUEST_SYSENTER_CS, data);
 954                 break;
 955         case MSR_IA32_SYSENTER_EIP:
 956                 vmcs_writel(GUEST_SYSENTER_EIP, data);
 957                 break;
 958         case MSR_IA32_SYSENTER_ESP:
 959                 vmcs_writel(GUEST_SYSENTER_ESP, data);
 960                 break;
 961         case MSR_IA32_TIME_STAMP_COUNTER:
 962                 guest_write_tsc(data);
 963                 break;
 964         case MSR_P6_PERFCTR0:
 965         case MSR_P6_PERFCTR1:
 966         case MSR_P6_EVNTSEL0:
 967         case MSR_P6_EVNTSEL1:
 968                 /*
 969                  * Just discard all writes to the performance counters; this
 970                  * should keep both older linux and windows 64-bit guests
 971                  * happy
 972                  */
 973                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
 974
 975                 break;
 976         case MSR_IA32_CR_PAT:
 977                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
 978                         vmcs_write64(GUEST_IA32_PAT, data);
 979                         vcpu->arch.pat = data;
 980                         break;
 981                 }
 982                 /* Otherwise falls through to kvm_set_msr_common */
 983         default:
 984                 vmx_load_host_state(vmx);
 985                 msr = find_msr_entry(vmx, msr_index);
 986                 if (msr) {
 987                         msr->data = data;
 988                         break;
 989                 }
 990                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 991         }
 992
 993         return ret;
 994 }
 995
 996 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
 997 {
 998         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
 999         switch (reg) {
1000         case VCPU_REGS_RSP:
1001                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1002                 break;
1003         case VCPU_REGS_RIP:
1004                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1005                 break;
1006         default:
1007                 break;
1008         }
1009 }
1010
1011 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1012 {
1013         int old_debug = vcpu->guest_debug;
1014         unsigned long flags;
1015
1016         vcpu->guest_debug = dbg->control;
1017         if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
1018                 vcpu->guest_debug = 0;
1019
1020         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1021                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1022         else
1023                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1024
1025         flags = vmcs_readl(GUEST_RFLAGS);
1026         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1027                 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1028         else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1029                 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1030         vmcs_writel(GUEST_RFLAGS, flags);
1031
1032         update_exception_bitmap(vcpu);
1033
1034         return 0;
1035 }
1036
1037 static int vmx_get_irq(struct kvm_vcpu *vcpu)
1038 {
1039         if (!vcpu->arch.interrupt.pending)
1040                 return -1;
1041         return vcpu->arch.interrupt.nr;
1042 }
1043
1044 static __init int cpu_has_kvm_support(void)
1045 {
1046         return cpu_has_vmx();
1047 }
1048
1049 static __init int vmx_disabled_by_bios(void)
1050 {
1051         u64 msr;
1052
1053         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1054         return (msr & (FEATURE_CONTROL_LOCKED |
1055                        FEATURE_CONTROL_VMXON_ENABLED))
1056             == FEATURE_CONTROL_LOCKED;
1057         /* locked but not enabled */
1058 }
1059
1060 static void hardware_enable(void *garbage)
1061 {
1062         int cpu = raw_smp_processor_id();
1063         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1064         u64 old;
1065
1066         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1067         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1068         if ((old & (FEATURE_CONTROL_LOCKED |
1069                     FEATURE_CONTROL_VMXON_ENABLED))
1070             != (FEATURE_CONTROL_LOCKED |
1071                 FEATURE_CONTROL_VMXON_ENABLED))
1072                 /* enable and lock */
1073                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1074                        FEATURE_CONTROL_LOCKED |
1075                        FEATURE_CONTROL_VMXON_ENABLED);
1076         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1077         asm volatile (ASM_VMX_VMXON_RAX
1078                       : : "a"(&phys_addr), "m"(phys_addr)
1079                       : "memory", "cc");
1080 }
1081
1082 static void vmclear_local_vcpus(void)
1083 {
1084         int cpu = raw_smp_processor_id();
1085         struct vcpu_vmx *vmx, *n;
1086
1087         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1088                                  local_vcpus_link)
1089                 __vcpu_clear(vmx);
1090 }
1091
1092
1093 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1094  * tricks.
1095  */
1096 static void kvm_cpu_vmxoff(void)
1097 {
1098         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1099         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1100 }
1101
1102 static void hardware_disable(void *garbage)
1103 {
1104         vmclear_local_vcpus();
1105         kvm_cpu_vmxoff();
1106 }
1107
1108 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1109                                       u32 msr, u32 *result)
1110 {
1111         u32 vmx_msr_low, vmx_msr_high;
1112         u32 ctl = ctl_min | ctl_opt;
1113
1114         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1115
1116         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1117         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1118
1119         /* Ensure minimum (required) set of control bits are supported. */
1120         if (ctl_min & ~ctl)
1121                 return -EIO;
1122
1123         *result = ctl;
1124         return 0;
1125 }
1126
1127 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1128 {
1129         u32 vmx_msr_low, vmx_msr_high;
1130         u32 min, opt, min2, opt2;
1131         u32 _pin_based_exec_control = 0;
1132         u32 _cpu_based_exec_control = 0;
1133         u32 _cpu_based_2nd_exec_control = 0;
1134         u32 _vmexit_control = 0;
1135         u32 _vmentry_control = 0;
1136
1137         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1138         opt = PIN_BASED_VIRTUAL_NMIS;
1139         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1140                                 &_pin_based_exec_control) < 0)
1141                 return -EIO;
1142
1143         min = CPU_BASED_HLT_EXITING |
1144 #ifdef CONFIG_X86_64
1145               CPU_BASED_CR8_LOAD_EXITING |
1146               CPU_BASED_CR8_STORE_EXITING |
1147 #endif
1148               CPU_BASED_CR3_LOAD_EXITING |
1149               CPU_BASED_CR3_STORE_EXITING |
1150               CPU_BASED_USE_IO_BITMAPS |
1151               CPU_BASED_MOV_DR_EXITING |
1152               CPU_BASED_USE_TSC_OFFSETING |
1153               CPU_BASED_INVLPG_EXITING;
1154         opt = CPU_BASED_TPR_SHADOW |
1155               CPU_BASED_USE_MSR_BITMAPS |
1156               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1157         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1158                                 &_cpu_based_exec_control) < 0)
1159                 return -EIO;
1160 #ifdef CONFIG_X86_64
1161         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1162                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1163                                            ~CPU_BASED_CR8_STORE_EXITING;
1164 #endif
1165         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1166                 min2 = 0;
1167                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1168                         SECONDARY_EXEC_WBINVD_EXITING |
1169                         SECONDARY_EXEC_ENABLE_VPID |
1170                         SECONDARY_EXEC_ENABLE_EPT;
1171                 if (adjust_vmx_controls(min2, opt2,
1172                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1173                                         &_cpu_based_2nd_exec_control) < 0)
1174                         return -EIO;
1175         }
1176 #ifndef CONFIG_X86_64
1177         if (!(_cpu_based_2nd_exec_control &
1178                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1179                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1180 #endif
1181         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1182                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1183                    enabled */
1184                 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1185                          CPU_BASED_CR3_STORE_EXITING |
1186                          CPU_BASED_INVLPG_EXITING);
1187                 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1188                                         &_cpu_based_exec_control) < 0)
1189                         return -EIO;
1190                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1191                       vmx_capability.ept, vmx_capability.vpid);
1192         }
1193
1194         min = 0;
1195 #ifdef CONFIG_X86_64
1196         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1197 #endif
1198         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1199         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1200                                 &_vmexit_control) < 0)
1201                 return -EIO;
1202
1203         min = 0;
1204         opt = VM_ENTRY_LOAD_IA32_PAT;
1205         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1206                                 &_vmentry_control) < 0)
1207                 return -EIO;
1208
1209         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1210
1211         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1212         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1213                 return -EIO;
1214
1215 #ifdef CONFIG_X86_64
1216         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1217         if (vmx_msr_high & (1u<<16))
1218                 return -EIO;
1219 #endif
1220
1221         /* Require Write-Back (WB) memory type for VMCS accesses. */
1222         if (((vmx_msr_high >> 18) & 15) != 6)
1223                 return -EIO;
1224
1225         vmcs_conf->size = vmx_msr_high & 0x1fff;
1226         vmcs_conf->order = get_order(vmcs_config.size);
1227         vmcs_conf->revision_id = vmx_msr_low;
1228
1229         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1230         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1231         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1232         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1233         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1234
1235         return 0;
1236 }
1237
1238 static struct vmcs *alloc_vmcs_cpu(int cpu)
1239 {
1240         int node = cpu_to_node(cpu);
1241         struct page *pages;
1242         struct vmcs *vmcs;
1243
1244         pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1245         if (!pages)
1246                 return NULL;
1247         vmcs = page_address(pages);
1248         memset(vmcs, 0, vmcs_config.size);
1249         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1250         return vmcs;
1251 }
1252
1253 static struct vmcs *alloc_vmcs(void)
1254 {
1255         return alloc_vmcs_cpu(raw_smp_processor_id());
1256 }
1257
1258 static void free_vmcs(struct vmcs *vmcs)
1259 {
1260         free_pages((unsigned long)vmcs, vmcs_config.order);
1261 }
1262
1263 static void free_kvm_area(void)
1264 {
1265         int cpu;
1266
1267         for_each_online_cpu(cpu)
1268                 free_vmcs(per_cpu(vmxarea, cpu));
1269 }
1270
1271 static __init int alloc_kvm_area(void)
1272 {
1273         int cpu;
1274
1275         for_each_online_cpu(cpu) {
1276                 struct vmcs *vmcs;
1277
1278                 vmcs = alloc_vmcs_cpu(cpu);
1279                 if (!vmcs) {
1280                         free_kvm_area();
1281                         return -ENOMEM;
1282                 }
1283
1284                 per_cpu(vmxarea, cpu) = vmcs;
1285         }
1286         return 0;
1287 }
1288
1289 static __init int hardware_setup(void)
1290 {
1291         if (setup_vmcs_config(&vmcs_config) < 0)
1292                 return -EIO;
1293
1294         if (boot_cpu_has(X86_FEATURE_NX))
1295                 kvm_enable_efer_bits(EFER_NX);
1296
1297         return alloc_kvm_area();
1298 }
1299
1300 static __exit void hardware_unsetup(void)
1301 {
1302         free_kvm_area();
1303 }
1304
1305 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1306 {
1307         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1308
1309         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1310                 vmcs_write16(sf->selector, save->selector);
1311                 vmcs_writel(sf->base, save->base);
1312                 vmcs_write32(sf->limit, save->limit);
1313                 vmcs_write32(sf->ar_bytes, save->ar);
1314         } else {
1315                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1316                         << AR_DPL_SHIFT;
1317                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1318         }
1319 }
1320
1321 static void enter_pmode(struct kvm_vcpu *vcpu)
1322 {
1323         unsigned long flags;
1324         struct vcpu_vmx *vmx = to_vmx(vcpu);
1325
1326         vmx->emulation_required = 1;
1327         vcpu->arch.rmode.active = 0;
1328
1329         vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1330         vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1331         vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1332
1333         flags = vmcs_readl(GUEST_RFLAGS);
1334         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1335         flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1336         vmcs_writel(GUEST_RFLAGS, flags);
1337
1338         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1339                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1340
1341         update_exception_bitmap(vcpu);
1342
1343         if (emulate_invalid_guest_state)
1344                 return;
1345
1346         fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1347         fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1348         fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1349         fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1350
1351         vmcs_write16(GUEST_SS_SELECTOR, 0);
1352         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1353
1354         vmcs_write16(GUEST_CS_SELECTOR,
1355                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1356         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1357 }
1358
1359 static gva_t rmode_tss_base(struct kvm *kvm)
1360 {
1361         if (!kvm->arch.tss_addr) {
1362                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1363                                  kvm->memslots[0].npages - 3;
1364                 return base_gfn << PAGE_SHIFT;
1365         }
1366         return kvm->arch.tss_addr;
1367 }
1368
1369 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1370 {
1371         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1372
1373         save->selector = vmcs_read16(sf->selector);
1374         save->base = vmcs_readl(sf->base);
1375         save->limit = vmcs_read32(sf->limit);
1376         save->ar = vmcs_read32(sf->ar_bytes);
1377         vmcs_write16(sf->selector, save->base >> 4);
1378         vmcs_write32(sf->base, save->base & 0xfffff);
1379         vmcs_write32(sf->limit, 0xffff);
1380         vmcs_write32(sf->ar_bytes, 0xf3);
1381 }
1382
1383 static void enter_rmode(struct kvm_vcpu *vcpu)
1384 {
1385         unsigned long flags;
1386         struct vcpu_vmx *vmx = to_vmx(vcpu);
1387
1388         vmx->emulation_required = 1;
1389         vcpu->arch.rmode.active = 1;
1390
1391         vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1392         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1393
1394         vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1395         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1396
1397         vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1398         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1399
1400         flags = vmcs_readl(GUEST_RFLAGS);
1401         vcpu->arch.rmode.save_iopl
1402                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1403
1404         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1405
1406         vmcs_writel(GUEST_RFLAGS, flags);
1407         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1408         update_exception_bitmap(vcpu);
1409
1410         if (emulate_invalid_guest_state)
1411                 goto continue_rmode;
1412
1413         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1414         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1415         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1416
1417         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1418         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1419         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1420                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1421         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1422
1423         fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1424         fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1425         fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1426         fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1427
1428 continue_rmode:
1429         kvm_mmu_reset_context(vcpu);
1430         init_rmode(vcpu->kvm);
1431 }
1432
1433 #ifdef CONFIG_X86_64
1434
1435 static void enter_lmode(struct kvm_vcpu *vcpu)
1436 {
1437         u32 guest_tr_ar;
1438
1439         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1440         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1441                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1442                        __func__);
1443                 vmcs_write32(GUEST_TR_AR_BYTES,
1444                              (guest_tr_ar & ~AR_TYPE_MASK)
1445                              | AR_TYPE_BUSY_64_TSS);
1446         }
1447
1448         vcpu->arch.shadow_efer |= EFER_LMA;
1449
1450         find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1451         vmcs_write32(VM_ENTRY_CONTROLS,
1452                      vmcs_read32(VM_ENTRY_CONTROLS)
1453                      | VM_ENTRY_IA32E_MODE);
1454 }
1455
1456 static void exit_lmode(struct kvm_vcpu *vcpu)
1457 {
1458         vcpu->arch.shadow_efer &= ~EFER_LMA;
1459
1460         vmcs_write32(VM_ENTRY_CONTROLS,
1461                      vmcs_read32(VM_ENTRY_CONTROLS)
1462                      & ~VM_ENTRY_IA32E_MODE);
1463 }
1464
1465 #endif
1466
1467 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1468 {
1469         vpid_sync_vcpu_all(to_vmx(vcpu));
1470         if (vm_need_ept())
1471                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1472 }
1473
1474 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1475 {
1476         vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1477         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1478 }
1479
1480 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1481 {
1482         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1483                 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1484                         printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1485                         return;
1486                 }
1487                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1488                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1489                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1490                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1491         }
1492 }
1493
1494 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1495
1496 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1497                                         unsigned long cr0,
1498                                         struct kvm_vcpu *vcpu)
1499 {
1500         if (!(cr0 & X86_CR0_PG)) {
1501                 /* From paging/starting to nonpaging */
1502                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1503                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1504                              (CPU_BASED_CR3_LOAD_EXITING |
1505                               CPU_BASED_CR3_STORE_EXITING));
1506                 vcpu->arch.cr0 = cr0;
1507                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1508                 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1509                 *hw_cr0 &= ~X86_CR0_WP;
1510         } else if (!is_paging(vcpu)) {
1511                 /* From nonpaging to paging */
1512                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1513                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1514                              ~(CPU_BASED_CR3_LOAD_EXITING |
1515                                CPU_BASED_CR3_STORE_EXITING));
1516                 vcpu->arch.cr0 = cr0;
1517                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1518                 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1519                         *hw_cr0 &= ~X86_CR0_WP;
1520         }
1521 }
1522
1523 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1524                                         struct kvm_vcpu *vcpu)
1525 {
1526         if (!is_paging(vcpu)) {
1527                 *hw_cr4 &= ~X86_CR4_PAE;
1528                 *hw_cr4 |= X86_CR4_PSE;
1529         } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1530                 *hw_cr4 &= ~X86_CR4_PAE;
1531 }
1532
1533 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1534 {
1535         unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1536                                 KVM_VM_CR0_ALWAYS_ON;
1537
1538         vmx_fpu_deactivate(vcpu);
1539
1540         if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
1541                 enter_pmode(vcpu);
1542
1543         if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
1544                 enter_rmode(vcpu);
1545
1546 #ifdef CONFIG_X86_64
1547         if (vcpu->arch.shadow_efer & EFER_LME) {
1548                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1549                         enter_lmode(vcpu);
1550                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1551                         exit_lmode(vcpu);
1552         }
1553 #endif
1554
1555         if (vm_need_ept())
1556                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1557
1558         vmcs_writel(CR0_READ_SHADOW, cr0);
1559         vmcs_writel(GUEST_CR0, hw_cr0);
1560         vcpu->arch.cr0 = cr0;
1561
1562         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1563                 vmx_fpu_activate(vcpu);
1564 }
1565
1566 static u64 construct_eptp(unsigned long root_hpa)
1567 {
1568         u64 eptp;
1569
1570         /* TODO write the value reading from MSR */
1571         eptp = VMX_EPT_DEFAULT_MT |
1572                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1573         eptp |= (root_hpa & PAGE_MASK);
1574
1575         return eptp;
1576 }
1577
1578 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1579 {
1580         unsigned long guest_cr3;
1581         u64 eptp;
1582
1583         guest_cr3 = cr3;
1584         if (vm_need_ept()) {
1585                 eptp = construct_eptp(cr3);
1586                 vmcs_write64(EPT_POINTER, eptp);
1587                 ept_sync_context(eptp);
1588                 ept_load_pdptrs(vcpu);
1589                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1590                         VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1591         }
1592
1593         vmx_flush_tlb(vcpu);
1594         vmcs_writel(GUEST_CR3, guest_cr3);
1595         if (vcpu->arch.cr0 & X86_CR0_PE)
1596                 vmx_fpu_deactivate(vcpu);
1597 }
1598
1599 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1600 {
1601         unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1602                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1603
1604         vcpu->arch.cr4 = cr4;
1605         if (vm_need_ept())
1606                 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1607
1608         vmcs_writel(CR4_READ_SHADOW, cr4);
1609         vmcs_writel(GUEST_CR4, hw_cr4);
1610 }
1611
1612 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1613 {
1614         struct vcpu_vmx *vmx = to_vmx(vcpu);
1615         struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1616
1617         vcpu->arch.shadow_efer = efer;
1618         if (!msr)
1619                 return;
1620         if (efer & EFER_LMA) {
1621                 vmcs_write32(VM_ENTRY_CONTROLS,
1622                                      vmcs_read32(VM_ENTRY_CONTROLS) |
1623                                      VM_ENTRY_IA32E_MODE);
1624                 msr->data = efer;
1625
1626         } else {
1627                 vmcs_write32(VM_ENTRY_CONTROLS,
1628                                      vmcs_read32(VM_ENTRY_CONTROLS) &
1629                                      ~VM_ENTRY_IA32E_MODE);
1630
1631                 msr->data = efer & ~EFER_LME;
1632         }
1633         setup_msrs(vmx);
1634 }
1635
1636 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1637 {
1638         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1639
1640         return vmcs_readl(sf->base);
1641 }
1642
1643 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1644                             struct kvm_segment *var, int seg)
1645 {
1646         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1647         u32 ar;
1648
1649         var->base = vmcs_readl(sf->base);
1650         var->limit = vmcs_read32(sf->limit);
1651         var->selector = vmcs_read16(sf->selector);
1652         ar = vmcs_read32(sf->ar_bytes);
1653         if (ar & AR_UNUSABLE_MASK)
1654                 ar = 0;
1655         var->type = ar & 15;
1656         var->s = (ar >> 4) & 1;
1657         var->dpl = (ar >> 5) & 3;
1658         var->present = (ar >> 7) & 1;
1659         var->avl = (ar >> 12) & 1;
1660         var->l = (ar >> 13) & 1;
1661         var->db = (ar >> 14) & 1;
1662         var->g = (ar >> 15) & 1;
1663         var->unusable = (ar >> 16) & 1;
1664 }
1665
1666 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1667 {
1668         struct kvm_segment kvm_seg;
1669
1670         if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1671                 return 0;
1672
1673         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1674                 return 3;
1675
1676         vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1677         return kvm_seg.selector & 3;
1678 }
1679
1680 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1681 {
1682         u32 ar;
1683
1684         if (var->unusable)
1685                 ar = 1 << 16;
1686         else {
1687                 ar = var->type & 15;
1688                 ar |= (var->s & 1) << 4;
1689                 ar |= (var->dpl & 3) << 5;
1690                 ar |= (var->present & 1) << 7;
1691                 ar |= (var->avl & 1) << 12;
1692                 ar |= (var->l & 1) << 13;
1693                 ar |= (var->db & 1) << 14;
1694                 ar |= (var->g & 1) << 15;
1695         }
1696         if (ar == 0) /* a 0 value means unusable */
1697                 ar = AR_UNUSABLE_MASK;
1698
1699         return ar;
1700 }
1701
1702 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1703                             struct kvm_segment *var, int seg)
1704 {
1705         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1706         u32 ar;
1707
1708         if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1709                 vcpu->arch.rmode.tr.selector = var->selector;
1710                 vcpu->arch.rmode.tr.base = var->base;
1711                 vcpu->arch.rmode.tr.limit = var->limit;
1712                 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1713                 return;
1714         }
1715         vmcs_writel(sf->base, var->base);
1716         vmcs_write32(sf->limit, var->limit);
1717         vmcs_write16(sf->selector, var->selector);
1718         if (vcpu->arch.rmode.active && var->s) {
1719                 /*
1720                  * Hack real-mode segments into vm86 compatibility.
1721                  */
1722                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1723                         vmcs_writel(sf->base, 0xf0000);
1724                 ar = 0xf3;
1725         } else
1726                 ar = vmx_segment_access_rights(var);
1727         vmcs_write32(sf->ar_bytes, ar);
1728 }
1729
1730 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1731 {
1732         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1733
1734         *db = (ar >> 14) & 1;
1735         *l = (ar >> 13) & 1;
1736 }
1737
1738 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1739 {
1740         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1741         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1742 }
1743
1744 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1745 {
1746         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1747         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1748 }
1749
1750 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1751 {
1752         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1753         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1754 }
1755
1756 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1757 {
1758         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1759         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1760 }
1761
1762 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1763 {
1764         struct kvm_segment var;
1765         u32 ar;
1766
1767         vmx_get_segment(vcpu, &var, seg);
1768         ar = vmx_segment_access_rights(&var);
1769
1770         if (var.base != (var.selector << 4))
1771                 return false;
1772         if (var.limit != 0xffff)
1773                 return false;
1774         if (ar != 0xf3)
1775                 return false;
1776
1777         return true;
1778 }
1779
1780 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1781 {
1782         struct kvm_segment cs;
1783         unsigned int cs_rpl;
1784
1785         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1786         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1787
1788         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1789                 return false;
1790         if (!cs.s)
1791                 return false;
1792         if (!(~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK))) {
1793                 if (cs.dpl > cs_rpl)
1794                         return false;
1795         } else if (cs.type & AR_TYPE_CODE_MASK) {
1796                 if (cs.dpl != cs_rpl)
1797                         return false;
1798         }
1799         if (!cs.present)
1800                 return false;
1801
1802         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1803         return true;
1804 }
1805
1806 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1807 {
1808         struct kvm_segment ss;
1809         unsigned int ss_rpl;
1810
1811         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1812         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1813
1814         if ((ss.type != 3) || (ss.type != 7))
1815                 return false;
1816         if (!ss.s)
1817                 return false;
1818         if (ss.dpl != ss_rpl) /* DPL != RPL */
1819                 return false;
1820         if (!ss.present)
1821                 return false;
1822
1823         return true;
1824 }
1825
1826 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1827 {
1828         struct kvm_segment var;
1829         unsigned int rpl;
1830
1831         vmx_get_segment(vcpu, &var, seg);
1832         rpl = var.selector & SELECTOR_RPL_MASK;
1833
1834         if (!var.s)
1835                 return false;
1836         if (!var.present)
1837                 return false;
1838         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1839                 if (var.dpl < rpl) /* DPL < RPL */
1840                         return false;
1841         }
1842
1843         /* TODO: Add other members to kvm_segment_field to allow checking for other access
1844          * rights flags
1845          */
1846         return true;
1847 }
1848
1849 static bool tr_valid(struct kvm_vcpu *vcpu)
1850 {
1851         struct kvm_segment tr;
1852
1853         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1854
1855         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
1856                 return false;
1857         if ((tr.type != 3) || (tr.type != 11)) /* TODO: Check if guest is in IA32e mode */
1858                 return false;
1859         if (!tr.present)
1860                 return false;
1861
1862         return true;
1863 }
1864
1865 static bool ldtr_valid(struct kvm_vcpu *vcpu)
1866 {
1867         struct kvm_segment ldtr;
1868
1869         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1870
1871         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
1872                 return false;
1873         if (ldtr.type != 2)
1874                 return false;
1875         if (!ldtr.present)
1876                 return false;
1877
1878         return true;
1879 }
1880
1881 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
1882 {
1883         struct kvm_segment cs, ss;
1884
1885         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1886         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1887
1888         return ((cs.selector & SELECTOR_RPL_MASK) ==
1889                  (ss.selector & SELECTOR_RPL_MASK));
1890 }
1891
1892 /*
1893  * Check if guest state is valid. Returns true if valid, false if
1894  * not.
1895  * We assume that registers are always usable
1896  */
1897 static bool guest_state_valid(struct kvm_vcpu *vcpu)
1898 {
1899         /* real mode guest state checks */
1900         if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
1901                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
1902                         return false;
1903                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
1904                         return false;
1905                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
1906                         return false;
1907                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
1908                         return false;
1909                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
1910                         return false;
1911                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
1912                         return false;
1913         } else {
1914         /* protected mode guest state checks */
1915                 if (!cs_ss_rpl_check(vcpu))
1916                         return false;
1917                 if (!code_segment_valid(vcpu))
1918                         return false;
1919                 if (!stack_segment_valid(vcpu))
1920                         return false;
1921                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
1922                         return false;
1923                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
1924                         return false;
1925                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
1926                         return false;
1927                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
1928                         return false;
1929                 if (!tr_valid(vcpu))
1930                         return false;
1931                 if (!ldtr_valid(vcpu))
1932                         return false;
1933         }
1934         /* TODO:
1935          * - Add checks on RIP
1936          * - Add checks on RFLAGS
1937          */
1938
1939         return true;
1940 }
1941
1942 static int init_rmode_tss(struct kvm *kvm)
1943 {
1944         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1945         u16 data = 0;
1946         int ret = 0;
1947         int r;
1948
1949         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1950         if (r < 0)
1951                 goto out;
1952         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1953         r = kvm_write_guest_page(kvm, fn++, &data,
1954                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
1955         if (r < 0)
1956                 goto out;
1957         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1958         if (r < 0)
1959                 goto out;
1960         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1961         if (r < 0)
1962                 goto out;
1963         data = ~0;
1964         r = kvm_write_guest_page(kvm, fn, &data,
1965                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1966                                  sizeof(u8));
1967         if (r < 0)
1968                 goto out;
1969
1970         ret = 1;
1971 out:
1972         return ret;
1973 }
1974
1975 static int init_rmode_identity_map(struct kvm *kvm)
1976 {
1977         int i, r, ret;
1978         pfn_t identity_map_pfn;
1979         u32 tmp;
1980
1981         if (!vm_need_ept())
1982                 return 1;
1983         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
1984                 printk(KERN_ERR "EPT: identity-mapping pagetable "
1985                         "haven't been allocated!\n");
1986                 return 0;
1987         }
1988         if (likely(kvm->arch.ept_identity_pagetable_done))
1989                 return 1;
1990         ret = 0;
1991         identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
1992         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
1993         if (r < 0)
1994                 goto out;
1995         /* Set up identity-mapping pagetable for EPT in real mode */
1996         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
1997                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
1998                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
1999                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2000                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2001                 if (r < 0)
2002                         goto out;
2003         }
2004         kvm->arch.ept_identity_pagetable_done = true;
2005         ret = 1;
2006 out:
2007         return ret;
2008 }
2009
2010 static void seg_setup(int seg)
2011 {
2012         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2013
2014         vmcs_write16(sf->selector, 0);
2015         vmcs_writel(sf->base, 0);
2016         vmcs_write32(sf->limit, 0xffff);
2017         vmcs_write32(sf->ar_bytes, 0xf3);
2018 }
2019
2020 static int alloc_apic_access_page(struct kvm *kvm)
2021 {
2022         struct kvm_userspace_memory_region kvm_userspace_mem;
2023         int r = 0;
2024
2025         down_write(&kvm->slots_lock);
2026         if (kvm->arch.apic_access_page)
2027                 goto out;
2028         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2029         kvm_userspace_mem.flags = 0;
2030         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2031         kvm_userspace_mem.memory_size = PAGE_SIZE;
2032         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2033         if (r)
2034                 goto out;
2035
2036         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2037 out:
2038         up_write(&kvm->slots_lock);
2039         return r;
2040 }
2041
2042 static int alloc_identity_pagetable(struct kvm *kvm)
2043 {
2044         struct kvm_userspace_memory_region kvm_userspace_mem;
2045         int r = 0;
2046
2047         down_write(&kvm->slots_lock);
2048         if (kvm->arch.ept_identity_pagetable)
2049                 goto out;
2050         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2051         kvm_userspace_mem.flags = 0;
2052         kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2053         kvm_userspace_mem.memory_size = PAGE_SIZE;
2054         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2055         if (r)
2056                 goto out;
2057
2058         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2059                         VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
2060 out:
2061         up_write(&kvm->slots_lock);
2062         return r;
2063 }
2064
2065 static void allocate_vpid(struct vcpu_vmx *vmx)
2066 {
2067         int vpid;
2068
2069         vmx->vpid = 0;
2070         if (!enable_vpid || !cpu_has_vmx_vpid())
2071                 return;
2072         spin_lock(&vmx_vpid_lock);
2073         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2074         if (vpid < VMX_NR_VPIDS) {
2075                 vmx->vpid = vpid;
2076                 __set_bit(vpid, vmx_vpid_bitmap);
2077         }
2078         spin_unlock(&vmx_vpid_lock);
2079 }
2080
2081 static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr)
2082 {
2083         void *va;
2084
2085         if (!cpu_has_vmx_msr_bitmap())
2086                 return;
2087
2088         /*
2089          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2090          * have the write-low and read-high bitmap offsets the wrong way round.
2091          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2092          */
2093         va = kmap(msr_bitmap);
2094         if (msr <= 0x1fff) {
2095                 __clear_bit(msr, va + 0x000); /* read-low */
2096                 __clear_bit(msr, va + 0x800); /* write-low */
2097         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2098                 msr &= 0x1fff;
2099                 __clear_bit(msr, va + 0x400); /* read-high */
2100                 __clear_bit(msr, va + 0xc00); /* write-high */
2101         }
2102         kunmap(msr_bitmap);
2103 }
2104
2105 /*
2106  * Sets up the vmcs for emulated real mode.
2107  */
2108 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2109 {
2110         u32 host_sysenter_cs, msr_low, msr_high;
2111         u32 junk;
2112         u64 host_pat;
2113         unsigned long a;
2114         struct descriptor_table dt;
2115         int i;
2116         unsigned long kvm_vmx_return;
2117         u32 exec_control;
2118
2119         /* I/O */
2120         vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
2121         vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
2122
2123         if (cpu_has_vmx_msr_bitmap())
2124                 vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap));
2125
2126         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2127
2128         /* Control */
2129         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2130                 vmcs_config.pin_based_exec_ctrl);
2131
2132         exec_control = vmcs_config.cpu_based_exec_ctrl;
2133         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2134                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2135 #ifdef CONFIG_X86_64
2136                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2137                                 CPU_BASED_CR8_LOAD_EXITING;
2138 #endif
2139         }
2140         if (!vm_need_ept())
2141                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2142                                 CPU_BASED_CR3_LOAD_EXITING  |
2143                                 CPU_BASED_INVLPG_EXITING;
2144         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2145
2146         if (cpu_has_secondary_exec_ctrls()) {
2147                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2148                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2149                         exec_control &=
2150                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2151                 if (vmx->vpid == 0)
2152                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2153                 if (!vm_need_ept())
2154                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2155                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2156         }
2157
2158         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2159         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2160         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2161
2162         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
2163         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2164         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2165
2166         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2167         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2168         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2169         vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs());    /* 22.2.4 */
2170         vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs());    /* 22.2.4 */
2171         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2172 #ifdef CONFIG_X86_64
2173         rdmsrl(MSR_FS_BASE, a);
2174         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2175         rdmsrl(MSR_GS_BASE, a);
2176         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2177 #else
2178         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2179         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2180 #endif
2181
2182         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2183
2184         kvm_get_idt(&dt);
2185         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
2186
2187         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2188         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2189         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2190         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2191         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2192
2193         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2194         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2195         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2196         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2197         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2198         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2199
2200         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2201                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2202                 host_pat = msr_low | ((u64) msr_high << 32);
2203                 vmcs_write64(HOST_IA32_PAT, host_pat);
2204         }
2205         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2206                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2207                 host_pat = msr_low | ((u64) msr_high << 32);
2208                 /* Write the default value follow host pat */
2209                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2210                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2211                 vmx->vcpu.arch.pat = host_pat;
2212         }
2213
2214         for (i = 0; i < NR_VMX_MSR; ++i) {
2215                 u32 index = vmx_msr_index[i];
2216                 u32 data_low, data_high;
2217                 u64 data;
2218                 int j = vmx->nmsrs;
2219
2220                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2221                         continue;
2222                 if (wrmsr_safe(index, data_low, data_high) < 0)
2223                         continue;
2224                 data = data_low | ((u64)data_high << 32);
2225                 vmx->host_msrs[j].index = index;
2226                 vmx->host_msrs[j].reserved = 0;
2227                 vmx->host_msrs[j].data = data;
2228                 vmx->guest_msrs[j] = vmx->host_msrs[j];
2229                 ++vmx->nmsrs;
2230         }
2231
2232         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2233
2234         /* 22.2.1, 20.8.1 */
2235         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2236
2237         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2238         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2239
2240
2241         return 0;
2242 }
2243
2244 static int init_rmode(struct kvm *kvm)
2245 {
2246         if (!init_rmode_tss(kvm))
2247                 return 0;
2248         if (!init_rmode_identity_map(kvm))
2249                 return 0;
2250         return 1;
2251 }
2252
2253 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2254 {
2255         struct vcpu_vmx *vmx = to_vmx(vcpu);
2256         u64 msr;
2257         int ret;
2258
2259         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2260         down_read(&vcpu->kvm->slots_lock);
2261         if (!init_rmode(vmx->vcpu.kvm)) {
2262                 ret = -ENOMEM;
2263                 goto out;
2264         }
2265
2266         vmx->vcpu.arch.rmode.active = 0;
2267
2268         vmx->soft_vnmi_blocked = 0;
2269
2270         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2271         kvm_set_cr8(&vmx->vcpu, 0);
2272         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2273         if (vmx->vcpu.vcpu_id == 0)
2274                 msr |= MSR_IA32_APICBASE_BSP;
2275         kvm_set_apic_base(&vmx->vcpu, msr);
2276
2277         fx_init(&vmx->vcpu);
2278
2279         seg_setup(VCPU_SREG_CS);
2280         /*
2281          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2282          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2283          */
2284         if (vmx->vcpu.vcpu_id == 0) {
2285                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2286                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2287         } else {
2288                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2289                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2290         }
2291
2292         seg_setup(VCPU_SREG_DS);
2293         seg_setup(VCPU_SREG_ES);
2294         seg_setup(VCPU_SREG_FS);
2295         seg_setup(VCPU_SREG_GS);
2296         seg_setup(VCPU_SREG_SS);
2297
2298         vmcs_write16(GUEST_TR_SELECTOR, 0);
2299         vmcs_writel(GUEST_TR_BASE, 0);
2300         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2301         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2302
2303         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2304         vmcs_writel(GUEST_LDTR_BASE, 0);
2305         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2306         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2307
2308         vmcs_write32(GUEST_SYSENTER_CS, 0);
2309         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2310         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2311
2312         vmcs_writel(GUEST_RFLAGS, 0x02);
2313         if (vmx->vcpu.vcpu_id == 0)
2314                 kvm_rip_write(vcpu, 0xfff0);
2315         else
2316                 kvm_rip_write(vcpu, 0);
2317         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2318
2319         vmcs_writel(GUEST_DR7, 0x400);
2320
2321         vmcs_writel(GUEST_GDTR_BASE, 0);
2322         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2323
2324         vmcs_writel(GUEST_IDTR_BASE, 0);
2325         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2326
2327         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2328         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2329         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2330
2331         guest_write_tsc(0);
2332
2333         /* Special registers */
2334         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2335
2336         setup_msrs(vmx);
2337
2338         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2339
2340         if (cpu_has_vmx_tpr_shadow()) {
2341                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2342                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2343                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2344                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2345                 vmcs_write32(TPR_THRESHOLD, 0);
2346         }
2347
2348         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2349                 vmcs_write64(APIC_ACCESS_ADDR,
2350                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2351
2352         if (vmx->vpid != 0)
2353                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2354
2355         vmx->vcpu.arch.cr0 = 0x60000010;
2356         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2357         vmx_set_cr4(&vmx->vcpu, 0);
2358         vmx_set_efer(&vmx->vcpu, 0);
2359         vmx_fpu_activate(&vmx->vcpu);
2360         update_exception_bitmap(&vmx->vcpu);
2361
2362         vpid_sync_vcpu_all(vmx);
2363
2364         ret = 0;
2365
2366         /* HACK: Don't enable emulation on guest boot/reset */
2367         vmx->emulation_required = 0;
2368
2369 out:
2370         up_read(&vcpu->kvm->slots_lock);
2371         return ret;
2372 }
2373
2374 static void enable_irq_window(struct kvm_vcpu *vcpu)
2375 {
2376         u32 cpu_based_vm_exec_control;
2377
2378         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2379         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2380         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2381 }
2382
2383 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2384 {
2385         u32 cpu_based_vm_exec_control;
2386
2387         if (!cpu_has_virtual_nmis()) {
2388                 enable_irq_window(vcpu);
2389                 return;
2390         }
2391
2392         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2393         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2394         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2395 }
2396
2397 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2398 {
2399         struct vcpu_vmx *vmx = to_vmx(vcpu);
2400
2401         KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2402
2403         ++vcpu->stat.irq_injections;
2404         if (vcpu->arch.rmode.active) {
2405                 vmx->rmode.irq.pending = true;
2406                 vmx->rmode.irq.vector = irq;
2407                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2408                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2409                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2410                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2411                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2412                 return;
2413         }
2414         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2415                         irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2416 }
2417
2418 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2419 {
2420         struct vcpu_vmx *vmx = to_vmx(vcpu);
2421
2422         if (!cpu_has_virtual_nmis()) {
2423                 /*
2424                  * Tracking the NMI-blocked state in software is built upon
2425                  * finding the next open IRQ window. This, in turn, depends on
2426                  * well-behaving guests: They have to keep IRQs disabled at
2427                  * least as long as the NMI handler runs. Otherwise we may
2428                  * cause NMI nesting, maybe breaking the guest. But as this is
2429                  * highly unlikely, we can live with the residual risk.
2430                  */
2431                 vmx->soft_vnmi_blocked = 1;
2432                 vmx->vnmi_blocked_time = 0;
2433         }
2434
2435         ++vcpu->stat.nmi_injections;
2436         if (vcpu->arch.rmode.active) {
2437                 vmx->rmode.irq.pending = true;
2438                 vmx->rmode.irq.vector = NMI_VECTOR;
2439                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2440                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2441                              NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2442                              INTR_INFO_VALID_MASK);
2443                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2444                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2445                 return;
2446         }
2447         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2448                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2449 }
2450
2451 static void vmx_update_window_states(struct kvm_vcpu *vcpu)
2452 {
2453         u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2454
2455         vcpu->arch.nmi_window_open =
2456                 !(guest_intr & (GUEST_INTR_STATE_STI |
2457                                 GUEST_INTR_STATE_MOV_SS |
2458                                 GUEST_INTR_STATE_NMI));
2459         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2460                 vcpu->arch.nmi_window_open = 0;
2461
2462         vcpu->arch.interrupt_window_open =
2463                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2464                  !(guest_intr & (GUEST_INTR_STATE_STI |
2465                                  GUEST_INTR_STATE_MOV_SS)));
2466 }
2467
2468 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
2469 {
2470         int word_index = __ffs(vcpu->arch.irq_summary);
2471         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
2472         int irq = word_index * BITS_PER_LONG + bit_index;
2473
2474         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2475         if (!vcpu->arch.irq_pending[word_index])
2476                 clear_bit(word_index, &vcpu->arch.irq_summary);
2477         kvm_queue_interrupt(vcpu, irq);
2478 }
2479
2480 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2481                                        struct kvm_run *kvm_run)
2482 {
2483         vmx_update_window_states(vcpu);
2484
2485         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
2486                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2487                                 GUEST_INTR_STATE_STI |
2488                                 GUEST_INTR_STATE_MOV_SS);
2489
2490         if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
2491                 if (vcpu->arch.interrupt.pending) {
2492                         enable_nmi_window(vcpu);
2493                 } else if (vcpu->arch.nmi_window_open) {
2494                         vcpu->arch.nmi_pending = false;
2495                         vcpu->arch.nmi_injected = true;
2496                 } else {
2497                         enable_nmi_window(vcpu);
2498                         return;
2499                 }
2500         }
2501         if (vcpu->arch.nmi_injected) {
2502                 vmx_inject_nmi(vcpu);
2503                 if (vcpu->arch.nmi_pending)
2504                         enable_nmi_window(vcpu);
2505                 else if (vcpu->arch.irq_summary
2506                          || kvm_run->request_interrupt_window)
2507                         enable_irq_window(vcpu);
2508                 return;
2509         }
2510
2511         if (vcpu->arch.interrupt_window_open) {
2512                 if (vcpu->arch.irq_summary && !vcpu->arch.interrupt.pending)
2513                         kvm_do_inject_irq(vcpu);
2514
2515                 if (vcpu->arch.interrupt.pending)
2516                         vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
2517         }
2518         if (!vcpu->arch.interrupt_window_open &&
2519             (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
2520                 enable_irq_window(vcpu);
2521 }
2522
2523 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2524 {
2525         int ret;
2526         struct kvm_userspace_memory_region tss_mem = {
2527                 .slot = TSS_PRIVATE_MEMSLOT,
2528                 .guest_phys_addr = addr,
2529                 .memory_size = PAGE_SIZE * 3,
2530                 .flags = 0,
2531         };
2532
2533         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2534         if (ret)
2535                 return ret;
2536         kvm->arch.tss_addr = addr;
2537         return 0;
2538 }
2539
2540 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2541                                   int vec, u32 err_code)
2542 {
2543         /*
2544          * Instruction with address size override prefix opcode 0x67
2545          * Cause the #SS fault with 0 error code in VM86 mode.
2546          */
2547         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2548                 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2549                         return 1;
2550         /*
2551          * Forward all other exceptions that are valid in real mode.
2552          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2553          *        the required debugging infrastructure rework.
2554          */
2555         switch (vec) {
2556         case DB_VECTOR:
2557                 if (vcpu->guest_debug &
2558                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2559                         return 0;
2560                 kvm_queue_exception(vcpu, vec);
2561                 return 1;
2562         case BP_VECTOR:
2563                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2564                         return 0;
2565                 /* fall through */
2566         case DE_VECTOR:
2567         case OF_VECTOR:
2568         case BR_VECTOR:
2569         case UD_VECTOR:
2570         case DF_VECTOR:
2571         case SS_VECTOR:
2572         case GP_VECTOR:
2573         case MF_VECTOR:
2574                 kvm_queue_exception(vcpu, vec);
2575                 return 1;
2576         }
2577         return 0;
2578 }
2579
2580 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2581 {
2582         struct vcpu_vmx *vmx = to_vmx(vcpu);
2583         u32 intr_info, ex_no, error_code;
2584         unsigned long cr2, rip, dr6;
2585         u32 vect_info;
2586         enum emulation_result er;
2587
2588         vect_info = vmx->idt_vectoring_info;
2589         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2590
2591         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2592                                                 !is_page_fault(intr_info))
2593                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2594                        "intr info 0x%x\n", __func__, vect_info, intr_info);
2595
2596         if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
2597                 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
2598                 set_bit(irq, vcpu->arch.irq_pending);
2599                 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
2600         }
2601
2602         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2603                 return 1;  /* already handled by vmx_vcpu_run() */
2604
2605         if (is_no_device(intr_info)) {
2606                 vmx_fpu_activate(vcpu);
2607                 return 1;
2608         }
2609
2610         if (is_invalid_opcode(intr_info)) {
2611                 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2612                 if (er != EMULATE_DONE)
2613                         kvm_queue_exception(vcpu, UD_VECTOR);
2614                 return 1;
2615         }
2616
2617         error_code = 0;
2618         rip = kvm_rip_read(vcpu);
2619         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2620                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2621         if (is_page_fault(intr_info)) {
2622                 /* EPT won't cause page fault directly */
2623                 if (vm_need_ept())
2624                         BUG();
2625                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2626                 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2627                             (u32)((u64)cr2 >> 32), handler);
2628                 if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending)
2629                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
2630                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2631         }
2632
2633         if (vcpu->arch.rmode.active &&
2634             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2635                                                                 error_code)) {
2636                 if (vcpu->arch.halt_request) {
2637                         vcpu->arch.halt_request = 0;
2638                         return kvm_emulate_halt(vcpu);
2639                 }
2640                 return 1;
2641         }
2642
2643         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2644         switch (ex_no) {
2645         case DB_VECTOR:
2646                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2647                 if (!(vcpu->guest_debug &
2648                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2649                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2650                         kvm_queue_exception(vcpu, DB_VECTOR);
2651                         return 1;
2652                 }
2653                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2654                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2655                 /* fall through */
2656         case BP_VECTOR:
2657                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2658                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2659                 kvm_run->debug.arch.exception = ex_no;
2660                 break;
2661         default:
2662                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2663                 kvm_run->ex.exception = ex_no;
2664                 kvm_run->ex.error_code = error_code;
2665                 break;
2666         }
2667         return 0;
2668 }
2669
2670 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2671                                      struct kvm_run *kvm_run)
2672 {
2673         ++vcpu->stat.irq_exits;
2674         KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
2675         return 1;
2676 }
2677
2678 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2679 {
2680         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2681         return 0;
2682 }
2683
2684 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2685 {
2686         unsigned long exit_qualification;
2687         int size, down, in, string, rep;
2688         unsigned port;
2689
2690         ++vcpu->stat.io_exits;
2691         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2692         string = (exit_qualification & 16) != 0;
2693
2694         if (string) {
2695                 if (emulate_instruction(vcpu,
2696                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2697                         return 0;
2698                 return 1;
2699         }
2700
2701         size = (exit_qualification & 7) + 1;
2702         in = (exit_qualification & 8) != 0;
2703         down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
2704         rep = (exit_qualification & 32) != 0;
2705         port = exit_qualification >> 16;
2706
2707         skip_emulated_instruction(vcpu);
2708         return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2709 }
2710
2711 static void
2712 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2713 {
2714         /*
2715          * Patch in the VMCALL instruction:
2716          */
2717         hypercall[0] = 0x0f;
2718         hypercall[1] = 0x01;
2719         hypercall[2] = 0xc1;
2720 }
2721
2722 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2723 {
2724         unsigned long exit_qualification;
2725         int cr;
2726         int reg;
2727
2728         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2729         cr = exit_qualification & 15;
2730         reg = (exit_qualification >> 8) & 15;
2731         switch ((exit_qualification >> 4) & 3) {
2732         case 0: /* mov to cr */
2733                 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2734                             (u32)kvm_register_read(vcpu, reg),
2735                             (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2736                             handler);
2737                 switch (cr) {
2738                 case 0:
2739                         kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
2740                         skip_emulated_instruction(vcpu);
2741                         return 1;
2742                 case 3:
2743                         kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
2744                         skip_emulated_instruction(vcpu);
2745                         return 1;
2746                 case 4:
2747                         kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
2748                         skip_emulated_instruction(vcpu);
2749                         return 1;
2750                 case 8:
2751                         kvm_set_cr8(vcpu, kvm_register_read(vcpu, reg));
2752                         skip_emulated_instruction(vcpu);
2753                         if (irqchip_in_kernel(vcpu->kvm))
2754                                 return 1;
2755                         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2756                         return 0;
2757                 };
2758                 break;
2759         case 2: /* clts */
2760                 vmx_fpu_deactivate(vcpu);
2761                 vcpu->arch.cr0 &= ~X86_CR0_TS;
2762                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2763                 vmx_fpu_activate(vcpu);
2764                 KVMTRACE_0D(CLTS, vcpu, handler);
2765                 skip_emulated_instruction(vcpu);
2766                 return 1;
2767         case 1: /*mov from cr*/
2768                 switch (cr) {
2769                 case 3:
2770                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2771                         KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2772                                     (u32)kvm_register_read(vcpu, reg),
2773                                     (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2774                                     handler);
2775                         skip_emulated_instruction(vcpu);
2776                         return 1;
2777                 case 8:
2778                         kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2779                         KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2780                                     (u32)kvm_register_read(vcpu, reg), handler);
2781                         skip_emulated_instruction(vcpu);
2782                         return 1;
2783                 }
2784                 break;
2785         case 3: /* lmsw */
2786                 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2787
2788                 skip_emulated_instruction(vcpu);
2789                 return 1;
2790         default:
2791                 break;
2792         }
2793         kvm_run->exit_reason = 0;
2794         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2795                (int)(exit_qualification >> 4) & 3, cr);
2796         return 0;
2797 }
2798
2799 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2800 {
2801         unsigned long exit_qualification;
2802         unsigned long val;
2803         int dr, reg;
2804
2805         dr = vmcs_readl(GUEST_DR7);
2806         if (dr & DR7_GD) {
2807                 /*
2808                  * As the vm-exit takes precedence over the debug trap, we
2809                  * need to emulate the latter, either for the host or the
2810                  * guest debugging itself.
2811                  */
2812                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2813                         kvm_run->debug.arch.dr6 = vcpu->arch.dr6;
2814                         kvm_run->debug.arch.dr7 = dr;
2815                         kvm_run->debug.arch.pc =
2816                                 vmcs_readl(GUEST_CS_BASE) +
2817                                 vmcs_readl(GUEST_RIP);
2818                         kvm_run->debug.arch.exception = DB_VECTOR;
2819                         kvm_run->exit_reason = KVM_EXIT_DEBUG;
2820                         return 0;
2821                 } else {
2822                         vcpu->arch.dr7 &= ~DR7_GD;
2823                         vcpu->arch.dr6 |= DR6_BD;
2824                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2825                         kvm_queue_exception(vcpu, DB_VECTOR);
2826                         return 1;
2827                 }
2828         }
2829
2830         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2831         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2832         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2833         if (exit_qualification & TYPE_MOV_FROM_DR) {
2834                 switch (dr) {
2835                 case 0 ... 3:
2836                         val = vcpu->arch.db[dr];
2837                         break;
2838                 case 6:
2839                         val = vcpu->arch.dr6;
2840                         break;
2841                 case 7:
2842                         val = vcpu->arch.dr7;
2843                         break;
2844                 default:
2845                         val = 0;
2846                 }
2847                 kvm_register_write(vcpu, reg, val);
2848                 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
2849         } else {
2850                 val = vcpu->arch.regs[reg];
2851                 switch (dr) {
2852                 case 0 ... 3:
2853                         vcpu->arch.db[dr] = val;
2854                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2855                                 vcpu->arch.eff_db[dr] = val;
2856                         break;
2857                 case 4 ... 5:
2858                         if (vcpu->arch.cr4 & X86_CR4_DE)
2859                                 kvm_queue_exception(vcpu, UD_VECTOR);
2860                         break;
2861                 case 6:
2862                         if (val & 0xffffffff00000000ULL) {
2863                                 kvm_queue_exception(vcpu, GP_VECTOR);
2864                                 break;
2865                         }
2866                         vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
2867                         break;
2868                 case 7:
2869                         if (val & 0xffffffff00000000ULL) {
2870                                 kvm_queue_exception(vcpu, GP_VECTOR);
2871                                 break;
2872                         }
2873                         vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
2874                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
2875                                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2876                                 vcpu->arch.switch_db_regs =
2877                                         (val & DR7_BP_EN_MASK);
2878                         }
2879                         break;
2880                 }
2881                 KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)val, handler);
2882         }
2883         skip_emulated_instruction(vcpu);
2884         return 1;
2885 }
2886
2887 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2888 {
2889         kvm_emulate_cpuid(vcpu);
2890         return 1;
2891 }
2892
2893 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2894 {
2895         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2896         u64 data;
2897
2898         if (vmx_get_msr(vcpu, ecx, &data)) {
2899                 kvm_inject_gp(vcpu, 0);
2900                 return 1;
2901         }
2902
2903         KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2904                     handler);
2905
2906         /* FIXME: handling of bits 32:63 of rax, rdx */
2907         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2908         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2909         skip_emulated_instruction(vcpu);
2910         return 1;
2911 }
2912
2913 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2914 {
2915         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2916         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2917                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2918
2919         KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2920                     handler);
2921
2922         if (vmx_set_msr(vcpu, ecx, data) != 0) {
2923                 kvm_inject_gp(vcpu, 0);
2924                 return 1;
2925         }
2926
2927         skip_emulated_instruction(vcpu);
2928         return 1;
2929 }
2930
2931 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2932                                       struct kvm_run *kvm_run)
2933 {
2934         return 1;
2935 }
2936
2937 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2938                                    struct kvm_run *kvm_run)
2939 {
2940         u32 cpu_based_vm_exec_control;
2941
2942         /* clear pending irq */
2943         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2944         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2945         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2946
2947         KVMTRACE_0D(PEND_INTR, vcpu, handler);
2948         ++vcpu->stat.irq_window_exits;
2949
2950         /*
2951          * If the user space waits to inject interrupts, exit as soon as
2952          * possible
2953          */
2954         if (kvm_run->request_interrupt_window &&
2955             !vcpu->arch.irq_summary) {
2956                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2957                 return 0;
2958         }
2959         return 1;
2960 }
2961
2962 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2963 {
2964         skip_emulated_instruction(vcpu);
2965         return kvm_emulate_halt(vcpu);
2966 }
2967
2968 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2969 {
2970         skip_emulated_instruction(vcpu);
2971         kvm_emulate_hypercall(vcpu);
2972         return 1;
2973 }
2974
2975 static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2976 {
2977         u64 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2978
2979         kvm_mmu_invlpg(vcpu, exit_qualification);
2980         skip_emulated_instruction(vcpu);
2981         return 1;
2982 }
2983
2984 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2985 {
2986         skip_emulated_instruction(vcpu);
2987         /* TODO: Add support for VT-d/pass-through device */
2988         return 1;
2989 }
2990
2991 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2992 {
2993         u64 exit_qualification;
2994         enum emulation_result er;
2995         unsigned long offset;
2996
2997         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2998         offset = exit_qualification & 0xffful;
2999
3000         er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3001
3002         if (er !=  EMULATE_DONE) {
3003                 printk(KERN_ERR
3004                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3005                        offset);
3006                 return -ENOTSUPP;
3007         }
3008         return 1;
3009 }
3010
3011 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3012 {
3013         struct vcpu_vmx *vmx = to_vmx(vcpu);
3014         unsigned long exit_qualification;
3015         u16 tss_selector;
3016         int reason;
3017
3018         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3019
3020         reason = (u32)exit_qualification >> 30;
3021         if (reason == TASK_SWITCH_GATE && vmx->vcpu.arch.nmi_injected &&
3022             (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
3023             (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK)
3024             == INTR_TYPE_NMI_INTR) {
3025                 vcpu->arch.nmi_injected = false;
3026                 if (cpu_has_virtual_nmis())
3027                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3028                                       GUEST_INTR_STATE_NMI);
3029         }
3030         tss_selector = exit_qualification;
3031
3032         if (!kvm_task_switch(vcpu, tss_selector, reason))
3033                 return 0;
3034
3035         /* clear all local breakpoint enable flags */
3036         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3037
3038         /*
3039          * TODO: What about debug traps on tss switch?
3040          *       Are we supposed to inject them and update dr6?
3041          */
3042
3043         return 1;
3044 }
3045
3046 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3047 {
3048         u64 exit_qualification;
3049         enum emulation_result er;
3050         gpa_t gpa;
3051         unsigned long hva;
3052         int gla_validity;
3053         int r;
3054
3055         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
3056
3057         if (exit_qualification & (1 << 6)) {
3058                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3059                 return -ENOTSUPP;
3060         }
3061
3062         gla_validity = (exit_qualification >> 7) & 0x3;
3063         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3064                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3065                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3066                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3067                         (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
3068                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3069                         (long unsigned int)exit_qualification);
3070                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3071                 kvm_run->hw.hardware_exit_reason = 0;
3072                 return -ENOTSUPP;
3073         }
3074
3075         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3076         hva = gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT);
3077         if (!kvm_is_error_hva(hva)) {
3078                 r = kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3079                 if (r < 0) {
3080                         printk(KERN_ERR "EPT: Not enough memory!\n");
3081                         return -ENOMEM;
3082                 }
3083                 return 1;
3084         } else {
3085                 /* must be MMIO */
3086                 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3087
3088                 if (er == EMULATE_FAIL) {
3089                         printk(KERN_ERR
3090                          "EPT: Fail to handle EPT violation vmexit!er is %d\n",
3091                          er);
3092                         printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3093                          (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3094                          (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
3095                         printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3096                                 (long unsigned int)exit_qualification);
3097                         return -ENOTSUPP;
3098                 } else if (er == EMULATE_DO_MMIO)
3099                         return 0;
3100         }
3101         return 1;
3102 }
3103
3104 static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3105 {
3106         u32 cpu_based_vm_exec_control;
3107
3108         /* clear pending NMI */
3109         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3110         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3111         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3112         ++vcpu->stat.nmi_window_exits;
3113
3114         return 1;
3115 }
3116
3117 static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3118                                 struct kvm_run *kvm_run)
3119 {
3120         struct vcpu_vmx *vmx = to_vmx(vcpu);
3121         int err;
3122
3123         preempt_enable();
3124         local_irq_enable();
3125
3126         while (!guest_state_valid(vcpu)) {
3127                 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3128
3129                 if (err == EMULATE_DO_MMIO)
3130                         break;
3131
3132                 if (err != EMULATE_DONE) {
3133                         kvm_report_emulation_failure(vcpu, "emulation failure");
3134                         return;
3135                 }
3136
3137                 if (signal_pending(current))
3138                         break;
3139                 if (need_resched())
3140                         schedule();
3141         }
3142
3143         local_irq_disable();
3144         preempt_disable();
3145
3146         /* Guest state should be valid now except if we need to
3147          * emulate an MMIO */
3148         if (guest_state_valid(vcpu))
3149                 vmx->emulation_required = 0;
3150 }
3151
3152 /*
3153  * The exit handlers return 1 if the exit was handled fully and guest execution
3154  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3155  * to be done to userspace and return 0.
3156  */
3157 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3158                                       struct kvm_run *kvm_run) = {
3159         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3160         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3161         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3162         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3163         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3164         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3165         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3166         [EXIT_REASON_CPUID]                   = handle_cpuid,
3167         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3168         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3169         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3170         [EXIT_REASON_HLT]                     = handle_halt,
3171         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3172         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3173         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3174         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3175         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3176         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3177         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3178 };
3179
3180 static const int kvm_vmx_max_exit_handlers =
3181         ARRAY_SIZE(kvm_vmx_exit_handlers);
3182
3183 /*
3184  * The guest has exited.  See if we can fix it or if we need userspace
3185  * assistance.
3186  */
3187 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
3188 {
3189         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
3190         struct vcpu_vmx *vmx = to_vmx(vcpu);
3191         u32 vectoring_info = vmx->idt_vectoring_info;
3192
3193         KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
3194                     (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
3195
3196         /* If we need to emulate an MMIO from handle_invalid_guest_state
3197          * we just return 0 */
3198         if (vmx->emulation_required && emulate_invalid_guest_state)
3199                 return 0;
3200
3201         /* Access CR3 don't cause VMExit in paging mode, so we need
3202          * to sync with guest real CR3. */
3203         if (vm_need_ept() && is_paging(vcpu)) {
3204                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3205                 ept_load_pdptrs(vcpu);
3206         }
3207
3208         if (unlikely(vmx->fail)) {
3209                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3210                 kvm_run->fail_entry.hardware_entry_failure_reason
3211                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3212                 return 0;
3213         }
3214
3215         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3216                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3217                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3218                         exit_reason != EXIT_REASON_TASK_SWITCH))
3219                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3220                        "(0x%x) and exit reason is 0x%x\n",
3221                        __func__, vectoring_info, exit_reason);
3222
3223         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3224                 if (vcpu->arch.interrupt_window_open) {
3225                         vmx->soft_vnmi_blocked = 0;
3226                         vcpu->arch.nmi_window_open = 1;
3227                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3228                            vcpu->arch.nmi_pending) {
3229                         /*
3230                          * This CPU don't support us in finding the end of an
3231                          * NMI-blocked window if the guest runs with IRQs
3232                          * disabled. So we pull the trigger after 1 s of
3233                          * futile waiting, but inform the user about this.
3234                          */
3235                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3236                                "state on VCPU %d after 1 s timeout\n",
3237                                __func__, vcpu->vcpu_id);
3238                         vmx->soft_vnmi_blocked = 0;
3239                         vmx->vcpu.arch.nmi_window_open = 1;
3240                 }
3241         }
3242
3243         if (exit_reason < kvm_vmx_max_exit_handlers
3244             && kvm_vmx_exit_handlers[exit_reason])
3245                 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3246         else {
3247                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3248                 kvm_run->hw.hardware_exit_reason = exit_reason;
3249         }
3250         return 0;
3251 }
3252
3253 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
3254 {
3255         int max_irr, tpr;
3256
3257         if (!vm_need_tpr_shadow(vcpu->kvm))
3258                 return;
3259
3260         if (!kvm_lapic_enabled(vcpu) ||
3261             ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
3262                 vmcs_write32(TPR_THRESHOLD, 0);
3263                 return;
3264         }
3265
3266         tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
3267         vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
3268 }
3269
3270 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3271 {
3272         u32 exit_intr_info;
3273         u32 idt_vectoring_info;
3274         bool unblock_nmi;
3275         u8 vector;
3276         int type;
3277         bool idtv_info_valid;
3278         u32 error;
3279
3280         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3281         if (cpu_has_virtual_nmis()) {
3282                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3283                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3284                 /*
3285                  * SDM 3: 25.7.1.2
3286                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3287                  * a guest IRET fault.
3288                  */
3289                 if (unblock_nmi && vector != DF_VECTOR)
3290                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3291                                       GUEST_INTR_STATE_NMI);
3292         } else if (unlikely(vmx->soft_vnmi_blocked))
3293                 vmx->vnmi_blocked_time +=
3294                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3295
3296         idt_vectoring_info = vmx->idt_vectoring_info;
3297         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3298         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3299         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3300         if (vmx->vcpu.arch.nmi_injected) {
3301                 /*
3302                  * SDM 3: 25.7.1.2
3303                  * Clear bit "block by NMI" before VM entry if a NMI delivery
3304                  * faulted.
3305                  */
3306                 if (idtv_info_valid && type == INTR_TYPE_NMI_INTR)
3307                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3308                                         GUEST_INTR_STATE_NMI);
3309                 else
3310                         vmx->vcpu.arch.nmi_injected = false;
3311         }
3312         kvm_clear_exception_queue(&vmx->vcpu);
3313         if (idtv_info_valid && (type == INTR_TYPE_HARD_EXCEPTION ||
3314                                 type == INTR_TYPE_SOFT_EXCEPTION)) {
3315                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3316                         error = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3317                         kvm_queue_exception_e(&vmx->vcpu, vector, error);
3318                 } else
3319                         kvm_queue_exception(&vmx->vcpu, vector);
3320                 vmx->idt_vectoring_info = 0;
3321         }
3322         kvm_clear_interrupt_queue(&vmx->vcpu);
3323         if (idtv_info_valid && type == INTR_TYPE_EXT_INTR) {
3324                 kvm_queue_interrupt(&vmx->vcpu, vector);
3325                 vmx->idt_vectoring_info = 0;
3326         }
3327 }
3328
3329 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
3330 {
3331         update_tpr_threshold(vcpu);
3332
3333         vmx_update_window_states(vcpu);
3334
3335         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3336                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3337                                 GUEST_INTR_STATE_STI |
3338                                 GUEST_INTR_STATE_MOV_SS);
3339
3340         if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
3341                 if (vcpu->arch.interrupt.pending) {
3342                         enable_nmi_window(vcpu);
3343                 } else if (vcpu->arch.nmi_window_open) {
3344                         vcpu->arch.nmi_pending = false;
3345                         vcpu->arch.nmi_injected = true;
3346                 } else {
3347                         enable_nmi_window(vcpu);
3348                         return;
3349                 }
3350         }
3351         if (vcpu->arch.nmi_injected) {
3352                 vmx_inject_nmi(vcpu);
3353                 if (vcpu->arch.nmi_pending)
3354                         enable_nmi_window(vcpu);
3355                 else if (kvm_cpu_has_interrupt(vcpu))
3356                         enable_irq_window(vcpu);
3357                 return;
3358         }
3359         if (!vcpu->arch.interrupt.pending && kvm_cpu_has_interrupt(vcpu)) {
3360                 if (vcpu->arch.interrupt_window_open)
3361                         kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu));
3362                 else
3363                         enable_irq_window(vcpu);
3364         }
3365         if (vcpu->arch.interrupt.pending) {
3366                 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
3367                 if (kvm_cpu_has_interrupt(vcpu))
3368                         enable_irq_window(vcpu);
3369         }
3370 }
3371
3372 /*
3373  * Failure to inject an interrupt should give us the information
3374  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3375  * when fetching the interrupt redirection bitmap in the real-mode
3376  * tss, this doesn't happen.  So we do it ourselves.
3377  */
3378 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3379 {
3380         vmx->rmode.irq.pending = 0;
3381         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3382                 return;
3383         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3384         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3385                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3386                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3387                 return;
3388         }
3389         vmx->idt_vectoring_info =
3390                 VECTORING_INFO_VALID_MASK
3391                 | INTR_TYPE_EXT_INTR
3392                 | vmx->rmode.irq.vector;
3393 }
3394
3395 #ifdef CONFIG_X86_64
3396 #define R "r"
3397 #define Q "q"
3398 #else
3399 #define R "e"
3400 #define Q "l"
3401 #endif
3402
3403 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3404 {
3405         struct vcpu_vmx *vmx = to_vmx(vcpu);
3406         u32 intr_info;
3407
3408         /* Record the guest's net vcpu time for enforced NMI injections. */
3409         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3410                 vmx->entry_time = ktime_get();
3411
3412         /* Handle invalid guest state instead of entering VMX */
3413         if (vmx->emulation_required && emulate_invalid_guest_state) {
3414                 handle_invalid_guest_state(vcpu, kvm_run);
3415                 return;
3416         }
3417
3418         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3419                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3420         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3421                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3422
3423         /*
3424          * Loading guest fpu may have cleared host cr0.ts
3425          */
3426         vmcs_writel(HOST_CR0, read_cr0());
3427
3428         set_debugreg(vcpu->arch.dr6, 6);
3429
3430         asm(
3431                 /* Store host registers */
3432                 "push %%"R"dx; push %%"R"bp;"
3433                 "push %%"R"cx \n\t"
3434                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3435                 "je 1f \n\t"
3436                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3437                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3438                 "1: \n\t"
3439                 /* Check if vmlaunch of vmresume is needed */
3440                 "cmpl $0, %c[launched](%0) \n\t"
3441                 /* Load guest registers.  Don't clobber flags. */
3442                 "mov %c[cr2](%0), %%"R"ax \n\t"
3443                 "mov %%"R"ax, %%cr2 \n\t"
3444                 "mov %c[rax](%0), %%"R"ax \n\t"
3445                 "mov %c[rbx](%0), %%"R"bx \n\t"
3446                 "mov %c[rdx](%0), %%"R"dx \n\t"
3447                 "mov %c[rsi](%0), %%"R"si \n\t"
3448                 "mov %c[rdi](%0), %%"R"di \n\t"
3449                 "mov %c[rbp](%0), %%"R"bp \n\t"
3450 #ifdef CONFIG_X86_64
3451                 "mov %c[r8](%0),  %%r8  \n\t"
3452                 "mov %c[r9](%0),  %%r9  \n\t"
3453                 "mov %c[r10](%0), %%r10 \n\t"
3454                 "mov %c[r11](%0), %%r11 \n\t"
3455                 "mov %c[r12](%0), %%r12 \n\t"
3456                 "mov %c[r13](%0), %%r13 \n\t"
3457                 "mov %c[r14](%0), %%r14 \n\t"
3458                 "mov %c[r15](%0), %%r15 \n\t"
3459 #endif
3460                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3461
3462                 /* Enter guest mode */
3463                 "jne .Llaunched \n\t"
3464                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3465                 "jmp .Lkvm_vmx_return \n\t"
3466                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3467                 ".Lkvm_vmx_return: "
3468                 /* Save guest registers, load host registers, keep flags */
3469                 "xchg %0,     (%%"R"sp) \n\t"
3470                 "mov %%"R"ax, %c[rax](%0) \n\t"
3471                 "mov %%"R"bx, %c[rbx](%0) \n\t"
3472                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3473                 "mov %%"R"dx, %c[rdx](%0) \n\t"
3474                 "mov %%"R"si, %c[rsi](%0) \n\t"
3475                 "mov %%"R"di, %c[rdi](%0) \n\t"
3476                 "mov %%"R"bp, %c[rbp](%0) \n\t"
3477 #ifdef CONFIG_X86_64
3478                 "mov %%r8,  %c[r8](%0) \n\t"
3479                 "mov %%r9,  %c[r9](%0) \n\t"
3480                 "mov %%r10, %c[r10](%0) \n\t"
3481                 "mov %%r11, %c[r11](%0) \n\t"
3482                 "mov %%r12, %c[r12](%0) \n\t"
3483                 "mov %%r13, %c[r13](%0) \n\t"
3484                 "mov %%r14, %c[r14](%0) \n\t"
3485                 "mov %%r15, %c[r15](%0) \n\t"
3486 #endif
3487                 "mov %%cr2, %%"R"ax   \n\t"
3488                 "mov %%"R"ax, %c[cr2](%0) \n\t"
3489
3490                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
3491                 "setbe %c[fail](%0) \n\t"
3492               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3493                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3494                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3495                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3496                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3497                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3498                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3499                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3500                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3501                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3502                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3503 #ifdef CONFIG_X86_64
3504                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3505                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3506                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3507                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3508                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3509                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3510                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3511                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3512 #endif
3513                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3514               : "cc", "memory"
3515                 , R"bx", R"di", R"si"
3516 #ifdef CONFIG_X86_64
3517                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3518 #endif
3519               );
3520
3521         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3522         vcpu->arch.regs_dirty = 0;
3523
3524         get_debugreg(vcpu->arch.dr6, 6);
3525
3526         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3527         if (vmx->rmode.irq.pending)
3528                 fixup_rmode_irq(vmx);
3529
3530         vmx_update_window_states(vcpu);
3531
3532         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3533         vmx->launched = 1;
3534
3535         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3536
3537         /* We need to handle NMIs before interrupts are enabled */
3538         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3539             (intr_info & INTR_INFO_VALID_MASK)) {
3540                 KVMTRACE_0D(NMI, vcpu, handler);
3541                 asm("int $2");
3542         }
3543
3544         vmx_complete_interrupts(vmx);
3545 }
3546
3547 #undef R
3548 #undef Q
3549
3550 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3551 {
3552         struct vcpu_vmx *vmx = to_vmx(vcpu);
3553
3554         if (vmx->vmcs) {
3555                 vcpu_clear(vmx);
3556                 free_vmcs(vmx->vmcs);
3557                 vmx->vmcs = NULL;
3558         }
3559 }
3560
3561 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3562 {
3563         struct vcpu_vmx *vmx = to_vmx(vcpu);
3564
3565         spin_lock(&vmx_vpid_lock);
3566         if (vmx->vpid != 0)
3567                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3568         spin_unlock(&vmx_vpid_lock);
3569         vmx_free_vmcs(vcpu);
3570         kfree(vmx->host_msrs);
3571         kfree(vmx->guest_msrs);
3572         kvm_vcpu_uninit(vcpu);
3573         kmem_cache_free(kvm_vcpu_cache, vmx);
3574 }
3575
3576 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3577 {
3578         int err;
3579         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3580         int cpu;
3581
3582         if (!vmx)
3583                 return ERR_PTR(-ENOMEM);
3584
3585         allocate_vpid(vmx);
3586
3587         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3588         if (err)
3589                 goto free_vcpu;
3590
3591         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3592         if (!vmx->guest_msrs) {
3593                 err = -ENOMEM;
3594                 goto uninit_vcpu;
3595         }
3596
3597         vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3598         if (!vmx->host_msrs)
3599                 goto free_guest_msrs;
3600
3601         vmx->vmcs = alloc_vmcs();
3602         if (!vmx->vmcs)
3603                 goto free_msrs;
3604
3605         vmcs_clear(vmx->vmcs);
3606
3607         cpu = get_cpu();
3608         vmx_vcpu_load(&vmx->vcpu, cpu);
3609         err = vmx_vcpu_setup(vmx);
3610         vmx_vcpu_put(&vmx->vcpu);
3611         put_cpu();
3612         if (err)
3613                 goto free_vmcs;
3614         if (vm_need_virtualize_apic_accesses(kvm))
3615                 if (alloc_apic_access_page(kvm) != 0)
3616                         goto free_vmcs;
3617
3618         if (vm_need_ept())
3619                 if (alloc_identity_pagetable(kvm) != 0)
3620                         goto free_vmcs;
3621
3622         return &vmx->vcpu;
3623
3624 free_vmcs:
3625         free_vmcs(vmx->vmcs);
3626 free_msrs:
3627         kfree(vmx->host_msrs);
3628 free_guest_msrs:
3629         kfree(vmx->guest_msrs);
3630 uninit_vcpu:
3631         kvm_vcpu_uninit(&vmx->vcpu);
3632 free_vcpu:
3633         kmem_cache_free(kvm_vcpu_cache, vmx);
3634         return ERR_PTR(err);
3635 }
3636
3637 static void __init vmx_check_processor_compat(void *rtn)
3638 {
3639         struct vmcs_config vmcs_conf;
3640
3641         *(int *)rtn = 0;
3642         if (setup_vmcs_config(&vmcs_conf) < 0)
3643                 *(int *)rtn = -EIO;
3644         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3645                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3646                                 smp_processor_id());
3647                 *(int *)rtn = -EIO;
3648         }
3649 }
3650
3651 static int get_ept_level(void)
3652 {
3653         return VMX_EPT_DEFAULT_GAW + 1;
3654 }
3655
3656 static int vmx_get_mt_mask_shift(void)
3657 {
3658         return VMX_EPT_MT_EPTE_SHIFT;
3659 }
3660
3661 static struct kvm_x86_ops vmx_x86_ops = {
3662         .cpu_has_kvm_support = cpu_has_kvm_support,
3663         .disabled_by_bios = vmx_disabled_by_bios,
3664         .hardware_setup = hardware_setup,
3665         .hardware_unsetup = hardware_unsetup,
3666         .check_processor_compatibility = vmx_check_processor_compat,
3667         .hardware_enable = hardware_enable,
3668         .hardware_disable = hardware_disable,
3669         .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
3670
3671         .vcpu_create = vmx_create_vcpu,
3672         .vcpu_free = vmx_free_vcpu,
3673         .vcpu_reset = vmx_vcpu_reset,
3674
3675         .prepare_guest_switch = vmx_save_host_state,
3676         .vcpu_load = vmx_vcpu_load,
3677         .vcpu_put = vmx_vcpu_put,
3678
3679         .set_guest_debug = set_guest_debug,
3680         .get_msr = vmx_get_msr,
3681         .set_msr = vmx_set_msr,
3682         .get_segment_base = vmx_get_segment_base,
3683         .get_segment = vmx_get_segment,
3684         .set_segment = vmx_set_segment,
3685         .get_cpl = vmx_get_cpl,
3686         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3687         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3688         .set_cr0 = vmx_set_cr0,
3689         .set_cr3 = vmx_set_cr3,
3690         .set_cr4 = vmx_set_cr4,
3691         .set_efer = vmx_set_efer,
3692         .get_idt = vmx_get_idt,
3693         .set_idt = vmx_set_idt,
3694         .get_gdt = vmx_get_gdt,
3695         .set_gdt = vmx_set_gdt,
3696         .cache_reg = vmx_cache_reg,
3697         .get_rflags = vmx_get_rflags,
3698         .set_rflags = vmx_set_rflags,
3699
3700         .tlb_flush = vmx_flush_tlb,
3701
3702         .run = vmx_vcpu_run,
3703         .handle_exit = kvm_handle_exit,
3704         .skip_emulated_instruction = skip_emulated_instruction,
3705         .patch_hypercall = vmx_patch_hypercall,
3706         .get_irq = vmx_get_irq,
3707         .set_irq = vmx_inject_irq,
3708         .queue_exception = vmx_queue_exception,
3709         .exception_injected = vmx_exception_injected,
3710         .inject_pending_irq = vmx_intr_assist,
3711         .inject_pending_vectors = do_interrupt_requests,
3712
3713         .set_tss_addr = vmx_set_tss_addr,
3714         .get_tdp_level = get_ept_level,
3715         .get_mt_mask_shift = vmx_get_mt_mask_shift,
3716 };
3717
3718 static int __init vmx_init(void)
3719 {
3720         void *va;
3721         int r;
3722
3723         vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3724         if (!vmx_io_bitmap_a)
3725                 return -ENOMEM;
3726
3727         vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3728         if (!vmx_io_bitmap_b) {
3729                 r = -ENOMEM;
3730                 goto out;
3731         }
3732
3733         vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3734         if (!vmx_msr_bitmap) {
3735                 r = -ENOMEM;
3736                 goto out1;
3737         }
3738
3739         /*
3740          * Allow direct access to the PC debug port (it is often used for I/O
3741          * delays, but the vmexits simply slow things down).
3742          */
3743         va = kmap(vmx_io_bitmap_a);
3744         memset(va, 0xff, PAGE_SIZE);
3745         clear_bit(0x80, va);
3746         kunmap(vmx_io_bitmap_a);
3747
3748         va = kmap(vmx_io_bitmap_b);
3749         memset(va, 0xff, PAGE_SIZE);
3750         kunmap(vmx_io_bitmap_b);
3751
3752         va = kmap(vmx_msr_bitmap);
3753         memset(va, 0xff, PAGE_SIZE);
3754         kunmap(vmx_msr_bitmap);
3755
3756         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3757
3758         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
3759         if (r)
3760                 goto out2;
3761
3762         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE);
3763         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE);
3764         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS);
3765         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP);
3766         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP);
3767
3768         if (vm_need_ept()) {
3769                 bypass_guest_pf = 0;
3770                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3771                         VMX_EPT_WRITABLE_MASK);
3772                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
3773                                 VMX_EPT_EXECUTABLE_MASK,
3774                                 VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
3775                 kvm_enable_tdp();
3776         } else
3777                 kvm_disable_tdp();
3778
3779         if (bypass_guest_pf)
3780                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3781
3782         ept_sync_global();
3783
3784         return 0;
3785
3786 out2:
3787         __free_page(vmx_msr_bitmap);
3788 out1:
3789         __free_page(vmx_io_bitmap_b);
3790 out:
3791         __free_page(vmx_io_bitmap_a);
3792         return r;
3793 }
3794
3795 static void __exit vmx_exit(void)
3796 {
3797         __free_page(vmx_msr_bitmap);
3798         __free_page(vmx_io_bitmap_b);
3799         __free_page(vmx_io_bitmap_a);
3800
3801         kvm_exit();
3802 }
3803
3804 module_init(vmx_init)
3805 module_exit(vmx_exit)