SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/mm.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/ftrace_event.h>
  29 #include "kvm_cache_regs.h"
  30 #include "x86.h"
  31
  32 #include <asm/io.h>
  33 #include <asm/desc.h>
  34 #include <asm/vmx.h>
  35 #include <asm/virtext.h>
  36 #include <asm/mce.h>
  37
  38 #include "trace.h"
  39
  40 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  41
  42 MODULE_AUTHOR("Qumranet");
  43 MODULE_LICENSE("GPL");
  44
  45 static int __read_mostly bypass_guest_pf = 1;
  46 module_param(bypass_guest_pf, bool, S_IRUGO);
  47
  48 static int __read_mostly enable_vpid = 1;
  49 module_param_named(vpid, enable_vpid, bool, 0444);
  50
  51 static int __read_mostly flexpriority_enabled = 1;
  52 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  53
  54 static int __read_mostly enable_ept = 1;
  55 module_param_named(ept, enable_ept, bool, S_IRUGO);
  56
  57 static int __read_mostly enable_unrestricted_guest = 1;
  58 module_param_named(unrestricted_guest,
  59                         enable_unrestricted_guest, bool, S_IRUGO);
  60
  61 static int __read_mostly emulate_invalid_guest_state = 0;
  62 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  63
  64 /*
  65  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
  66  * ple_gap:    upper bound on the amount of time between two successive
  67  *             executions of PAUSE in a loop. Also indicate if ple enabled.
  68  *             According to test, this time is usually small than 41 cycles.
  69  * ple_window: upper bound on the amount of time a guest is allowed to execute
  70  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
  71  *             less than 2^12 cycles
  72  * Time is measured based on a counter that runs at the same rate as the TSC,
  73  * refer SDM volume 3b section 21.6.13 & 22.1.3.
  74  */
  75 #define KVM_VMX_DEFAULT_PLE_GAP    41
  76 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
  77 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
  78 module_param(ple_gap, int, S_IRUGO);
  79
  80 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
  81 module_param(ple_window, int, S_IRUGO);
  82
  83 struct vmcs {
  84         u32 revision_id;
  85         u32 abort;
  86         char data[0];
  87 };
  88
  89 struct shared_msr_entry {
  90         unsigned index;
  91         u64 data;
  92 };
  93
  94 struct vcpu_vmx {
  95         struct kvm_vcpu       vcpu;
  96         struct list_head      local_vcpus_link;
  97         unsigned long         host_rsp;
  98         int                   launched;
  99         u8                    fail;
 100         u32                   idt_vectoring_info;
 101         struct shared_msr_entry *guest_msrs;
 102         int                   nmsrs;
 103         int                   save_nmsrs;
 104 #ifdef CONFIG_X86_64
 105         u64                   msr_host_kernel_gs_base;
 106         u64                   msr_guest_kernel_gs_base;
 107 #endif
 108         struct vmcs          *vmcs;
 109         struct {
 110                 int           loaded;
 111                 u16           fs_sel, gs_sel, ldt_sel;
 112                 int           gs_ldt_reload_needed;
 113                 int           fs_reload_needed;
 114         } host_state;
 115         struct {
 116                 int vm86_active;
 117                 u8 save_iopl;
 118                 struct kvm_save_segment {
 119                         u16 selector;
 120                         unsigned long base;
 121                         u32 limit;
 122                         u32 ar;
 123                 } tr, es, ds, fs, gs;
 124                 struct {
 125                         bool pending;
 126                         u8 vector;
 127                         unsigned rip;
 128                 } irq;
 129         } rmode;
 130         int vpid;
 131         bool emulation_required;
 132
 133         /* Support for vnmi-less CPUs */
 134         int soft_vnmi_blocked;
 135         ktime_t entry_time;
 136         s64 vnmi_blocked_time;
 137         u32 exit_reason;
 138 };
 139
 140 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 141 {
 142         return container_of(vcpu, struct vcpu_vmx, vcpu);
 143 }
 144
 145 static int init_rmode(struct kvm *kvm);
 146 static u64 construct_eptp(unsigned long root_hpa);
 147
 148 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 149 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 150 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 151
 152 static unsigned long *vmx_io_bitmap_a;
 153 static unsigned long *vmx_io_bitmap_b;
 154 static unsigned long *vmx_msr_bitmap_legacy;
 155 static unsigned long *vmx_msr_bitmap_longmode;
 156
 157 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 158 static DEFINE_SPINLOCK(vmx_vpid_lock);
 159
 160 static struct vmcs_config {
 161         int size;
 162         int order;
 163         u32 revision_id;
 164         u32 pin_based_exec_ctrl;
 165         u32 cpu_based_exec_ctrl;
 166         u32 cpu_based_2nd_exec_ctrl;
 167         u32 vmexit_ctrl;
 168         u32 vmentry_ctrl;
 169 } vmcs_config;
 170
 171 static struct vmx_capability {
 172         u32 ept;
 173         u32 vpid;
 174 } vmx_capability;
 175
 176 #define VMX_SEGMENT_FIELD(seg)                                  \
 177         [VCPU_SREG_##seg] = {                                   \
 178                 .selector = GUEST_##seg##_SELECTOR,             \
 179                 .base = GUEST_##seg##_BASE,                     \
 180                 .limit = GUEST_##seg##_LIMIT,                   \
 181                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 182         }
 183
 184 static struct kvm_vmx_segment_field {
 185         unsigned selector;
 186         unsigned base;
 187         unsigned limit;
 188         unsigned ar_bytes;
 189 } kvm_vmx_segment_fields[] = {
 190         VMX_SEGMENT_FIELD(CS),
 191         VMX_SEGMENT_FIELD(DS),
 192         VMX_SEGMENT_FIELD(ES),
 193         VMX_SEGMENT_FIELD(FS),
 194         VMX_SEGMENT_FIELD(GS),
 195         VMX_SEGMENT_FIELD(SS),
 196         VMX_SEGMENT_FIELD(TR),
 197         VMX_SEGMENT_FIELD(LDTR),
 198 };
 199
 200 static u64 host_efer;
 201
 202 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 203
 204 /*
 205  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 206  * away by decrementing the array size.
 207  */
 208 static const u32 vmx_msr_index[] = {
 209 #ifdef CONFIG_X86_64
 210         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 211 #endif
 212         MSR_EFER, MSR_K6_STAR,
 213 };
 214 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 215
 216 static inline int is_page_fault(u32 intr_info)
 217 {
 218         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 219                              INTR_INFO_VALID_MASK)) ==
 220                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 221 }
 222
 223 static inline int is_no_device(u32 intr_info)
 224 {
 225         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 226                              INTR_INFO_VALID_MASK)) ==
 227                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 228 }
 229
 230 static inline int is_invalid_opcode(u32 intr_info)
 231 {
 232         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 233                              INTR_INFO_VALID_MASK)) ==
 234                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 235 }
 236
 237 static inline int is_external_interrupt(u32 intr_info)
 238 {
 239         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 240                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 241 }
 242
 243 static inline int is_machine_check(u32 intr_info)
 244 {
 245         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 246                              INTR_INFO_VALID_MASK)) ==
 247                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 248 }
 249
 250 static inline int cpu_has_vmx_msr_bitmap(void)
 251 {
 252         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 253 }
 254
 255 static inline int cpu_has_vmx_tpr_shadow(void)
 256 {
 257         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 258 }
 259
 260 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 261 {
 262         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 263 }
 264
 265 static inline int cpu_has_secondary_exec_ctrls(void)
 266 {
 267         return vmcs_config.cpu_based_exec_ctrl &
 268                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 269 }
 270
 271 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 272 {
 273         return vmcs_config.cpu_based_2nd_exec_ctrl &
 274                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 275 }
 276
 277 static inline bool cpu_has_vmx_flexpriority(void)
 278 {
 279         return cpu_has_vmx_tpr_shadow() &&
 280                 cpu_has_vmx_virtualize_apic_accesses();
 281 }
 282
 283 static inline bool cpu_has_vmx_ept_execute_only(void)
 284 {
 285         return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
 286 }
 287
 288 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 289 {
 290         return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
 291 }
 292
 293 static inline bool cpu_has_vmx_eptp_writeback(void)
 294 {
 295         return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
 296 }
 297
 298 static inline bool cpu_has_vmx_ept_2m_page(void)
 299 {
 300         return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
 301 }
 302
 303 static inline int cpu_has_vmx_invept_individual_addr(void)
 304 {
 305         return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
 306 }
 307
 308 static inline int cpu_has_vmx_invept_context(void)
 309 {
 310         return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
 311 }
 312
 313 static inline int cpu_has_vmx_invept_global(void)
 314 {
 315         return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
 316 }
 317
 318 static inline int cpu_has_vmx_ept(void)
 319 {
 320         return vmcs_config.cpu_based_2nd_exec_ctrl &
 321                 SECONDARY_EXEC_ENABLE_EPT;
 322 }
 323
 324 static inline int cpu_has_vmx_unrestricted_guest(void)
 325 {
 326         return vmcs_config.cpu_based_2nd_exec_ctrl &
 327                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 328 }
 329
 330 static inline int cpu_has_vmx_ple(void)
 331 {
 332         return vmcs_config.cpu_based_2nd_exec_ctrl &
 333                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 334 }
 335
 336 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 337 {
 338         return flexpriority_enabled &&
 339                 (cpu_has_vmx_virtualize_apic_accesses()) &&
 340                 (irqchip_in_kernel(kvm));
 341 }
 342
 343 static inline int cpu_has_vmx_vpid(void)
 344 {
 345         return vmcs_config.cpu_based_2nd_exec_ctrl &
 346                 SECONDARY_EXEC_ENABLE_VPID;
 347 }
 348
 349 static inline int cpu_has_virtual_nmis(void)
 350 {
 351         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 352 }
 353
 354 static inline bool report_flexpriority(void)
 355 {
 356         return flexpriority_enabled;
 357 }
 358
 359 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 360 {
 361         int i;
 362
 363         for (i = 0; i < vmx->nmsrs; ++i)
 364                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 365                         return i;
 366         return -1;
 367 }
 368
 369 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 370 {
 371     struct {
 372         u64 vpid : 16;
 373         u64 rsvd : 48;
 374         u64 gva;
 375     } operand = { vpid, 0, gva };
 376
 377     asm volatile (__ex(ASM_VMX_INVVPID)
 378                   /* CF==1 or ZF==1 --> rc = -1 */
 379                   "; ja 1f ; ud2 ; 1:"
 380                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 381 }
 382
 383 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 384 {
 385         struct {
 386                 u64 eptp, gpa;
 387         } operand = {eptp, gpa};
 388
 389         asm volatile (__ex(ASM_VMX_INVEPT)
 390                         /* CF==1 or ZF==1 --> rc = -1 */
 391                         "; ja 1f ; ud2 ; 1:\n"
 392                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 393 }
 394
 395 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 396 {
 397         int i;
 398
 399         i = __find_msr_index(vmx, msr);
 400         if (i >= 0)
 401                 return &vmx->guest_msrs[i];
 402         return NULL;
 403 }
 404
 405 static void vmcs_clear(struct vmcs *vmcs)
 406 {
 407         u64 phys_addr = __pa(vmcs);
 408         u8 error;
 409
 410         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 411                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 412                       : "cc", "memory");
 413         if (error)
 414                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 415                        vmcs, phys_addr);
 416 }
 417
 418 static void __vcpu_clear(void *arg)
 419 {
 420         struct vcpu_vmx *vmx = arg;
 421         int cpu = raw_smp_processor_id();
 422
 423         if (vmx->vcpu.cpu == cpu)
 424                 vmcs_clear(vmx->vmcs);
 425         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 426                 per_cpu(current_vmcs, cpu) = NULL;
 427         rdtscll(vmx->vcpu.arch.host_tsc);
 428         list_del(&vmx->local_vcpus_link);
 429         vmx->vcpu.cpu = -1;
 430         vmx->launched = 0;
 431 }
 432
 433 static void vcpu_clear(struct vcpu_vmx *vmx)
 434 {
 435         if (vmx->vcpu.cpu == -1)
 436                 return;
 437         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 438 }
 439
 440 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 441 {
 442         if (vmx->vpid == 0)
 443                 return;
 444
 445         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 446 }
 447
 448 static inline void ept_sync_global(void)
 449 {
 450         if (cpu_has_vmx_invept_global())
 451                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 452 }
 453
 454 static inline void ept_sync_context(u64 eptp)
 455 {
 456         if (enable_ept) {
 457                 if (cpu_has_vmx_invept_context())
 458                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 459                 else
 460                         ept_sync_global();
 461         }
 462 }
 463
 464 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 465 {
 466         if (enable_ept) {
 467                 if (cpu_has_vmx_invept_individual_addr())
 468                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 469                                         eptp, gpa);
 470                 else
 471                         ept_sync_context(eptp);
 472         }
 473 }
 474
 475 static unsigned long vmcs_readl(unsigned long field)
 476 {
 477         unsigned long value;
 478
 479         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 480                       : "=a"(value) : "d"(field) : "cc");
 481         return value;
 482 }
 483
 484 static u16 vmcs_read16(unsigned long field)
 485 {
 486         return vmcs_readl(field);
 487 }
 488
 489 static u32 vmcs_read32(unsigned long field)
 490 {
 491         return vmcs_readl(field);
 492 }
 493
 494 static u64 vmcs_read64(unsigned long field)
 495 {
 496 #ifdef CONFIG_X86_64
 497         return vmcs_readl(field);
 498 #else
 499         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 500 #endif
 501 }
 502
 503 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 504 {
 505         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 506                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 507         dump_stack();
 508 }
 509
 510 static void vmcs_writel(unsigned long field, unsigned long value)
 511 {
 512         u8 error;
 513
 514         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 515                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 516         if (unlikely(error))
 517                 vmwrite_error(field, value);
 518 }
 519
 520 static void vmcs_write16(unsigned long field, u16 value)
 521 {
 522         vmcs_writel(field, value);
 523 }
 524
 525 static void vmcs_write32(unsigned long field, u32 value)
 526 {
 527         vmcs_writel(field, value);
 528 }
 529
 530 static void vmcs_write64(unsigned long field, u64 value)
 531 {
 532         vmcs_writel(field, value);
 533 #ifndef CONFIG_X86_64
 534         asm volatile ("");
 535         vmcs_writel(field+1, value >> 32);
 536 #endif
 537 }
 538
 539 static void vmcs_clear_bits(unsigned long field, u32 mask)
 540 {
 541         vmcs_writel(field, vmcs_readl(field) & ~mask);
 542 }
 543
 544 static void vmcs_set_bits(unsigned long field, u32 mask)
 545 {
 546         vmcs_writel(field, vmcs_readl(field) | mask);
 547 }
 548
 549 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 550 {
 551         u32 eb;
 552
 553         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
 554         if (!vcpu->fpu_active)
 555                 eb |= 1u << NM_VECTOR;
 556         /*
 557          * Unconditionally intercept #DB so we can maintain dr6 without
 558          * reading it every exit.
 559          */
 560         eb |= 1u << DB_VECTOR;
 561         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
 562                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
 563                         eb |= 1u << BP_VECTOR;
 564         }
 565         if (to_vmx(vcpu)->rmode.vm86_active)
 566                 eb = ~0;
 567         if (enable_ept)
 568                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 569         vmcs_write32(EXCEPTION_BITMAP, eb);
 570 }
 571
 572 static void reload_tss(void)
 573 {
 574         /*
 575          * VT restores TR but not its size.  Useless.
 576          */
 577         struct descriptor_table gdt;
 578         struct desc_struct *descs;
 579
 580         kvm_get_gdt(&gdt);
 581         descs = (void *)gdt.base;
 582         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 583         load_TR_desc();
 584 }
 585
 586 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 587 {
 588         u64 guest_efer;
 589         u64 ignore_bits;
 590
 591         guest_efer = vmx->vcpu.arch.shadow_efer;
 592
 593         /*
 594          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 595          * outside long mode
 596          */
 597         ignore_bits = EFER_NX | EFER_SCE;
 598 #ifdef CONFIG_X86_64
 599         ignore_bits |= EFER_LMA | EFER_LME;
 600         /* SCE is meaningful only in long mode on Intel */
 601         if (guest_efer & EFER_LMA)
 602                 ignore_bits &= ~(u64)EFER_SCE;
 603 #endif
 604         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
 605                 return false;
 606
 607         guest_efer &= ~ignore_bits;
 608         guest_efer |= host_efer & ignore_bits;
 609         vmx->guest_msrs[efer_offset].data = guest_efer;
 610         return true;
 611 }
 612
 613 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 614 {
 615         struct vcpu_vmx *vmx = to_vmx(vcpu);
 616         int i;
 617
 618         if (vmx->host_state.loaded)
 619                 return;
 620
 621         vmx->host_state.loaded = 1;
 622         /*
 623          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 624          * allow segment selectors with cpl > 0 or ti == 1.
 625          */
 626         vmx->host_state.ldt_sel = kvm_read_ldt();
 627         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 628         vmx->host_state.fs_sel = kvm_read_fs();
 629         if (!(vmx->host_state.fs_sel & 7)) {
 630                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 631                 vmx->host_state.fs_reload_needed = 0;
 632         } else {
 633                 vmcs_write16(HOST_FS_SELECTOR, 0);
 634                 vmx->host_state.fs_reload_needed = 1;
 635         }
 636         vmx->host_state.gs_sel = kvm_read_gs();
 637         if (!(vmx->host_state.gs_sel & 7))
 638                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 639         else {
 640                 vmcs_write16(HOST_GS_SELECTOR, 0);
 641                 vmx->host_state.gs_ldt_reload_needed = 1;
 642         }
 643
 644 #ifdef CONFIG_X86_64
 645         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 646         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 647 #else
 648         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 649         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 650 #endif
 651
 652 #ifdef CONFIG_X86_64
 653         if (is_long_mode(&vmx->vcpu)) {
 654                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 655                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 656         }
 657 #endif
 658         for (i = 0; i < vmx->save_nmsrs; ++i)
 659                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
 660                                    vmx->guest_msrs[i].data);
 661 }
 662
 663 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 664 {
 665         unsigned long flags;
 666
 667         if (!vmx->host_state.loaded)
 668                 return;
 669
 670         ++vmx->vcpu.stat.host_state_reload;
 671         vmx->host_state.loaded = 0;
 672         if (vmx->host_state.fs_reload_needed)
 673                 kvm_load_fs(vmx->host_state.fs_sel);
 674         if (vmx->host_state.gs_ldt_reload_needed) {
 675                 kvm_load_ldt(vmx->host_state.ldt_sel);
 676                 /*
 677                  * If we have to reload gs, we must take care to
 678                  * preserve our gs base.
 679                  */
 680                 local_irq_save(flags);
 681                 kvm_load_gs(vmx->host_state.gs_sel);
 682 #ifdef CONFIG_X86_64
 683                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 684 #endif
 685                 local_irq_restore(flags);
 686         }
 687         reload_tss();
 688 #ifdef CONFIG_X86_64
 689         if (is_long_mode(&vmx->vcpu)) {
 690                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 691                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 692         }
 693 #endif
 694 }
 695
 696 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 697 {
 698         preempt_disable();
 699         __vmx_load_host_state(vmx);
 700         preempt_enable();
 701 }
 702
 703 /*
 704  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 705  * vcpu mutex is already taken.
 706  */
 707 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 708 {
 709         struct vcpu_vmx *vmx = to_vmx(vcpu);
 710         u64 phys_addr = __pa(vmx->vmcs);
 711         u64 tsc_this, delta, new_offset;
 712
 713         if (vcpu->cpu != cpu) {
 714                 vcpu_clear(vmx);
 715                 kvm_migrate_timers(vcpu);
 716                 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
 717                 local_irq_disable();
 718                 list_add(&vmx->local_vcpus_link,
 719                          &per_cpu(vcpus_on_cpu, cpu));
 720                 local_irq_enable();
 721         }
 722
 723         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 724                 u8 error;
 725
 726                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 727                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 728                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 729                               : "cc");
 730                 if (error)
 731                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 732                                vmx->vmcs, phys_addr);
 733         }
 734
 735         if (vcpu->cpu != cpu) {
 736                 struct descriptor_table dt;
 737                 unsigned long sysenter_esp;
 738
 739                 vcpu->cpu = cpu;
 740                 /*
 741                  * Linux uses per-cpu TSS and GDT, so set these when switching
 742                  * processors.
 743                  */
 744                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 745                 kvm_get_gdt(&dt);
 746                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 747
 748                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 749                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 750
 751                 /*
 752                  * Make sure the time stamp counter is monotonous.
 753                  */
 754                 rdtscll(tsc_this);
 755                 if (tsc_this < vcpu->arch.host_tsc) {
 756                         delta = vcpu->arch.host_tsc - tsc_this;
 757                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 758                         vmcs_write64(TSC_OFFSET, new_offset);
 759                 }
 760         }
 761 }
 762
 763 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 764 {
 765         __vmx_load_host_state(to_vmx(vcpu));
 766 }
 767
 768 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 769 {
 770         if (vcpu->fpu_active)
 771                 return;
 772         vcpu->fpu_active = 1;
 773         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 774         if (vcpu->arch.cr0 & X86_CR0_TS)
 775                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 776         update_exception_bitmap(vcpu);
 777 }
 778
 779 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 780 {
 781         if (!vcpu->fpu_active)
 782                 return;
 783         vcpu->fpu_active = 0;
 784         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 785         update_exception_bitmap(vcpu);
 786 }
 787
 788 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 789 {
 790         unsigned long rflags;
 791
 792         rflags = vmcs_readl(GUEST_RFLAGS);
 793         if (to_vmx(vcpu)->rmode.vm86_active)
 794                 rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
 795         return rflags;
 796 }
 797
 798 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 799 {
 800         if (to_vmx(vcpu)->rmode.vm86_active)
 801                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 802         vmcs_writel(GUEST_RFLAGS, rflags);
 803 }
 804
 805 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 806 {
 807         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 808         int ret = 0;
 809
 810         if (interruptibility & GUEST_INTR_STATE_STI)
 811                 ret |= X86_SHADOW_INT_STI;
 812         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
 813                 ret |= X86_SHADOW_INT_MOV_SS;
 814
 815         return ret & mask;
 816 }
 817
 818 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 819 {
 820         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 821         u32 interruptibility = interruptibility_old;
 822
 823         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
 824
 825         if (mask & X86_SHADOW_INT_MOV_SS)
 826                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
 827         if (mask & X86_SHADOW_INT_STI)
 828                 interruptibility |= GUEST_INTR_STATE_STI;
 829
 830         if ((interruptibility != interruptibility_old))
 831                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
 832 }
 833
 834 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 835 {
 836         unsigned long rip;
 837
 838         rip = kvm_rip_read(vcpu);
 839         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 840         kvm_rip_write(vcpu, rip);
 841
 842         /* skipping an emulated instruction also counts */
 843         vmx_set_interrupt_shadow(vcpu, 0);
 844 }
 845
 846 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 847                                 bool has_error_code, u32 error_code)
 848 {
 849         struct vcpu_vmx *vmx = to_vmx(vcpu);
 850         u32 intr_info = nr | INTR_INFO_VALID_MASK;
 851
 852         if (has_error_code) {
 853                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 854                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
 855         }
 856
 857         if (vmx->rmode.vm86_active) {
 858                 vmx->rmode.irq.pending = true;
 859                 vmx->rmode.irq.vector = nr;
 860                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
 861                 if (kvm_exception_is_soft(nr))
 862                         vmx->rmode.irq.rip +=
 863                                 vmx->vcpu.arch.event_exit_inst_len;
 864                 intr_info |= INTR_TYPE_SOFT_INTR;
 865                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 866                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
 867                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
 868                 return;
 869         }
 870
 871         if (kvm_exception_is_soft(nr)) {
 872                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
 873                              vmx->vcpu.arch.event_exit_inst_len);
 874                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
 875         } else
 876                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
 877
 878         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 879 }
 880
 881 /*
 882  * Swap MSR entry in host/guest MSR entry array.
 883  */
 884 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 885 {
 886         struct shared_msr_entry tmp;
 887
 888         tmp = vmx->guest_msrs[to];
 889         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 890         vmx->guest_msrs[from] = tmp;
 891 }
 892
 893 /*
 894  * Set up the vmcs to automatically save and restore system
 895  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 896  * mode, as fiddling with msrs is very expensive.
 897  */
 898 static void setup_msrs(struct vcpu_vmx *vmx)
 899 {
 900         int save_nmsrs, index;
 901         unsigned long *msr_bitmap;
 902
 903         vmx_load_host_state(vmx);
 904         save_nmsrs = 0;
 905 #ifdef CONFIG_X86_64
 906         if (is_long_mode(&vmx->vcpu)) {
 907                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 908                 if (index >= 0)
 909                         move_msr_up(vmx, index, save_nmsrs++);
 910                 index = __find_msr_index(vmx, MSR_LSTAR);
 911                 if (index >= 0)
 912                         move_msr_up(vmx, index, save_nmsrs++);
 913                 index = __find_msr_index(vmx, MSR_CSTAR);
 914                 if (index >= 0)
 915                         move_msr_up(vmx, index, save_nmsrs++);
 916                 /*
 917                  * MSR_K6_STAR is only needed on long mode guests, and only
 918                  * if efer.sce is enabled.
 919                  */
 920                 index = __find_msr_index(vmx, MSR_K6_STAR);
 921                 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
 922                         move_msr_up(vmx, index, save_nmsrs++);
 923         }
 924 #endif
 925         index = __find_msr_index(vmx, MSR_EFER);
 926         if (index >= 0 && update_transition_efer(vmx, index))
 927                 move_msr_up(vmx, index, save_nmsrs++);
 928
 929         vmx->save_nmsrs = save_nmsrs;
 930
 931         if (cpu_has_vmx_msr_bitmap()) {
 932                 if (is_long_mode(&vmx->vcpu))
 933                         msr_bitmap = vmx_msr_bitmap_longmode;
 934                 else
 935                         msr_bitmap = vmx_msr_bitmap_legacy;
 936
 937                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
 938         }
 939 }
 940
 941 /*
 942  * reads and returns guest's timestamp counter "register"
 943  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 944  */
 945 static u64 guest_read_tsc(void)
 946 {
 947         u64 host_tsc, tsc_offset;
 948
 949         rdtscll(host_tsc);
 950         tsc_offset = vmcs_read64(TSC_OFFSET);
 951         return host_tsc + tsc_offset;
 952 }
 953
 954 /*
 955  * writes 'guest_tsc' into guest's timestamp counter "register"
 956  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 957  */
 958 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
 959 {
 960         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 961 }
 962
 963 /*
 964  * Reads an msr value (of 'msr_index') into 'pdata'.
 965  * Returns 0 on success, non-0 otherwise.
 966  * Assumes vcpu_load() was already called.
 967  */
 968 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
 969 {
 970         u64 data;
 971         struct shared_msr_entry *msr;
 972
 973         if (!pdata) {
 974                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
 975                 return -EINVAL;
 976         }
 977
 978         switch (msr_index) {
 979 #ifdef CONFIG_X86_64
 980         case MSR_FS_BASE:
 981                 data = vmcs_readl(GUEST_FS_BASE);
 982                 break;
 983         case MSR_GS_BASE:
 984                 data = vmcs_readl(GUEST_GS_BASE);
 985                 break;
 986         case MSR_KERNEL_GS_BASE:
 987                 vmx_load_host_state(to_vmx(vcpu));
 988                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
 989                 break;
 990 #endif
 991         case MSR_EFER:
 992                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 993         case MSR_IA32_TSC:
 994                 data = guest_read_tsc();
 995                 break;
 996         case MSR_IA32_SYSENTER_CS:
 997                 data = vmcs_read32(GUEST_SYSENTER_CS);
 998                 break;
 999         case MSR_IA32_SYSENTER_EIP:
1000                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1001                 break;
1002         case MSR_IA32_SYSENTER_ESP:
1003                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1004                 break;
1005         default:
1006                 vmx_load_host_state(to_vmx(vcpu));
1007                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1008                 if (msr) {
1009                         vmx_load_host_state(to_vmx(vcpu));
1010                         data = msr->data;
1011                         break;
1012                 }
1013                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1014         }
1015
1016         *pdata = data;
1017         return 0;
1018 }
1019
1020 /*
1021  * Writes msr value into into the appropriate "register".
1022  * Returns 0 on success, non-0 otherwise.
1023  * Assumes vcpu_load() was already called.
1024  */
1025 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1026 {
1027         struct vcpu_vmx *vmx = to_vmx(vcpu);
1028         struct shared_msr_entry *msr;
1029         u64 host_tsc;
1030         int ret = 0;
1031
1032         switch (msr_index) {
1033         case MSR_EFER:
1034                 vmx_load_host_state(vmx);
1035                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1036                 break;
1037 #ifdef CONFIG_X86_64
1038         case MSR_FS_BASE:
1039                 vmcs_writel(GUEST_FS_BASE, data);
1040                 break;
1041         case MSR_GS_BASE:
1042                 vmcs_writel(GUEST_GS_BASE, data);
1043                 break;
1044         case MSR_KERNEL_GS_BASE:
1045                 vmx_load_host_state(vmx);
1046                 vmx->msr_guest_kernel_gs_base = data;
1047                 break;
1048 #endif
1049         case MSR_IA32_SYSENTER_CS:
1050                 vmcs_write32(GUEST_SYSENTER_CS, data);
1051                 break;
1052         case MSR_IA32_SYSENTER_EIP:
1053                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1054                 break;
1055         case MSR_IA32_SYSENTER_ESP:
1056                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1057                 break;
1058         case MSR_IA32_TSC:
1059                 rdtscll(host_tsc);
1060                 guest_write_tsc(data, host_tsc);
1061                 break;
1062         case MSR_IA32_CR_PAT:
1063                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1064                         vmcs_write64(GUEST_IA32_PAT, data);
1065                         vcpu->arch.pat = data;
1066                         break;
1067                 }
1068                 /* Otherwise falls through to kvm_set_msr_common */
1069         default:
1070                 msr = find_msr_entry(vmx, msr_index);
1071                 if (msr) {
1072                         vmx_load_host_state(vmx);
1073                         msr->data = data;
1074                         break;
1075                 }
1076                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1077         }
1078
1079         return ret;
1080 }
1081
1082 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1083 {
1084         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1085         switch (reg) {
1086         case VCPU_REGS_RSP:
1087                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1088                 break;
1089         case VCPU_REGS_RIP:
1090                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1091                 break;
1092         case VCPU_EXREG_PDPTR:
1093                 if (enable_ept)
1094                         ept_save_pdptrs(vcpu);
1095                 break;
1096         default:
1097                 break;
1098         }
1099 }
1100
1101 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1102 {
1103         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1104                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1105         else
1106                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1107
1108         update_exception_bitmap(vcpu);
1109 }
1110
1111 static __init int cpu_has_kvm_support(void)
1112 {
1113         return cpu_has_vmx();
1114 }
1115
1116 static __init int vmx_disabled_by_bios(void)
1117 {
1118         u64 msr;
1119
1120         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1121         return (msr & (FEATURE_CONTROL_LOCKED |
1122                        FEATURE_CONTROL_VMXON_ENABLED))
1123             == FEATURE_CONTROL_LOCKED;
1124         /* locked but not enabled */
1125 }
1126
1127 static int hardware_enable(void *garbage)
1128 {
1129         int cpu = raw_smp_processor_id();
1130         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1131         u64 old;
1132
1133         if (read_cr4() & X86_CR4_VMXE)
1134                 return -EBUSY;
1135
1136         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1137         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1138         if ((old & (FEATURE_CONTROL_LOCKED |
1139                     FEATURE_CONTROL_VMXON_ENABLED))
1140             != (FEATURE_CONTROL_LOCKED |
1141                 FEATURE_CONTROL_VMXON_ENABLED))
1142                 /* enable and lock */
1143                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1144                        FEATURE_CONTROL_LOCKED |
1145                        FEATURE_CONTROL_VMXON_ENABLED);
1146         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1147         asm volatile (ASM_VMX_VMXON_RAX
1148                       : : "a"(&phys_addr), "m"(phys_addr)
1149                       : "memory", "cc");
1150
1151         ept_sync_global();
1152
1153         return 0;
1154 }
1155
1156 static void vmclear_local_vcpus(void)
1157 {
1158         int cpu = raw_smp_processor_id();
1159         struct vcpu_vmx *vmx, *n;
1160
1161         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1162                                  local_vcpus_link)
1163                 __vcpu_clear(vmx);
1164 }
1165
1166
1167 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1168  * tricks.
1169  */
1170 static void kvm_cpu_vmxoff(void)
1171 {
1172         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1173         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1174 }
1175
1176 static void hardware_disable(void *garbage)
1177 {
1178         vmclear_local_vcpus();
1179         kvm_cpu_vmxoff();
1180 }
1181
1182 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1183                                       u32 msr, u32 *result)
1184 {
1185         u32 vmx_msr_low, vmx_msr_high;
1186         u32 ctl = ctl_min | ctl_opt;
1187
1188         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1189
1190         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1191         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1192
1193         /* Ensure minimum (required) set of control bits are supported. */
1194         if (ctl_min & ~ctl)
1195                 return -EIO;
1196
1197         *result = ctl;
1198         return 0;
1199 }
1200
1201 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1202 {
1203         u32 vmx_msr_low, vmx_msr_high;
1204         u32 min, opt, min2, opt2;
1205         u32 _pin_based_exec_control = 0;
1206         u32 _cpu_based_exec_control = 0;
1207         u32 _cpu_based_2nd_exec_control = 0;
1208         u32 _vmexit_control = 0;
1209         u32 _vmentry_control = 0;
1210
1211         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1212         opt = PIN_BASED_VIRTUAL_NMIS;
1213         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1214                                 &_pin_based_exec_control) < 0)
1215                 return -EIO;
1216
1217         min = CPU_BASED_HLT_EXITING |
1218 #ifdef CONFIG_X86_64
1219               CPU_BASED_CR8_LOAD_EXITING |
1220               CPU_BASED_CR8_STORE_EXITING |
1221 #endif
1222               CPU_BASED_CR3_LOAD_EXITING |
1223               CPU_BASED_CR3_STORE_EXITING |
1224               CPU_BASED_USE_IO_BITMAPS |
1225               CPU_BASED_MOV_DR_EXITING |
1226               CPU_BASED_USE_TSC_OFFSETING |
1227               CPU_BASED_INVLPG_EXITING;
1228         opt = CPU_BASED_TPR_SHADOW |
1229               CPU_BASED_USE_MSR_BITMAPS |
1230               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1231         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1232                                 &_cpu_based_exec_control) < 0)
1233                 return -EIO;
1234 #ifdef CONFIG_X86_64
1235         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1236                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1237                                            ~CPU_BASED_CR8_STORE_EXITING;
1238 #endif
1239         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1240                 min2 = 0;
1241                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1242                         SECONDARY_EXEC_WBINVD_EXITING |
1243                         SECONDARY_EXEC_ENABLE_VPID |
1244                         SECONDARY_EXEC_ENABLE_EPT |
1245                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
1246                         SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1247                 if (adjust_vmx_controls(min2, opt2,
1248                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1249                                         &_cpu_based_2nd_exec_control) < 0)
1250                         return -EIO;
1251         }
1252 #ifndef CONFIG_X86_64
1253         if (!(_cpu_based_2nd_exec_control &
1254                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1255                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1256 #endif
1257         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1258                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1259                    enabled */
1260                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1261                                              CPU_BASED_CR3_STORE_EXITING |
1262                                              CPU_BASED_INVLPG_EXITING);
1263                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1264                       vmx_capability.ept, vmx_capability.vpid);
1265         }
1266
1267         min = 0;
1268 #ifdef CONFIG_X86_64
1269         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1270 #endif
1271         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1272         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1273                                 &_vmexit_control) < 0)
1274                 return -EIO;
1275
1276         min = 0;
1277         opt = VM_ENTRY_LOAD_IA32_PAT;
1278         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1279                                 &_vmentry_control) < 0)
1280                 return -EIO;
1281
1282         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1283
1284         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1285         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1286                 return -EIO;
1287
1288 #ifdef CONFIG_X86_64
1289         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1290         if (vmx_msr_high & (1u<<16))
1291                 return -EIO;
1292 #endif
1293
1294         /* Require Write-Back (WB) memory type for VMCS accesses. */
1295         if (((vmx_msr_high >> 18) & 15) != 6)
1296                 return -EIO;
1297
1298         vmcs_conf->size = vmx_msr_high & 0x1fff;
1299         vmcs_conf->order = get_order(vmcs_config.size);
1300         vmcs_conf->revision_id = vmx_msr_low;
1301
1302         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1303         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1304         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1305         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1306         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1307
1308         return 0;
1309 }
1310
1311 static struct vmcs *alloc_vmcs_cpu(int cpu)
1312 {
1313         int node = cpu_to_node(cpu);
1314         struct page *pages;
1315         struct vmcs *vmcs;
1316
1317         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1318         if (!pages)
1319                 return NULL;
1320         vmcs = page_address(pages);
1321         memset(vmcs, 0, vmcs_config.size);
1322         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1323         return vmcs;
1324 }
1325
1326 static struct vmcs *alloc_vmcs(void)
1327 {
1328         return alloc_vmcs_cpu(raw_smp_processor_id());
1329 }
1330
1331 static void free_vmcs(struct vmcs *vmcs)
1332 {
1333         free_pages((unsigned long)vmcs, vmcs_config.order);
1334 }
1335
1336 static void free_kvm_area(void)
1337 {
1338         int cpu;
1339
1340         for_each_possible_cpu(cpu) {
1341                 free_vmcs(per_cpu(vmxarea, cpu));
1342                 per_cpu(vmxarea, cpu) = NULL;
1343         }
1344 }
1345
1346 static __init int alloc_kvm_area(void)
1347 {
1348         int cpu;
1349
1350         for_each_possible_cpu(cpu) {
1351                 struct vmcs *vmcs;
1352
1353                 vmcs = alloc_vmcs_cpu(cpu);
1354                 if (!vmcs) {
1355                         free_kvm_area();
1356                         return -ENOMEM;
1357                 }
1358
1359                 per_cpu(vmxarea, cpu) = vmcs;
1360         }
1361         return 0;
1362 }
1363
1364 static __init int hardware_setup(void)
1365 {
1366         if (setup_vmcs_config(&vmcs_config) < 0)
1367                 return -EIO;
1368
1369         if (boot_cpu_has(X86_FEATURE_NX))
1370                 kvm_enable_efer_bits(EFER_NX);
1371
1372         if (!cpu_has_vmx_vpid())
1373                 enable_vpid = 0;
1374
1375         if (!cpu_has_vmx_ept()) {
1376                 enable_ept = 0;
1377                 enable_unrestricted_guest = 0;
1378         }
1379
1380         if (!cpu_has_vmx_unrestricted_guest())
1381                 enable_unrestricted_guest = 0;
1382
1383         if (!cpu_has_vmx_flexpriority())
1384                 flexpriority_enabled = 0;
1385
1386         if (!cpu_has_vmx_tpr_shadow())
1387                 kvm_x86_ops->update_cr8_intercept = NULL;
1388
1389         if (enable_ept && !cpu_has_vmx_ept_2m_page())
1390                 kvm_disable_largepages();
1391
1392         if (!cpu_has_vmx_ple())
1393                 ple_gap = 0;
1394
1395         return alloc_kvm_area();
1396 }
1397
1398 static __exit void hardware_unsetup(void)
1399 {
1400         free_kvm_area();
1401 }
1402
1403 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1404 {
1405         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1406
1407         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1408                 vmcs_write16(sf->selector, save->selector);
1409                 vmcs_writel(sf->base, save->base);
1410                 vmcs_write32(sf->limit, save->limit);
1411                 vmcs_write32(sf->ar_bytes, save->ar);
1412         } else {
1413                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1414                         << AR_DPL_SHIFT;
1415                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1416         }
1417 }
1418
1419 static void enter_pmode(struct kvm_vcpu *vcpu)
1420 {
1421         unsigned long flags;
1422         struct vcpu_vmx *vmx = to_vmx(vcpu);
1423
1424         vmx->emulation_required = 1;
1425         vmx->rmode.vm86_active = 0;
1426
1427         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1428         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1429         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1430
1431         flags = vmcs_readl(GUEST_RFLAGS);
1432         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1433         flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
1434         vmcs_writel(GUEST_RFLAGS, flags);
1435
1436         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1437                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1438
1439         update_exception_bitmap(vcpu);
1440
1441         if (emulate_invalid_guest_state)
1442                 return;
1443
1444         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1445         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1446         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1447         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1448
1449         vmcs_write16(GUEST_SS_SELECTOR, 0);
1450         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1451
1452         vmcs_write16(GUEST_CS_SELECTOR,
1453                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1454         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1455 }
1456
1457 static gva_t rmode_tss_base(struct kvm *kvm)
1458 {
1459         if (!kvm->arch.tss_addr) {
1460                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1461                                  kvm->memslots[0].npages - 3;
1462                 return base_gfn << PAGE_SHIFT;
1463         }
1464         return kvm->arch.tss_addr;
1465 }
1466
1467 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1468 {
1469         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1470
1471         save->selector = vmcs_read16(sf->selector);
1472         save->base = vmcs_readl(sf->base);
1473         save->limit = vmcs_read32(sf->limit);
1474         save->ar = vmcs_read32(sf->ar_bytes);
1475         vmcs_write16(sf->selector, save->base >> 4);
1476         vmcs_write32(sf->base, save->base & 0xfffff);
1477         vmcs_write32(sf->limit, 0xffff);
1478         vmcs_write32(sf->ar_bytes, 0xf3);
1479 }
1480
1481 static void enter_rmode(struct kvm_vcpu *vcpu)
1482 {
1483         unsigned long flags;
1484         struct vcpu_vmx *vmx = to_vmx(vcpu);
1485
1486         if (enable_unrestricted_guest)
1487                 return;
1488
1489         vmx->emulation_required = 1;
1490         vmx->rmode.vm86_active = 1;
1491
1492         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1493         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1494
1495         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1496         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1497
1498         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1499         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1500
1501         flags = vmcs_readl(GUEST_RFLAGS);
1502         vmx->rmode.save_iopl
1503                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1504
1505         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1506
1507         vmcs_writel(GUEST_RFLAGS, flags);
1508         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1509         update_exception_bitmap(vcpu);
1510
1511         if (emulate_invalid_guest_state)
1512                 goto continue_rmode;
1513
1514         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1515         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1516         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1517
1518         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1519         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1520         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1521                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1522         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1523
1524         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1525         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1526         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1527         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1528
1529 continue_rmode:
1530         kvm_mmu_reset_context(vcpu);
1531         init_rmode(vcpu->kvm);
1532 }
1533
1534 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1535 {
1536         struct vcpu_vmx *vmx = to_vmx(vcpu);
1537         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1538
1539         if (!msr)
1540                 return;
1541
1542         /*
1543          * Force kernel_gs_base reloading before EFER changes, as control
1544          * of this msr depends on is_long_mode().
1545          */
1546         vmx_load_host_state(to_vmx(vcpu));
1547         vcpu->arch.shadow_efer = efer;
1548         if (!msr)
1549                 return;
1550         if (efer & EFER_LMA) {
1551                 vmcs_write32(VM_ENTRY_CONTROLS,
1552                              vmcs_read32(VM_ENTRY_CONTROLS) |
1553                              VM_ENTRY_IA32E_MODE);
1554                 msr->data = efer;
1555         } else {
1556                 vmcs_write32(VM_ENTRY_CONTROLS,
1557                              vmcs_read32(VM_ENTRY_CONTROLS) &
1558                              ~VM_ENTRY_IA32E_MODE);
1559
1560                 msr->data = efer & ~EFER_LME;
1561         }
1562         setup_msrs(vmx);
1563 }
1564
1565 #ifdef CONFIG_X86_64
1566
1567 static void enter_lmode(struct kvm_vcpu *vcpu)
1568 {
1569         u32 guest_tr_ar;
1570
1571         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1572         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1573                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1574                        __func__);
1575                 vmcs_write32(GUEST_TR_AR_BYTES,
1576                              (guest_tr_ar & ~AR_TYPE_MASK)
1577                              | AR_TYPE_BUSY_64_TSS);
1578         }
1579         vcpu->arch.shadow_efer |= EFER_LMA;
1580         vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
1581 }
1582
1583 static void exit_lmode(struct kvm_vcpu *vcpu)
1584 {
1585         vcpu->arch.shadow_efer &= ~EFER_LMA;
1586
1587         vmcs_write32(VM_ENTRY_CONTROLS,
1588                      vmcs_read32(VM_ENTRY_CONTROLS)
1589                      & ~VM_ENTRY_IA32E_MODE);
1590 }
1591
1592 #endif
1593
1594 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1595 {
1596         vpid_sync_vcpu_all(to_vmx(vcpu));
1597         if (enable_ept)
1598                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1599 }
1600
1601 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1602 {
1603         vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1604         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1605 }
1606
1607 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1608 {
1609         if (!test_bit(VCPU_EXREG_PDPTR,
1610                       (unsigned long *)&vcpu->arch.regs_dirty))
1611                 return;
1612
1613         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1614                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1615                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1616                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1617                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1618         }
1619 }
1620
1621 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1622 {
1623         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1624                 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1625                 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1626                 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1627                 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1628         }
1629
1630         __set_bit(VCPU_EXREG_PDPTR,
1631                   (unsigned long *)&vcpu->arch.regs_avail);
1632         __set_bit(VCPU_EXREG_PDPTR,
1633                   (unsigned long *)&vcpu->arch.regs_dirty);
1634 }
1635
1636 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1637
1638 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1639                                         unsigned long cr0,
1640                                         struct kvm_vcpu *vcpu)
1641 {
1642         if (!(cr0 & X86_CR0_PG)) {
1643                 /* From paging/starting to nonpaging */
1644                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1645                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1646                              (CPU_BASED_CR3_LOAD_EXITING |
1647                               CPU_BASED_CR3_STORE_EXITING));
1648                 vcpu->arch.cr0 = cr0;
1649                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1650         } else if (!is_paging(vcpu)) {
1651                 /* From nonpaging to paging */
1652                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1653                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1654                              ~(CPU_BASED_CR3_LOAD_EXITING |
1655                                CPU_BASED_CR3_STORE_EXITING));
1656                 vcpu->arch.cr0 = cr0;
1657                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1658         }
1659
1660         if (!(cr0 & X86_CR0_WP))
1661                 *hw_cr0 &= ~X86_CR0_WP;
1662 }
1663
1664 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1665                                         struct kvm_vcpu *vcpu)
1666 {
1667         if (!is_paging(vcpu)) {
1668                 *hw_cr4 &= ~X86_CR4_PAE;
1669                 *hw_cr4 |= X86_CR4_PSE;
1670         } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1671                 *hw_cr4 &= ~X86_CR4_PAE;
1672 }
1673
1674 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1675 {
1676         struct vcpu_vmx *vmx = to_vmx(vcpu);
1677         unsigned long hw_cr0;
1678
1679         if (enable_unrestricted_guest)
1680                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1681                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1682         else
1683                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1684
1685         vmx_fpu_deactivate(vcpu);
1686
1687         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1688                 enter_pmode(vcpu);
1689
1690         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1691                 enter_rmode(vcpu);
1692
1693 #ifdef CONFIG_X86_64
1694         if (vcpu->arch.shadow_efer & EFER_LME) {
1695                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1696                         enter_lmode(vcpu);
1697                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1698                         exit_lmode(vcpu);
1699         }
1700 #endif
1701
1702         if (enable_ept)
1703                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1704
1705         vmcs_writel(CR0_READ_SHADOW, cr0);
1706         vmcs_writel(GUEST_CR0, hw_cr0);
1707         vcpu->arch.cr0 = cr0;
1708
1709         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1710                 vmx_fpu_activate(vcpu);
1711 }
1712
1713 static u64 construct_eptp(unsigned long root_hpa)
1714 {
1715         u64 eptp;
1716
1717         /* TODO write the value reading from MSR */
1718         eptp = VMX_EPT_DEFAULT_MT |
1719                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1720         eptp |= (root_hpa & PAGE_MASK);
1721
1722         return eptp;
1723 }
1724
1725 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1726 {
1727         unsigned long guest_cr3;
1728         u64 eptp;
1729
1730         guest_cr3 = cr3;
1731         if (enable_ept) {
1732                 eptp = construct_eptp(cr3);
1733                 vmcs_write64(EPT_POINTER, eptp);
1734                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1735                         vcpu->kvm->arch.ept_identity_map_addr;
1736                 ept_load_pdptrs(vcpu);
1737         }
1738
1739         vmx_flush_tlb(vcpu);
1740         vmcs_writel(GUEST_CR3, guest_cr3);
1741         if (vcpu->arch.cr0 & X86_CR0_PE)
1742                 vmx_fpu_deactivate(vcpu);
1743 }
1744
1745 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1746 {
1747         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1748                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1749
1750         vcpu->arch.cr4 = cr4;
1751         if (enable_ept)
1752                 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1753
1754         vmcs_writel(CR4_READ_SHADOW, cr4);
1755         vmcs_writel(GUEST_CR4, hw_cr4);
1756 }
1757
1758 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1759 {
1760         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1761
1762         return vmcs_readl(sf->base);
1763 }
1764
1765 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1766                             struct kvm_segment *var, int seg)
1767 {
1768         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1769         u32 ar;
1770
1771         var->base = vmcs_readl(sf->base);
1772         var->limit = vmcs_read32(sf->limit);
1773         var->selector = vmcs_read16(sf->selector);
1774         ar = vmcs_read32(sf->ar_bytes);
1775         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1776                 ar = 0;
1777         var->type = ar & 15;
1778         var->s = (ar >> 4) & 1;
1779         var->dpl = (ar >> 5) & 3;
1780         var->present = (ar >> 7) & 1;
1781         var->avl = (ar >> 12) & 1;
1782         var->l = (ar >> 13) & 1;
1783         var->db = (ar >> 14) & 1;
1784         var->g = (ar >> 15) & 1;
1785         var->unusable = (ar >> 16) & 1;
1786 }
1787
1788 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1789 {
1790         if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1791                 return 0;
1792
1793         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1794                 return 3;
1795
1796         return vmcs_read16(GUEST_CS_SELECTOR) & 3;
1797 }
1798
1799 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1800 {
1801         u32 ar;
1802
1803         if (var->unusable)
1804                 ar = 1 << 16;
1805         else {
1806                 ar = var->type & 15;
1807                 ar |= (var->s & 1) << 4;
1808                 ar |= (var->dpl & 3) << 5;
1809                 ar |= (var->present & 1) << 7;
1810                 ar |= (var->avl & 1) << 12;
1811                 ar |= (var->l & 1) << 13;
1812                 ar |= (var->db & 1) << 14;
1813                 ar |= (var->g & 1) << 15;
1814         }
1815         if (ar == 0) /* a 0 value means unusable */
1816                 ar = AR_UNUSABLE_MASK;
1817
1818         return ar;
1819 }
1820
1821 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1822                             struct kvm_segment *var, int seg)
1823 {
1824         struct vcpu_vmx *vmx = to_vmx(vcpu);
1825         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1826         u32 ar;
1827
1828         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1829                 vmx->rmode.tr.selector = var->selector;
1830                 vmx->rmode.tr.base = var->base;
1831                 vmx->rmode.tr.limit = var->limit;
1832                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
1833                 return;
1834         }
1835         vmcs_writel(sf->base, var->base);
1836         vmcs_write32(sf->limit, var->limit);
1837         vmcs_write16(sf->selector, var->selector);
1838         if (vmx->rmode.vm86_active && var->s) {
1839                 /*
1840                  * Hack real-mode segments into vm86 compatibility.
1841                  */
1842                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1843                         vmcs_writel(sf->base, 0xf0000);
1844                 ar = 0xf3;
1845         } else
1846                 ar = vmx_segment_access_rights(var);
1847
1848         /*
1849          *   Fix the "Accessed" bit in AR field of segment registers for older
1850          * qemu binaries.
1851          *   IA32 arch specifies that at the time of processor reset the
1852          * "Accessed" bit in the AR field of segment registers is 1. And qemu
1853          * is setting it to 0 in the usedland code. This causes invalid guest
1854          * state vmexit when "unrestricted guest" mode is turned on.
1855          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
1856          * tree. Newer qemu binaries with that qemu fix would not need this
1857          * kvm hack.
1858          */
1859         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1860                 ar |= 0x1; /* Accessed */
1861
1862         vmcs_write32(sf->ar_bytes, ar);
1863 }
1864
1865 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1866 {
1867         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1868
1869         *db = (ar >> 14) & 1;
1870         *l = (ar >> 13) & 1;
1871 }
1872
1873 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1874 {
1875         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1876         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1877 }
1878
1879 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1880 {
1881         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1882         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1883 }
1884
1885 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1886 {
1887         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1888         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1889 }
1890
1891 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1892 {
1893         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1894         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1895 }
1896
1897 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1898 {
1899         struct kvm_segment var;
1900         u32 ar;
1901
1902         vmx_get_segment(vcpu, &var, seg);
1903         ar = vmx_segment_access_rights(&var);
1904
1905         if (var.base != (var.selector << 4))
1906                 return false;
1907         if (var.limit != 0xffff)
1908                 return false;
1909         if (ar != 0xf3)
1910                 return false;
1911
1912         return true;
1913 }
1914
1915 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1916 {
1917         struct kvm_segment cs;
1918         unsigned int cs_rpl;
1919
1920         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1921         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1922
1923         if (cs.unusable)
1924                 return false;
1925         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1926                 return false;
1927         if (!cs.s)
1928                 return false;
1929         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1930                 if (cs.dpl > cs_rpl)
1931                         return false;
1932         } else {
1933                 if (cs.dpl != cs_rpl)
1934                         return false;
1935         }
1936         if (!cs.present)
1937                 return false;
1938
1939         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1940         return true;
1941 }
1942
1943 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1944 {
1945         struct kvm_segment ss;
1946         unsigned int ss_rpl;
1947
1948         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1949         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1950
1951         if (ss.unusable)
1952                 return true;
1953         if (ss.type != 3 && ss.type != 7)
1954                 return false;
1955         if (!ss.s)
1956                 return false;
1957         if (ss.dpl != ss_rpl) /* DPL != RPL */
1958                 return false;
1959         if (!ss.present)
1960                 return false;
1961
1962         return true;
1963 }
1964
1965 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1966 {
1967         struct kvm_segment var;
1968         unsigned int rpl;
1969
1970         vmx_get_segment(vcpu, &var, seg);
1971         rpl = var.selector & SELECTOR_RPL_MASK;
1972
1973         if (var.unusable)
1974                 return true;
1975         if (!var.s)
1976                 return false;
1977         if (!var.present)
1978                 return false;
1979         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1980                 if (var.dpl < rpl) /* DPL < RPL */
1981                         return false;
1982         }
1983
1984         /* TODO: Add other members to kvm_segment_field to allow checking for other access
1985          * rights flags
1986          */
1987         return true;
1988 }
1989
1990 static bool tr_valid(struct kvm_vcpu *vcpu)
1991 {
1992         struct kvm_segment tr;
1993
1994         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1995
1996         if (tr.unusable)
1997                 return false;
1998         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
1999                 return false;
2000         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2001                 return false;
2002         if (!tr.present)
2003                 return false;
2004
2005         return true;
2006 }
2007
2008 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2009 {
2010         struct kvm_segment ldtr;
2011
2012         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2013
2014         if (ldtr.unusable)
2015                 return true;
2016         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
2017                 return false;
2018         if (ldtr.type != 2)
2019                 return false;
2020         if (!ldtr.present)
2021                 return false;
2022
2023         return true;
2024 }
2025
2026 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2027 {
2028         struct kvm_segment cs, ss;
2029
2030         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2031         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2032
2033         return ((cs.selector & SELECTOR_RPL_MASK) ==
2034                  (ss.selector & SELECTOR_RPL_MASK));
2035 }
2036
2037 /*
2038  * Check if guest state is valid. Returns true if valid, false if
2039  * not.
2040  * We assume that registers are always usable
2041  */
2042 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2043 {
2044         /* real mode guest state checks */
2045         if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
2046                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2047                         return false;
2048                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2049                         return false;
2050                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2051                         return false;
2052                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2053                         return false;
2054                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2055                         return false;
2056                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2057                         return false;
2058         } else {
2059         /* protected mode guest state checks */
2060                 if (!cs_ss_rpl_check(vcpu))
2061                         return false;
2062                 if (!code_segment_valid(vcpu))
2063                         return false;
2064                 if (!stack_segment_valid(vcpu))
2065                         return false;
2066                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2067                         return false;
2068                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2069                         return false;
2070                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2071                         return false;
2072                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2073                         return false;
2074                 if (!tr_valid(vcpu))
2075                         return false;
2076                 if (!ldtr_valid(vcpu))
2077                         return false;
2078         }
2079         /* TODO:
2080          * - Add checks on RIP
2081          * - Add checks on RFLAGS
2082          */
2083
2084         return true;
2085 }
2086
2087 static int init_rmode_tss(struct kvm *kvm)
2088 {
2089         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2090         u16 data = 0;
2091         int ret = 0;
2092         int r;
2093
2094         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2095         if (r < 0)
2096                 goto out;
2097         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2098         r = kvm_write_guest_page(kvm, fn++, &data,
2099                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
2100         if (r < 0)
2101                 goto out;
2102         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2103         if (r < 0)
2104                 goto out;
2105         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2106         if (r < 0)
2107                 goto out;
2108         data = ~0;
2109         r = kvm_write_guest_page(kvm, fn, &data,
2110                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2111                                  sizeof(u8));
2112         if (r < 0)
2113                 goto out;
2114
2115         ret = 1;
2116 out:
2117         return ret;
2118 }
2119
2120 static int init_rmode_identity_map(struct kvm *kvm)
2121 {
2122         int i, r, ret;
2123         pfn_t identity_map_pfn;
2124         u32 tmp;
2125
2126         if (!enable_ept)
2127                 return 1;
2128         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2129                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2130                         "haven't been allocated!\n");
2131                 return 0;
2132         }
2133         if (likely(kvm->arch.ept_identity_pagetable_done))
2134                 return 1;
2135         ret = 0;
2136         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2137         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2138         if (r < 0)
2139                 goto out;
2140         /* Set up identity-mapping pagetable for EPT in real mode */
2141         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2142                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2143                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2144                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2145                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2146                 if (r < 0)
2147                         goto out;
2148         }
2149         kvm->arch.ept_identity_pagetable_done = true;
2150         ret = 1;
2151 out:
2152         return ret;
2153 }
2154
2155 static void seg_setup(int seg)
2156 {
2157         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2158         unsigned int ar;
2159
2160         vmcs_write16(sf->selector, 0);
2161         vmcs_writel(sf->base, 0);
2162         vmcs_write32(sf->limit, 0xffff);
2163         if (enable_unrestricted_guest) {
2164                 ar = 0x93;
2165                 if (seg == VCPU_SREG_CS)
2166                         ar |= 0x08; /* code segment */
2167         } else
2168                 ar = 0xf3;
2169
2170         vmcs_write32(sf->ar_bytes, ar);
2171 }
2172
2173 static int alloc_apic_access_page(struct kvm *kvm)
2174 {
2175         struct kvm_userspace_memory_region kvm_userspace_mem;
2176         int r = 0;
2177
2178         down_write(&kvm->slots_lock);
2179         if (kvm->arch.apic_access_page)
2180                 goto out;
2181         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2182         kvm_userspace_mem.flags = 0;
2183         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2184         kvm_userspace_mem.memory_size = PAGE_SIZE;
2185         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2186         if (r)
2187                 goto out;
2188
2189         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2190 out:
2191         up_write(&kvm->slots_lock);
2192         return r;
2193 }
2194
2195 static int alloc_identity_pagetable(struct kvm *kvm)
2196 {
2197         struct kvm_userspace_memory_region kvm_userspace_mem;
2198         int r = 0;
2199
2200         down_write(&kvm->slots_lock);
2201         if (kvm->arch.ept_identity_pagetable)
2202                 goto out;
2203         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2204         kvm_userspace_mem.flags = 0;
2205         kvm_userspace_mem.guest_phys_addr =
2206                 kvm->arch.ept_identity_map_addr;
2207         kvm_userspace_mem.memory_size = PAGE_SIZE;
2208         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2209         if (r)
2210                 goto out;
2211
2212         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2213                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2214 out:
2215         up_write(&kvm->slots_lock);
2216         return r;
2217 }
2218
2219 static void allocate_vpid(struct vcpu_vmx *vmx)
2220 {
2221         int vpid;
2222
2223         vmx->vpid = 0;
2224         if (!enable_vpid)
2225                 return;
2226         spin_lock(&vmx_vpid_lock);
2227         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2228         if (vpid < VMX_NR_VPIDS) {
2229                 vmx->vpid = vpid;
2230                 __set_bit(vpid, vmx_vpid_bitmap);
2231         }
2232         spin_unlock(&vmx_vpid_lock);
2233 }
2234
2235 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2236 {
2237         int f = sizeof(unsigned long);
2238
2239         if (!cpu_has_vmx_msr_bitmap())
2240                 return;
2241
2242         /*
2243          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2244          * have the write-low and read-high bitmap offsets the wrong way round.
2245          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2246          */
2247         if (msr <= 0x1fff) {
2248                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2249                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2250         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2251                 msr &= 0x1fff;
2252                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2253                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2254         }
2255 }
2256
2257 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2258 {
2259         if (!longmode_only)
2260                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2261         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2262 }
2263
2264 /*
2265  * Sets up the vmcs for emulated real mode.
2266  */
2267 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2268 {
2269         u32 host_sysenter_cs, msr_low, msr_high;
2270         u32 junk;
2271         u64 host_pat, tsc_this, tsc_base;
2272         unsigned long a;
2273         struct descriptor_table dt;
2274         int i;
2275         unsigned long kvm_vmx_return;
2276         u32 exec_control;
2277
2278         /* I/O */
2279         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2280         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2281
2282         if (cpu_has_vmx_msr_bitmap())
2283                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2284
2285         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2286
2287         /* Control */
2288         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2289                 vmcs_config.pin_based_exec_ctrl);
2290
2291         exec_control = vmcs_config.cpu_based_exec_ctrl;
2292         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2293                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2294 #ifdef CONFIG_X86_64
2295                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2296                                 CPU_BASED_CR8_LOAD_EXITING;
2297 #endif
2298         }
2299         if (!enable_ept)
2300                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2301                                 CPU_BASED_CR3_LOAD_EXITING  |
2302                                 CPU_BASED_INVLPG_EXITING;
2303         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2304
2305         if (cpu_has_secondary_exec_ctrls()) {
2306                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2307                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2308                         exec_control &=
2309                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2310                 if (vmx->vpid == 0)
2311                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2312                 if (!enable_ept)
2313                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2314                 if (!enable_unrestricted_guest)
2315                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2316                 if (!ple_gap)
2317                         exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2318                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2319         }
2320
2321         if (ple_gap) {
2322                 vmcs_write32(PLE_GAP, ple_gap);
2323                 vmcs_write32(PLE_WINDOW, ple_window);
2324         }
2325
2326         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2327         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2328         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2329
2330         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
2331         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2332         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2333
2334         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2335         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2336         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2337         vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs());    /* 22.2.4 */
2338         vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs());    /* 22.2.4 */
2339         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2340 #ifdef CONFIG_X86_64
2341         rdmsrl(MSR_FS_BASE, a);
2342         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2343         rdmsrl(MSR_GS_BASE, a);
2344         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2345 #else
2346         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2347         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2348 #endif
2349
2350         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2351
2352         kvm_get_idt(&dt);
2353         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
2354
2355         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2356         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2357         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2358         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2359         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2360
2361         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2362         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2363         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2364         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2365         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2366         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2367
2368         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2369                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2370                 host_pat = msr_low | ((u64) msr_high << 32);
2371                 vmcs_write64(HOST_IA32_PAT, host_pat);
2372         }
2373         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2374                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2375                 host_pat = msr_low | ((u64) msr_high << 32);
2376                 /* Write the default value follow host pat */
2377                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2378                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2379                 vmx->vcpu.arch.pat = host_pat;
2380         }
2381
2382         for (i = 0; i < NR_VMX_MSR; ++i) {
2383                 u32 index = vmx_msr_index[i];
2384                 u32 data_low, data_high;
2385                 u64 data;
2386                 int j = vmx->nmsrs;
2387
2388                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2389                         continue;
2390                 if (wrmsr_safe(index, data_low, data_high) < 0)
2391                         continue;
2392                 data = data_low | ((u64)data_high << 32);
2393                 vmx->guest_msrs[j].index = i;
2394                 vmx->guest_msrs[j].data = 0;
2395                 ++vmx->nmsrs;
2396         }
2397
2398         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2399
2400         /* 22.2.1, 20.8.1 */
2401         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2402
2403         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2404         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2405
2406         tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2407         rdtscll(tsc_this);
2408         if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2409                 tsc_base = tsc_this;
2410
2411         guest_write_tsc(0, tsc_base);
2412
2413         return 0;
2414 }
2415
2416 static int init_rmode(struct kvm *kvm)
2417 {
2418         if (!init_rmode_tss(kvm))
2419                 return 0;
2420         if (!init_rmode_identity_map(kvm))
2421                 return 0;
2422         return 1;
2423 }
2424
2425 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2426 {
2427         struct vcpu_vmx *vmx = to_vmx(vcpu);
2428         u64 msr;
2429         int ret;
2430
2431         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2432         down_read(&vcpu->kvm->slots_lock);
2433         if (!init_rmode(vmx->vcpu.kvm)) {
2434                 ret = -ENOMEM;
2435                 goto out;
2436         }
2437
2438         vmx->rmode.vm86_active = 0;
2439
2440         vmx->soft_vnmi_blocked = 0;
2441
2442         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2443         kvm_set_cr8(&vmx->vcpu, 0);
2444         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2445         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2446                 msr |= MSR_IA32_APICBASE_BSP;
2447         kvm_set_apic_base(&vmx->vcpu, msr);
2448
2449         fx_init(&vmx->vcpu);
2450
2451         seg_setup(VCPU_SREG_CS);
2452         /*
2453          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2454          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2455          */
2456         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2457                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2458                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2459         } else {
2460                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2461                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2462         }
2463
2464         seg_setup(VCPU_SREG_DS);
2465         seg_setup(VCPU_SREG_ES);
2466         seg_setup(VCPU_SREG_FS);
2467         seg_setup(VCPU_SREG_GS);
2468         seg_setup(VCPU_SREG_SS);
2469
2470         vmcs_write16(GUEST_TR_SELECTOR, 0);
2471         vmcs_writel(GUEST_TR_BASE, 0);
2472         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2473         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2474
2475         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2476         vmcs_writel(GUEST_LDTR_BASE, 0);
2477         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2478         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2479
2480         vmcs_write32(GUEST_SYSENTER_CS, 0);
2481         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2482         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2483
2484         vmcs_writel(GUEST_RFLAGS, 0x02);
2485         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2486                 kvm_rip_write(vcpu, 0xfff0);
2487         else
2488                 kvm_rip_write(vcpu, 0);
2489         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2490
2491         vmcs_writel(GUEST_DR7, 0x400);
2492
2493         vmcs_writel(GUEST_GDTR_BASE, 0);
2494         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2495
2496         vmcs_writel(GUEST_IDTR_BASE, 0);
2497         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2498
2499         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2500         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2501         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2502
2503         /* Special registers */
2504         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2505
2506         setup_msrs(vmx);
2507
2508         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2509
2510         if (cpu_has_vmx_tpr_shadow()) {
2511                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2512                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2513                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2514                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2515                 vmcs_write32(TPR_THRESHOLD, 0);
2516         }
2517
2518         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2519                 vmcs_write64(APIC_ACCESS_ADDR,
2520                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2521
2522         if (vmx->vpid != 0)
2523                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2524
2525         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2526         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2527         vmx_set_cr4(&vmx->vcpu, 0);
2528         vmx_set_efer(&vmx->vcpu, 0);
2529         vmx_fpu_activate(&vmx->vcpu);
2530         update_exception_bitmap(&vmx->vcpu);
2531
2532         vpid_sync_vcpu_all(vmx);
2533
2534         ret = 0;
2535
2536         /* HACK: Don't enable emulation on guest boot/reset */
2537         vmx->emulation_required = 0;
2538
2539 out:
2540         up_read(&vcpu->kvm->slots_lock);
2541         return ret;
2542 }
2543
2544 static void enable_irq_window(struct kvm_vcpu *vcpu)
2545 {
2546         u32 cpu_based_vm_exec_control;
2547
2548         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2549         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2550         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2551 }
2552
2553 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2554 {
2555         u32 cpu_based_vm_exec_control;
2556
2557         if (!cpu_has_virtual_nmis()) {
2558                 enable_irq_window(vcpu);
2559                 return;
2560         }
2561
2562         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2563         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2564         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2565 }
2566
2567 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2568 {
2569         struct vcpu_vmx *vmx = to_vmx(vcpu);
2570         uint32_t intr;
2571         int irq = vcpu->arch.interrupt.nr;
2572
2573         trace_kvm_inj_virq(irq);
2574
2575         ++vcpu->stat.irq_injections;
2576         if (vmx->rmode.vm86_active) {
2577                 vmx->rmode.irq.pending = true;
2578                 vmx->rmode.irq.vector = irq;
2579                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2580                 if (vcpu->arch.interrupt.soft)
2581                         vmx->rmode.irq.rip +=
2582                                 vmx->vcpu.arch.event_exit_inst_len;
2583                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2584                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2585                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2586                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2587                 return;
2588         }
2589         intr = irq | INTR_INFO_VALID_MASK;
2590         if (vcpu->arch.interrupt.soft) {
2591                 intr |= INTR_TYPE_SOFT_INTR;
2592                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2593                              vmx->vcpu.arch.event_exit_inst_len);
2594         } else
2595                 intr |= INTR_TYPE_EXT_INTR;
2596         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2597 }
2598
2599 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2600 {
2601         struct vcpu_vmx *vmx = to_vmx(vcpu);
2602
2603         if (!cpu_has_virtual_nmis()) {
2604                 /*
2605                  * Tracking the NMI-blocked state in software is built upon
2606                  * finding the next open IRQ window. This, in turn, depends on
2607                  * well-behaving guests: They have to keep IRQs disabled at
2608                  * least as long as the NMI handler runs. Otherwise we may
2609                  * cause NMI nesting, maybe breaking the guest. But as this is
2610                  * highly unlikely, we can live with the residual risk.
2611                  */
2612                 vmx->soft_vnmi_blocked = 1;
2613                 vmx->vnmi_blocked_time = 0;
2614         }
2615
2616         ++vcpu->stat.nmi_injections;
2617         if (vmx->rmode.vm86_active) {
2618                 vmx->rmode.irq.pending = true;
2619                 vmx->rmode.irq.vector = NMI_VECTOR;
2620                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2621                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2622                              NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2623                              INTR_INFO_VALID_MASK);
2624                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2625                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2626                 return;
2627         }
2628         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2629                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2630 }
2631
2632 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2633 {
2634         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2635                 return 0;
2636
2637         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2638                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2639                                 GUEST_INTR_STATE_NMI));
2640 }
2641
2642 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2643 {
2644         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2645                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2646                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2647 }
2648
2649 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2650 {
2651         int ret;
2652         struct kvm_userspace_memory_region tss_mem = {
2653                 .slot = TSS_PRIVATE_MEMSLOT,
2654                 .guest_phys_addr = addr,
2655                 .memory_size = PAGE_SIZE * 3,
2656                 .flags = 0,
2657         };
2658
2659         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2660         if (ret)
2661                 return ret;
2662         kvm->arch.tss_addr = addr;
2663         return 0;
2664 }
2665
2666 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2667                                   int vec, u32 err_code)
2668 {
2669         /*
2670          * Instruction with address size override prefix opcode 0x67
2671          * Cause the #SS fault with 0 error code in VM86 mode.
2672          */
2673         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2674                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2675                         return 1;
2676         /*
2677          * Forward all other exceptions that are valid in real mode.
2678          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2679          *        the required debugging infrastructure rework.
2680          */
2681         switch (vec) {
2682         case DB_VECTOR:
2683                 if (vcpu->guest_debug &
2684                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2685                         return 0;
2686                 kvm_queue_exception(vcpu, vec);
2687                 return 1;
2688         case BP_VECTOR:
2689                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2690                         return 0;
2691                 /* fall through */
2692         case DE_VECTOR:
2693         case OF_VECTOR:
2694         case BR_VECTOR:
2695         case UD_VECTOR:
2696         case DF_VECTOR:
2697         case SS_VECTOR:
2698         case GP_VECTOR:
2699         case MF_VECTOR:
2700                 kvm_queue_exception(vcpu, vec);
2701                 return 1;
2702         }
2703         return 0;
2704 }
2705
2706 /*
2707  * Trigger machine check on the host. We assume all the MSRs are already set up
2708  * by the CPU and that we still run on the same CPU as the MCE occurred on.
2709  * We pass a fake environment to the machine check handler because we want
2710  * the guest to be always treated like user space, no matter what context
2711  * it used internally.
2712  */
2713 static void kvm_machine_check(void)
2714 {
2715 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2716         struct pt_regs regs = {
2717                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2718                 .flags = X86_EFLAGS_IF,
2719         };
2720
2721         do_machine_check(&regs, 0);
2722 #endif
2723 }
2724
2725 static int handle_machine_check(struct kvm_vcpu *vcpu)
2726 {
2727         /* already handled by vcpu_run */
2728         return 1;
2729 }
2730
2731 static int handle_exception(struct kvm_vcpu *vcpu)
2732 {
2733         struct vcpu_vmx *vmx = to_vmx(vcpu);
2734         struct kvm_run *kvm_run = vcpu->run;
2735         u32 intr_info, ex_no, error_code;
2736         unsigned long cr2, rip, dr6;
2737         u32 vect_info;
2738         enum emulation_result er;
2739
2740         vect_info = vmx->idt_vectoring_info;
2741         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2742
2743         if (is_machine_check(intr_info))
2744                 return handle_machine_check(vcpu);
2745
2746         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2747                                                 !is_page_fault(intr_info))
2748                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2749                        "intr info 0x%x\n", __func__, vect_info, intr_info);
2750
2751         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2752                 return 1;  /* already handled by vmx_vcpu_run() */
2753
2754         if (is_no_device(intr_info)) {
2755                 vmx_fpu_activate(vcpu);
2756                 return 1;
2757         }
2758
2759         if (is_invalid_opcode(intr_info)) {
2760                 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
2761                 if (er != EMULATE_DONE)
2762                         kvm_queue_exception(vcpu, UD_VECTOR);
2763                 return 1;
2764         }
2765
2766         error_code = 0;
2767         rip = kvm_rip_read(vcpu);
2768         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2769                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2770         if (is_page_fault(intr_info)) {
2771                 /* EPT won't cause page fault directly */
2772                 if (enable_ept)
2773                         BUG();
2774                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2775                 trace_kvm_page_fault(cr2, error_code);
2776
2777                 if (kvm_event_needs_reinjection(vcpu))
2778                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
2779                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2780         }
2781
2782         if (vmx->rmode.vm86_active &&
2783             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2784                                                                 error_code)) {
2785                 if (vcpu->arch.halt_request) {
2786                         vcpu->arch.halt_request = 0;
2787                         return kvm_emulate_halt(vcpu);
2788                 }
2789                 return 1;
2790         }
2791
2792         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2793         switch (ex_no) {
2794         case DB_VECTOR:
2795                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2796                 if (!(vcpu->guest_debug &
2797                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2798                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2799                         kvm_queue_exception(vcpu, DB_VECTOR);
2800                         return 1;
2801                 }
2802                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2803                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2804                 /* fall through */
2805         case BP_VECTOR:
2806                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2807                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2808                 kvm_run->debug.arch.exception = ex_no;
2809                 break;
2810         default:
2811                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2812                 kvm_run->ex.exception = ex_no;
2813                 kvm_run->ex.error_code = error_code;
2814                 break;
2815         }
2816         return 0;
2817 }
2818
2819 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
2820 {
2821         ++vcpu->stat.irq_exits;
2822         return 1;
2823 }
2824
2825 static int handle_triple_fault(struct kvm_vcpu *vcpu)
2826 {
2827         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
2828         return 0;
2829 }
2830
2831 static int handle_io(struct kvm_vcpu *vcpu)
2832 {
2833         unsigned long exit_qualification;
2834         int size, in, string;
2835         unsigned port;
2836
2837         ++vcpu->stat.io_exits;
2838         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2839         string = (exit_qualification & 16) != 0;
2840
2841         if (string) {
2842                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO)
2843                         return 0;
2844                 return 1;
2845         }
2846
2847         size = (exit_qualification & 7) + 1;
2848         in = (exit_qualification & 8) != 0;
2849         port = exit_qualification >> 16;
2850
2851         skip_emulated_instruction(vcpu);
2852         return kvm_emulate_pio(vcpu, in, size, port);
2853 }
2854
2855 static void
2856 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2857 {
2858         /*
2859          * Patch in the VMCALL instruction:
2860          */
2861         hypercall[0] = 0x0f;
2862         hypercall[1] = 0x01;
2863         hypercall[2] = 0xc1;
2864 }
2865
2866 static int handle_cr(struct kvm_vcpu *vcpu)
2867 {
2868         unsigned long exit_qualification, val;
2869         int cr;
2870         int reg;
2871
2872         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2873         cr = exit_qualification & 15;
2874         reg = (exit_qualification >> 8) & 15;
2875         switch ((exit_qualification >> 4) & 3) {
2876         case 0: /* mov to cr */
2877                 val = kvm_register_read(vcpu, reg);
2878                 trace_kvm_cr_write(cr, val);
2879                 switch (cr) {
2880                 case 0:
2881                         kvm_set_cr0(vcpu, val);
2882                         skip_emulated_instruction(vcpu);
2883                         return 1;
2884                 case 3:
2885                         kvm_set_cr3(vcpu, val);
2886                         skip_emulated_instruction(vcpu);
2887                         return 1;
2888                 case 4:
2889                         kvm_set_cr4(vcpu, val);
2890                         skip_emulated_instruction(vcpu);
2891                         return 1;
2892                 case 8: {
2893                                 u8 cr8_prev = kvm_get_cr8(vcpu);
2894                                 u8 cr8 = kvm_register_read(vcpu, reg);
2895                                 kvm_set_cr8(vcpu, cr8);
2896                                 skip_emulated_instruction(vcpu);
2897                                 if (irqchip_in_kernel(vcpu->kvm))
2898                                         return 1;
2899                                 if (cr8_prev <= cr8)
2900                                         return 1;
2901                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
2902                                 return 0;
2903                         }
2904                 };
2905                 break;
2906         case 2: /* clts */
2907                 vmx_fpu_deactivate(vcpu);
2908                 vcpu->arch.cr0 &= ~X86_CR0_TS;
2909                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2910                 vmx_fpu_activate(vcpu);
2911                 skip_emulated_instruction(vcpu);
2912                 return 1;
2913         case 1: /*mov from cr*/
2914                 switch (cr) {
2915                 case 3:
2916                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2917                         trace_kvm_cr_read(cr, vcpu->arch.cr3);
2918                         skip_emulated_instruction(vcpu);
2919                         return 1;
2920                 case 8:
2921                         val = kvm_get_cr8(vcpu);
2922                         kvm_register_write(vcpu, reg, val);
2923                         trace_kvm_cr_read(cr, val);
2924                         skip_emulated_instruction(vcpu);
2925                         return 1;
2926                 }
2927                 break;
2928         case 3: /* lmsw */
2929                 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2930
2931                 skip_emulated_instruction(vcpu);
2932                 return 1;
2933         default:
2934                 break;
2935         }
2936         vcpu->run->exit_reason = 0;
2937         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2938                (int)(exit_qualification >> 4) & 3, cr);
2939         return 0;
2940 }
2941
2942 static int handle_dr(struct kvm_vcpu *vcpu)
2943 {
2944         unsigned long exit_qualification;
2945         unsigned long val;
2946         int dr, reg;
2947
2948         if (!kvm_require_cpl(vcpu, 0))
2949                 return 1;
2950         dr = vmcs_readl(GUEST_DR7);
2951         if (dr & DR7_GD) {
2952                 /*
2953                  * As the vm-exit takes precedence over the debug trap, we
2954                  * need to emulate the latter, either for the host or the
2955                  * guest debugging itself.
2956                  */
2957                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2958                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
2959                         vcpu->run->debug.arch.dr7 = dr;
2960                         vcpu->run->debug.arch.pc =
2961                                 vmcs_readl(GUEST_CS_BASE) +
2962                                 vmcs_readl(GUEST_RIP);
2963                         vcpu->run->debug.arch.exception = DB_VECTOR;
2964                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
2965                         return 0;
2966                 } else {
2967                         vcpu->arch.dr7 &= ~DR7_GD;
2968                         vcpu->arch.dr6 |= DR6_BD;
2969                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2970                         kvm_queue_exception(vcpu, DB_VECTOR);
2971                         return 1;
2972                 }
2973         }
2974
2975         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2976         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2977         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2978         if (exit_qualification & TYPE_MOV_FROM_DR) {
2979                 switch (dr) {
2980                 case 0 ... 3:
2981                         val = vcpu->arch.db[dr];
2982                         break;
2983                 case 6:
2984                         val = vcpu->arch.dr6;
2985                         break;
2986                 case 7:
2987                         val = vcpu->arch.dr7;
2988                         break;
2989                 default:
2990                         val = 0;
2991                 }
2992                 kvm_register_write(vcpu, reg, val);
2993         } else {
2994                 val = vcpu->arch.regs[reg];
2995                 switch (dr) {
2996                 case 0 ... 3:
2997                         vcpu->arch.db[dr] = val;
2998                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2999                                 vcpu->arch.eff_db[dr] = val;
3000                         break;
3001                 case 4 ... 5:
3002                         if (vcpu->arch.cr4 & X86_CR4_DE)
3003                                 kvm_queue_exception(vcpu, UD_VECTOR);
3004                         break;
3005                 case 6:
3006                         if (val & 0xffffffff00000000ULL) {
3007                                 kvm_queue_exception(vcpu, GP_VECTOR);
3008                                 break;
3009                         }
3010                         vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
3011                         break;
3012                 case 7:
3013                         if (val & 0xffffffff00000000ULL) {
3014                                 kvm_queue_exception(vcpu, GP_VECTOR);
3015                                 break;
3016                         }
3017                         vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3018                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3019                                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3020                                 vcpu->arch.switch_db_regs =
3021                                         (val & DR7_BP_EN_MASK);
3022                         }
3023                         break;
3024                 }
3025         }
3026         skip_emulated_instruction(vcpu);
3027         return 1;
3028 }
3029
3030 static int handle_cpuid(struct kvm_vcpu *vcpu)
3031 {
3032         kvm_emulate_cpuid(vcpu);
3033         return 1;
3034 }
3035
3036 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3037 {
3038         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3039         u64 data;
3040
3041         if (vmx_get_msr(vcpu, ecx, &data)) {
3042                 kvm_inject_gp(vcpu, 0);
3043                 return 1;
3044         }
3045
3046         trace_kvm_msr_read(ecx, data);
3047
3048         /* FIXME: handling of bits 32:63 of rax, rdx */
3049         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3050         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3051         skip_emulated_instruction(vcpu);
3052         return 1;
3053 }
3054
3055 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3056 {
3057         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3058         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3059                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3060
3061         trace_kvm_msr_write(ecx, data);
3062
3063         if (vmx_set_msr(vcpu, ecx, data) != 0) {
3064                 kvm_inject_gp(vcpu, 0);
3065                 return 1;
3066         }
3067
3068         skip_emulated_instruction(vcpu);
3069         return 1;
3070 }
3071
3072 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3073 {
3074         return 1;
3075 }
3076
3077 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3078 {
3079         u32 cpu_based_vm_exec_control;
3080
3081         /* clear pending irq */
3082         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3083         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3084         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3085
3086         ++vcpu->stat.irq_window_exits;
3087
3088         /*
3089          * If the user space waits to inject interrupts, exit as soon as
3090          * possible
3091          */
3092         if (!irqchip_in_kernel(vcpu->kvm) &&
3093             vcpu->run->request_interrupt_window &&
3094             !kvm_cpu_has_interrupt(vcpu)) {
3095                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3096                 return 0;
3097         }
3098         return 1;
3099 }
3100
3101 static int handle_halt(struct kvm_vcpu *vcpu)
3102 {
3103         skip_emulated_instruction(vcpu);
3104         return kvm_emulate_halt(vcpu);
3105 }
3106
3107 static int handle_vmcall(struct kvm_vcpu *vcpu)
3108 {
3109         skip_emulated_instruction(vcpu);
3110         kvm_emulate_hypercall(vcpu);
3111         return 1;
3112 }
3113
3114 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3115 {
3116         kvm_queue_exception(vcpu, UD_VECTOR);
3117         return 1;
3118 }
3119
3120 static int handle_invlpg(struct kvm_vcpu *vcpu)
3121 {
3122         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3123
3124         kvm_mmu_invlpg(vcpu, exit_qualification);
3125         skip_emulated_instruction(vcpu);
3126         return 1;
3127 }
3128
3129 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3130 {
3131         skip_emulated_instruction(vcpu);
3132         /* TODO: Add support for VT-d/pass-through device */
3133         return 1;
3134 }
3135
3136 static int handle_apic_access(struct kvm_vcpu *vcpu)
3137 {
3138         unsigned long exit_qualification;
3139         enum emulation_result er;
3140         unsigned long offset;
3141
3142         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3143         offset = exit_qualification & 0xffful;
3144
3145         er = emulate_instruction(vcpu, 0, 0, 0);
3146
3147         if (er !=  EMULATE_DONE) {
3148                 printk(KERN_ERR
3149                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3150                        offset);
3151                 return -ENOEXEC;
3152         }
3153         return 1;
3154 }
3155
3156 static int handle_task_switch(struct kvm_vcpu *vcpu)
3157 {
3158         struct vcpu_vmx *vmx = to_vmx(vcpu);
3159         unsigned long exit_qualification;
3160         u16 tss_selector;
3161         int reason, type, idt_v;
3162
3163         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3164         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3165
3166         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3167
3168         reason = (u32)exit_qualification >> 30;
3169         if (reason == TASK_SWITCH_GATE && idt_v) {
3170                 switch (type) {
3171                 case INTR_TYPE_NMI_INTR:
3172                         vcpu->arch.nmi_injected = false;
3173                         if (cpu_has_virtual_nmis())
3174                                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3175                                               GUEST_INTR_STATE_NMI);
3176                         break;
3177                 case INTR_TYPE_EXT_INTR:
3178                 case INTR_TYPE_SOFT_INTR:
3179                         kvm_clear_interrupt_queue(vcpu);
3180                         break;
3181                 case INTR_TYPE_HARD_EXCEPTION:
3182                 case INTR_TYPE_SOFT_EXCEPTION:
3183                         kvm_clear_exception_queue(vcpu);
3184                         break;
3185                 default:
3186                         break;
3187                 }
3188         }
3189         tss_selector = exit_qualification;
3190
3191         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3192                        type != INTR_TYPE_EXT_INTR &&
3193                        type != INTR_TYPE_NMI_INTR))
3194                 skip_emulated_instruction(vcpu);
3195
3196         if (!kvm_task_switch(vcpu, tss_selector, reason))
3197                 return 0;
3198
3199         /* clear all local breakpoint enable flags */
3200         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3201
3202         /*
3203          * TODO: What about debug traps on tss switch?
3204          *       Are we supposed to inject them and update dr6?
3205          */
3206
3207         return 1;
3208 }
3209
3210 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3211 {
3212         unsigned long exit_qualification;
3213         gpa_t gpa;
3214         int gla_validity;
3215
3216         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3217
3218         if (exit_qualification & (1 << 6)) {
3219                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3220                 return -EINVAL;
3221         }
3222
3223         gla_validity = (exit_qualification >> 7) & 0x3;
3224         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3225                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3226                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3227                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3228                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3229                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3230                         (long unsigned int)exit_qualification);
3231                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3232                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3233                 return 0;
3234         }
3235
3236         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3237         trace_kvm_page_fault(gpa, exit_qualification);
3238         return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3239 }
3240
3241 static u64 ept_rsvd_mask(u64 spte, int level)
3242 {
3243         int i;
3244         u64 mask = 0;
3245
3246         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3247                 mask |= (1ULL << i);
3248
3249         if (level > 2)
3250                 /* bits 7:3 reserved */
3251                 mask |= 0xf8;
3252         else if (level == 2) {
3253                 if (spte & (1ULL << 7))
3254                         /* 2MB ref, bits 20:12 reserved */
3255                         mask |= 0x1ff000;
3256                 else
3257                         /* bits 6:3 reserved */
3258                         mask |= 0x78;
3259         }
3260
3261         return mask;
3262 }
3263
3264 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3265                                        int level)
3266 {
3267         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3268
3269         /* 010b (write-only) */
3270         WARN_ON((spte & 0x7) == 0x2);
3271
3272         /* 110b (write/execute) */
3273         WARN_ON((spte & 0x7) == 0x6);
3274
3275         /* 100b (execute-only) and value not supported by logical processor */
3276         if (!cpu_has_vmx_ept_execute_only())
3277                 WARN_ON((spte & 0x7) == 0x4);
3278
3279         /* not 000b */
3280         if ((spte & 0x7)) {
3281                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3282
3283                 if (rsvd_bits != 0) {
3284                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3285                                          __func__, rsvd_bits);
3286                         WARN_ON(1);
3287                 }
3288
3289                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3290                         u64 ept_mem_type = (spte & 0x38) >> 3;
3291
3292                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
3293                             ept_mem_type == 7) {
3294                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3295                                                 __func__, ept_mem_type);
3296                                 WARN_ON(1);
3297                         }
3298                 }
3299         }
3300 }
3301
3302 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3303 {
3304         u64 sptes[4];
3305         int nr_sptes, i;
3306         gpa_t gpa;
3307
3308         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3309
3310         printk(KERN_ERR "EPT: Misconfiguration.\n");
3311         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3312
3313         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3314
3315         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3316                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3317
3318         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3319         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3320
3321         return 0;
3322 }
3323
3324 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3325 {
3326         u32 cpu_based_vm_exec_control;
3327
3328         /* clear pending NMI */
3329         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3330         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3331         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3332         ++vcpu->stat.nmi_window_exits;
3333
3334         return 1;
3335 }
3336
3337 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3338 {
3339         struct vcpu_vmx *vmx = to_vmx(vcpu);
3340         enum emulation_result err = EMULATE_DONE;
3341         int ret = 1;
3342
3343         while (!guest_state_valid(vcpu)) {
3344                 err = emulate_instruction(vcpu, 0, 0, 0);
3345
3346                 if (err == EMULATE_DO_MMIO) {
3347                         ret = 0;
3348                         goto out;
3349                 }
3350
3351                 if (err != EMULATE_DONE) {
3352                         kvm_report_emulation_failure(vcpu, "emulation failure");
3353                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3354                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3355                         ret = 0;
3356                         goto out;
3357                 }
3358
3359                 if (signal_pending(current))
3360                         goto out;
3361                 if (need_resched())
3362                         schedule();
3363         }
3364
3365         vmx->emulation_required = 0;
3366 out:
3367         return ret;
3368 }
3369
3370 /*
3371  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3372  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3373  */
3374 static int handle_pause(struct kvm_vcpu *vcpu)
3375 {
3376         skip_emulated_instruction(vcpu);
3377         kvm_vcpu_on_spin(vcpu);
3378
3379         return 1;
3380 }
3381
3382 /*
3383  * The exit handlers return 1 if the exit was handled fully and guest execution
3384  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3385  * to be done to userspace and return 0.
3386  */
3387 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3388         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3389         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3390         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3391         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3392         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3393         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3394         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3395         [EXIT_REASON_CPUID]                   = handle_cpuid,
3396         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3397         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3398         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3399         [EXIT_REASON_HLT]                     = handle_halt,
3400         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3401         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3402         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
3403         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
3404         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
3405         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
3406         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
3407         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
3408         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
3409         [EXIT_REASON_VMOFF]                   = handle_vmx_insn,
3410         [EXIT_REASON_VMON]                    = handle_vmx_insn,
3411         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3412         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3413         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3414         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3415         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
3416         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3417         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
3418         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
3419 };
3420
3421 static const int kvm_vmx_max_exit_handlers =
3422         ARRAY_SIZE(kvm_vmx_exit_handlers);
3423
3424 /*
3425  * The guest has exited.  See if we can fix it or if we need userspace
3426  * assistance.
3427  */
3428 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3429 {
3430         struct vcpu_vmx *vmx = to_vmx(vcpu);
3431         u32 exit_reason = vmx->exit_reason;
3432         u32 vectoring_info = vmx->idt_vectoring_info;
3433
3434         trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
3435
3436         /* If guest state is invalid, start emulating */
3437         if (vmx->emulation_required && emulate_invalid_guest_state)
3438                 return handle_invalid_guest_state(vcpu);
3439
3440         /* Access CR3 don't cause VMExit in paging mode, so we need
3441          * to sync with guest real CR3. */
3442         if (enable_ept && is_paging(vcpu))
3443                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3444
3445         if (unlikely(vmx->fail)) {
3446                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3447                 vcpu->run->fail_entry.hardware_entry_failure_reason
3448                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3449                 return 0;
3450         }
3451
3452         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3453                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3454                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3455                         exit_reason != EXIT_REASON_TASK_SWITCH))
3456                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3457                        "(0x%x) and exit reason is 0x%x\n",
3458                        __func__, vectoring_info, exit_reason);
3459
3460         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3461                 if (vmx_interrupt_allowed(vcpu)) {
3462                         vmx->soft_vnmi_blocked = 0;
3463                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3464                            vcpu->arch.nmi_pending) {
3465                         /*
3466                          * This CPU don't support us in finding the end of an
3467                          * NMI-blocked window if the guest runs with IRQs
3468                          * disabled. So we pull the trigger after 1 s of
3469                          * futile waiting, but inform the user about this.
3470                          */
3471                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3472                                "state on VCPU %d after 1 s timeout\n",
3473                                __func__, vcpu->vcpu_id);
3474                         vmx->soft_vnmi_blocked = 0;
3475                 }
3476         }
3477
3478         if (exit_reason < kvm_vmx_max_exit_handlers
3479             && kvm_vmx_exit_handlers[exit_reason])
3480                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3481         else {
3482                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3483                 vcpu->run->hw.hardware_exit_reason = exit_reason;
3484         }
3485         return 0;
3486 }
3487
3488 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3489 {
3490         if (irr == -1 || tpr < irr) {
3491                 vmcs_write32(TPR_THRESHOLD, 0);
3492                 return;
3493         }
3494
3495         vmcs_write32(TPR_THRESHOLD, irr);
3496 }
3497
3498 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3499 {
3500         u32 exit_intr_info;
3501         u32 idt_vectoring_info = vmx->idt_vectoring_info;
3502         bool unblock_nmi;
3503         u8 vector;
3504         int type;
3505         bool idtv_info_valid;
3506
3507         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3508
3509         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3510
3511         /* Handle machine checks before interrupts are enabled */
3512         if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3513             || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3514                 && is_machine_check(exit_intr_info)))
3515                 kvm_machine_check();
3516
3517         /* We need to handle NMIs before interrupts are enabled */
3518         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3519             (exit_intr_info & INTR_INFO_VALID_MASK))
3520                 asm("int $2");
3521
3522         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3523
3524         if (cpu_has_virtual_nmis()) {
3525                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3526                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3527                 /*
3528                  * SDM 3: 27.7.1.2 (September 2008)
3529                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3530                  * a guest IRET fault.
3531                  * SDM 3: 23.2.2 (September 2008)
3532                  * Bit 12 is undefined in any of the following cases:
3533                  *  If the VM exit sets the valid bit in the IDT-vectoring
3534                  *   information field.
3535                  *  If the VM exit is due to a double fault.
3536                  */
3537                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3538                     vector != DF_VECTOR && !idtv_info_valid)
3539                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3540                                       GUEST_INTR_STATE_NMI);
3541         } else if (unlikely(vmx->soft_vnmi_blocked))
3542                 vmx->vnmi_blocked_time +=
3543                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3544
3545         vmx->vcpu.arch.nmi_injected = false;
3546         kvm_clear_exception_queue(&vmx->vcpu);
3547         kvm_clear_interrupt_queue(&vmx->vcpu);
3548
3549         if (!idtv_info_valid)
3550                 return;
3551
3552         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3553         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3554
3555         switch (type) {
3556         case INTR_TYPE_NMI_INTR:
3557                 vmx->vcpu.arch.nmi_injected = true;
3558                 /*
3559                  * SDM 3: 27.7.1.2 (September 2008)
3560                  * Clear bit "block by NMI" before VM entry if a NMI
3561                  * delivery faulted.
3562                  */
3563                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3564                                 GUEST_INTR_STATE_NMI);
3565                 break;
3566         case INTR_TYPE_SOFT_EXCEPTION:
3567                 vmx->vcpu.arch.event_exit_inst_len =
3568                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3569                 /* fall through */
3570         case INTR_TYPE_HARD_EXCEPTION:
3571                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3572                         u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3573                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
3574                 } else
3575                         kvm_queue_exception(&vmx->vcpu, vector);
3576                 break;
3577         case INTR_TYPE_SOFT_INTR:
3578                 vmx->vcpu.arch.event_exit_inst_len =
3579                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3580                 /* fall through */
3581         case INTR_TYPE_EXT_INTR:
3582                 kvm_queue_interrupt(&vmx->vcpu, vector,
3583                         type == INTR_TYPE_SOFT_INTR);
3584                 break;
3585         default:
3586                 break;
3587         }
3588 }
3589
3590 /*
3591  * Failure to inject an interrupt should give us the information
3592  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3593  * when fetching the interrupt redirection bitmap in the real-mode
3594  * tss, this doesn't happen.  So we do it ourselves.
3595  */
3596 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3597 {
3598         vmx->rmode.irq.pending = 0;
3599         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3600                 return;
3601         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3602         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3603                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3604                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3605                 return;
3606         }
3607         vmx->idt_vectoring_info =
3608                 VECTORING_INFO_VALID_MASK
3609                 | INTR_TYPE_EXT_INTR
3610                 | vmx->rmode.irq.vector;
3611 }
3612
3613 #ifdef CONFIG_X86_64
3614 #define R "r"
3615 #define Q "q"
3616 #else
3617 #define R "e"
3618 #define Q "l"
3619 #endif
3620
3621 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3622 {
3623         struct vcpu_vmx *vmx = to_vmx(vcpu);
3624
3625         /* Record the guest's net vcpu time for enforced NMI injections. */
3626         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3627                 vmx->entry_time = ktime_get();
3628
3629         /* Don't enter VMX if guest state is invalid, let the exit handler
3630            start emulation until we arrive back to a valid state */
3631         if (vmx->emulation_required && emulate_invalid_guest_state)
3632                 return;
3633
3634         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3635                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3636         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3637                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3638
3639         /* When single-stepping over STI and MOV SS, we must clear the
3640          * corresponding interruptibility bits in the guest state. Otherwise
3641          * vmentry fails as it then expects bit 14 (BS) in pending debug
3642          * exceptions being set, but that's not correct for the guest debugging
3643          * case. */
3644         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3645                 vmx_set_interrupt_shadow(vcpu, 0);
3646
3647         /*
3648          * Loading guest fpu may have cleared host cr0.ts
3649          */
3650         vmcs_writel(HOST_CR0, read_cr0());
3651
3652         if (vcpu->arch.switch_db_regs)
3653                 set_debugreg(vcpu->arch.dr6, 6);
3654
3655         asm(
3656                 /* Store host registers */
3657                 "push %%"R"dx; push %%"R"bp;"
3658                 "push %%"R"cx \n\t"
3659                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3660                 "je 1f \n\t"
3661                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3662                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3663                 "1: \n\t"
3664                 /* Reload cr2 if changed */
3665                 "mov %c[cr2](%0), %%"R"ax \n\t"
3666                 "mov %%cr2, %%"R"dx \n\t"
3667                 "cmp %%"R"ax, %%"R"dx \n\t"
3668                 "je 2f \n\t"
3669                 "mov %%"R"ax, %%cr2 \n\t"
3670                 "2: \n\t"
3671                 /* Check if vmlaunch of vmresume is needed */
3672                 "cmpl $0, %c[launched](%0) \n\t"
3673                 /* Load guest registers.  Don't clobber flags. */
3674                 "mov %c[rax](%0), %%"R"ax \n\t"
3675                 "mov %c[rbx](%0), %%"R"bx \n\t"
3676                 "mov %c[rdx](%0), %%"R"dx \n\t"
3677                 "mov %c[rsi](%0), %%"R"si \n\t"
3678                 "mov %c[rdi](%0), %%"R"di \n\t"
3679                 "mov %c[rbp](%0), %%"R"bp \n\t"
3680 #ifdef CONFIG_X86_64
3681                 "mov %c[r8](%0),  %%r8  \n\t"
3682                 "mov %c[r9](%0),  %%r9  \n\t"
3683                 "mov %c[r10](%0), %%r10 \n\t"
3684                 "mov %c[r11](%0), %%r11 \n\t"
3685                 "mov %c[r12](%0), %%r12 \n\t"
3686                 "mov %c[r13](%0), %%r13 \n\t"
3687                 "mov %c[r14](%0), %%r14 \n\t"
3688                 "mov %c[r15](%0), %%r15 \n\t"
3689 #endif
3690                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3691
3692                 /* Enter guest mode */
3693                 "jne .Llaunched \n\t"
3694                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3695                 "jmp .Lkvm_vmx_return \n\t"
3696                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3697                 ".Lkvm_vmx_return: "
3698                 /* Save guest registers, load host registers, keep flags */
3699                 "xchg %0,     (%%"R"sp) \n\t"
3700                 "mov %%"R"ax, %c[rax](%0) \n\t"
3701                 "mov %%"R"bx, %c[rbx](%0) \n\t"
3702                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3703                 "mov %%"R"dx, %c[rdx](%0) \n\t"
3704                 "mov %%"R"si, %c[rsi](%0) \n\t"
3705                 "mov %%"R"di, %c[rdi](%0) \n\t"
3706                 "mov %%"R"bp, %c[rbp](%0) \n\t"
3707 #ifdef CONFIG_X86_64
3708                 "mov %%r8,  %c[r8](%0) \n\t"
3709                 "mov %%r9,  %c[r9](%0) \n\t"
3710                 "mov %%r10, %c[r10](%0) \n\t"
3711                 "mov %%r11, %c[r11](%0) \n\t"
3712                 "mov %%r12, %c[r12](%0) \n\t"
3713                 "mov %%r13, %c[r13](%0) \n\t"
3714                 "mov %%r14, %c[r14](%0) \n\t"
3715                 "mov %%r15, %c[r15](%0) \n\t"
3716 #endif
3717                 "mov %%cr2, %%"R"ax   \n\t"
3718                 "mov %%"R"ax, %c[cr2](%0) \n\t"
3719
3720                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
3721                 "setbe %c[fail](%0) \n\t"
3722               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3723                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3724                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3725                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3726                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3727                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3728                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3729                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3730                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3731                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3732                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3733 #ifdef CONFIG_X86_64
3734                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3735                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3736                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3737                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3738                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3739                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3740                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3741                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3742 #endif
3743                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3744               : "cc", "memory"
3745                 , R"bx", R"di", R"si"
3746 #ifdef CONFIG_X86_64
3747                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3748 #endif
3749               );
3750
3751         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3752                                   | (1 << VCPU_EXREG_PDPTR));
3753         vcpu->arch.regs_dirty = 0;
3754
3755         if (vcpu->arch.switch_db_regs)
3756                 get_debugreg(vcpu->arch.dr6, 6);
3757
3758         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3759         if (vmx->rmode.irq.pending)
3760                 fixup_rmode_irq(vmx);
3761
3762         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3763         vmx->launched = 1;
3764
3765         vmx_complete_interrupts(vmx);
3766 }
3767
3768 #undef R
3769 #undef Q
3770
3771 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3772 {
3773         struct vcpu_vmx *vmx = to_vmx(vcpu);
3774
3775         if (vmx->vmcs) {
3776                 vcpu_clear(vmx);
3777                 free_vmcs(vmx->vmcs);
3778                 vmx->vmcs = NULL;
3779         }
3780 }
3781
3782 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3783 {
3784         struct vcpu_vmx *vmx = to_vmx(vcpu);
3785
3786         spin_lock(&vmx_vpid_lock);
3787         if (vmx->vpid != 0)
3788                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3789         spin_unlock(&vmx_vpid_lock);
3790         vmx_free_vmcs(vcpu);
3791         kfree(vmx->guest_msrs);
3792         kvm_vcpu_uninit(vcpu);
3793         kmem_cache_free(kvm_vcpu_cache, vmx);
3794 }
3795
3796 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3797 {
3798         int err;
3799         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3800         int cpu;
3801
3802         if (!vmx)
3803                 return ERR_PTR(-ENOMEM);
3804
3805         allocate_vpid(vmx);
3806
3807         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3808         if (err)
3809                 goto free_vcpu;
3810
3811         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3812         if (!vmx->guest_msrs) {
3813                 err = -ENOMEM;
3814                 goto uninit_vcpu;
3815         }
3816
3817         vmx->vmcs = alloc_vmcs();
3818         if (!vmx->vmcs)
3819                 goto free_msrs;
3820
3821         vmcs_clear(vmx->vmcs);
3822
3823         cpu = get_cpu();
3824         vmx_vcpu_load(&vmx->vcpu, cpu);
3825         err = vmx_vcpu_setup(vmx);
3826         vmx_vcpu_put(&vmx->vcpu);
3827         put_cpu();
3828         if (err)
3829                 goto free_vmcs;
3830         if (vm_need_virtualize_apic_accesses(kvm))
3831                 if (alloc_apic_access_page(kvm) != 0)
3832                         goto free_vmcs;
3833
3834         if (enable_ept) {
3835                 if (!kvm->arch.ept_identity_map_addr)
3836                         kvm->arch.ept_identity_map_addr =
3837                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3838                 if (alloc_identity_pagetable(kvm) != 0)
3839                         goto free_vmcs;
3840         }
3841
3842         return &vmx->vcpu;
3843
3844 free_vmcs:
3845         free_vmcs(vmx->vmcs);
3846 free_msrs:
3847         kfree(vmx->guest_msrs);
3848 uninit_vcpu:
3849         kvm_vcpu_uninit(&vmx->vcpu);
3850 free_vcpu:
3851         kmem_cache_free(kvm_vcpu_cache, vmx);
3852         return ERR_PTR(err);
3853 }
3854
3855 static void __init vmx_check_processor_compat(void *rtn)
3856 {
3857         struct vmcs_config vmcs_conf;
3858
3859         *(int *)rtn = 0;
3860         if (setup_vmcs_config(&vmcs_conf) < 0)
3861                 *(int *)rtn = -EIO;
3862         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3863                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3864                                 smp_processor_id());
3865                 *(int *)rtn = -EIO;
3866         }
3867 }
3868
3869 static int get_ept_level(void)
3870 {
3871         return VMX_EPT_DEFAULT_GAW + 1;
3872 }
3873
3874 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3875 {
3876         u64 ret;
3877
3878         /* For VT-d and EPT combination
3879          * 1. MMIO: always map as UC
3880          * 2. EPT with VT-d:
3881          *   a. VT-d without snooping control feature: can't guarantee the
3882          *      result, try to trust guest.
3883          *   b. VT-d with snooping control feature: snooping control feature of
3884          *      VT-d engine can guarantee the cache correctness. Just set it
3885          *      to WB to keep consistent with host. So the same as item 3.
3886          * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3887          *    consistent with host MTRR
3888          */
3889         if (is_mmio)
3890                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
3891         else if (vcpu->kvm->arch.iommu_domain &&
3892                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3893                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3894                       VMX_EPT_MT_EPTE_SHIFT;
3895         else
3896                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3897                         | VMX_EPT_IGMT_BIT;
3898
3899         return ret;
3900 }
3901
3902 static const struct trace_print_flags vmx_exit_reasons_str[] = {
3903         { EXIT_REASON_EXCEPTION_NMI,           "exception" },
3904         { EXIT_REASON_EXTERNAL_INTERRUPT,      "ext_irq" },
3905         { EXIT_REASON_TRIPLE_FAULT,            "triple_fault" },
3906         { EXIT_REASON_NMI_WINDOW,              "nmi_window" },
3907         { EXIT_REASON_IO_INSTRUCTION,          "io_instruction" },
3908         { EXIT_REASON_CR_ACCESS,               "cr_access" },
3909         { EXIT_REASON_DR_ACCESS,               "dr_access" },
3910         { EXIT_REASON_CPUID,                   "cpuid" },
3911         { EXIT_REASON_MSR_READ,                "rdmsr" },
3912         { EXIT_REASON_MSR_WRITE,               "wrmsr" },
3913         { EXIT_REASON_PENDING_INTERRUPT,       "interrupt_window" },
3914         { EXIT_REASON_HLT,                     "halt" },
3915         { EXIT_REASON_INVLPG,                  "invlpg" },
3916         { EXIT_REASON_VMCALL,                  "hypercall" },
3917         { EXIT_REASON_TPR_BELOW_THRESHOLD,     "tpr_below_thres" },
3918         { EXIT_REASON_APIC_ACCESS,             "apic_access" },
3919         { EXIT_REASON_WBINVD,                  "wbinvd" },
3920         { EXIT_REASON_TASK_SWITCH,             "task_switch" },
3921         { EXIT_REASON_EPT_VIOLATION,           "ept_violation" },
3922         { -1, NULL }
3923 };
3924
3925 static bool vmx_gb_page_enable(void)
3926 {
3927         return false;
3928 }
3929
3930 static struct kvm_x86_ops vmx_x86_ops = {
3931         .cpu_has_kvm_support = cpu_has_kvm_support,
3932         .disabled_by_bios = vmx_disabled_by_bios,
3933         .hardware_setup = hardware_setup,
3934         .hardware_unsetup = hardware_unsetup,
3935         .check_processor_compatibility = vmx_check_processor_compat,
3936         .hardware_enable = hardware_enable,
3937         .hardware_disable = hardware_disable,
3938         .cpu_has_accelerated_tpr = report_flexpriority,
3939
3940         .vcpu_create = vmx_create_vcpu,
3941         .vcpu_free = vmx_free_vcpu,
3942         .vcpu_reset = vmx_vcpu_reset,
3943
3944         .prepare_guest_switch = vmx_save_host_state,
3945         .vcpu_load = vmx_vcpu_load,
3946         .vcpu_put = vmx_vcpu_put,
3947
3948         .set_guest_debug = set_guest_debug,
3949         .get_msr = vmx_get_msr,
3950         .set_msr = vmx_set_msr,
3951         .get_segment_base = vmx_get_segment_base,
3952         .get_segment = vmx_get_segment,
3953         .set_segment = vmx_set_segment,
3954         .get_cpl = vmx_get_cpl,
3955         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3956         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3957         .set_cr0 = vmx_set_cr0,
3958         .set_cr3 = vmx_set_cr3,
3959         .set_cr4 = vmx_set_cr4,
3960         .set_efer = vmx_set_efer,
3961         .get_idt = vmx_get_idt,
3962         .set_idt = vmx_set_idt,
3963         .get_gdt = vmx_get_gdt,
3964         .set_gdt = vmx_set_gdt,
3965         .cache_reg = vmx_cache_reg,
3966         .get_rflags = vmx_get_rflags,
3967         .set_rflags = vmx_set_rflags,
3968
3969         .tlb_flush = vmx_flush_tlb,
3970
3971         .run = vmx_vcpu_run,
3972         .handle_exit = vmx_handle_exit,
3973         .skip_emulated_instruction = skip_emulated_instruction,
3974         .set_interrupt_shadow = vmx_set_interrupt_shadow,
3975         .get_interrupt_shadow = vmx_get_interrupt_shadow,
3976         .patch_hypercall = vmx_patch_hypercall,
3977         .set_irq = vmx_inject_irq,
3978         .set_nmi = vmx_inject_nmi,
3979         .queue_exception = vmx_queue_exception,
3980         .interrupt_allowed = vmx_interrupt_allowed,
3981         .nmi_allowed = vmx_nmi_allowed,
3982         .enable_nmi_window = enable_nmi_window,
3983         .enable_irq_window = enable_irq_window,
3984         .update_cr8_intercept = update_cr8_intercept,
3985
3986         .set_tss_addr = vmx_set_tss_addr,
3987         .get_tdp_level = get_ept_level,
3988         .get_mt_mask = vmx_get_mt_mask,
3989
3990         .exit_reasons_str = vmx_exit_reasons_str,
3991         .gb_page_enable = vmx_gb_page_enable,
3992 };
3993
3994 static int __init vmx_init(void)
3995 {
3996         int r, i;
3997
3998         rdmsrl_safe(MSR_EFER, &host_efer);
3999
4000         for (i = 0; i < NR_VMX_MSR; ++i)
4001                 kvm_define_shared_msr(i, vmx_msr_index[i]);
4002
4003         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4004         if (!vmx_io_bitmap_a)
4005                 return -ENOMEM;
4006
4007         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4008         if (!vmx_io_bitmap_b) {
4009                 r = -ENOMEM;
4010                 goto out;
4011         }
4012
4013         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4014         if (!vmx_msr_bitmap_legacy) {
4015                 r = -ENOMEM;
4016                 goto out1;
4017         }
4018
4019         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4020         if (!vmx_msr_bitmap_longmode) {
4021                 r = -ENOMEM;
4022                 goto out2;
4023         }
4024
4025         /*
4026          * Allow direct access to the PC debug port (it is often used for I/O
4027          * delays, but the vmexits simply slow things down).
4028          */
4029         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4030         clear_bit(0x80, vmx_io_bitmap_a);
4031
4032         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4033
4034         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4035         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4036
4037         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4038
4039         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
4040         if (r)
4041                 goto out3;
4042
4043         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4044         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4045         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4046         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4047         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4048         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4049
4050         if (enable_ept) {
4051                 bypass_guest_pf = 0;
4052                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4053                         VMX_EPT_WRITABLE_MASK);
4054                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4055                                 VMX_EPT_EXECUTABLE_MASK);
4056                 kvm_enable_tdp();
4057         } else
4058                 kvm_disable_tdp();
4059
4060         if (bypass_guest_pf)
4061                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4062
4063         return 0;
4064
4065 out3:
4066         free_page((unsigned long)vmx_msr_bitmap_longmode);
4067 out2:
4068         free_page((unsigned long)vmx_msr_bitmap_legacy);
4069 out1:
4070         free_page((unsigned long)vmx_io_bitmap_b);
4071 out:
4072         free_page((unsigned long)vmx_io_bitmap_a);
4073         return r;
4074 }
4075
4076 static void __exit vmx_exit(void)
4077 {
4078         free_page((unsigned long)vmx_msr_bitmap_legacy);
4079         free_page((unsigned long)vmx_msr_bitmap_longmode);
4080         free_page((unsigned long)vmx_io_bitmap_b);
4081         free_page((unsigned long)vmx_io_bitmap_a);
4082
4083         kvm_exit();
4084 }
4085
4086 module_init(vmx_init)
4087 module_exit(vmx_exit)