SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/mm.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/ftrace_event.h>
  29 #include "kvm_cache_regs.h"
  30 #include "x86.h"
  31
  32 #include <asm/io.h>
  33 #include <asm/desc.h>
  34 #include <asm/vmx.h>
  35 #include <asm/virtext.h>
  36 #include <asm/mce.h>
  37
  38 #include "trace.h"
  39
  40 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  41
  42 MODULE_AUTHOR("Qumranet");
  43 MODULE_LICENSE("GPL");
  44
  45 static int __read_mostly bypass_guest_pf = 1;
  46 module_param(bypass_guest_pf, bool, S_IRUGO);
  47
  48 static int __read_mostly enable_vpid = 1;
  49 module_param_named(vpid, enable_vpid, bool, 0444);
  50
  51 static int __read_mostly flexpriority_enabled = 1;
  52 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  53
  54 static int __read_mostly enable_ept = 1;
  55 module_param_named(ept, enable_ept, bool, S_IRUGO);
  56
  57 static int __read_mostly enable_unrestricted_guest = 1;
  58 module_param_named(unrestricted_guest,
  59                         enable_unrestricted_guest, bool, S_IRUGO);
  60
  61 static int __read_mostly emulate_invalid_guest_state = 0;
  62 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  63
  64 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  65         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  66 #define KVM_GUEST_CR0_MASK                                              \
  67         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  68 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  69         (X86_CR0_WP | X86_CR0_NE | X86_CR0_TS | X86_CR0_MP)
  70 #define KVM_VM_CR0_ALWAYS_ON                                            \
  71         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  72 #define KVM_CR4_GUEST_OWNED_BITS                                      \
  73         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
  74          | X86_CR4_OSXMMEXCPT)
  75
  76 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
  77 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
  78
  79 /*
  80  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
  81  * ple_gap:    upper bound on the amount of time between two successive
  82  *             executions of PAUSE in a loop. Also indicate if ple enabled.
  83  *             According to test, this time is usually small than 41 cycles.
  84  * ple_window: upper bound on the amount of time a guest is allowed to execute
  85  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
  86  *             less than 2^12 cycles
  87  * Time is measured based on a counter that runs at the same rate as the TSC,
  88  * refer SDM volume 3b section 21.6.13 & 22.1.3.
  89  */
  90 #define KVM_VMX_DEFAULT_PLE_GAP    41
  91 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
  92 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
  93 module_param(ple_gap, int, S_IRUGO);
  94
  95 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
  96 module_param(ple_window, int, S_IRUGO);
  97
  98 struct vmcs {
  99         u32 revision_id;
 100         u32 abort;
 101         char data[0];
 102 };
 103
 104 struct shared_msr_entry {
 105         unsigned index;
 106         u64 data;
 107         u64 mask;
 108 };
 109
 110 struct vcpu_vmx {
 111         struct kvm_vcpu       vcpu;
 112         struct list_head      local_vcpus_link;
 113         unsigned long         host_rsp;
 114         int                   launched;
 115         u8                    fail;
 116         u32                   idt_vectoring_info;
 117         struct shared_msr_entry *guest_msrs;
 118         int                   nmsrs;
 119         int                   save_nmsrs;
 120 #ifdef CONFIG_X86_64
 121         u64                   msr_host_kernel_gs_base;
 122         u64                   msr_guest_kernel_gs_base;
 123 #endif
 124         struct vmcs          *vmcs;
 125         struct {
 126                 int           loaded;
 127                 u16           fs_sel, gs_sel, ldt_sel;
 128                 int           gs_ldt_reload_needed;
 129                 int           fs_reload_needed;
 130         } host_state;
 131         struct {
 132                 int vm86_active;
 133                 u8 save_iopl;
 134                 struct kvm_save_segment {
 135                         u16 selector;
 136                         unsigned long base;
 137                         u32 limit;
 138                         u32 ar;
 139                 } tr, es, ds, fs, gs;
 140                 struct {
 141                         bool pending;
 142                         u8 vector;
 143                         unsigned rip;
 144                 } irq;
 145         } rmode;
 146         int vpid;
 147         bool emulation_required;
 148
 149         /* Support for vnmi-less CPUs */
 150         int soft_vnmi_blocked;
 151         ktime_t entry_time;
 152         s64 vnmi_blocked_time;
 153         u32 exit_reason;
 154
 155         bool rdtscp_enabled;
 156 };
 157
 158 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 159 {
 160         return container_of(vcpu, struct vcpu_vmx, vcpu);
 161 }
 162
 163 static int init_rmode(struct kvm *kvm);
 164 static u64 construct_eptp(unsigned long root_hpa);
 165
 166 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 167 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 168 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 169
 170 static unsigned long *vmx_io_bitmap_a;
 171 static unsigned long *vmx_io_bitmap_b;
 172 static unsigned long *vmx_msr_bitmap_legacy;
 173 static unsigned long *vmx_msr_bitmap_longmode;
 174
 175 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 176 static DEFINE_SPINLOCK(vmx_vpid_lock);
 177
 178 static struct vmcs_config {
 179         int size;
 180         int order;
 181         u32 revision_id;
 182         u32 pin_based_exec_ctrl;
 183         u32 cpu_based_exec_ctrl;
 184         u32 cpu_based_2nd_exec_ctrl;
 185         u32 vmexit_ctrl;
 186         u32 vmentry_ctrl;
 187 } vmcs_config;
 188
 189 static struct vmx_capability {
 190         u32 ept;
 191         u32 vpid;
 192 } vmx_capability;
 193
 194 #define VMX_SEGMENT_FIELD(seg)                                  \
 195         [VCPU_SREG_##seg] = {                                   \
 196                 .selector = GUEST_##seg##_SELECTOR,             \
 197                 .base = GUEST_##seg##_BASE,                     \
 198                 .limit = GUEST_##seg##_LIMIT,                   \
 199                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 200         }
 201
 202 static struct kvm_vmx_segment_field {
 203         unsigned selector;
 204         unsigned base;
 205         unsigned limit;
 206         unsigned ar_bytes;
 207 } kvm_vmx_segment_fields[] = {
 208         VMX_SEGMENT_FIELD(CS),
 209         VMX_SEGMENT_FIELD(DS),
 210         VMX_SEGMENT_FIELD(ES),
 211         VMX_SEGMENT_FIELD(FS),
 212         VMX_SEGMENT_FIELD(GS),
 213         VMX_SEGMENT_FIELD(SS),
 214         VMX_SEGMENT_FIELD(TR),
 215         VMX_SEGMENT_FIELD(LDTR),
 216 };
 217
 218 static u64 host_efer;
 219
 220 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 221
 222 /*
 223  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 224  * away by decrementing the array size.
 225  */
 226 static const u32 vmx_msr_index[] = {
 227 #ifdef CONFIG_X86_64
 228         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 229 #endif
 230         MSR_EFER, MSR_TSC_AUX, MSR_K6_STAR,
 231 };
 232 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 233
 234 static inline int is_page_fault(u32 intr_info)
 235 {
 236         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 237                              INTR_INFO_VALID_MASK)) ==
 238                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 239 }
 240
 241 static inline int is_no_device(u32 intr_info)
 242 {
 243         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 244                              INTR_INFO_VALID_MASK)) ==
 245                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 246 }
 247
 248 static inline int is_invalid_opcode(u32 intr_info)
 249 {
 250         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 251                              INTR_INFO_VALID_MASK)) ==
 252                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 253 }
 254
 255 static inline int is_external_interrupt(u32 intr_info)
 256 {
 257         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 258                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 259 }
 260
 261 static inline int is_machine_check(u32 intr_info)
 262 {
 263         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 264                              INTR_INFO_VALID_MASK)) ==
 265                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 266 }
 267
 268 static inline int cpu_has_vmx_msr_bitmap(void)
 269 {
 270         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 271 }
 272
 273 static inline int cpu_has_vmx_tpr_shadow(void)
 274 {
 275         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 276 }
 277
 278 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 279 {
 280         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 281 }
 282
 283 static inline int cpu_has_secondary_exec_ctrls(void)
 284 {
 285         return vmcs_config.cpu_based_exec_ctrl &
 286                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 287 }
 288
 289 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 290 {
 291         return vmcs_config.cpu_based_2nd_exec_ctrl &
 292                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 293 }
 294
 295 static inline bool cpu_has_vmx_flexpriority(void)
 296 {
 297         return cpu_has_vmx_tpr_shadow() &&
 298                 cpu_has_vmx_virtualize_apic_accesses();
 299 }
 300
 301 static inline bool cpu_has_vmx_ept_execute_only(void)
 302 {
 303         return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
 304 }
 305
 306 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 307 {
 308         return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
 309 }
 310
 311 static inline bool cpu_has_vmx_eptp_writeback(void)
 312 {
 313         return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
 314 }
 315
 316 static inline bool cpu_has_vmx_ept_2m_page(void)
 317 {
 318         return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
 319 }
 320
 321 static inline bool cpu_has_vmx_ept_1g_page(void)
 322 {
 323         return !!(vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT);
 324 }
 325
 326 static inline int cpu_has_vmx_invept_individual_addr(void)
 327 {
 328         return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
 329 }
 330
 331 static inline int cpu_has_vmx_invept_context(void)
 332 {
 333         return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
 334 }
 335
 336 static inline int cpu_has_vmx_invept_global(void)
 337 {
 338         return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
 339 }
 340
 341 static inline int cpu_has_vmx_ept(void)
 342 {
 343         return vmcs_config.cpu_based_2nd_exec_ctrl &
 344                 SECONDARY_EXEC_ENABLE_EPT;
 345 }
 346
 347 static inline int cpu_has_vmx_unrestricted_guest(void)
 348 {
 349         return vmcs_config.cpu_based_2nd_exec_ctrl &
 350                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 351 }
 352
 353 static inline int cpu_has_vmx_ple(void)
 354 {
 355         return vmcs_config.cpu_based_2nd_exec_ctrl &
 356                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 357 }
 358
 359 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 360 {
 361         return flexpriority_enabled &&
 362                 (cpu_has_vmx_virtualize_apic_accesses()) &&
 363                 (irqchip_in_kernel(kvm));
 364 }
 365
 366 static inline int cpu_has_vmx_vpid(void)
 367 {
 368         return vmcs_config.cpu_based_2nd_exec_ctrl &
 369                 SECONDARY_EXEC_ENABLE_VPID;
 370 }
 371
 372 static inline int cpu_has_vmx_rdtscp(void)
 373 {
 374         return vmcs_config.cpu_based_2nd_exec_ctrl &
 375                 SECONDARY_EXEC_RDTSCP;
 376 }
 377
 378 static inline int cpu_has_virtual_nmis(void)
 379 {
 380         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 381 }
 382
 383 static inline bool report_flexpriority(void)
 384 {
 385         return flexpriority_enabled;
 386 }
 387
 388 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 389 {
 390         int i;
 391
 392         for (i = 0; i < vmx->nmsrs; ++i)
 393                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 394                         return i;
 395         return -1;
 396 }
 397
 398 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 399 {
 400     struct {
 401         u64 vpid : 16;
 402         u64 rsvd : 48;
 403         u64 gva;
 404     } operand = { vpid, 0, gva };
 405
 406     asm volatile (__ex(ASM_VMX_INVVPID)
 407                   /* CF==1 or ZF==1 --> rc = -1 */
 408                   "; ja 1f ; ud2 ; 1:"
 409                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 410 }
 411
 412 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 413 {
 414         struct {
 415                 u64 eptp, gpa;
 416         } operand = {eptp, gpa};
 417
 418         asm volatile (__ex(ASM_VMX_INVEPT)
 419                         /* CF==1 or ZF==1 --> rc = -1 */
 420                         "; ja 1f ; ud2 ; 1:\n"
 421                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 422 }
 423
 424 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 425 {
 426         int i;
 427
 428         i = __find_msr_index(vmx, msr);
 429         if (i >= 0)
 430                 return &vmx->guest_msrs[i];
 431         return NULL;
 432 }
 433
 434 static void vmcs_clear(struct vmcs *vmcs)
 435 {
 436         u64 phys_addr = __pa(vmcs);
 437         u8 error;
 438
 439         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 440                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 441                       : "cc", "memory");
 442         if (error)
 443                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 444                        vmcs, phys_addr);
 445 }
 446
 447 static void __vcpu_clear(void *arg)
 448 {
 449         struct vcpu_vmx *vmx = arg;
 450         int cpu = raw_smp_processor_id();
 451
 452         if (vmx->vcpu.cpu == cpu)
 453                 vmcs_clear(vmx->vmcs);
 454         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 455                 per_cpu(current_vmcs, cpu) = NULL;
 456         rdtscll(vmx->vcpu.arch.host_tsc);
 457         list_del(&vmx->local_vcpus_link);
 458         vmx->vcpu.cpu = -1;
 459         vmx->launched = 0;
 460 }
 461
 462 static void vcpu_clear(struct vcpu_vmx *vmx)
 463 {
 464         if (vmx->vcpu.cpu == -1)
 465                 return;
 466         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 467 }
 468
 469 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 470 {
 471         if (vmx->vpid == 0)
 472                 return;
 473
 474         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 475 }
 476
 477 static inline void ept_sync_global(void)
 478 {
 479         if (cpu_has_vmx_invept_global())
 480                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 481 }
 482
 483 static inline void ept_sync_context(u64 eptp)
 484 {
 485         if (enable_ept) {
 486                 if (cpu_has_vmx_invept_context())
 487                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 488                 else
 489                         ept_sync_global();
 490         }
 491 }
 492
 493 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 494 {
 495         if (enable_ept) {
 496                 if (cpu_has_vmx_invept_individual_addr())
 497                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 498                                         eptp, gpa);
 499                 else
 500                         ept_sync_context(eptp);
 501         }
 502 }
 503
 504 static unsigned long vmcs_readl(unsigned long field)
 505 {
 506         unsigned long value;
 507
 508         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 509                       : "=a"(value) : "d"(field) : "cc");
 510         return value;
 511 }
 512
 513 static u16 vmcs_read16(unsigned long field)
 514 {
 515         return vmcs_readl(field);
 516 }
 517
 518 static u32 vmcs_read32(unsigned long field)
 519 {
 520         return vmcs_readl(field);
 521 }
 522
 523 static u64 vmcs_read64(unsigned long field)
 524 {
 525 #ifdef CONFIG_X86_64
 526         return vmcs_readl(field);
 527 #else
 528         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 529 #endif
 530 }
 531
 532 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 533 {
 534         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 535                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 536         dump_stack();
 537 }
 538
 539 static void vmcs_writel(unsigned long field, unsigned long value)
 540 {
 541         u8 error;
 542
 543         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 544                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 545         if (unlikely(error))
 546                 vmwrite_error(field, value);
 547 }
 548
 549 static void vmcs_write16(unsigned long field, u16 value)
 550 {
 551         vmcs_writel(field, value);
 552 }
 553
 554 static void vmcs_write32(unsigned long field, u32 value)
 555 {
 556         vmcs_writel(field, value);
 557 }
 558
 559 static void vmcs_write64(unsigned long field, u64 value)
 560 {
 561         vmcs_writel(field, value);
 562 #ifndef CONFIG_X86_64
 563         asm volatile ("");
 564         vmcs_writel(field+1, value >> 32);
 565 #endif
 566 }
 567
 568 static void vmcs_clear_bits(unsigned long field, u32 mask)
 569 {
 570         vmcs_writel(field, vmcs_readl(field) & ~mask);
 571 }
 572
 573 static void vmcs_set_bits(unsigned long field, u32 mask)
 574 {
 575         vmcs_writel(field, vmcs_readl(field) | mask);
 576 }
 577
 578 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 579 {
 580         u32 eb;
 581
 582         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
 583         if (!vcpu->fpu_active)
 584                 eb |= 1u << NM_VECTOR;
 585         /*
 586          * Unconditionally intercept #DB so we can maintain dr6 without
 587          * reading it every exit.
 588          */
 589         eb |= 1u << DB_VECTOR;
 590         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
 591                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
 592                         eb |= 1u << BP_VECTOR;
 593         }
 594         if (to_vmx(vcpu)->rmode.vm86_active)
 595                 eb = ~0;
 596         if (enable_ept)
 597                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 598         vmcs_write32(EXCEPTION_BITMAP, eb);
 599 }
 600
 601 static void reload_tss(void)
 602 {
 603         /*
 604          * VT restores TR but not its size.  Useless.
 605          */
 606         struct descriptor_table gdt;
 607         struct desc_struct *descs;
 608
 609         kvm_get_gdt(&gdt);
 610         descs = (void *)gdt.base;
 611         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 612         load_TR_desc();
 613 }
 614
 615 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 616 {
 617         u64 guest_efer;
 618         u64 ignore_bits;
 619
 620         guest_efer = vmx->vcpu.arch.shadow_efer;
 621
 622         /*
 623          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 624          * outside long mode
 625          */
 626         ignore_bits = EFER_NX | EFER_SCE;
 627 #ifdef CONFIG_X86_64
 628         ignore_bits |= EFER_LMA | EFER_LME;
 629         /* SCE is meaningful only in long mode on Intel */
 630         if (guest_efer & EFER_LMA)
 631                 ignore_bits &= ~(u64)EFER_SCE;
 632 #endif
 633         guest_efer &= ~ignore_bits;
 634         guest_efer |= host_efer & ignore_bits;
 635         vmx->guest_msrs[efer_offset].data = guest_efer;
 636         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
 637         return true;
 638 }
 639
 640 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 641 {
 642         struct vcpu_vmx *vmx = to_vmx(vcpu);
 643         int i;
 644
 645         if (vmx->host_state.loaded)
 646                 return;
 647
 648         vmx->host_state.loaded = 1;
 649         /*
 650          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 651          * allow segment selectors with cpl > 0 or ti == 1.
 652          */
 653         vmx->host_state.ldt_sel = kvm_read_ldt();
 654         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 655         vmx->host_state.fs_sel = kvm_read_fs();
 656         if (!(vmx->host_state.fs_sel & 7)) {
 657                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 658                 vmx->host_state.fs_reload_needed = 0;
 659         } else {
 660                 vmcs_write16(HOST_FS_SELECTOR, 0);
 661                 vmx->host_state.fs_reload_needed = 1;
 662         }
 663         vmx->host_state.gs_sel = kvm_read_gs();
 664         if (!(vmx->host_state.gs_sel & 7))
 665                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 666         else {
 667                 vmcs_write16(HOST_GS_SELECTOR, 0);
 668                 vmx->host_state.gs_ldt_reload_needed = 1;
 669         }
 670
 671 #ifdef CONFIG_X86_64
 672         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 673         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 674 #else
 675         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 676         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 677 #endif
 678
 679 #ifdef CONFIG_X86_64
 680         if (is_long_mode(&vmx->vcpu)) {
 681                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 682                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 683         }
 684 #endif
 685         for (i = 0; i < vmx->save_nmsrs; ++i)
 686                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
 687                                    vmx->guest_msrs[i].data,
 688                                    vmx->guest_msrs[i].mask);
 689 }
 690
 691 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 692 {
 693         unsigned long flags;
 694
 695         if (!vmx->host_state.loaded)
 696                 return;
 697
 698         ++vmx->vcpu.stat.host_state_reload;
 699         vmx->host_state.loaded = 0;
 700         if (vmx->host_state.fs_reload_needed)
 701                 kvm_load_fs(vmx->host_state.fs_sel);
 702         if (vmx->host_state.gs_ldt_reload_needed) {
 703                 kvm_load_ldt(vmx->host_state.ldt_sel);
 704                 /*
 705                  * If we have to reload gs, we must take care to
 706                  * preserve our gs base.
 707                  */
 708                 local_irq_save(flags);
 709                 kvm_load_gs(vmx->host_state.gs_sel);
 710 #ifdef CONFIG_X86_64
 711                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 712 #endif
 713                 local_irq_restore(flags);
 714         }
 715         reload_tss();
 716 #ifdef CONFIG_X86_64
 717         if (is_long_mode(&vmx->vcpu)) {
 718                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 719                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 720         }
 721 #endif
 722 }
 723
 724 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 725 {
 726         preempt_disable();
 727         __vmx_load_host_state(vmx);
 728         preempt_enable();
 729 }
 730
 731 /*
 732  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 733  * vcpu mutex is already taken.
 734  */
 735 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 736 {
 737         struct vcpu_vmx *vmx = to_vmx(vcpu);
 738         u64 phys_addr = __pa(vmx->vmcs);
 739         u64 tsc_this, delta, new_offset;
 740
 741         if (vcpu->cpu != cpu) {
 742                 vcpu_clear(vmx);
 743                 kvm_migrate_timers(vcpu);
 744                 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
 745                 local_irq_disable();
 746                 list_add(&vmx->local_vcpus_link,
 747                          &per_cpu(vcpus_on_cpu, cpu));
 748                 local_irq_enable();
 749         }
 750
 751         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 752                 u8 error;
 753
 754                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 755                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 756                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 757                               : "cc");
 758                 if (error)
 759                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 760                                vmx->vmcs, phys_addr);
 761         }
 762
 763         if (vcpu->cpu != cpu) {
 764                 struct descriptor_table dt;
 765                 unsigned long sysenter_esp;
 766
 767                 vcpu->cpu = cpu;
 768                 /*
 769                  * Linux uses per-cpu TSS and GDT, so set these when switching
 770                  * processors.
 771                  */
 772                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 773                 kvm_get_gdt(&dt);
 774                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 775
 776                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 777                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 778
 779                 /*
 780                  * Make sure the time stamp counter is monotonous.
 781                  */
 782                 rdtscll(tsc_this);
 783                 if (tsc_this < vcpu->arch.host_tsc) {
 784                         delta = vcpu->arch.host_tsc - tsc_this;
 785                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 786                         vmcs_write64(TSC_OFFSET, new_offset);
 787                 }
 788         }
 789 }
 790
 791 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 792 {
 793         __vmx_load_host_state(to_vmx(vcpu));
 794 }
 795
 796 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 797 {
 798         if (vcpu->fpu_active)
 799                 return;
 800         vcpu->fpu_active = 1;
 801         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 802         if (vcpu->arch.cr0 & X86_CR0_TS)
 803                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 804         update_exception_bitmap(vcpu);
 805 }
 806
 807 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 808 {
 809         if (!vcpu->fpu_active)
 810                 return;
 811         vcpu->fpu_active = 0;
 812         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 813         update_exception_bitmap(vcpu);
 814 }
 815
 816 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 817 {
 818         unsigned long rflags;
 819
 820         rflags = vmcs_readl(GUEST_RFLAGS);
 821         if (to_vmx(vcpu)->rmode.vm86_active)
 822                 rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
 823         return rflags;
 824 }
 825
 826 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 827 {
 828         if (to_vmx(vcpu)->rmode.vm86_active)
 829                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 830         vmcs_writel(GUEST_RFLAGS, rflags);
 831 }
 832
 833 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 834 {
 835         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 836         int ret = 0;
 837
 838         if (interruptibility & GUEST_INTR_STATE_STI)
 839                 ret |= X86_SHADOW_INT_STI;
 840         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
 841                 ret |= X86_SHADOW_INT_MOV_SS;
 842
 843         return ret & mask;
 844 }
 845
 846 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 847 {
 848         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 849         u32 interruptibility = interruptibility_old;
 850
 851         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
 852
 853         if (mask & X86_SHADOW_INT_MOV_SS)
 854                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
 855         if (mask & X86_SHADOW_INT_STI)
 856                 interruptibility |= GUEST_INTR_STATE_STI;
 857
 858         if ((interruptibility != interruptibility_old))
 859                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
 860 }
 861
 862 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 863 {
 864         unsigned long rip;
 865
 866         rip = kvm_rip_read(vcpu);
 867         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 868         kvm_rip_write(vcpu, rip);
 869
 870         /* skipping an emulated instruction also counts */
 871         vmx_set_interrupt_shadow(vcpu, 0);
 872 }
 873
 874 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 875                                 bool has_error_code, u32 error_code)
 876 {
 877         struct vcpu_vmx *vmx = to_vmx(vcpu);
 878         u32 intr_info = nr | INTR_INFO_VALID_MASK;
 879
 880         if (has_error_code) {
 881                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 882                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
 883         }
 884
 885         if (vmx->rmode.vm86_active) {
 886                 vmx->rmode.irq.pending = true;
 887                 vmx->rmode.irq.vector = nr;
 888                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
 889                 if (kvm_exception_is_soft(nr))
 890                         vmx->rmode.irq.rip +=
 891                                 vmx->vcpu.arch.event_exit_inst_len;
 892                 intr_info |= INTR_TYPE_SOFT_INTR;
 893                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 894                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
 895                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
 896                 return;
 897         }
 898
 899         if (kvm_exception_is_soft(nr)) {
 900                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
 901                              vmx->vcpu.arch.event_exit_inst_len);
 902                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
 903         } else
 904                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
 905
 906         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 907 }
 908
 909 static bool vmx_rdtscp_supported(void)
 910 {
 911         return cpu_has_vmx_rdtscp();
 912 }
 913
 914 /*
 915  * Swap MSR entry in host/guest MSR entry array.
 916  */
 917 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 918 {
 919         struct shared_msr_entry tmp;
 920
 921         tmp = vmx->guest_msrs[to];
 922         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 923         vmx->guest_msrs[from] = tmp;
 924 }
 925
 926 /*
 927  * Set up the vmcs to automatically save and restore system
 928  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 929  * mode, as fiddling with msrs is very expensive.
 930  */
 931 static void setup_msrs(struct vcpu_vmx *vmx)
 932 {
 933         int save_nmsrs, index;
 934         unsigned long *msr_bitmap;
 935
 936         vmx_load_host_state(vmx);
 937         save_nmsrs = 0;
 938 #ifdef CONFIG_X86_64
 939         if (is_long_mode(&vmx->vcpu)) {
 940                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 941                 if (index >= 0)
 942                         move_msr_up(vmx, index, save_nmsrs++);
 943                 index = __find_msr_index(vmx, MSR_LSTAR);
 944                 if (index >= 0)
 945                         move_msr_up(vmx, index, save_nmsrs++);
 946                 index = __find_msr_index(vmx, MSR_CSTAR);
 947                 if (index >= 0)
 948                         move_msr_up(vmx, index, save_nmsrs++);
 949                 index = __find_msr_index(vmx, MSR_TSC_AUX);
 950                 if (index >= 0 && vmx->rdtscp_enabled)
 951                         move_msr_up(vmx, index, save_nmsrs++);
 952                 /*
 953                  * MSR_K6_STAR is only needed on long mode guests, and only
 954                  * if efer.sce is enabled.
 955                  */
 956                 index = __find_msr_index(vmx, MSR_K6_STAR);
 957                 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
 958                         move_msr_up(vmx, index, save_nmsrs++);
 959         }
 960 #endif
 961         index = __find_msr_index(vmx, MSR_EFER);
 962         if (index >= 0 && update_transition_efer(vmx, index))
 963                 move_msr_up(vmx, index, save_nmsrs++);
 964
 965         vmx->save_nmsrs = save_nmsrs;
 966
 967         if (cpu_has_vmx_msr_bitmap()) {
 968                 if (is_long_mode(&vmx->vcpu))
 969                         msr_bitmap = vmx_msr_bitmap_longmode;
 970                 else
 971                         msr_bitmap = vmx_msr_bitmap_legacy;
 972
 973                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
 974         }
 975 }
 976
 977 /*
 978  * reads and returns guest's timestamp counter "register"
 979  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 980  */
 981 static u64 guest_read_tsc(void)
 982 {
 983         u64 host_tsc, tsc_offset;
 984
 985         rdtscll(host_tsc);
 986         tsc_offset = vmcs_read64(TSC_OFFSET);
 987         return host_tsc + tsc_offset;
 988 }
 989
 990 /*
 991  * writes 'guest_tsc' into guest's timestamp counter "register"
 992  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 993  */
 994 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
 995 {
 996         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 997 }
 998
 999 /*
1000  * Reads an msr value (of 'msr_index') into 'pdata'.
1001  * Returns 0 on success, non-0 otherwise.
1002  * Assumes vcpu_load() was already called.
1003  */
1004 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1005 {
1006         u64 data;
1007         struct shared_msr_entry *msr;
1008
1009         if (!pdata) {
1010                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1011                 return -EINVAL;
1012         }
1013
1014         switch (msr_index) {
1015 #ifdef CONFIG_X86_64
1016         case MSR_FS_BASE:
1017                 data = vmcs_readl(GUEST_FS_BASE);
1018                 break;
1019         case MSR_GS_BASE:
1020                 data = vmcs_readl(GUEST_GS_BASE);
1021                 break;
1022         case MSR_KERNEL_GS_BASE:
1023                 vmx_load_host_state(to_vmx(vcpu));
1024                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1025                 break;
1026 #endif
1027         case MSR_EFER:
1028                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1029         case MSR_IA32_TSC:
1030                 data = guest_read_tsc();
1031                 break;
1032         case MSR_IA32_SYSENTER_CS:
1033                 data = vmcs_read32(GUEST_SYSENTER_CS);
1034                 break;
1035         case MSR_IA32_SYSENTER_EIP:
1036                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1037                 break;
1038         case MSR_IA32_SYSENTER_ESP:
1039                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1040                 break;
1041         case MSR_TSC_AUX:
1042                 if (!to_vmx(vcpu)->rdtscp_enabled)
1043                         return 1;
1044                 /* Otherwise falls through */
1045         default:
1046                 vmx_load_host_state(to_vmx(vcpu));
1047                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1048                 if (msr) {
1049                         vmx_load_host_state(to_vmx(vcpu));
1050                         data = msr->data;
1051                         break;
1052                 }
1053                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1054         }
1055
1056         *pdata = data;
1057         return 0;
1058 }
1059
1060 /*
1061  * Writes msr value into into the appropriate "register".
1062  * Returns 0 on success, non-0 otherwise.
1063  * Assumes vcpu_load() was already called.
1064  */
1065 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1066 {
1067         struct vcpu_vmx *vmx = to_vmx(vcpu);
1068         struct shared_msr_entry *msr;
1069         u64 host_tsc;
1070         int ret = 0;
1071
1072         switch (msr_index) {
1073         case MSR_EFER:
1074                 vmx_load_host_state(vmx);
1075                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1076                 break;
1077 #ifdef CONFIG_X86_64
1078         case MSR_FS_BASE:
1079                 vmcs_writel(GUEST_FS_BASE, data);
1080                 break;
1081         case MSR_GS_BASE:
1082                 vmcs_writel(GUEST_GS_BASE, data);
1083                 break;
1084         case MSR_KERNEL_GS_BASE:
1085                 vmx_load_host_state(vmx);
1086                 vmx->msr_guest_kernel_gs_base = data;
1087                 break;
1088 #endif
1089         case MSR_IA32_SYSENTER_CS:
1090                 vmcs_write32(GUEST_SYSENTER_CS, data);
1091                 break;
1092         case MSR_IA32_SYSENTER_EIP:
1093                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1094                 break;
1095         case MSR_IA32_SYSENTER_ESP:
1096                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1097                 break;
1098         case MSR_IA32_TSC:
1099                 rdtscll(host_tsc);
1100                 guest_write_tsc(data, host_tsc);
1101                 break;
1102         case MSR_IA32_CR_PAT:
1103                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1104                         vmcs_write64(GUEST_IA32_PAT, data);
1105                         vcpu->arch.pat = data;
1106                         break;
1107                 }
1108                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1109                 break;
1110         case MSR_TSC_AUX:
1111                 if (!vmx->rdtscp_enabled)
1112                         return 1;
1113                 /* Check reserved bit, higher 32 bits should be zero */
1114                 if ((data >> 32) != 0)
1115                         return 1;
1116                 /* Otherwise falls through */
1117         default:
1118                 msr = find_msr_entry(vmx, msr_index);
1119                 if (msr) {
1120                         vmx_load_host_state(vmx);
1121                         msr->data = data;
1122                         break;
1123                 }
1124                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1125         }
1126
1127         return ret;
1128 }
1129
1130 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1131 {
1132         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1133         switch (reg) {
1134         case VCPU_REGS_RSP:
1135                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1136                 break;
1137         case VCPU_REGS_RIP:
1138                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1139                 break;
1140         case VCPU_EXREG_PDPTR:
1141                 if (enable_ept)
1142                         ept_save_pdptrs(vcpu);
1143                 break;
1144         default:
1145                 break;
1146         }
1147 }
1148
1149 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1150 {
1151         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1152                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1153         else
1154                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1155
1156         update_exception_bitmap(vcpu);
1157 }
1158
1159 static __init int cpu_has_kvm_support(void)
1160 {
1161         return cpu_has_vmx();
1162 }
1163
1164 static __init int vmx_disabled_by_bios(void)
1165 {
1166         u64 msr;
1167
1168         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1169         return (msr & (FEATURE_CONTROL_LOCKED |
1170                        FEATURE_CONTROL_VMXON_ENABLED))
1171             == FEATURE_CONTROL_LOCKED;
1172         /* locked but not enabled */
1173 }
1174
1175 static int hardware_enable(void *garbage)
1176 {
1177         int cpu = raw_smp_processor_id();
1178         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1179         u64 old;
1180
1181         if (read_cr4() & X86_CR4_VMXE)
1182                 return -EBUSY;
1183
1184         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1185         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1186         if ((old & (FEATURE_CONTROL_LOCKED |
1187                     FEATURE_CONTROL_VMXON_ENABLED))
1188             != (FEATURE_CONTROL_LOCKED |
1189                 FEATURE_CONTROL_VMXON_ENABLED))
1190                 /* enable and lock */
1191                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1192                        FEATURE_CONTROL_LOCKED |
1193                        FEATURE_CONTROL_VMXON_ENABLED);
1194         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1195         asm volatile (ASM_VMX_VMXON_RAX
1196                       : : "a"(&phys_addr), "m"(phys_addr)
1197                       : "memory", "cc");
1198
1199         ept_sync_global();
1200
1201         return 0;
1202 }
1203
1204 static void vmclear_local_vcpus(void)
1205 {
1206         int cpu = raw_smp_processor_id();
1207         struct vcpu_vmx *vmx, *n;
1208
1209         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1210                                  local_vcpus_link)
1211                 __vcpu_clear(vmx);
1212 }
1213
1214
1215 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1216  * tricks.
1217  */
1218 static void kvm_cpu_vmxoff(void)
1219 {
1220         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1221         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1222 }
1223
1224 static void hardware_disable(void *garbage)
1225 {
1226         vmclear_local_vcpus();
1227         kvm_cpu_vmxoff();
1228 }
1229
1230 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1231                                       u32 msr, u32 *result)
1232 {
1233         u32 vmx_msr_low, vmx_msr_high;
1234         u32 ctl = ctl_min | ctl_opt;
1235
1236         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1237
1238         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1239         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1240
1241         /* Ensure minimum (required) set of control bits are supported. */
1242         if (ctl_min & ~ctl)
1243                 return -EIO;
1244
1245         *result = ctl;
1246         return 0;
1247 }
1248
1249 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1250 {
1251         u32 vmx_msr_low, vmx_msr_high;
1252         u32 min, opt, min2, opt2;
1253         u32 _pin_based_exec_control = 0;
1254         u32 _cpu_based_exec_control = 0;
1255         u32 _cpu_based_2nd_exec_control = 0;
1256         u32 _vmexit_control = 0;
1257         u32 _vmentry_control = 0;
1258
1259         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1260         opt = PIN_BASED_VIRTUAL_NMIS;
1261         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1262                                 &_pin_based_exec_control) < 0)
1263                 return -EIO;
1264
1265         min = CPU_BASED_HLT_EXITING |
1266 #ifdef CONFIG_X86_64
1267               CPU_BASED_CR8_LOAD_EXITING |
1268               CPU_BASED_CR8_STORE_EXITING |
1269 #endif
1270               CPU_BASED_CR3_LOAD_EXITING |
1271               CPU_BASED_CR3_STORE_EXITING |
1272               CPU_BASED_USE_IO_BITMAPS |
1273               CPU_BASED_MOV_DR_EXITING |
1274               CPU_BASED_USE_TSC_OFFSETING |
1275               CPU_BASED_MWAIT_EXITING |
1276               CPU_BASED_MONITOR_EXITING |
1277               CPU_BASED_INVLPG_EXITING;
1278         opt = CPU_BASED_TPR_SHADOW |
1279               CPU_BASED_USE_MSR_BITMAPS |
1280               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1281         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1282                                 &_cpu_based_exec_control) < 0)
1283                 return -EIO;
1284 #ifdef CONFIG_X86_64
1285         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1286                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1287                                            ~CPU_BASED_CR8_STORE_EXITING;
1288 #endif
1289         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1290                 min2 = 0;
1291                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1292                         SECONDARY_EXEC_WBINVD_EXITING |
1293                         SECONDARY_EXEC_ENABLE_VPID |
1294                         SECONDARY_EXEC_ENABLE_EPT |
1295                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
1296                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1297                         SECONDARY_EXEC_RDTSCP;
1298                 if (adjust_vmx_controls(min2, opt2,
1299                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1300                                         &_cpu_based_2nd_exec_control) < 0)
1301                         return -EIO;
1302         }
1303 #ifndef CONFIG_X86_64
1304         if (!(_cpu_based_2nd_exec_control &
1305                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1306                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1307 #endif
1308         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1309                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1310                    enabled */
1311                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1312                                              CPU_BASED_CR3_STORE_EXITING |
1313                                              CPU_BASED_INVLPG_EXITING);
1314                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1315                       vmx_capability.ept, vmx_capability.vpid);
1316         }
1317
1318         min = 0;
1319 #ifdef CONFIG_X86_64
1320         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1321 #endif
1322         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1323         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1324                                 &_vmexit_control) < 0)
1325                 return -EIO;
1326
1327         min = 0;
1328         opt = VM_ENTRY_LOAD_IA32_PAT;
1329         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1330                                 &_vmentry_control) < 0)
1331                 return -EIO;
1332
1333         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1334
1335         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1336         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1337                 return -EIO;
1338
1339 #ifdef CONFIG_X86_64
1340         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1341         if (vmx_msr_high & (1u<<16))
1342                 return -EIO;
1343 #endif
1344
1345         /* Require Write-Back (WB) memory type for VMCS accesses. */
1346         if (((vmx_msr_high >> 18) & 15) != 6)
1347                 return -EIO;
1348
1349         vmcs_conf->size = vmx_msr_high & 0x1fff;
1350         vmcs_conf->order = get_order(vmcs_config.size);
1351         vmcs_conf->revision_id = vmx_msr_low;
1352
1353         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1354         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1355         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1356         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1357         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1358
1359         return 0;
1360 }
1361
1362 static struct vmcs *alloc_vmcs_cpu(int cpu)
1363 {
1364         int node = cpu_to_node(cpu);
1365         struct page *pages;
1366         struct vmcs *vmcs;
1367
1368         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1369         if (!pages)
1370                 return NULL;
1371         vmcs = page_address(pages);
1372         memset(vmcs, 0, vmcs_config.size);
1373         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1374         return vmcs;
1375 }
1376
1377 static struct vmcs *alloc_vmcs(void)
1378 {
1379         return alloc_vmcs_cpu(raw_smp_processor_id());
1380 }
1381
1382 static void free_vmcs(struct vmcs *vmcs)
1383 {
1384         free_pages((unsigned long)vmcs, vmcs_config.order);
1385 }
1386
1387 static void free_kvm_area(void)
1388 {
1389         int cpu;
1390
1391         for_each_possible_cpu(cpu) {
1392                 free_vmcs(per_cpu(vmxarea, cpu));
1393                 per_cpu(vmxarea, cpu) = NULL;
1394         }
1395 }
1396
1397 static __init int alloc_kvm_area(void)
1398 {
1399         int cpu;
1400
1401         for_each_possible_cpu(cpu) {
1402                 struct vmcs *vmcs;
1403
1404                 vmcs = alloc_vmcs_cpu(cpu);
1405                 if (!vmcs) {
1406                         free_kvm_area();
1407                         return -ENOMEM;
1408                 }
1409
1410                 per_cpu(vmxarea, cpu) = vmcs;
1411         }
1412         return 0;
1413 }
1414
1415 static __init int hardware_setup(void)
1416 {
1417         if (setup_vmcs_config(&vmcs_config) < 0)
1418                 return -EIO;
1419
1420         if (boot_cpu_has(X86_FEATURE_NX))
1421                 kvm_enable_efer_bits(EFER_NX);
1422
1423         if (!cpu_has_vmx_vpid())
1424                 enable_vpid = 0;
1425
1426         if (!cpu_has_vmx_ept()) {
1427                 enable_ept = 0;
1428                 enable_unrestricted_guest = 0;
1429         }
1430
1431         if (!cpu_has_vmx_unrestricted_guest())
1432                 enable_unrestricted_guest = 0;
1433
1434         if (!cpu_has_vmx_flexpriority())
1435                 flexpriority_enabled = 0;
1436
1437         if (!cpu_has_vmx_tpr_shadow())
1438                 kvm_x86_ops->update_cr8_intercept = NULL;
1439
1440         if (enable_ept && !cpu_has_vmx_ept_2m_page())
1441                 kvm_disable_largepages();
1442
1443         if (!cpu_has_vmx_ple())
1444                 ple_gap = 0;
1445
1446         return alloc_kvm_area();
1447 }
1448
1449 static __exit void hardware_unsetup(void)
1450 {
1451         free_kvm_area();
1452 }
1453
1454 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1455 {
1456         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1457
1458         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1459                 vmcs_write16(sf->selector, save->selector);
1460                 vmcs_writel(sf->base, save->base);
1461                 vmcs_write32(sf->limit, save->limit);
1462                 vmcs_write32(sf->ar_bytes, save->ar);
1463         } else {
1464                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1465                         << AR_DPL_SHIFT;
1466                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1467         }
1468 }
1469
1470 static void enter_pmode(struct kvm_vcpu *vcpu)
1471 {
1472         unsigned long flags;
1473         struct vcpu_vmx *vmx = to_vmx(vcpu);
1474
1475         vmx->emulation_required = 1;
1476         vmx->rmode.vm86_active = 0;
1477
1478         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1479         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1480         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1481
1482         flags = vmcs_readl(GUEST_RFLAGS);
1483         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1484         flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
1485         vmcs_writel(GUEST_RFLAGS, flags);
1486
1487         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1488                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1489
1490         update_exception_bitmap(vcpu);
1491
1492         if (emulate_invalid_guest_state)
1493                 return;
1494
1495         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1496         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1497         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1498         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1499
1500         vmcs_write16(GUEST_SS_SELECTOR, 0);
1501         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1502
1503         vmcs_write16(GUEST_CS_SELECTOR,
1504                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1505         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1506 }
1507
1508 static gva_t rmode_tss_base(struct kvm *kvm)
1509 {
1510         if (!kvm->arch.tss_addr) {
1511                 struct kvm_memslots *slots;
1512                 gfn_t base_gfn;
1513
1514                 slots = rcu_dereference(kvm->memslots);
1515                 base_gfn = kvm->memslots->memslots[0].base_gfn +
1516                                  kvm->memslots->memslots[0].npages - 3;
1517                 return base_gfn << PAGE_SHIFT;
1518         }
1519         return kvm->arch.tss_addr;
1520 }
1521
1522 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1523 {
1524         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1525
1526         save->selector = vmcs_read16(sf->selector);
1527         save->base = vmcs_readl(sf->base);
1528         save->limit = vmcs_read32(sf->limit);
1529         save->ar = vmcs_read32(sf->ar_bytes);
1530         vmcs_write16(sf->selector, save->base >> 4);
1531         vmcs_write32(sf->base, save->base & 0xfffff);
1532         vmcs_write32(sf->limit, 0xffff);
1533         vmcs_write32(sf->ar_bytes, 0xf3);
1534 }
1535
1536 static void enter_rmode(struct kvm_vcpu *vcpu)
1537 {
1538         unsigned long flags;
1539         struct vcpu_vmx *vmx = to_vmx(vcpu);
1540
1541         if (enable_unrestricted_guest)
1542                 return;
1543
1544         vmx->emulation_required = 1;
1545         vmx->rmode.vm86_active = 1;
1546
1547         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1548         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1549
1550         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1551         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1552
1553         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1554         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1555
1556         flags = vmcs_readl(GUEST_RFLAGS);
1557         vmx->rmode.save_iopl
1558                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1559
1560         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1561
1562         vmcs_writel(GUEST_RFLAGS, flags);
1563         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1564         update_exception_bitmap(vcpu);
1565
1566         if (emulate_invalid_guest_state)
1567                 goto continue_rmode;
1568
1569         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1570         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1571         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1572
1573         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1574         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1575         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1576                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1577         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1578
1579         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1580         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1581         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1582         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1583
1584 continue_rmode:
1585         kvm_mmu_reset_context(vcpu);
1586         init_rmode(vcpu->kvm);
1587 }
1588
1589 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1590 {
1591         struct vcpu_vmx *vmx = to_vmx(vcpu);
1592         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1593
1594         if (!msr)
1595                 return;
1596
1597         /*
1598          * Force kernel_gs_base reloading before EFER changes, as control
1599          * of this msr depends on is_long_mode().
1600          */
1601         vmx_load_host_state(to_vmx(vcpu));
1602         vcpu->arch.shadow_efer = efer;
1603         if (!msr)
1604                 return;
1605         if (efer & EFER_LMA) {
1606                 vmcs_write32(VM_ENTRY_CONTROLS,
1607                              vmcs_read32(VM_ENTRY_CONTROLS) |
1608                              VM_ENTRY_IA32E_MODE);
1609                 msr->data = efer;
1610         } else {
1611                 vmcs_write32(VM_ENTRY_CONTROLS,
1612                              vmcs_read32(VM_ENTRY_CONTROLS) &
1613                              ~VM_ENTRY_IA32E_MODE);
1614
1615                 msr->data = efer & ~EFER_LME;
1616         }
1617         setup_msrs(vmx);
1618 }
1619
1620 #ifdef CONFIG_X86_64
1621
1622 static void enter_lmode(struct kvm_vcpu *vcpu)
1623 {
1624         u32 guest_tr_ar;
1625
1626         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1627         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1628                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1629                        __func__);
1630                 vmcs_write32(GUEST_TR_AR_BYTES,
1631                              (guest_tr_ar & ~AR_TYPE_MASK)
1632                              | AR_TYPE_BUSY_64_TSS);
1633         }
1634         vcpu->arch.shadow_efer |= EFER_LMA;
1635         vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
1636 }
1637
1638 static void exit_lmode(struct kvm_vcpu *vcpu)
1639 {
1640         vcpu->arch.shadow_efer &= ~EFER_LMA;
1641
1642         vmcs_write32(VM_ENTRY_CONTROLS,
1643                      vmcs_read32(VM_ENTRY_CONTROLS)
1644                      & ~VM_ENTRY_IA32E_MODE);
1645 }
1646
1647 #endif
1648
1649 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1650 {
1651         vpid_sync_vcpu_all(to_vmx(vcpu));
1652         if (enable_ept)
1653                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1654 }
1655
1656 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1657 {
1658         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1659
1660         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1661         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1662 }
1663
1664 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1665 {
1666         if (!test_bit(VCPU_EXREG_PDPTR,
1667                       (unsigned long *)&vcpu->arch.regs_dirty))
1668                 return;
1669
1670         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1671                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1672                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1673                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1674                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1675         }
1676 }
1677
1678 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1679 {
1680         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1681                 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1682                 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1683                 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1684                 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1685         }
1686
1687         __set_bit(VCPU_EXREG_PDPTR,
1688                   (unsigned long *)&vcpu->arch.regs_avail);
1689         __set_bit(VCPU_EXREG_PDPTR,
1690                   (unsigned long *)&vcpu->arch.regs_dirty);
1691 }
1692
1693 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1694
1695 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1696                                         unsigned long cr0,
1697                                         struct kvm_vcpu *vcpu)
1698 {
1699         if (!(cr0 & X86_CR0_PG)) {
1700                 /* From paging/starting to nonpaging */
1701                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1702                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1703                              (CPU_BASED_CR3_LOAD_EXITING |
1704                               CPU_BASED_CR3_STORE_EXITING));
1705                 vcpu->arch.cr0 = cr0;
1706                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1707         } else if (!is_paging(vcpu)) {
1708                 /* From nonpaging to paging */
1709                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1710                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1711                              ~(CPU_BASED_CR3_LOAD_EXITING |
1712                                CPU_BASED_CR3_STORE_EXITING));
1713                 vcpu->arch.cr0 = cr0;
1714                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1715         }
1716
1717         if (!(cr0 & X86_CR0_WP))
1718                 *hw_cr0 &= ~X86_CR0_WP;
1719 }
1720
1721 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1722 {
1723         struct vcpu_vmx *vmx = to_vmx(vcpu);
1724         unsigned long hw_cr0;
1725
1726         if (enable_unrestricted_guest)
1727                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1728                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1729         else
1730                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1731
1732         vmx_fpu_deactivate(vcpu);
1733
1734         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1735                 enter_pmode(vcpu);
1736
1737         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1738                 enter_rmode(vcpu);
1739
1740 #ifdef CONFIG_X86_64
1741         if (vcpu->arch.shadow_efer & EFER_LME) {
1742                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1743                         enter_lmode(vcpu);
1744                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1745                         exit_lmode(vcpu);
1746         }
1747 #endif
1748
1749         if (enable_ept)
1750                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1751
1752         vmcs_writel(CR0_READ_SHADOW, cr0);
1753         vmcs_writel(GUEST_CR0, hw_cr0);
1754         vcpu->arch.cr0 = cr0;
1755
1756         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1757                 vmx_fpu_activate(vcpu);
1758 }
1759
1760 static u64 construct_eptp(unsigned long root_hpa)
1761 {
1762         u64 eptp;
1763
1764         /* TODO write the value reading from MSR */
1765         eptp = VMX_EPT_DEFAULT_MT |
1766                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1767         eptp |= (root_hpa & PAGE_MASK);
1768
1769         return eptp;
1770 }
1771
1772 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1773 {
1774         unsigned long guest_cr3;
1775         u64 eptp;
1776
1777         guest_cr3 = cr3;
1778         if (enable_ept) {
1779                 eptp = construct_eptp(cr3);
1780                 vmcs_write64(EPT_POINTER, eptp);
1781                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1782                         vcpu->kvm->arch.ept_identity_map_addr;
1783                 ept_load_pdptrs(vcpu);
1784         }
1785
1786         vmx_flush_tlb(vcpu);
1787         vmcs_writel(GUEST_CR3, guest_cr3);
1788         if (vcpu->arch.cr0 & X86_CR0_PE)
1789                 vmx_fpu_deactivate(vcpu);
1790 }
1791
1792 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1793 {
1794         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1795                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1796
1797         vcpu->arch.cr4 = cr4;
1798         if (enable_ept) {
1799                 if (!is_paging(vcpu)) {
1800                         hw_cr4 &= ~X86_CR4_PAE;
1801                         hw_cr4 |= X86_CR4_PSE;
1802                 } else if (!(cr4 & X86_CR4_PAE)) {
1803                         hw_cr4 &= ~X86_CR4_PAE;
1804                 }
1805         }
1806
1807         vmcs_writel(CR4_READ_SHADOW, cr4);
1808         vmcs_writel(GUEST_CR4, hw_cr4);
1809 }
1810
1811 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1812 {
1813         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1814
1815         return vmcs_readl(sf->base);
1816 }
1817
1818 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1819                             struct kvm_segment *var, int seg)
1820 {
1821         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1822         u32 ar;
1823
1824         var->base = vmcs_readl(sf->base);
1825         var->limit = vmcs_read32(sf->limit);
1826         var->selector = vmcs_read16(sf->selector);
1827         ar = vmcs_read32(sf->ar_bytes);
1828         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1829                 ar = 0;
1830         var->type = ar & 15;
1831         var->s = (ar >> 4) & 1;
1832         var->dpl = (ar >> 5) & 3;
1833         var->present = (ar >> 7) & 1;
1834         var->avl = (ar >> 12) & 1;
1835         var->l = (ar >> 13) & 1;
1836         var->db = (ar >> 14) & 1;
1837         var->g = (ar >> 15) & 1;
1838         var->unusable = (ar >> 16) & 1;
1839 }
1840
1841 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1842 {
1843         if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1844                 return 0;
1845
1846         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1847                 return 3;
1848
1849         return vmcs_read16(GUEST_CS_SELECTOR) & 3;
1850 }
1851
1852 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1853 {
1854         u32 ar;
1855
1856         if (var->unusable)
1857                 ar = 1 << 16;
1858         else {
1859                 ar = var->type & 15;
1860                 ar |= (var->s & 1) << 4;
1861                 ar |= (var->dpl & 3) << 5;
1862                 ar |= (var->present & 1) << 7;
1863                 ar |= (var->avl & 1) << 12;
1864                 ar |= (var->l & 1) << 13;
1865                 ar |= (var->db & 1) << 14;
1866                 ar |= (var->g & 1) << 15;
1867         }
1868         if (ar == 0) /* a 0 value means unusable */
1869                 ar = AR_UNUSABLE_MASK;
1870
1871         return ar;
1872 }
1873
1874 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1875                             struct kvm_segment *var, int seg)
1876 {
1877         struct vcpu_vmx *vmx = to_vmx(vcpu);
1878         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1879         u32 ar;
1880
1881         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1882                 vmx->rmode.tr.selector = var->selector;
1883                 vmx->rmode.tr.base = var->base;
1884                 vmx->rmode.tr.limit = var->limit;
1885                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
1886                 return;
1887         }
1888         vmcs_writel(sf->base, var->base);
1889         vmcs_write32(sf->limit, var->limit);
1890         vmcs_write16(sf->selector, var->selector);
1891         if (vmx->rmode.vm86_active && var->s) {
1892                 /*
1893                  * Hack real-mode segments into vm86 compatibility.
1894                  */
1895                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1896                         vmcs_writel(sf->base, 0xf0000);
1897                 ar = 0xf3;
1898         } else
1899                 ar = vmx_segment_access_rights(var);
1900
1901         /*
1902          *   Fix the "Accessed" bit in AR field of segment registers for older
1903          * qemu binaries.
1904          *   IA32 arch specifies that at the time of processor reset the
1905          * "Accessed" bit in the AR field of segment registers is 1. And qemu
1906          * is setting it to 0 in the usedland code. This causes invalid guest
1907          * state vmexit when "unrestricted guest" mode is turned on.
1908          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
1909          * tree. Newer qemu binaries with that qemu fix would not need this
1910          * kvm hack.
1911          */
1912         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1913                 ar |= 0x1; /* Accessed */
1914
1915         vmcs_write32(sf->ar_bytes, ar);
1916 }
1917
1918 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1919 {
1920         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1921
1922         *db = (ar >> 14) & 1;
1923         *l = (ar >> 13) & 1;
1924 }
1925
1926 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1927 {
1928         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1929         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1930 }
1931
1932 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1933 {
1934         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1935         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1936 }
1937
1938 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1939 {
1940         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1941         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1942 }
1943
1944 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1945 {
1946         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1947         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1948 }
1949
1950 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1951 {
1952         struct kvm_segment var;
1953         u32 ar;
1954
1955         vmx_get_segment(vcpu, &var, seg);
1956         ar = vmx_segment_access_rights(&var);
1957
1958         if (var.base != (var.selector << 4))
1959                 return false;
1960         if (var.limit != 0xffff)
1961                 return false;
1962         if (ar != 0xf3)
1963                 return false;
1964
1965         return true;
1966 }
1967
1968 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1969 {
1970         struct kvm_segment cs;
1971         unsigned int cs_rpl;
1972
1973         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1974         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1975
1976         if (cs.unusable)
1977                 return false;
1978         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1979                 return false;
1980         if (!cs.s)
1981                 return false;
1982         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1983                 if (cs.dpl > cs_rpl)
1984                         return false;
1985         } else {
1986                 if (cs.dpl != cs_rpl)
1987                         return false;
1988         }
1989         if (!cs.present)
1990                 return false;
1991
1992         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1993         return true;
1994 }
1995
1996 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1997 {
1998         struct kvm_segment ss;
1999         unsigned int ss_rpl;
2000
2001         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2002         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2003
2004         if (ss.unusable)
2005                 return true;
2006         if (ss.type != 3 && ss.type != 7)
2007                 return false;
2008         if (!ss.s)
2009                 return false;
2010         if (ss.dpl != ss_rpl) /* DPL != RPL */
2011                 return false;
2012         if (!ss.present)
2013                 return false;
2014
2015         return true;
2016 }
2017
2018 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2019 {
2020         struct kvm_segment var;
2021         unsigned int rpl;
2022
2023         vmx_get_segment(vcpu, &var, seg);
2024         rpl = var.selector & SELECTOR_RPL_MASK;
2025
2026         if (var.unusable)
2027                 return true;
2028         if (!var.s)
2029                 return false;
2030         if (!var.present)
2031                 return false;
2032         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2033                 if (var.dpl < rpl) /* DPL < RPL */
2034                         return false;
2035         }
2036
2037         /* TODO: Add other members to kvm_segment_field to allow checking for other access
2038          * rights flags
2039          */
2040         return true;
2041 }
2042
2043 static bool tr_valid(struct kvm_vcpu *vcpu)
2044 {
2045         struct kvm_segment tr;
2046
2047         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2048
2049         if (tr.unusable)
2050                 return false;
2051         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
2052                 return false;
2053         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2054                 return false;
2055         if (!tr.present)
2056                 return false;
2057
2058         return true;
2059 }
2060
2061 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2062 {
2063         struct kvm_segment ldtr;
2064
2065         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2066
2067         if (ldtr.unusable)
2068                 return true;
2069         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
2070                 return false;
2071         if (ldtr.type != 2)
2072                 return false;
2073         if (!ldtr.present)
2074                 return false;
2075
2076         return true;
2077 }
2078
2079 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2080 {
2081         struct kvm_segment cs, ss;
2082
2083         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2084         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2085
2086         return ((cs.selector & SELECTOR_RPL_MASK) ==
2087                  (ss.selector & SELECTOR_RPL_MASK));
2088 }
2089
2090 /*
2091  * Check if guest state is valid. Returns true if valid, false if
2092  * not.
2093  * We assume that registers are always usable
2094  */
2095 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2096 {
2097         /* real mode guest state checks */
2098         if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
2099                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2100                         return false;
2101                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2102                         return false;
2103                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2104                         return false;
2105                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2106                         return false;
2107                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2108                         return false;
2109                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2110                         return false;
2111         } else {
2112         /* protected mode guest state checks */
2113                 if (!cs_ss_rpl_check(vcpu))
2114                         return false;
2115                 if (!code_segment_valid(vcpu))
2116                         return false;
2117                 if (!stack_segment_valid(vcpu))
2118                         return false;
2119                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2120                         return false;
2121                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2122                         return false;
2123                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2124                         return false;
2125                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2126                         return false;
2127                 if (!tr_valid(vcpu))
2128                         return false;
2129                 if (!ldtr_valid(vcpu))
2130                         return false;
2131         }
2132         /* TODO:
2133          * - Add checks on RIP
2134          * - Add checks on RFLAGS
2135          */
2136
2137         return true;
2138 }
2139
2140 static int init_rmode_tss(struct kvm *kvm)
2141 {
2142         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2143         u16 data = 0;
2144         int ret = 0;
2145         int r;
2146
2147         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2148         if (r < 0)
2149                 goto out;
2150         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2151         r = kvm_write_guest_page(kvm, fn++, &data,
2152                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
2153         if (r < 0)
2154                 goto out;
2155         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2156         if (r < 0)
2157                 goto out;
2158         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2159         if (r < 0)
2160                 goto out;
2161         data = ~0;
2162         r = kvm_write_guest_page(kvm, fn, &data,
2163                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2164                                  sizeof(u8));
2165         if (r < 0)
2166                 goto out;
2167
2168         ret = 1;
2169 out:
2170         return ret;
2171 }
2172
2173 static int init_rmode_identity_map(struct kvm *kvm)
2174 {
2175         int i, r, ret;
2176         pfn_t identity_map_pfn;
2177         u32 tmp;
2178
2179         if (!enable_ept)
2180                 return 1;
2181         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2182                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2183                         "haven't been allocated!\n");
2184                 return 0;
2185         }
2186         if (likely(kvm->arch.ept_identity_pagetable_done))
2187                 return 1;
2188         ret = 0;
2189         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2190         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2191         if (r < 0)
2192                 goto out;
2193         /* Set up identity-mapping pagetable for EPT in real mode */
2194         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2195                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2196                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2197                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2198                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2199                 if (r < 0)
2200                         goto out;
2201         }
2202         kvm->arch.ept_identity_pagetable_done = true;
2203         ret = 1;
2204 out:
2205         return ret;
2206 }
2207
2208 static void seg_setup(int seg)
2209 {
2210         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2211         unsigned int ar;
2212
2213         vmcs_write16(sf->selector, 0);
2214         vmcs_writel(sf->base, 0);
2215         vmcs_write32(sf->limit, 0xffff);
2216         if (enable_unrestricted_guest) {
2217                 ar = 0x93;
2218                 if (seg == VCPU_SREG_CS)
2219                         ar |= 0x08; /* code segment */
2220         } else
2221                 ar = 0xf3;
2222
2223         vmcs_write32(sf->ar_bytes, ar);
2224 }
2225
2226 static int alloc_apic_access_page(struct kvm *kvm)
2227 {
2228         struct kvm_userspace_memory_region kvm_userspace_mem;
2229         int r = 0;
2230
2231         mutex_lock(&kvm->slots_lock);
2232         if (kvm->arch.apic_access_page)
2233                 goto out;
2234         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2235         kvm_userspace_mem.flags = 0;
2236         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2237         kvm_userspace_mem.memory_size = PAGE_SIZE;
2238         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2239         if (r)
2240                 goto out;
2241
2242         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2243 out:
2244         mutex_unlock(&kvm->slots_lock);
2245         return r;
2246 }
2247
2248 static int alloc_identity_pagetable(struct kvm *kvm)
2249 {
2250         struct kvm_userspace_memory_region kvm_userspace_mem;
2251         int r = 0;
2252
2253         mutex_lock(&kvm->slots_lock);
2254         if (kvm->arch.ept_identity_pagetable)
2255                 goto out;
2256         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2257         kvm_userspace_mem.flags = 0;
2258         kvm_userspace_mem.guest_phys_addr =
2259                 kvm->arch.ept_identity_map_addr;
2260         kvm_userspace_mem.memory_size = PAGE_SIZE;
2261         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2262         if (r)
2263                 goto out;
2264
2265         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2266                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2267 out:
2268         mutex_unlock(&kvm->slots_lock);
2269         return r;
2270 }
2271
2272 static void allocate_vpid(struct vcpu_vmx *vmx)
2273 {
2274         int vpid;
2275
2276         vmx->vpid = 0;
2277         if (!enable_vpid)
2278                 return;
2279         spin_lock(&vmx_vpid_lock);
2280         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2281         if (vpid < VMX_NR_VPIDS) {
2282                 vmx->vpid = vpid;
2283                 __set_bit(vpid, vmx_vpid_bitmap);
2284         }
2285         spin_unlock(&vmx_vpid_lock);
2286 }
2287
2288 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2289 {
2290         int f = sizeof(unsigned long);
2291
2292         if (!cpu_has_vmx_msr_bitmap())
2293                 return;
2294
2295         /*
2296          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2297          * have the write-low and read-high bitmap offsets the wrong way round.
2298          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2299          */
2300         if (msr <= 0x1fff) {
2301                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2302                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2303         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2304                 msr &= 0x1fff;
2305                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2306                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2307         }
2308 }
2309
2310 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2311 {
2312         if (!longmode_only)
2313                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2314         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2315 }
2316
2317 /*
2318  * Sets up the vmcs for emulated real mode.
2319  */
2320 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2321 {
2322         u32 host_sysenter_cs, msr_low, msr_high;
2323         u32 junk;
2324         u64 host_pat, tsc_this, tsc_base;
2325         unsigned long a;
2326         struct descriptor_table dt;
2327         int i;
2328         unsigned long kvm_vmx_return;
2329         u32 exec_control;
2330
2331         /* I/O */
2332         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2333         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2334
2335         if (cpu_has_vmx_msr_bitmap())
2336                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2337
2338         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2339
2340         /* Control */
2341         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2342                 vmcs_config.pin_based_exec_ctrl);
2343
2344         exec_control = vmcs_config.cpu_based_exec_ctrl;
2345         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2346                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2347 #ifdef CONFIG_X86_64
2348                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2349                                 CPU_BASED_CR8_LOAD_EXITING;
2350 #endif
2351         }
2352         if (!enable_ept)
2353                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2354                                 CPU_BASED_CR3_LOAD_EXITING  |
2355                                 CPU_BASED_INVLPG_EXITING;
2356         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2357
2358         if (cpu_has_secondary_exec_ctrls()) {
2359                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2360                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2361                         exec_control &=
2362                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2363                 if (vmx->vpid == 0)
2364                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2365                 if (!enable_ept) {
2366                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2367                         enable_unrestricted_guest = 0;
2368                 }
2369                 if (!enable_unrestricted_guest)
2370                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2371                 if (!ple_gap)
2372                         exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2373                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2374         }
2375
2376         if (ple_gap) {
2377                 vmcs_write32(PLE_GAP, ple_gap);
2378                 vmcs_write32(PLE_WINDOW, ple_window);
2379         }
2380
2381         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2382         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2383         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2384
2385         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
2386         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2387         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2388
2389         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2390         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2391         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2392         vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs());    /* 22.2.4 */
2393         vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs());    /* 22.2.4 */
2394         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2395 #ifdef CONFIG_X86_64
2396         rdmsrl(MSR_FS_BASE, a);
2397         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2398         rdmsrl(MSR_GS_BASE, a);
2399         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2400 #else
2401         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2402         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2403 #endif
2404
2405         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2406
2407         kvm_get_idt(&dt);
2408         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
2409
2410         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2411         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2412         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2413         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2414         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2415
2416         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2417         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2418         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2419         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2420         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2421         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2422
2423         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2424                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2425                 host_pat = msr_low | ((u64) msr_high << 32);
2426                 vmcs_write64(HOST_IA32_PAT, host_pat);
2427         }
2428         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2429                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2430                 host_pat = msr_low | ((u64) msr_high << 32);
2431                 /* Write the default value follow host pat */
2432                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2433                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2434                 vmx->vcpu.arch.pat = host_pat;
2435         }
2436
2437         for (i = 0; i < NR_VMX_MSR; ++i) {
2438                 u32 index = vmx_msr_index[i];
2439                 u32 data_low, data_high;
2440                 int j = vmx->nmsrs;
2441
2442                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2443                         continue;
2444                 if (wrmsr_safe(index, data_low, data_high) < 0)
2445                         continue;
2446                 vmx->guest_msrs[j].index = i;
2447                 vmx->guest_msrs[j].data = 0;
2448                 vmx->guest_msrs[j].mask = -1ull;
2449                 ++vmx->nmsrs;
2450         }
2451
2452         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2453
2454         /* 22.2.1, 20.8.1 */
2455         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2456
2457         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2458         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2459         if (enable_ept)
2460                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2461         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2462
2463         tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2464         rdtscll(tsc_this);
2465         if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2466                 tsc_base = tsc_this;
2467
2468         guest_write_tsc(0, tsc_base);
2469
2470         return 0;
2471 }
2472
2473 static int init_rmode(struct kvm *kvm)
2474 {
2475         if (!init_rmode_tss(kvm))
2476                 return 0;
2477         if (!init_rmode_identity_map(kvm))
2478                 return 0;
2479         return 1;
2480 }
2481
2482 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2483 {
2484         struct vcpu_vmx *vmx = to_vmx(vcpu);
2485         u64 msr;
2486         int ret, idx;
2487
2488         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2489         idx = srcu_read_lock(&vcpu->kvm->srcu);
2490         if (!init_rmode(vmx->vcpu.kvm)) {
2491                 ret = -ENOMEM;
2492                 goto out;
2493         }
2494
2495         vmx->rmode.vm86_active = 0;
2496
2497         vmx->soft_vnmi_blocked = 0;
2498
2499         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2500         kvm_set_cr8(&vmx->vcpu, 0);
2501         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2502         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2503                 msr |= MSR_IA32_APICBASE_BSP;
2504         kvm_set_apic_base(&vmx->vcpu, msr);
2505
2506         fx_init(&vmx->vcpu);
2507
2508         seg_setup(VCPU_SREG_CS);
2509         /*
2510          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2511          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2512          */
2513         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2514                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2515                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2516         } else {
2517                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2518                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2519         }
2520
2521         seg_setup(VCPU_SREG_DS);
2522         seg_setup(VCPU_SREG_ES);
2523         seg_setup(VCPU_SREG_FS);
2524         seg_setup(VCPU_SREG_GS);
2525         seg_setup(VCPU_SREG_SS);
2526
2527         vmcs_write16(GUEST_TR_SELECTOR, 0);
2528         vmcs_writel(GUEST_TR_BASE, 0);
2529         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2530         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2531
2532         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2533         vmcs_writel(GUEST_LDTR_BASE, 0);
2534         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2535         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2536
2537         vmcs_write32(GUEST_SYSENTER_CS, 0);
2538         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2539         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2540
2541         vmcs_writel(GUEST_RFLAGS, 0x02);
2542         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2543                 kvm_rip_write(vcpu, 0xfff0);
2544         else
2545                 kvm_rip_write(vcpu, 0);
2546         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2547
2548         vmcs_writel(GUEST_DR7, 0x400);
2549
2550         vmcs_writel(GUEST_GDTR_BASE, 0);
2551         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2552
2553         vmcs_writel(GUEST_IDTR_BASE, 0);
2554         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2555
2556         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2557         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2558         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2559
2560         /* Special registers */
2561         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2562
2563         setup_msrs(vmx);
2564
2565         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2566
2567         if (cpu_has_vmx_tpr_shadow()) {
2568                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2569                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2570                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2571                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2572                 vmcs_write32(TPR_THRESHOLD, 0);
2573         }
2574
2575         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2576                 vmcs_write64(APIC_ACCESS_ADDR,
2577                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2578
2579         if (vmx->vpid != 0)
2580                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2581
2582         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2583         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2584         vmx_set_cr4(&vmx->vcpu, 0);
2585         vmx_set_efer(&vmx->vcpu, 0);
2586         vmx_fpu_activate(&vmx->vcpu);
2587         update_exception_bitmap(&vmx->vcpu);
2588
2589         vpid_sync_vcpu_all(vmx);
2590
2591         ret = 0;
2592
2593         /* HACK: Don't enable emulation on guest boot/reset */
2594         vmx->emulation_required = 0;
2595
2596 out:
2597         srcu_read_unlock(&vcpu->kvm->srcu, idx);
2598         return ret;
2599 }
2600
2601 static void enable_irq_window(struct kvm_vcpu *vcpu)
2602 {
2603         u32 cpu_based_vm_exec_control;
2604
2605         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2606         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2607         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2608 }
2609
2610 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2611 {
2612         u32 cpu_based_vm_exec_control;
2613
2614         if (!cpu_has_virtual_nmis()) {
2615                 enable_irq_window(vcpu);
2616                 return;
2617         }
2618
2619         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2620         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2621         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2622 }
2623
2624 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2625 {
2626         struct vcpu_vmx *vmx = to_vmx(vcpu);
2627         uint32_t intr;
2628         int irq = vcpu->arch.interrupt.nr;
2629
2630         trace_kvm_inj_virq(irq);
2631
2632         ++vcpu->stat.irq_injections;
2633         if (vmx->rmode.vm86_active) {
2634                 vmx->rmode.irq.pending = true;
2635                 vmx->rmode.irq.vector = irq;
2636                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2637                 if (vcpu->arch.interrupt.soft)
2638                         vmx->rmode.irq.rip +=
2639                                 vmx->vcpu.arch.event_exit_inst_len;
2640                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2641                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2642                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2643                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2644                 return;
2645         }
2646         intr = irq | INTR_INFO_VALID_MASK;
2647         if (vcpu->arch.interrupt.soft) {
2648                 intr |= INTR_TYPE_SOFT_INTR;
2649                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2650                              vmx->vcpu.arch.event_exit_inst_len);
2651         } else
2652                 intr |= INTR_TYPE_EXT_INTR;
2653         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2654 }
2655
2656 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2657 {
2658         struct vcpu_vmx *vmx = to_vmx(vcpu);
2659
2660         if (!cpu_has_virtual_nmis()) {
2661                 /*
2662                  * Tracking the NMI-blocked state in software is built upon
2663                  * finding the next open IRQ window. This, in turn, depends on
2664                  * well-behaving guests: They have to keep IRQs disabled at
2665                  * least as long as the NMI handler runs. Otherwise we may
2666                  * cause NMI nesting, maybe breaking the guest. But as this is
2667                  * highly unlikely, we can live with the residual risk.
2668                  */
2669                 vmx->soft_vnmi_blocked = 1;
2670                 vmx->vnmi_blocked_time = 0;
2671         }
2672
2673         ++vcpu->stat.nmi_injections;
2674         if (vmx->rmode.vm86_active) {
2675                 vmx->rmode.irq.pending = true;
2676                 vmx->rmode.irq.vector = NMI_VECTOR;
2677                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2678                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2679                              NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2680                              INTR_INFO_VALID_MASK);
2681                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2682                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2683                 return;
2684         }
2685         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2686                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2687 }
2688
2689 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2690 {
2691         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2692                 return 0;
2693
2694         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2695                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2696                                 GUEST_INTR_STATE_NMI));
2697 }
2698
2699 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2700 {
2701         if (!cpu_has_virtual_nmis())
2702                 return to_vmx(vcpu)->soft_vnmi_blocked;
2703         else
2704                 return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2705                           GUEST_INTR_STATE_NMI);
2706 }
2707
2708 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2709 {
2710         struct vcpu_vmx *vmx = to_vmx(vcpu);
2711
2712         if (!cpu_has_virtual_nmis()) {
2713                 if (vmx->soft_vnmi_blocked != masked) {
2714                         vmx->soft_vnmi_blocked = masked;
2715                         vmx->vnmi_blocked_time = 0;
2716                 }
2717         } else {
2718                 if (masked)
2719                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2720                                       GUEST_INTR_STATE_NMI);
2721                 else
2722                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2723                                         GUEST_INTR_STATE_NMI);
2724         }
2725 }
2726
2727 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2728 {
2729         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2730                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2731                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2732 }
2733
2734 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2735 {
2736         int ret;
2737         struct kvm_userspace_memory_region tss_mem = {
2738                 .slot = TSS_PRIVATE_MEMSLOT,
2739                 .guest_phys_addr = addr,
2740                 .memory_size = PAGE_SIZE * 3,
2741                 .flags = 0,
2742         };
2743
2744         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2745         if (ret)
2746                 return ret;
2747         kvm->arch.tss_addr = addr;
2748         return 0;
2749 }
2750
2751 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2752                                   int vec, u32 err_code)
2753 {
2754         /*
2755          * Instruction with address size override prefix opcode 0x67
2756          * Cause the #SS fault with 0 error code in VM86 mode.
2757          */
2758         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2759                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2760                         return 1;
2761         /*
2762          * Forward all other exceptions that are valid in real mode.
2763          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2764          *        the required debugging infrastructure rework.
2765          */
2766         switch (vec) {
2767         case DB_VECTOR:
2768                 if (vcpu->guest_debug &
2769                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2770                         return 0;
2771                 kvm_queue_exception(vcpu, vec);
2772                 return 1;
2773         case BP_VECTOR:
2774                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2775                         return 0;
2776                 /* fall through */
2777         case DE_VECTOR:
2778         case OF_VECTOR:
2779         case BR_VECTOR:
2780         case UD_VECTOR:
2781         case DF_VECTOR:
2782         case SS_VECTOR:
2783         case GP_VECTOR:
2784         case MF_VECTOR:
2785                 kvm_queue_exception(vcpu, vec);
2786                 return 1;
2787         }
2788         return 0;
2789 }
2790
2791 /*
2792  * Trigger machine check on the host. We assume all the MSRs are already set up
2793  * by the CPU and that we still run on the same CPU as the MCE occurred on.
2794  * We pass a fake environment to the machine check handler because we want
2795  * the guest to be always treated like user space, no matter what context
2796  * it used internally.
2797  */
2798 static void kvm_machine_check(void)
2799 {
2800 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2801         struct pt_regs regs = {
2802                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2803                 .flags = X86_EFLAGS_IF,
2804         };
2805
2806         do_machine_check(&regs, 0);
2807 #endif
2808 }
2809
2810 static int handle_machine_check(struct kvm_vcpu *vcpu)
2811 {
2812         /* already handled by vcpu_run */
2813         return 1;
2814 }
2815
2816 static int handle_exception(struct kvm_vcpu *vcpu)
2817 {
2818         struct vcpu_vmx *vmx = to_vmx(vcpu);
2819         struct kvm_run *kvm_run = vcpu->run;
2820         u32 intr_info, ex_no, error_code;
2821         unsigned long cr2, rip, dr6;
2822         u32 vect_info;
2823         enum emulation_result er;
2824
2825         vect_info = vmx->idt_vectoring_info;
2826         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2827
2828         if (is_machine_check(intr_info))
2829                 return handle_machine_check(vcpu);
2830
2831         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2832             !is_page_fault(intr_info)) {
2833                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2834                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2835                 vcpu->run->internal.ndata = 2;
2836                 vcpu->run->internal.data[0] = vect_info;
2837                 vcpu->run->internal.data[1] = intr_info;
2838                 return 0;
2839         }
2840
2841         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2842                 return 1;  /* already handled by vmx_vcpu_run() */
2843
2844         if (is_no_device(intr_info)) {
2845                 vmx_fpu_activate(vcpu);
2846                 return 1;
2847         }
2848
2849         if (is_invalid_opcode(intr_info)) {
2850                 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
2851                 if (er != EMULATE_DONE)
2852                         kvm_queue_exception(vcpu, UD_VECTOR);
2853                 return 1;
2854         }
2855
2856         error_code = 0;
2857         rip = kvm_rip_read(vcpu);
2858         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2859                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2860         if (is_page_fault(intr_info)) {
2861                 /* EPT won't cause page fault directly */
2862                 if (enable_ept)
2863                         BUG();
2864                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2865                 trace_kvm_page_fault(cr2, error_code);
2866
2867                 if (kvm_event_needs_reinjection(vcpu))
2868                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
2869                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2870         }
2871
2872         if (vmx->rmode.vm86_active &&
2873             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2874                                                                 error_code)) {
2875                 if (vcpu->arch.halt_request) {
2876                         vcpu->arch.halt_request = 0;
2877                         return kvm_emulate_halt(vcpu);
2878                 }
2879                 return 1;
2880         }
2881
2882         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2883         switch (ex_no) {
2884         case DB_VECTOR:
2885                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2886                 if (!(vcpu->guest_debug &
2887                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2888                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2889                         kvm_queue_exception(vcpu, DB_VECTOR);
2890                         return 1;
2891                 }
2892                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2893                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2894                 /* fall through */
2895         case BP_VECTOR:
2896                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2897                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2898                 kvm_run->debug.arch.exception = ex_no;
2899                 break;
2900         default:
2901                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2902                 kvm_run->ex.exception = ex_no;
2903                 kvm_run->ex.error_code = error_code;
2904                 break;
2905         }
2906         return 0;
2907 }
2908
2909 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
2910 {
2911         ++vcpu->stat.irq_exits;
2912         return 1;
2913 }
2914
2915 static int handle_triple_fault(struct kvm_vcpu *vcpu)
2916 {
2917         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
2918         return 0;
2919 }
2920
2921 static int handle_io(struct kvm_vcpu *vcpu)
2922 {
2923         unsigned long exit_qualification;
2924         int size, in, string;
2925         unsigned port;
2926
2927         ++vcpu->stat.io_exits;
2928         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2929         string = (exit_qualification & 16) != 0;
2930
2931         if (string) {
2932                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO)
2933                         return 0;
2934                 return 1;
2935         }
2936
2937         size = (exit_qualification & 7) + 1;
2938         in = (exit_qualification & 8) != 0;
2939         port = exit_qualification >> 16;
2940
2941         skip_emulated_instruction(vcpu);
2942         return kvm_emulate_pio(vcpu, in, size, port);
2943 }
2944
2945 static void
2946 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2947 {
2948         /*
2949          * Patch in the VMCALL instruction:
2950          */
2951         hypercall[0] = 0x0f;
2952         hypercall[1] = 0x01;
2953         hypercall[2] = 0xc1;
2954 }
2955
2956 static int handle_cr(struct kvm_vcpu *vcpu)
2957 {
2958         unsigned long exit_qualification, val;
2959         int cr;
2960         int reg;
2961
2962         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2963         cr = exit_qualification & 15;
2964         reg = (exit_qualification >> 8) & 15;
2965         switch ((exit_qualification >> 4) & 3) {
2966         case 0: /* mov to cr */
2967                 val = kvm_register_read(vcpu, reg);
2968                 trace_kvm_cr_write(cr, val);
2969                 switch (cr) {
2970                 case 0:
2971                         kvm_set_cr0(vcpu, val);
2972                         skip_emulated_instruction(vcpu);
2973                         return 1;
2974                 case 3:
2975                         kvm_set_cr3(vcpu, val);
2976                         skip_emulated_instruction(vcpu);
2977                         return 1;
2978                 case 4:
2979                         kvm_set_cr4(vcpu, val);
2980                         skip_emulated_instruction(vcpu);
2981                         return 1;
2982                 case 8: {
2983                                 u8 cr8_prev = kvm_get_cr8(vcpu);
2984                                 u8 cr8 = kvm_register_read(vcpu, reg);
2985                                 kvm_set_cr8(vcpu, cr8);
2986                                 skip_emulated_instruction(vcpu);
2987                                 if (irqchip_in_kernel(vcpu->kvm))
2988                                         return 1;
2989                                 if (cr8_prev <= cr8)
2990                                         return 1;
2991                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
2992                                 return 0;
2993                         }
2994                 };
2995                 break;
2996         case 2: /* clts */
2997                 vmx_fpu_deactivate(vcpu);
2998                 vcpu->arch.cr0 &= ~X86_CR0_TS;
2999                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
3000                 trace_kvm_cr_write(0, vcpu->arch.cr0);
3001                 vmx_fpu_activate(vcpu);
3002                 skip_emulated_instruction(vcpu);
3003                 return 1;
3004         case 1: /*mov from cr*/
3005                 switch (cr) {
3006                 case 3:
3007                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
3008                         trace_kvm_cr_read(cr, vcpu->arch.cr3);
3009                         skip_emulated_instruction(vcpu);
3010                         return 1;
3011                 case 8:
3012                         val = kvm_get_cr8(vcpu);
3013                         kvm_register_write(vcpu, reg, val);
3014                         trace_kvm_cr_read(cr, val);
3015                         skip_emulated_instruction(vcpu);
3016                         return 1;
3017                 }
3018                 break;
3019         case 3: /* lmsw */
3020                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3021                 trace_kvm_cr_write(0, (vcpu->arch.cr0 & ~0xful) | val);
3022                 kvm_lmsw(vcpu, val);
3023
3024                 skip_emulated_instruction(vcpu);
3025                 return 1;
3026         default:
3027                 break;
3028         }
3029         vcpu->run->exit_reason = 0;
3030         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3031                (int)(exit_qualification >> 4) & 3, cr);
3032         return 0;
3033 }
3034
3035 static int handle_dr(struct kvm_vcpu *vcpu)
3036 {
3037         unsigned long exit_qualification;
3038         unsigned long val;
3039         int dr, reg;
3040
3041         if (!kvm_require_cpl(vcpu, 0))
3042                 return 1;
3043         dr = vmcs_readl(GUEST_DR7);
3044         if (dr & DR7_GD) {
3045                 /*
3046                  * As the vm-exit takes precedence over the debug trap, we
3047                  * need to emulate the latter, either for the host or the
3048                  * guest debugging itself.
3049                  */
3050                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3051                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3052                         vcpu->run->debug.arch.dr7 = dr;
3053                         vcpu->run->debug.arch.pc =
3054                                 vmcs_readl(GUEST_CS_BASE) +
3055                                 vmcs_readl(GUEST_RIP);
3056                         vcpu->run->debug.arch.exception = DB_VECTOR;
3057                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3058                         return 0;
3059                 } else {
3060                         vcpu->arch.dr7 &= ~DR7_GD;
3061                         vcpu->arch.dr6 |= DR6_BD;
3062                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3063                         kvm_queue_exception(vcpu, DB_VECTOR);
3064                         return 1;
3065                 }
3066         }
3067
3068         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3069         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3070         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3071         if (exit_qualification & TYPE_MOV_FROM_DR) {
3072                 switch (dr) {
3073                 case 0 ... 3:
3074                         val = vcpu->arch.db[dr];
3075                         break;
3076                 case 6:
3077                         val = vcpu->arch.dr6;
3078                         break;
3079                 case 7:
3080                         val = vcpu->arch.dr7;
3081                         break;
3082                 default:
3083                         val = 0;
3084                 }
3085                 kvm_register_write(vcpu, reg, val);
3086         } else {
3087                 val = vcpu->arch.regs[reg];
3088                 switch (dr) {
3089                 case 0 ... 3:
3090                         vcpu->arch.db[dr] = val;
3091                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
3092                                 vcpu->arch.eff_db[dr] = val;
3093                         break;
3094                 case 4 ... 5:
3095                         if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
3096                                 kvm_queue_exception(vcpu, UD_VECTOR);
3097                         break;
3098                 case 6:
3099                         if (val & 0xffffffff00000000ULL) {
3100                                 kvm_queue_exception(vcpu, GP_VECTOR);
3101                                 break;
3102                         }
3103                         vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
3104                         break;
3105                 case 7:
3106                         if (val & 0xffffffff00000000ULL) {
3107                                 kvm_queue_exception(vcpu, GP_VECTOR);
3108                                 break;
3109                         }
3110                         vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3111                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3112                                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3113                                 vcpu->arch.switch_db_regs =
3114                                         (val & DR7_BP_EN_MASK);
3115                         }
3116                         break;
3117                 }
3118         }
3119         skip_emulated_instruction(vcpu);
3120         return 1;
3121 }
3122
3123 static int handle_cpuid(struct kvm_vcpu *vcpu)
3124 {
3125         kvm_emulate_cpuid(vcpu);
3126         return 1;
3127 }
3128
3129 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3130 {
3131         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3132         u64 data;
3133
3134         if (vmx_get_msr(vcpu, ecx, &data)) {
3135                 kvm_inject_gp(vcpu, 0);
3136                 return 1;
3137         }
3138
3139         trace_kvm_msr_read(ecx, data);
3140
3141         /* FIXME: handling of bits 32:63 of rax, rdx */
3142         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3143         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3144         skip_emulated_instruction(vcpu);
3145         return 1;
3146 }
3147
3148 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3149 {
3150         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3151         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3152                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3153
3154         trace_kvm_msr_write(ecx, data);
3155
3156         if (vmx_set_msr(vcpu, ecx, data) != 0) {
3157                 kvm_inject_gp(vcpu, 0);
3158                 return 1;
3159         }
3160
3161         skip_emulated_instruction(vcpu);
3162         return 1;
3163 }
3164
3165 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3166 {
3167         return 1;
3168 }
3169
3170 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3171 {
3172         u32 cpu_based_vm_exec_control;
3173
3174         /* clear pending irq */
3175         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3176         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3177         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3178
3179         ++vcpu->stat.irq_window_exits;
3180
3181         /*
3182          * If the user space waits to inject interrupts, exit as soon as
3183          * possible
3184          */
3185         if (!irqchip_in_kernel(vcpu->kvm) &&
3186             vcpu->run->request_interrupt_window &&
3187             !kvm_cpu_has_interrupt(vcpu)) {
3188                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3189                 return 0;
3190         }
3191         return 1;
3192 }
3193
3194 static int handle_halt(struct kvm_vcpu *vcpu)
3195 {
3196         skip_emulated_instruction(vcpu);
3197         return kvm_emulate_halt(vcpu);
3198 }
3199
3200 static int handle_vmcall(struct kvm_vcpu *vcpu)
3201 {
3202         skip_emulated_instruction(vcpu);
3203         kvm_emulate_hypercall(vcpu);
3204         return 1;
3205 }
3206
3207 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3208 {
3209         kvm_queue_exception(vcpu, UD_VECTOR);
3210         return 1;
3211 }
3212
3213 static int handle_invlpg(struct kvm_vcpu *vcpu)
3214 {
3215         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3216
3217         kvm_mmu_invlpg(vcpu, exit_qualification);
3218         skip_emulated_instruction(vcpu);
3219         return 1;
3220 }
3221
3222 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3223 {
3224         skip_emulated_instruction(vcpu);
3225         /* TODO: Add support for VT-d/pass-through device */
3226         return 1;
3227 }
3228
3229 static int handle_apic_access(struct kvm_vcpu *vcpu)
3230 {
3231         unsigned long exit_qualification;
3232         enum emulation_result er;
3233         unsigned long offset;
3234
3235         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3236         offset = exit_qualification & 0xffful;
3237
3238         er = emulate_instruction(vcpu, 0, 0, 0);
3239
3240         if (er !=  EMULATE_DONE) {
3241                 printk(KERN_ERR
3242                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3243                        offset);
3244                 return -ENOEXEC;
3245         }
3246         return 1;
3247 }
3248
3249 static int handle_task_switch(struct kvm_vcpu *vcpu)
3250 {
3251         struct vcpu_vmx *vmx = to_vmx(vcpu);
3252         unsigned long exit_qualification;
3253         u16 tss_selector;
3254         int reason, type, idt_v;
3255
3256         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3257         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3258
3259         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3260
3261         reason = (u32)exit_qualification >> 30;
3262         if (reason == TASK_SWITCH_GATE && idt_v) {
3263                 switch (type) {
3264                 case INTR_TYPE_NMI_INTR:
3265                         vcpu->arch.nmi_injected = false;
3266                         if (cpu_has_virtual_nmis())
3267                                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3268                                               GUEST_INTR_STATE_NMI);
3269                         break;
3270                 case INTR_TYPE_EXT_INTR:
3271                 case INTR_TYPE_SOFT_INTR:
3272                         kvm_clear_interrupt_queue(vcpu);
3273                         break;
3274                 case INTR_TYPE_HARD_EXCEPTION:
3275                 case INTR_TYPE_SOFT_EXCEPTION:
3276                         kvm_clear_exception_queue(vcpu);
3277                         break;
3278                 default:
3279                         break;
3280                 }
3281         }
3282         tss_selector = exit_qualification;
3283
3284         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3285                        type != INTR_TYPE_EXT_INTR &&
3286                        type != INTR_TYPE_NMI_INTR))
3287                 skip_emulated_instruction(vcpu);
3288
3289         if (!kvm_task_switch(vcpu, tss_selector, reason))
3290                 return 0;
3291
3292         /* clear all local breakpoint enable flags */
3293         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3294
3295         /*
3296          * TODO: What about debug traps on tss switch?
3297          *       Are we supposed to inject them and update dr6?
3298          */
3299
3300         return 1;
3301 }
3302
3303 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3304 {
3305         unsigned long exit_qualification;
3306         gpa_t gpa;
3307         int gla_validity;
3308
3309         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3310
3311         if (exit_qualification & (1 << 6)) {
3312                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3313                 return -EINVAL;
3314         }
3315
3316         gla_validity = (exit_qualification >> 7) & 0x3;
3317         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3318                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3319                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3320                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3321                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3322                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3323                         (long unsigned int)exit_qualification);
3324                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3325                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3326                 return 0;
3327         }
3328
3329         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3330         trace_kvm_page_fault(gpa, exit_qualification);
3331         return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3332 }
3333
3334 static u64 ept_rsvd_mask(u64 spte, int level)
3335 {
3336         int i;
3337         u64 mask = 0;
3338
3339         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3340                 mask |= (1ULL << i);
3341
3342         if (level > 2)
3343                 /* bits 7:3 reserved */
3344                 mask |= 0xf8;
3345         else if (level == 2) {
3346                 if (spte & (1ULL << 7))
3347                         /* 2MB ref, bits 20:12 reserved */
3348                         mask |= 0x1ff000;
3349                 else
3350                         /* bits 6:3 reserved */
3351                         mask |= 0x78;
3352         }
3353
3354         return mask;
3355 }
3356
3357 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3358                                        int level)
3359 {
3360         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3361
3362         /* 010b (write-only) */
3363         WARN_ON((spte & 0x7) == 0x2);
3364
3365         /* 110b (write/execute) */
3366         WARN_ON((spte & 0x7) == 0x6);
3367
3368         /* 100b (execute-only) and value not supported by logical processor */
3369         if (!cpu_has_vmx_ept_execute_only())
3370                 WARN_ON((spte & 0x7) == 0x4);
3371
3372         /* not 000b */
3373         if ((spte & 0x7)) {
3374                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3375
3376                 if (rsvd_bits != 0) {
3377                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3378                                          __func__, rsvd_bits);
3379                         WARN_ON(1);
3380                 }
3381
3382                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3383                         u64 ept_mem_type = (spte & 0x38) >> 3;
3384
3385                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
3386                             ept_mem_type == 7) {
3387                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3388                                                 __func__, ept_mem_type);
3389                                 WARN_ON(1);
3390                         }
3391                 }
3392         }
3393 }
3394
3395 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3396 {
3397         u64 sptes[4];
3398         int nr_sptes, i;
3399         gpa_t gpa;
3400
3401         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3402
3403         printk(KERN_ERR "EPT: Misconfiguration.\n");
3404         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3405
3406         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3407
3408         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3409                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3410
3411         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3412         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3413
3414         return 0;
3415 }
3416
3417 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3418 {
3419         u32 cpu_based_vm_exec_control;
3420
3421         /* clear pending NMI */
3422         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3423         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3424         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3425         ++vcpu->stat.nmi_window_exits;
3426
3427         return 1;
3428 }
3429
3430 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3431 {
3432         struct vcpu_vmx *vmx = to_vmx(vcpu);
3433         enum emulation_result err = EMULATE_DONE;
3434         int ret = 1;
3435
3436         while (!guest_state_valid(vcpu)) {
3437                 err = emulate_instruction(vcpu, 0, 0, 0);
3438
3439                 if (err == EMULATE_DO_MMIO) {
3440                         ret = 0;
3441                         goto out;
3442                 }
3443
3444                 if (err != EMULATE_DONE) {
3445                         kvm_report_emulation_failure(vcpu, "emulation failure");
3446                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3447                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3448                         vcpu->run->internal.ndata = 0;
3449                         ret = 0;
3450                         goto out;
3451                 }
3452
3453                 if (signal_pending(current))
3454                         goto out;
3455                 if (need_resched())
3456                         schedule();
3457         }
3458
3459         vmx->emulation_required = 0;
3460 out:
3461         return ret;
3462 }
3463
3464 /*
3465  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3466  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3467  */
3468 static int handle_pause(struct kvm_vcpu *vcpu)
3469 {
3470         skip_emulated_instruction(vcpu);
3471         kvm_vcpu_on_spin(vcpu);
3472
3473         return 1;
3474 }
3475
3476 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3477 {
3478         kvm_queue_exception(vcpu, UD_VECTOR);
3479         return 1;
3480 }
3481
3482 /*
3483  * The exit handlers return 1 if the exit was handled fully and guest execution
3484  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3485  * to be done to userspace and return 0.
3486  */
3487 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3488         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3489         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3490         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3491         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3492         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3493         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3494         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3495         [EXIT_REASON_CPUID]                   = handle_cpuid,
3496         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3497         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3498         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3499         [EXIT_REASON_HLT]                     = handle_halt,
3500         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3501         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3502         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
3503         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
3504         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
3505         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
3506         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
3507         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
3508         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
3509         [EXIT_REASON_VMOFF]                   = handle_vmx_insn,
3510         [EXIT_REASON_VMON]                    = handle_vmx_insn,
3511         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3512         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3513         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3514         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3515         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
3516         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3517         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
3518         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
3519         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
3520         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
3521 };
3522
3523 static const int kvm_vmx_max_exit_handlers =
3524         ARRAY_SIZE(kvm_vmx_exit_handlers);
3525
3526 /*
3527  * The guest has exited.  See if we can fix it or if we need userspace
3528  * assistance.
3529  */
3530 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3531 {
3532         struct vcpu_vmx *vmx = to_vmx(vcpu);
3533         u32 exit_reason = vmx->exit_reason;
3534         u32 vectoring_info = vmx->idt_vectoring_info;
3535
3536         trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
3537
3538         /* If guest state is invalid, start emulating */
3539         if (vmx->emulation_required && emulate_invalid_guest_state)
3540                 return handle_invalid_guest_state(vcpu);
3541
3542         /* Access CR3 don't cause VMExit in paging mode, so we need
3543          * to sync with guest real CR3. */
3544         if (enable_ept && is_paging(vcpu))
3545                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3546
3547         if (unlikely(vmx->fail)) {
3548                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3549                 vcpu->run->fail_entry.hardware_entry_failure_reason
3550                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3551                 return 0;
3552         }
3553
3554         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3555                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3556                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3557                         exit_reason != EXIT_REASON_TASK_SWITCH))
3558                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3559                        "(0x%x) and exit reason is 0x%x\n",
3560                        __func__, vectoring_info, exit_reason);
3561
3562         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3563                 if (vmx_interrupt_allowed(vcpu)) {
3564                         vmx->soft_vnmi_blocked = 0;
3565                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3566                            vcpu->arch.nmi_pending) {
3567                         /*
3568                          * This CPU don't support us in finding the end of an
3569                          * NMI-blocked window if the guest runs with IRQs
3570                          * disabled. So we pull the trigger after 1 s of
3571                          * futile waiting, but inform the user about this.
3572                          */
3573                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3574                                "state on VCPU %d after 1 s timeout\n",
3575                                __func__, vcpu->vcpu_id);
3576                         vmx->soft_vnmi_blocked = 0;
3577                 }
3578         }
3579
3580         if (exit_reason < kvm_vmx_max_exit_handlers
3581             && kvm_vmx_exit_handlers[exit_reason])
3582                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3583         else {
3584                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3585                 vcpu->run->hw.hardware_exit_reason = exit_reason;
3586         }
3587         return 0;
3588 }
3589
3590 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3591 {
3592         if (irr == -1 || tpr < irr) {
3593                 vmcs_write32(TPR_THRESHOLD, 0);
3594                 return;
3595         }
3596
3597         vmcs_write32(TPR_THRESHOLD, irr);
3598 }
3599
3600 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3601 {
3602         u32 exit_intr_info;
3603         u32 idt_vectoring_info = vmx->idt_vectoring_info;
3604         bool unblock_nmi;
3605         u8 vector;
3606         int type;
3607         bool idtv_info_valid;
3608
3609         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3610
3611         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3612
3613         /* Handle machine checks before interrupts are enabled */
3614         if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3615             || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3616                 && is_machine_check(exit_intr_info)))
3617                 kvm_machine_check();
3618
3619         /* We need to handle NMIs before interrupts are enabled */
3620         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3621             (exit_intr_info & INTR_INFO_VALID_MASK))
3622                 asm("int $2");
3623
3624         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3625
3626         if (cpu_has_virtual_nmis()) {
3627                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3628                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3629                 /*
3630                  * SDM 3: 27.7.1.2 (September 2008)
3631                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3632                  * a guest IRET fault.
3633                  * SDM 3: 23.2.2 (September 2008)
3634                  * Bit 12 is undefined in any of the following cases:
3635                  *  If the VM exit sets the valid bit in the IDT-vectoring
3636                  *   information field.
3637                  *  If the VM exit is due to a double fault.
3638                  */
3639                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3640                     vector != DF_VECTOR && !idtv_info_valid)
3641                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3642                                       GUEST_INTR_STATE_NMI);
3643         } else if (unlikely(vmx->soft_vnmi_blocked))
3644                 vmx->vnmi_blocked_time +=
3645                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3646
3647         vmx->vcpu.arch.nmi_injected = false;
3648         kvm_clear_exception_queue(&vmx->vcpu);
3649         kvm_clear_interrupt_queue(&vmx->vcpu);
3650
3651         if (!idtv_info_valid)
3652                 return;
3653
3654         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3655         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3656
3657         switch (type) {
3658         case INTR_TYPE_NMI_INTR:
3659                 vmx->vcpu.arch.nmi_injected = true;
3660                 /*
3661                  * SDM 3: 27.7.1.2 (September 2008)
3662                  * Clear bit "block by NMI" before VM entry if a NMI
3663                  * delivery faulted.
3664                  */
3665                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3666                                 GUEST_INTR_STATE_NMI);
3667                 break;
3668         case INTR_TYPE_SOFT_EXCEPTION:
3669                 vmx->vcpu.arch.event_exit_inst_len =
3670                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3671                 /* fall through */
3672         case INTR_TYPE_HARD_EXCEPTION:
3673                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3674                         u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3675                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
3676                 } else
3677                         kvm_queue_exception(&vmx->vcpu, vector);
3678                 break;
3679         case INTR_TYPE_SOFT_INTR:
3680                 vmx->vcpu.arch.event_exit_inst_len =
3681                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3682                 /* fall through */
3683         case INTR_TYPE_EXT_INTR:
3684                 kvm_queue_interrupt(&vmx->vcpu, vector,
3685                         type == INTR_TYPE_SOFT_INTR);
3686                 break;
3687         default:
3688                 break;
3689         }
3690 }
3691
3692 /*
3693  * Failure to inject an interrupt should give us the information
3694  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3695  * when fetching the interrupt redirection bitmap in the real-mode
3696  * tss, this doesn't happen.  So we do it ourselves.
3697  */
3698 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3699 {
3700         vmx->rmode.irq.pending = 0;
3701         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3702                 return;
3703         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3704         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3705                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3706                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3707                 return;
3708         }
3709         vmx->idt_vectoring_info =
3710                 VECTORING_INFO_VALID_MASK
3711                 | INTR_TYPE_EXT_INTR
3712                 | vmx->rmode.irq.vector;
3713 }
3714
3715 #ifdef CONFIG_X86_64
3716 #define R "r"
3717 #define Q "q"
3718 #else
3719 #define R "e"
3720 #define Q "l"
3721 #endif
3722
3723 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3724 {
3725         struct vcpu_vmx *vmx = to_vmx(vcpu);
3726
3727         /* Record the guest's net vcpu time for enforced NMI injections. */
3728         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3729                 vmx->entry_time = ktime_get();
3730
3731         /* Don't enter VMX if guest state is invalid, let the exit handler
3732            start emulation until we arrive back to a valid state */
3733         if (vmx->emulation_required && emulate_invalid_guest_state)
3734                 return;
3735
3736         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3737                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3738         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3739                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3740
3741         /* When single-stepping over STI and MOV SS, we must clear the
3742          * corresponding interruptibility bits in the guest state. Otherwise
3743          * vmentry fails as it then expects bit 14 (BS) in pending debug
3744          * exceptions being set, but that's not correct for the guest debugging
3745          * case. */
3746         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3747                 vmx_set_interrupt_shadow(vcpu, 0);
3748
3749         /*
3750          * Loading guest fpu may have cleared host cr0.ts
3751          */
3752         vmcs_writel(HOST_CR0, read_cr0());
3753
3754         if (vcpu->arch.switch_db_regs)
3755                 set_debugreg(vcpu->arch.dr6, 6);
3756
3757         asm(
3758                 /* Store host registers */
3759                 "push %%"R"dx; push %%"R"bp;"
3760                 "push %%"R"cx \n\t"
3761                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3762                 "je 1f \n\t"
3763                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3764                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3765                 "1: \n\t"
3766                 /* Reload cr2 if changed */
3767                 "mov %c[cr2](%0), %%"R"ax \n\t"
3768                 "mov %%cr2, %%"R"dx \n\t"
3769                 "cmp %%"R"ax, %%"R"dx \n\t"
3770                 "je 2f \n\t"
3771                 "mov %%"R"ax, %%cr2 \n\t"
3772                 "2: \n\t"
3773                 /* Check if vmlaunch of vmresume is needed */
3774                 "cmpl $0, %c[launched](%0) \n\t"
3775                 /* Load guest registers.  Don't clobber flags. */
3776                 "mov %c[rax](%0), %%"R"ax \n\t"
3777                 "mov %c[rbx](%0), %%"R"bx \n\t"
3778                 "mov %c[rdx](%0), %%"R"dx \n\t"
3779                 "mov %c[rsi](%0), %%"R"si \n\t"
3780                 "mov %c[rdi](%0), %%"R"di \n\t"
3781                 "mov %c[rbp](%0), %%"R"bp \n\t"
3782 #ifdef CONFIG_X86_64
3783                 "mov %c[r8](%0),  %%r8  \n\t"
3784                 "mov %c[r9](%0),  %%r9  \n\t"
3785                 "mov %c[r10](%0), %%r10 \n\t"
3786                 "mov %c[r11](%0), %%r11 \n\t"
3787                 "mov %c[r12](%0), %%r12 \n\t"
3788                 "mov %c[r13](%0), %%r13 \n\t"
3789                 "mov %c[r14](%0), %%r14 \n\t"
3790                 "mov %c[r15](%0), %%r15 \n\t"
3791 #endif
3792                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3793
3794                 /* Enter guest mode */
3795                 "jne .Llaunched \n\t"
3796                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3797                 "jmp .Lkvm_vmx_return \n\t"
3798                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3799                 ".Lkvm_vmx_return: "
3800                 /* Save guest registers, load host registers, keep flags */
3801                 "xchg %0,     (%%"R"sp) \n\t"
3802                 "mov %%"R"ax, %c[rax](%0) \n\t"
3803                 "mov %%"R"bx, %c[rbx](%0) \n\t"
3804                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3805                 "mov %%"R"dx, %c[rdx](%0) \n\t"
3806                 "mov %%"R"si, %c[rsi](%0) \n\t"
3807                 "mov %%"R"di, %c[rdi](%0) \n\t"
3808                 "mov %%"R"bp, %c[rbp](%0) \n\t"
3809 #ifdef CONFIG_X86_64
3810                 "mov %%r8,  %c[r8](%0) \n\t"
3811                 "mov %%r9,  %c[r9](%0) \n\t"
3812                 "mov %%r10, %c[r10](%0) \n\t"
3813                 "mov %%r11, %c[r11](%0) \n\t"
3814                 "mov %%r12, %c[r12](%0) \n\t"
3815                 "mov %%r13, %c[r13](%0) \n\t"
3816                 "mov %%r14, %c[r14](%0) \n\t"
3817                 "mov %%r15, %c[r15](%0) \n\t"
3818 #endif
3819                 "mov %%cr2, %%"R"ax   \n\t"
3820                 "mov %%"R"ax, %c[cr2](%0) \n\t"
3821
3822                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
3823                 "setbe %c[fail](%0) \n\t"
3824               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3825                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3826                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3827                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3828                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3829                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3830                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3831                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3832                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3833                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3834                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3835 #ifdef CONFIG_X86_64
3836                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3837                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3838                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3839                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3840                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3841                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3842                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3843                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3844 #endif
3845                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3846               : "cc", "memory"
3847                 , R"bx", R"di", R"si"
3848 #ifdef CONFIG_X86_64
3849                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3850 #endif
3851               );
3852
3853         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3854                                   | (1 << VCPU_EXREG_PDPTR));
3855         vcpu->arch.regs_dirty = 0;
3856
3857         if (vcpu->arch.switch_db_regs)
3858                 get_debugreg(vcpu->arch.dr6, 6);
3859
3860         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3861         if (vmx->rmode.irq.pending)
3862                 fixup_rmode_irq(vmx);
3863
3864         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3865         vmx->launched = 1;
3866
3867         vmx_complete_interrupts(vmx);
3868 }
3869
3870 #undef R
3871 #undef Q
3872
3873 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3874 {
3875         struct vcpu_vmx *vmx = to_vmx(vcpu);
3876
3877         if (vmx->vmcs) {
3878                 vcpu_clear(vmx);
3879                 free_vmcs(vmx->vmcs);
3880                 vmx->vmcs = NULL;
3881         }
3882 }
3883
3884 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3885 {
3886         struct vcpu_vmx *vmx = to_vmx(vcpu);
3887
3888         spin_lock(&vmx_vpid_lock);
3889         if (vmx->vpid != 0)
3890                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3891         spin_unlock(&vmx_vpid_lock);
3892         vmx_free_vmcs(vcpu);
3893         kfree(vmx->guest_msrs);
3894         kvm_vcpu_uninit(vcpu);
3895         kmem_cache_free(kvm_vcpu_cache, vmx);
3896 }
3897
3898 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3899 {
3900         int err;
3901         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3902         int cpu;
3903
3904         if (!vmx)
3905                 return ERR_PTR(-ENOMEM);
3906
3907         allocate_vpid(vmx);
3908
3909         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3910         if (err)
3911                 goto free_vcpu;
3912
3913         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3914         if (!vmx->guest_msrs) {
3915                 err = -ENOMEM;
3916                 goto uninit_vcpu;
3917         }
3918
3919         vmx->vmcs = alloc_vmcs();
3920         if (!vmx->vmcs)
3921                 goto free_msrs;
3922
3923         vmcs_clear(vmx->vmcs);
3924
3925         cpu = get_cpu();
3926         vmx_vcpu_load(&vmx->vcpu, cpu);
3927         err = vmx_vcpu_setup(vmx);
3928         vmx_vcpu_put(&vmx->vcpu);
3929         put_cpu();
3930         if (err)
3931                 goto free_vmcs;
3932         if (vm_need_virtualize_apic_accesses(kvm))
3933                 if (alloc_apic_access_page(kvm) != 0)
3934                         goto free_vmcs;
3935
3936         if (enable_ept) {
3937                 if (!kvm->arch.ept_identity_map_addr)
3938                         kvm->arch.ept_identity_map_addr =
3939                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3940                 if (alloc_identity_pagetable(kvm) != 0)
3941                         goto free_vmcs;
3942         }
3943
3944         return &vmx->vcpu;
3945
3946 free_vmcs:
3947         free_vmcs(vmx->vmcs);
3948 free_msrs:
3949         kfree(vmx->guest_msrs);
3950 uninit_vcpu:
3951         kvm_vcpu_uninit(&vmx->vcpu);
3952 free_vcpu:
3953         kmem_cache_free(kvm_vcpu_cache, vmx);
3954         return ERR_PTR(err);
3955 }
3956
3957 static void __init vmx_check_processor_compat(void *rtn)
3958 {
3959         struct vmcs_config vmcs_conf;
3960
3961         *(int *)rtn = 0;
3962         if (setup_vmcs_config(&vmcs_conf) < 0)
3963                 *(int *)rtn = -EIO;
3964         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3965                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3966                                 smp_processor_id());
3967                 *(int *)rtn = -EIO;
3968         }
3969 }
3970
3971 static int get_ept_level(void)
3972 {
3973         return VMX_EPT_DEFAULT_GAW + 1;
3974 }
3975
3976 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3977 {
3978         u64 ret;
3979
3980         /* For VT-d and EPT combination
3981          * 1. MMIO: always map as UC
3982          * 2. EPT with VT-d:
3983          *   a. VT-d without snooping control feature: can't guarantee the
3984          *      result, try to trust guest.
3985          *   b. VT-d with snooping control feature: snooping control feature of
3986          *      VT-d engine can guarantee the cache correctness. Just set it
3987          *      to WB to keep consistent with host. So the same as item 3.
3988          * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3989          *    consistent with host MTRR
3990          */
3991         if (is_mmio)
3992                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
3993         else if (vcpu->kvm->arch.iommu_domain &&
3994                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3995                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3996                       VMX_EPT_MT_EPTE_SHIFT;
3997         else
3998                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3999                         | VMX_EPT_IGMT_BIT;
4000
4001         return ret;
4002 }
4003
4004 #define _ER(x) { EXIT_REASON_##x, #x }
4005
4006 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4007         _ER(EXCEPTION_NMI),
4008         _ER(EXTERNAL_INTERRUPT),
4009         _ER(TRIPLE_FAULT),
4010         _ER(PENDING_INTERRUPT),
4011         _ER(NMI_WINDOW),
4012         _ER(TASK_SWITCH),
4013         _ER(CPUID),
4014         _ER(HLT),
4015         _ER(INVLPG),
4016         _ER(RDPMC),
4017         _ER(RDTSC),
4018         _ER(VMCALL),
4019         _ER(VMCLEAR),
4020         _ER(VMLAUNCH),
4021         _ER(VMPTRLD),
4022         _ER(VMPTRST),
4023         _ER(VMREAD),
4024         _ER(VMRESUME),
4025         _ER(VMWRITE),
4026         _ER(VMOFF),
4027         _ER(VMON),
4028         _ER(CR_ACCESS),
4029         _ER(DR_ACCESS),
4030         _ER(IO_INSTRUCTION),
4031         _ER(MSR_READ),
4032         _ER(MSR_WRITE),
4033         _ER(MWAIT_INSTRUCTION),
4034         _ER(MONITOR_INSTRUCTION),
4035         _ER(PAUSE_INSTRUCTION),
4036         _ER(MCE_DURING_VMENTRY),
4037         _ER(TPR_BELOW_THRESHOLD),
4038         _ER(APIC_ACCESS),
4039         _ER(EPT_VIOLATION),
4040         _ER(EPT_MISCONFIG),
4041         _ER(WBINVD),
4042         { -1, NULL }
4043 };
4044
4045 #undef _ER
4046
4047 static int vmx_get_lpage_level(void)
4048 {
4049         if (enable_ept && !cpu_has_vmx_ept_1g_page())
4050                 return PT_DIRECTORY_LEVEL;
4051         else
4052                 /* For shadow and EPT supported 1GB page */
4053                 return PT_PDPE_LEVEL;
4054 }
4055
4056 static inline u32 bit(int bitno)
4057 {
4058         return 1 << (bitno & 31);
4059 }
4060
4061 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4062 {
4063         struct kvm_cpuid_entry2 *best;
4064         struct vcpu_vmx *vmx = to_vmx(vcpu);
4065         u32 exec_control;
4066
4067         vmx->rdtscp_enabled = false;
4068         if (vmx_rdtscp_supported()) {
4069                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4070                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4071                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4072                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4073                                 vmx->rdtscp_enabled = true;
4074                         else {
4075                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4076                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4077                                                 exec_control);
4078                         }
4079                 }
4080         }
4081 }
4082
4083 static struct kvm_x86_ops vmx_x86_ops = {
4084         .cpu_has_kvm_support = cpu_has_kvm_support,
4085         .disabled_by_bios = vmx_disabled_by_bios,
4086         .hardware_setup = hardware_setup,
4087         .hardware_unsetup = hardware_unsetup,
4088         .check_processor_compatibility = vmx_check_processor_compat,
4089         .hardware_enable = hardware_enable,
4090         .hardware_disable = hardware_disable,
4091         .cpu_has_accelerated_tpr = report_flexpriority,
4092
4093         .vcpu_create = vmx_create_vcpu,
4094         .vcpu_free = vmx_free_vcpu,
4095         .vcpu_reset = vmx_vcpu_reset,
4096
4097         .prepare_guest_switch = vmx_save_host_state,
4098         .vcpu_load = vmx_vcpu_load,
4099         .vcpu_put = vmx_vcpu_put,
4100
4101         .set_guest_debug = set_guest_debug,
4102         .get_msr = vmx_get_msr,
4103         .set_msr = vmx_set_msr,
4104         .get_segment_base = vmx_get_segment_base,
4105         .get_segment = vmx_get_segment,
4106         .set_segment = vmx_set_segment,
4107         .get_cpl = vmx_get_cpl,
4108         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4109         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4110         .set_cr0 = vmx_set_cr0,
4111         .set_cr3 = vmx_set_cr3,
4112         .set_cr4 = vmx_set_cr4,
4113         .set_efer = vmx_set_efer,
4114         .get_idt = vmx_get_idt,
4115         .set_idt = vmx_set_idt,
4116         .get_gdt = vmx_get_gdt,
4117         .set_gdt = vmx_set_gdt,
4118         .cache_reg = vmx_cache_reg,
4119         .get_rflags = vmx_get_rflags,
4120         .set_rflags = vmx_set_rflags,
4121
4122         .tlb_flush = vmx_flush_tlb,
4123
4124         .run = vmx_vcpu_run,
4125         .handle_exit = vmx_handle_exit,
4126         .skip_emulated_instruction = skip_emulated_instruction,
4127         .set_interrupt_shadow = vmx_set_interrupt_shadow,
4128         .get_interrupt_shadow = vmx_get_interrupt_shadow,
4129         .patch_hypercall = vmx_patch_hypercall,
4130         .set_irq = vmx_inject_irq,
4131         .set_nmi = vmx_inject_nmi,
4132         .queue_exception = vmx_queue_exception,
4133         .interrupt_allowed = vmx_interrupt_allowed,
4134         .nmi_allowed = vmx_nmi_allowed,
4135         .get_nmi_mask = vmx_get_nmi_mask,
4136         .set_nmi_mask = vmx_set_nmi_mask,
4137         .enable_nmi_window = enable_nmi_window,
4138         .enable_irq_window = enable_irq_window,
4139         .update_cr8_intercept = update_cr8_intercept,
4140
4141         .set_tss_addr = vmx_set_tss_addr,
4142         .get_tdp_level = get_ept_level,
4143         .get_mt_mask = vmx_get_mt_mask,
4144
4145         .exit_reasons_str = vmx_exit_reasons_str,
4146         .get_lpage_level = vmx_get_lpage_level,
4147
4148         .cpuid_update = vmx_cpuid_update,
4149
4150         .rdtscp_supported = vmx_rdtscp_supported,
4151 };
4152
4153 static int __init vmx_init(void)
4154 {
4155         int r, i;
4156
4157         rdmsrl_safe(MSR_EFER, &host_efer);
4158
4159         for (i = 0; i < NR_VMX_MSR; ++i)
4160                 kvm_define_shared_msr(i, vmx_msr_index[i]);
4161
4162         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4163         if (!vmx_io_bitmap_a)
4164                 return -ENOMEM;
4165
4166         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4167         if (!vmx_io_bitmap_b) {
4168                 r = -ENOMEM;
4169                 goto out;
4170         }
4171
4172         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4173         if (!vmx_msr_bitmap_legacy) {
4174                 r = -ENOMEM;
4175                 goto out1;
4176         }
4177
4178         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4179         if (!vmx_msr_bitmap_longmode) {
4180                 r = -ENOMEM;
4181                 goto out2;
4182         }
4183
4184         /*
4185          * Allow direct access to the PC debug port (it is often used for I/O
4186          * delays, but the vmexits simply slow things down).
4187          */
4188         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4189         clear_bit(0x80, vmx_io_bitmap_a);
4190
4191         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4192
4193         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4194         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4195
4196         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4197
4198         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
4199         if (r)
4200                 goto out3;
4201
4202         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4203         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4204         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4205         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4206         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4207         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4208
4209         if (enable_ept) {
4210                 bypass_guest_pf = 0;
4211                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4212                         VMX_EPT_WRITABLE_MASK);
4213                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4214                                 VMX_EPT_EXECUTABLE_MASK);
4215                 kvm_enable_tdp();
4216         } else
4217                 kvm_disable_tdp();
4218
4219         if (bypass_guest_pf)
4220                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4221
4222         return 0;
4223
4224 out3:
4225         free_page((unsigned long)vmx_msr_bitmap_longmode);
4226 out2:
4227         free_page((unsigned long)vmx_msr_bitmap_legacy);
4228 out1:
4229         free_page((unsigned long)vmx_io_bitmap_b);
4230 out:
4231         free_page((unsigned long)vmx_io_bitmap_a);
4232         return r;
4233 }
4234
4235 static void __exit vmx_exit(void)
4236 {
4237         free_page((unsigned long)vmx_msr_bitmap_legacy);
4238         free_page((unsigned long)vmx_msr_bitmap_longmode);
4239         free_page((unsigned long)vmx_io_bitmap_b);
4240         free_page((unsigned long)vmx_io_bitmap_a);
4241
4242         kvm_exit();
4243 }
4244
4245 module_init(vmx_init)
4246 module_exit(vmx_exit)