SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/mm.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27 #include <linux/moduleparam.h>
  28 #include "kvm_cache_regs.h"
  29 #include "x86.h"
  30
  31 #include <asm/io.h>
  32 #include <asm/desc.h>
  33 #include <asm/vmx.h>
  34 #include <asm/virtext.h>
  35
  36 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  37
  38 MODULE_AUTHOR("Qumranet");
  39 MODULE_LICENSE("GPL");
  40
  41 static int __read_mostly bypass_guest_pf = 1;
  42 module_param(bypass_guest_pf, bool, S_IRUGO);
  43
  44 static int __read_mostly enable_vpid = 1;
  45 module_param_named(vpid, enable_vpid, bool, 0444);
  46
  47 static int __read_mostly flexpriority_enabled = 1;
  48 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  49
  50 static int __read_mostly enable_ept = 1;
  51 module_param_named(ept, enable_ept, bool, S_IRUGO);
  52
  53 static int __read_mostly emulate_invalid_guest_state = 0;
  54 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  55
  56 struct vmcs {
  57         u32 revision_id;
  58         u32 abort;
  59         char data[0];
  60 };
  61
  62 struct vcpu_vmx {
  63         struct kvm_vcpu       vcpu;
  64         struct list_head      local_vcpus_link;
  65         unsigned long         host_rsp;
  66         int                   launched;
  67         u8                    fail;
  68         u32                   idt_vectoring_info;
  69         struct kvm_msr_entry *guest_msrs;
  70         struct kvm_msr_entry *host_msrs;
  71         int                   nmsrs;
  72         int                   save_nmsrs;
  73         int                   msr_offset_efer;
  74 #ifdef CONFIG_X86_64
  75         int                   msr_offset_kernel_gs_base;
  76 #endif
  77         struct vmcs          *vmcs;
  78         struct {
  79                 int           loaded;
  80                 u16           fs_sel, gs_sel, ldt_sel;
  81                 int           gs_ldt_reload_needed;
  82                 int           fs_reload_needed;
  83                 int           guest_efer_loaded;
  84         } host_state;
  85         struct {
  86                 struct {
  87                         bool pending;
  88                         u8 vector;
  89                         unsigned rip;
  90                 } irq;
  91         } rmode;
  92         int vpid;
  93         bool emulation_required;
  94         enum emulation_result invalid_state_emulation_result;
  95
  96         /* Support for vnmi-less CPUs */
  97         int soft_vnmi_blocked;
  98         ktime_t entry_time;
  99         s64 vnmi_blocked_time;
 100 };
 101
 102 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 103 {
 104         return container_of(vcpu, struct vcpu_vmx, vcpu);
 105 }
 106
 107 static int init_rmode(struct kvm *kvm);
 108 static u64 construct_eptp(unsigned long root_hpa);
 109
 110 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 111 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 112 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 113
 114 static unsigned long *vmx_io_bitmap_a;
 115 static unsigned long *vmx_io_bitmap_b;
 116 static unsigned long *vmx_msr_bitmap_legacy;
 117 static unsigned long *vmx_msr_bitmap_longmode;
 118
 119 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 120 static DEFINE_SPINLOCK(vmx_vpid_lock);
 121
 122 static struct vmcs_config {
 123         int size;
 124         int order;
 125         u32 revision_id;
 126         u32 pin_based_exec_ctrl;
 127         u32 cpu_based_exec_ctrl;
 128         u32 cpu_based_2nd_exec_ctrl;
 129         u32 vmexit_ctrl;
 130         u32 vmentry_ctrl;
 131 } vmcs_config;
 132
 133 static struct vmx_capability {
 134         u32 ept;
 135         u32 vpid;
 136 } vmx_capability;
 137
 138 #define VMX_SEGMENT_FIELD(seg)                                  \
 139         [VCPU_SREG_##seg] = {                                   \
 140                 .selector = GUEST_##seg##_SELECTOR,             \
 141                 .base = GUEST_##seg##_BASE,                     \
 142                 .limit = GUEST_##seg##_LIMIT,                   \
 143                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 144         }
 145
 146 static struct kvm_vmx_segment_field {
 147         unsigned selector;
 148         unsigned base;
 149         unsigned limit;
 150         unsigned ar_bytes;
 151 } kvm_vmx_segment_fields[] = {
 152         VMX_SEGMENT_FIELD(CS),
 153         VMX_SEGMENT_FIELD(DS),
 154         VMX_SEGMENT_FIELD(ES),
 155         VMX_SEGMENT_FIELD(FS),
 156         VMX_SEGMENT_FIELD(GS),
 157         VMX_SEGMENT_FIELD(SS),
 158         VMX_SEGMENT_FIELD(TR),
 159         VMX_SEGMENT_FIELD(LDTR),
 160 };
 161
 162 /*
 163  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 164  * away by decrementing the array size.
 165  */
 166 static const u32 vmx_msr_index[] = {
 167 #ifdef CONFIG_X86_64
 168         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
 169 #endif
 170         MSR_EFER, MSR_K6_STAR,
 171 };
 172 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 173
 174 static void load_msrs(struct kvm_msr_entry *e, int n)
 175 {
 176         int i;
 177
 178         for (i = 0; i < n; ++i)
 179                 wrmsrl(e[i].index, e[i].data);
 180 }
 181
 182 static void save_msrs(struct kvm_msr_entry *e, int n)
 183 {
 184         int i;
 185
 186         for (i = 0; i < n; ++i)
 187                 rdmsrl(e[i].index, e[i].data);
 188 }
 189
 190 static inline int is_page_fault(u32 intr_info)
 191 {
 192         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 193                              INTR_INFO_VALID_MASK)) ==
 194                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 195 }
 196
 197 static inline int is_no_device(u32 intr_info)
 198 {
 199         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 200                              INTR_INFO_VALID_MASK)) ==
 201                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 202 }
 203
 204 static inline int is_invalid_opcode(u32 intr_info)
 205 {
 206         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 207                              INTR_INFO_VALID_MASK)) ==
 208                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 209 }
 210
 211 static inline int is_external_interrupt(u32 intr_info)
 212 {
 213         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 214                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 215 }
 216
 217 static inline int cpu_has_vmx_msr_bitmap(void)
 218 {
 219         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 220 }
 221
 222 static inline int cpu_has_vmx_tpr_shadow(void)
 223 {
 224         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 225 }
 226
 227 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 228 {
 229         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 230 }
 231
 232 static inline int cpu_has_secondary_exec_ctrls(void)
 233 {
 234         return vmcs_config.cpu_based_exec_ctrl &
 235                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 236 }
 237
 238 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 239 {
 240         return vmcs_config.cpu_based_2nd_exec_ctrl &
 241                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 242 }
 243
 244 static inline bool cpu_has_vmx_flexpriority(void)
 245 {
 246         return cpu_has_vmx_tpr_shadow() &&
 247                 cpu_has_vmx_virtualize_apic_accesses();
 248 }
 249
 250 static inline int cpu_has_vmx_invept_individual_addr(void)
 251 {
 252         return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
 253 }
 254
 255 static inline int cpu_has_vmx_invept_context(void)
 256 {
 257         return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
 258 }
 259
 260 static inline int cpu_has_vmx_invept_global(void)
 261 {
 262         return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
 263 }
 264
 265 static inline int cpu_has_vmx_ept(void)
 266 {
 267         return vmcs_config.cpu_based_2nd_exec_ctrl &
 268                 SECONDARY_EXEC_ENABLE_EPT;
 269 }
 270
 271 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 272 {
 273         return flexpriority_enabled &&
 274                 (cpu_has_vmx_virtualize_apic_accesses()) &&
 275                 (irqchip_in_kernel(kvm));
 276 }
 277
 278 static inline int cpu_has_vmx_vpid(void)
 279 {
 280         return vmcs_config.cpu_based_2nd_exec_ctrl &
 281                 SECONDARY_EXEC_ENABLE_VPID;
 282 }
 283
 284 static inline int cpu_has_virtual_nmis(void)
 285 {
 286         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 287 }
 288
 289 static inline bool report_flexpriority(void)
 290 {
 291         return flexpriority_enabled;
 292 }
 293
 294 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 295 {
 296         int i;
 297
 298         for (i = 0; i < vmx->nmsrs; ++i)
 299                 if (vmx->guest_msrs[i].index == msr)
 300                         return i;
 301         return -1;
 302 }
 303
 304 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 305 {
 306     struct {
 307         u64 vpid : 16;
 308         u64 rsvd : 48;
 309         u64 gva;
 310     } operand = { vpid, 0, gva };
 311
 312     asm volatile (__ex(ASM_VMX_INVVPID)
 313                   /* CF==1 or ZF==1 --> rc = -1 */
 314                   "; ja 1f ; ud2 ; 1:"
 315                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 316 }
 317
 318 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 319 {
 320         struct {
 321                 u64 eptp, gpa;
 322         } operand = {eptp, gpa};
 323
 324         asm volatile (__ex(ASM_VMX_INVEPT)
 325                         /* CF==1 or ZF==1 --> rc = -1 */
 326                         "; ja 1f ; ud2 ; 1:\n"
 327                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 328 }
 329
 330 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 331 {
 332         int i;
 333
 334         i = __find_msr_index(vmx, msr);
 335         if (i >= 0)
 336                 return &vmx->guest_msrs[i];
 337         return NULL;
 338 }
 339
 340 static void vmcs_clear(struct vmcs *vmcs)
 341 {
 342         u64 phys_addr = __pa(vmcs);
 343         u8 error;
 344
 345         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 346                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 347                       : "cc", "memory");
 348         if (error)
 349                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 350                        vmcs, phys_addr);
 351 }
 352
 353 static void __vcpu_clear(void *arg)
 354 {
 355         struct vcpu_vmx *vmx = arg;
 356         int cpu = raw_smp_processor_id();
 357
 358         if (vmx->vcpu.cpu == cpu)
 359                 vmcs_clear(vmx->vmcs);
 360         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 361                 per_cpu(current_vmcs, cpu) = NULL;
 362         rdtscll(vmx->vcpu.arch.host_tsc);
 363         list_del(&vmx->local_vcpus_link);
 364         vmx->vcpu.cpu = -1;
 365         vmx->launched = 0;
 366 }
 367
 368 static void vcpu_clear(struct vcpu_vmx *vmx)
 369 {
 370         if (vmx->vcpu.cpu == -1)
 371                 return;
 372         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 373 }
 374
 375 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 376 {
 377         if (vmx->vpid == 0)
 378                 return;
 379
 380         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 381 }
 382
 383 static inline void ept_sync_global(void)
 384 {
 385         if (cpu_has_vmx_invept_global())
 386                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 387 }
 388
 389 static inline void ept_sync_context(u64 eptp)
 390 {
 391         if (enable_ept) {
 392                 if (cpu_has_vmx_invept_context())
 393                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 394                 else
 395                         ept_sync_global();
 396         }
 397 }
 398
 399 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 400 {
 401         if (enable_ept) {
 402                 if (cpu_has_vmx_invept_individual_addr())
 403                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 404                                         eptp, gpa);
 405                 else
 406                         ept_sync_context(eptp);
 407         }
 408 }
 409
 410 static unsigned long vmcs_readl(unsigned long field)
 411 {
 412         unsigned long value;
 413
 414         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 415                       : "=a"(value) : "d"(field) : "cc");
 416         return value;
 417 }
 418
 419 static u16 vmcs_read16(unsigned long field)
 420 {
 421         return vmcs_readl(field);
 422 }
 423
 424 static u32 vmcs_read32(unsigned long field)
 425 {
 426         return vmcs_readl(field);
 427 }
 428
 429 static u64 vmcs_read64(unsigned long field)
 430 {
 431 #ifdef CONFIG_X86_64
 432         return vmcs_readl(field);
 433 #else
 434         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 435 #endif
 436 }
 437
 438 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 439 {
 440         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 441                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 442         dump_stack();
 443 }
 444
 445 static void vmcs_writel(unsigned long field, unsigned long value)
 446 {
 447         u8 error;
 448
 449         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 450                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 451         if (unlikely(error))
 452                 vmwrite_error(field, value);
 453 }
 454
 455 static void vmcs_write16(unsigned long field, u16 value)
 456 {
 457         vmcs_writel(field, value);
 458 }
 459
 460 static void vmcs_write32(unsigned long field, u32 value)
 461 {
 462         vmcs_writel(field, value);
 463 }
 464
 465 static void vmcs_write64(unsigned long field, u64 value)
 466 {
 467         vmcs_writel(field, value);
 468 #ifndef CONFIG_X86_64
 469         asm volatile ("");
 470         vmcs_writel(field+1, value >> 32);
 471 #endif
 472 }
 473
 474 static void vmcs_clear_bits(unsigned long field, u32 mask)
 475 {
 476         vmcs_writel(field, vmcs_readl(field) & ~mask);
 477 }
 478
 479 static void vmcs_set_bits(unsigned long field, u32 mask)
 480 {
 481         vmcs_writel(field, vmcs_readl(field) | mask);
 482 }
 483
 484 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 485 {
 486         u32 eb;
 487
 488         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
 489         if (!vcpu->fpu_active)
 490                 eb |= 1u << NM_VECTOR;
 491         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
 492                 if (vcpu->guest_debug &
 493                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
 494                         eb |= 1u << DB_VECTOR;
 495                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
 496                         eb |= 1u << BP_VECTOR;
 497         }
 498         if (vcpu->arch.rmode.active)
 499                 eb = ~0;
 500         if (enable_ept)
 501                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 502         vmcs_write32(EXCEPTION_BITMAP, eb);
 503 }
 504
 505 static void reload_tss(void)
 506 {
 507         /*
 508          * VT restores TR but not its size.  Useless.
 509          */
 510         struct descriptor_table gdt;
 511         struct desc_struct *descs;
 512
 513         kvm_get_gdt(&gdt);
 514         descs = (void *)gdt.base;
 515         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 516         load_TR_desc();
 517 }
 518
 519 static void load_transition_efer(struct vcpu_vmx *vmx)
 520 {
 521         int efer_offset = vmx->msr_offset_efer;
 522         u64 host_efer = vmx->host_msrs[efer_offset].data;
 523         u64 guest_efer = vmx->guest_msrs[efer_offset].data;
 524         u64 ignore_bits;
 525
 526         if (efer_offset < 0)
 527                 return;
 528         /*
 529          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 530          * outside long mode
 531          */
 532         ignore_bits = EFER_NX | EFER_SCE;
 533 #ifdef CONFIG_X86_64
 534         ignore_bits |= EFER_LMA | EFER_LME;
 535         /* SCE is meaningful only in long mode on Intel */
 536         if (guest_efer & EFER_LMA)
 537                 ignore_bits &= ~(u64)EFER_SCE;
 538 #endif
 539         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
 540                 return;
 541
 542         vmx->host_state.guest_efer_loaded = 1;
 543         guest_efer &= ~ignore_bits;
 544         guest_efer |= host_efer & ignore_bits;
 545         wrmsrl(MSR_EFER, guest_efer);
 546         vmx->vcpu.stat.efer_reload++;
 547 }
 548
 549 static void reload_host_efer(struct vcpu_vmx *vmx)
 550 {
 551         if (vmx->host_state.guest_efer_loaded) {
 552                 vmx->host_state.guest_efer_loaded = 0;
 553                 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
 554         }
 555 }
 556
 557 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 558 {
 559         struct vcpu_vmx *vmx = to_vmx(vcpu);
 560
 561         if (vmx->host_state.loaded)
 562                 return;
 563
 564         vmx->host_state.loaded = 1;
 565         /*
 566          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 567          * allow segment selectors with cpl > 0 or ti == 1.
 568          */
 569         vmx->host_state.ldt_sel = kvm_read_ldt();
 570         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 571         vmx->host_state.fs_sel = kvm_read_fs();
 572         if (!(vmx->host_state.fs_sel & 7)) {
 573                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 574                 vmx->host_state.fs_reload_needed = 0;
 575         } else {
 576                 vmcs_write16(HOST_FS_SELECTOR, 0);
 577                 vmx->host_state.fs_reload_needed = 1;
 578         }
 579         vmx->host_state.gs_sel = kvm_read_gs();
 580         if (!(vmx->host_state.gs_sel & 7))
 581                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 582         else {
 583                 vmcs_write16(HOST_GS_SELECTOR, 0);
 584                 vmx->host_state.gs_ldt_reload_needed = 1;
 585         }
 586
 587 #ifdef CONFIG_X86_64
 588         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 589         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 590 #else
 591         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 592         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 593 #endif
 594
 595 #ifdef CONFIG_X86_64
 596         if (is_long_mode(&vmx->vcpu))
 597                 save_msrs(vmx->host_msrs +
 598                           vmx->msr_offset_kernel_gs_base, 1);
 599
 600 #endif
 601         load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 602         load_transition_efer(vmx);
 603 }
 604
 605 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 606 {
 607         unsigned long flags;
 608
 609         if (!vmx->host_state.loaded)
 610                 return;
 611
 612         ++vmx->vcpu.stat.host_state_reload;
 613         vmx->host_state.loaded = 0;
 614         if (vmx->host_state.fs_reload_needed)
 615                 kvm_load_fs(vmx->host_state.fs_sel);
 616         if (vmx->host_state.gs_ldt_reload_needed) {
 617                 kvm_load_ldt(vmx->host_state.ldt_sel);
 618                 /*
 619                  * If we have to reload gs, we must take care to
 620                  * preserve our gs base.
 621                  */
 622                 local_irq_save(flags);
 623                 kvm_load_gs(vmx->host_state.gs_sel);
 624 #ifdef CONFIG_X86_64
 625                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 626 #endif
 627                 local_irq_restore(flags);
 628         }
 629         reload_tss();
 630         save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 631         load_msrs(vmx->host_msrs, vmx->save_nmsrs);
 632         reload_host_efer(vmx);
 633 }
 634
 635 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 636 {
 637         preempt_disable();
 638         __vmx_load_host_state(vmx);
 639         preempt_enable();
 640 }
 641
 642 /*
 643  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 644  * vcpu mutex is already taken.
 645  */
 646 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 647 {
 648         struct vcpu_vmx *vmx = to_vmx(vcpu);
 649         u64 phys_addr = __pa(vmx->vmcs);
 650         u64 tsc_this, delta, new_offset;
 651
 652         if (vcpu->cpu != cpu) {
 653                 vcpu_clear(vmx);
 654                 kvm_migrate_timers(vcpu);
 655                 vpid_sync_vcpu_all(vmx);
 656                 local_irq_disable();
 657                 list_add(&vmx->local_vcpus_link,
 658                          &per_cpu(vcpus_on_cpu, cpu));
 659                 local_irq_enable();
 660         }
 661
 662         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 663                 u8 error;
 664
 665                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 666                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 667                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 668                               : "cc");
 669                 if (error)
 670                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 671                                vmx->vmcs, phys_addr);
 672         }
 673
 674         if (vcpu->cpu != cpu) {
 675                 struct descriptor_table dt;
 676                 unsigned long sysenter_esp;
 677
 678                 vcpu->cpu = cpu;
 679                 /*
 680                  * Linux uses per-cpu TSS and GDT, so set these when switching
 681                  * processors.
 682                  */
 683                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 684                 kvm_get_gdt(&dt);
 685                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 686
 687                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 688                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 689
 690                 /*
 691                  * Make sure the time stamp counter is monotonous.
 692                  */
 693                 rdtscll(tsc_this);
 694                 if (tsc_this < vcpu->arch.host_tsc) {
 695                         delta = vcpu->arch.host_tsc - tsc_this;
 696                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 697                         vmcs_write64(TSC_OFFSET, new_offset);
 698                 }
 699         }
 700 }
 701
 702 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 703 {
 704         __vmx_load_host_state(to_vmx(vcpu));
 705 }
 706
 707 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 708 {
 709         if (vcpu->fpu_active)
 710                 return;
 711         vcpu->fpu_active = 1;
 712         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 713         if (vcpu->arch.cr0 & X86_CR0_TS)
 714                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 715         update_exception_bitmap(vcpu);
 716 }
 717
 718 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 719 {
 720         if (!vcpu->fpu_active)
 721                 return;
 722         vcpu->fpu_active = 0;
 723         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 724         update_exception_bitmap(vcpu);
 725 }
 726
 727 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 728 {
 729         return vmcs_readl(GUEST_RFLAGS);
 730 }
 731
 732 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 733 {
 734         if (vcpu->arch.rmode.active)
 735                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 736         vmcs_writel(GUEST_RFLAGS, rflags);
 737 }
 738
 739 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 740 {
 741         unsigned long rip;
 742         u32 interruptibility;
 743
 744         rip = kvm_rip_read(vcpu);
 745         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 746         kvm_rip_write(vcpu, rip);
 747
 748         /*
 749          * We emulated an instruction, so temporary interrupt blocking
 750          * should be removed, if set.
 751          */
 752         interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 753         if (interruptibility & 3)
 754                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
 755                              interruptibility & ~3);
 756 }
 757
 758 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 759                                 bool has_error_code, u32 error_code)
 760 {
 761         struct vcpu_vmx *vmx = to_vmx(vcpu);
 762         u32 intr_info = nr | INTR_INFO_VALID_MASK;
 763
 764         if (has_error_code) {
 765                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 766                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
 767         }
 768
 769         if (vcpu->arch.rmode.active) {
 770                 vmx->rmode.irq.pending = true;
 771                 vmx->rmode.irq.vector = nr;
 772                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
 773                 if (nr == BP_VECTOR || nr == OF_VECTOR)
 774                         vmx->rmode.irq.rip++;
 775                 intr_info |= INTR_TYPE_SOFT_INTR;
 776                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 777                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
 778                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
 779                 return;
 780         }
 781
 782         if (nr == BP_VECTOR || nr == OF_VECTOR) {
 783                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
 784                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
 785         } else
 786                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
 787
 788         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 789 }
 790
 791 /*
 792  * Swap MSR entry in host/guest MSR entry array.
 793  */
 794 #ifdef CONFIG_X86_64
 795 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 796 {
 797         struct kvm_msr_entry tmp;
 798
 799         tmp = vmx->guest_msrs[to];
 800         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 801         vmx->guest_msrs[from] = tmp;
 802         tmp = vmx->host_msrs[to];
 803         vmx->host_msrs[to] = vmx->host_msrs[from];
 804         vmx->host_msrs[from] = tmp;
 805 }
 806 #endif
 807
 808 /*
 809  * Set up the vmcs to automatically save and restore system
 810  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 811  * mode, as fiddling with msrs is very expensive.
 812  */
 813 static void setup_msrs(struct vcpu_vmx *vmx)
 814 {
 815         int save_nmsrs;
 816         unsigned long *msr_bitmap;
 817
 818         vmx_load_host_state(vmx);
 819         save_nmsrs = 0;
 820 #ifdef CONFIG_X86_64
 821         if (is_long_mode(&vmx->vcpu)) {
 822                 int index;
 823
 824                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 825                 if (index >= 0)
 826                         move_msr_up(vmx, index, save_nmsrs++);
 827                 index = __find_msr_index(vmx, MSR_LSTAR);
 828                 if (index >= 0)
 829                         move_msr_up(vmx, index, save_nmsrs++);
 830                 index = __find_msr_index(vmx, MSR_CSTAR);
 831                 if (index >= 0)
 832                         move_msr_up(vmx, index, save_nmsrs++);
 833                 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 834                 if (index >= 0)
 835                         move_msr_up(vmx, index, save_nmsrs++);
 836                 /*
 837                  * MSR_K6_STAR is only needed on long mode guests, and only
 838                  * if efer.sce is enabled.
 839                  */
 840                 index = __find_msr_index(vmx, MSR_K6_STAR);
 841                 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
 842                         move_msr_up(vmx, index, save_nmsrs++);
 843         }
 844 #endif
 845         vmx->save_nmsrs = save_nmsrs;
 846
 847 #ifdef CONFIG_X86_64
 848         vmx->msr_offset_kernel_gs_base =
 849                 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 850 #endif
 851         vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
 852
 853         if (cpu_has_vmx_msr_bitmap()) {
 854                 if (is_long_mode(&vmx->vcpu))
 855                         msr_bitmap = vmx_msr_bitmap_longmode;
 856                 else
 857                         msr_bitmap = vmx_msr_bitmap_legacy;
 858
 859                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
 860         }
 861 }
 862
 863 /*
 864  * reads and returns guest's timestamp counter "register"
 865  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 866  */
 867 static u64 guest_read_tsc(void)
 868 {
 869         u64 host_tsc, tsc_offset;
 870
 871         rdtscll(host_tsc);
 872         tsc_offset = vmcs_read64(TSC_OFFSET);
 873         return host_tsc + tsc_offset;
 874 }
 875
 876 /*
 877  * writes 'guest_tsc' into guest's timestamp counter "register"
 878  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 879  */
 880 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
 881 {
 882         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 883 }
 884
 885 /*
 886  * Reads an msr value (of 'msr_index') into 'pdata'.
 887  * Returns 0 on success, non-0 otherwise.
 888  * Assumes vcpu_load() was already called.
 889  */
 890 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
 891 {
 892         u64 data;
 893         struct kvm_msr_entry *msr;
 894
 895         if (!pdata) {
 896                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
 897                 return -EINVAL;
 898         }
 899
 900         switch (msr_index) {
 901 #ifdef CONFIG_X86_64
 902         case MSR_FS_BASE:
 903                 data = vmcs_readl(GUEST_FS_BASE);
 904                 break;
 905         case MSR_GS_BASE:
 906                 data = vmcs_readl(GUEST_GS_BASE);
 907                 break;
 908         case MSR_EFER:
 909                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 910 #endif
 911         case MSR_IA32_TIME_STAMP_COUNTER:
 912                 data = guest_read_tsc();
 913                 break;
 914         case MSR_IA32_SYSENTER_CS:
 915                 data = vmcs_read32(GUEST_SYSENTER_CS);
 916                 break;
 917         case MSR_IA32_SYSENTER_EIP:
 918                 data = vmcs_readl(GUEST_SYSENTER_EIP);
 919                 break;
 920         case MSR_IA32_SYSENTER_ESP:
 921                 data = vmcs_readl(GUEST_SYSENTER_ESP);
 922                 break;
 923         default:
 924                 vmx_load_host_state(to_vmx(vcpu));
 925                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
 926                 if (msr) {
 927                         data = msr->data;
 928                         break;
 929                 }
 930                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 931         }
 932
 933         *pdata = data;
 934         return 0;
 935 }
 936
 937 /*
 938  * Writes msr value into into the appropriate "register".
 939  * Returns 0 on success, non-0 otherwise.
 940  * Assumes vcpu_load() was already called.
 941  */
 942 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
 943 {
 944         struct vcpu_vmx *vmx = to_vmx(vcpu);
 945         struct kvm_msr_entry *msr;
 946         u64 host_tsc;
 947         int ret = 0;
 948
 949         switch (msr_index) {
 950         case MSR_EFER:
 951                 vmx_load_host_state(vmx);
 952                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 953                 break;
 954 #ifdef CONFIG_X86_64
 955         case MSR_FS_BASE:
 956                 vmcs_writel(GUEST_FS_BASE, data);
 957                 break;
 958         case MSR_GS_BASE:
 959                 vmcs_writel(GUEST_GS_BASE, data);
 960                 break;
 961 #endif
 962         case MSR_IA32_SYSENTER_CS:
 963                 vmcs_write32(GUEST_SYSENTER_CS, data);
 964                 break;
 965         case MSR_IA32_SYSENTER_EIP:
 966                 vmcs_writel(GUEST_SYSENTER_EIP, data);
 967                 break;
 968         case MSR_IA32_SYSENTER_ESP:
 969                 vmcs_writel(GUEST_SYSENTER_ESP, data);
 970                 break;
 971         case MSR_IA32_TIME_STAMP_COUNTER:
 972                 rdtscll(host_tsc);
 973                 guest_write_tsc(data, host_tsc);
 974                 break;
 975         case MSR_P6_PERFCTR0:
 976         case MSR_P6_PERFCTR1:
 977         case MSR_P6_EVNTSEL0:
 978         case MSR_P6_EVNTSEL1:
 979                 /*
 980                  * Just discard all writes to the performance counters; this
 981                  * should keep both older linux and windows 64-bit guests
 982                  * happy
 983                  */
 984                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
 985
 986                 break;
 987         case MSR_IA32_CR_PAT:
 988                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
 989                         vmcs_write64(GUEST_IA32_PAT, data);
 990                         vcpu->arch.pat = data;
 991                         break;
 992                 }
 993                 /* Otherwise falls through to kvm_set_msr_common */
 994         default:
 995                 vmx_load_host_state(vmx);
 996                 msr = find_msr_entry(vmx, msr_index);
 997                 if (msr) {
 998                         msr->data = data;
 999                         break;
1000                 }
1001                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1002         }
1003
1004         return ret;
1005 }
1006
1007 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1008 {
1009         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1010         switch (reg) {
1011         case VCPU_REGS_RSP:
1012                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1013                 break;
1014         case VCPU_REGS_RIP:
1015                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1016                 break;
1017         default:
1018                 break;
1019         }
1020 }
1021
1022 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1023 {
1024         int old_debug = vcpu->guest_debug;
1025         unsigned long flags;
1026
1027         vcpu->guest_debug = dbg->control;
1028         if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
1029                 vcpu->guest_debug = 0;
1030
1031         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1032                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1033         else
1034                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1035
1036         flags = vmcs_readl(GUEST_RFLAGS);
1037         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1038                 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1039         else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1040                 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1041         vmcs_writel(GUEST_RFLAGS, flags);
1042
1043         update_exception_bitmap(vcpu);
1044
1045         return 0;
1046 }
1047
1048 static __init int cpu_has_kvm_support(void)
1049 {
1050         return cpu_has_vmx();
1051 }
1052
1053 static __init int vmx_disabled_by_bios(void)
1054 {
1055         u64 msr;
1056
1057         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1058         return (msr & (FEATURE_CONTROL_LOCKED |
1059                        FEATURE_CONTROL_VMXON_ENABLED))
1060             == FEATURE_CONTROL_LOCKED;
1061         /* locked but not enabled */
1062 }
1063
1064 static void hardware_enable(void *garbage)
1065 {
1066         int cpu = raw_smp_processor_id();
1067         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1068         u64 old;
1069
1070         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1071         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1072         if ((old & (FEATURE_CONTROL_LOCKED |
1073                     FEATURE_CONTROL_VMXON_ENABLED))
1074             != (FEATURE_CONTROL_LOCKED |
1075                 FEATURE_CONTROL_VMXON_ENABLED))
1076                 /* enable and lock */
1077                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1078                        FEATURE_CONTROL_LOCKED |
1079                        FEATURE_CONTROL_VMXON_ENABLED);
1080         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1081         asm volatile (ASM_VMX_VMXON_RAX
1082                       : : "a"(&phys_addr), "m"(phys_addr)
1083                       : "memory", "cc");
1084 }
1085
1086 static void vmclear_local_vcpus(void)
1087 {
1088         int cpu = raw_smp_processor_id();
1089         struct vcpu_vmx *vmx, *n;
1090
1091         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1092                                  local_vcpus_link)
1093                 __vcpu_clear(vmx);
1094 }
1095
1096
1097 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1098  * tricks.
1099  */
1100 static void kvm_cpu_vmxoff(void)
1101 {
1102         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1103         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1104 }
1105
1106 static void hardware_disable(void *garbage)
1107 {
1108         vmclear_local_vcpus();
1109         kvm_cpu_vmxoff();
1110 }
1111
1112 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1113                                       u32 msr, u32 *result)
1114 {
1115         u32 vmx_msr_low, vmx_msr_high;
1116         u32 ctl = ctl_min | ctl_opt;
1117
1118         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1119
1120         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1121         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1122
1123         /* Ensure minimum (required) set of control bits are supported. */
1124         if (ctl_min & ~ctl)
1125                 return -EIO;
1126
1127         *result = ctl;
1128         return 0;
1129 }
1130
1131 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1132 {
1133         u32 vmx_msr_low, vmx_msr_high;
1134         u32 min, opt, min2, opt2;
1135         u32 _pin_based_exec_control = 0;
1136         u32 _cpu_based_exec_control = 0;
1137         u32 _cpu_based_2nd_exec_control = 0;
1138         u32 _vmexit_control = 0;
1139         u32 _vmentry_control = 0;
1140
1141         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1142         opt = PIN_BASED_VIRTUAL_NMIS;
1143         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1144                                 &_pin_based_exec_control) < 0)
1145                 return -EIO;
1146
1147         min = CPU_BASED_HLT_EXITING |
1148 #ifdef CONFIG_X86_64
1149               CPU_BASED_CR8_LOAD_EXITING |
1150               CPU_BASED_CR8_STORE_EXITING |
1151 #endif
1152               CPU_BASED_CR3_LOAD_EXITING |
1153               CPU_BASED_CR3_STORE_EXITING |
1154               CPU_BASED_USE_IO_BITMAPS |
1155               CPU_BASED_MOV_DR_EXITING |
1156               CPU_BASED_USE_TSC_OFFSETING |
1157               CPU_BASED_INVLPG_EXITING;
1158         opt = CPU_BASED_TPR_SHADOW |
1159               CPU_BASED_USE_MSR_BITMAPS |
1160               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1161         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1162                                 &_cpu_based_exec_control) < 0)
1163                 return -EIO;
1164 #ifdef CONFIG_X86_64
1165         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1166                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1167                                            ~CPU_BASED_CR8_STORE_EXITING;
1168 #endif
1169         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1170                 min2 = 0;
1171                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1172                         SECONDARY_EXEC_WBINVD_EXITING |
1173                         SECONDARY_EXEC_ENABLE_VPID |
1174                         SECONDARY_EXEC_ENABLE_EPT;
1175                 if (adjust_vmx_controls(min2, opt2,
1176                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1177                                         &_cpu_based_2nd_exec_control) < 0)
1178                         return -EIO;
1179         }
1180 #ifndef CONFIG_X86_64
1181         if (!(_cpu_based_2nd_exec_control &
1182                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1183                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1184 #endif
1185         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1186                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1187                    enabled */
1188                 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1189                          CPU_BASED_CR3_STORE_EXITING |
1190                          CPU_BASED_INVLPG_EXITING);
1191                 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1192                                         &_cpu_based_exec_control) < 0)
1193                         return -EIO;
1194                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1195                       vmx_capability.ept, vmx_capability.vpid);
1196         }
1197
1198         min = 0;
1199 #ifdef CONFIG_X86_64
1200         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1201 #endif
1202         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1203         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1204                                 &_vmexit_control) < 0)
1205                 return -EIO;
1206
1207         min = 0;
1208         opt = VM_ENTRY_LOAD_IA32_PAT;
1209         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1210                                 &_vmentry_control) < 0)
1211                 return -EIO;
1212
1213         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1214
1215         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1216         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1217                 return -EIO;
1218
1219 #ifdef CONFIG_X86_64
1220         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1221         if (vmx_msr_high & (1u<<16))
1222                 return -EIO;
1223 #endif
1224
1225         /* Require Write-Back (WB) memory type for VMCS accesses. */
1226         if (((vmx_msr_high >> 18) & 15) != 6)
1227                 return -EIO;
1228
1229         vmcs_conf->size = vmx_msr_high & 0x1fff;
1230         vmcs_conf->order = get_order(vmcs_config.size);
1231         vmcs_conf->revision_id = vmx_msr_low;
1232
1233         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1234         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1235         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1236         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1237         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1238
1239         return 0;
1240 }
1241
1242 static struct vmcs *alloc_vmcs_cpu(int cpu)
1243 {
1244         int node = cpu_to_node(cpu);
1245         struct page *pages;
1246         struct vmcs *vmcs;
1247
1248         pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1249         if (!pages)
1250                 return NULL;
1251         vmcs = page_address(pages);
1252         memset(vmcs, 0, vmcs_config.size);
1253         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1254         return vmcs;
1255 }
1256
1257 static struct vmcs *alloc_vmcs(void)
1258 {
1259         return alloc_vmcs_cpu(raw_smp_processor_id());
1260 }
1261
1262 static void free_vmcs(struct vmcs *vmcs)
1263 {
1264         free_pages((unsigned long)vmcs, vmcs_config.order);
1265 }
1266
1267 static void free_kvm_area(void)
1268 {
1269         int cpu;
1270
1271         for_each_online_cpu(cpu)
1272                 free_vmcs(per_cpu(vmxarea, cpu));
1273 }
1274
1275 static __init int alloc_kvm_area(void)
1276 {
1277         int cpu;
1278
1279         for_each_online_cpu(cpu) {
1280                 struct vmcs *vmcs;
1281
1282                 vmcs = alloc_vmcs_cpu(cpu);
1283                 if (!vmcs) {
1284                         free_kvm_area();
1285                         return -ENOMEM;
1286                 }
1287
1288                 per_cpu(vmxarea, cpu) = vmcs;
1289         }
1290         return 0;
1291 }
1292
1293 static __init int hardware_setup(void)
1294 {
1295         if (setup_vmcs_config(&vmcs_config) < 0)
1296                 return -EIO;
1297
1298         if (boot_cpu_has(X86_FEATURE_NX))
1299                 kvm_enable_efer_bits(EFER_NX);
1300
1301         if (!cpu_has_vmx_vpid())
1302                 enable_vpid = 0;
1303
1304         if (!cpu_has_vmx_ept())
1305                 enable_ept = 0;
1306
1307         if (!cpu_has_vmx_flexpriority())
1308                 flexpriority_enabled = 0;
1309
1310         if (!cpu_has_vmx_tpr_shadow())
1311                 kvm_x86_ops->update_cr8_intercept = NULL;
1312
1313         return alloc_kvm_area();
1314 }
1315
1316 static __exit void hardware_unsetup(void)
1317 {
1318         free_kvm_area();
1319 }
1320
1321 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1322 {
1323         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1324
1325         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1326                 vmcs_write16(sf->selector, save->selector);
1327                 vmcs_writel(sf->base, save->base);
1328                 vmcs_write32(sf->limit, save->limit);
1329                 vmcs_write32(sf->ar_bytes, save->ar);
1330         } else {
1331                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1332                         << AR_DPL_SHIFT;
1333                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1334         }
1335 }
1336
1337 static void enter_pmode(struct kvm_vcpu *vcpu)
1338 {
1339         unsigned long flags;
1340         struct vcpu_vmx *vmx = to_vmx(vcpu);
1341
1342         vmx->emulation_required = 1;
1343         vcpu->arch.rmode.active = 0;
1344
1345         vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1346         vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1347         vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1348
1349         flags = vmcs_readl(GUEST_RFLAGS);
1350         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1351         flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1352         vmcs_writel(GUEST_RFLAGS, flags);
1353
1354         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1355                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1356
1357         update_exception_bitmap(vcpu);
1358
1359         if (emulate_invalid_guest_state)
1360                 return;
1361
1362         fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1363         fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1364         fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1365         fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1366
1367         vmcs_write16(GUEST_SS_SELECTOR, 0);
1368         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1369
1370         vmcs_write16(GUEST_CS_SELECTOR,
1371                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1372         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1373 }
1374
1375 static gva_t rmode_tss_base(struct kvm *kvm)
1376 {
1377         if (!kvm->arch.tss_addr) {
1378                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1379                                  kvm->memslots[0].npages - 3;
1380                 return base_gfn << PAGE_SHIFT;
1381         }
1382         return kvm->arch.tss_addr;
1383 }
1384
1385 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1386 {
1387         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1388
1389         save->selector = vmcs_read16(sf->selector);
1390         save->base = vmcs_readl(sf->base);
1391         save->limit = vmcs_read32(sf->limit);
1392         save->ar = vmcs_read32(sf->ar_bytes);
1393         vmcs_write16(sf->selector, save->base >> 4);
1394         vmcs_write32(sf->base, save->base & 0xfffff);
1395         vmcs_write32(sf->limit, 0xffff);
1396         vmcs_write32(sf->ar_bytes, 0xf3);
1397 }
1398
1399 static void enter_rmode(struct kvm_vcpu *vcpu)
1400 {
1401         unsigned long flags;
1402         struct vcpu_vmx *vmx = to_vmx(vcpu);
1403
1404         vmx->emulation_required = 1;
1405         vcpu->arch.rmode.active = 1;
1406
1407         vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1408         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1409
1410         vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1411         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1412
1413         vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1414         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1415
1416         flags = vmcs_readl(GUEST_RFLAGS);
1417         vcpu->arch.rmode.save_iopl
1418                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1419
1420         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1421
1422         vmcs_writel(GUEST_RFLAGS, flags);
1423         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1424         update_exception_bitmap(vcpu);
1425
1426         if (emulate_invalid_guest_state)
1427                 goto continue_rmode;
1428
1429         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1430         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1431         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1432
1433         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1434         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1435         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1436                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1437         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1438
1439         fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1440         fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1441         fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1442         fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1443
1444 continue_rmode:
1445         kvm_mmu_reset_context(vcpu);
1446         init_rmode(vcpu->kvm);
1447 }
1448
1449 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1450 {
1451         struct vcpu_vmx *vmx = to_vmx(vcpu);
1452         struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1453
1454         vcpu->arch.shadow_efer = efer;
1455         if (!msr)
1456                 return;
1457         if (efer & EFER_LMA) {
1458                 vmcs_write32(VM_ENTRY_CONTROLS,
1459                              vmcs_read32(VM_ENTRY_CONTROLS) |
1460                              VM_ENTRY_IA32E_MODE);
1461                 msr->data = efer;
1462         } else {
1463                 vmcs_write32(VM_ENTRY_CONTROLS,
1464                              vmcs_read32(VM_ENTRY_CONTROLS) &
1465                              ~VM_ENTRY_IA32E_MODE);
1466
1467                 msr->data = efer & ~EFER_LME;
1468         }
1469         setup_msrs(vmx);
1470 }
1471
1472 #ifdef CONFIG_X86_64
1473
1474 static void enter_lmode(struct kvm_vcpu *vcpu)
1475 {
1476         u32 guest_tr_ar;
1477
1478         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1479         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1480                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1481                        __func__);
1482                 vmcs_write32(GUEST_TR_AR_BYTES,
1483                              (guest_tr_ar & ~AR_TYPE_MASK)
1484                              | AR_TYPE_BUSY_64_TSS);
1485         }
1486         vcpu->arch.shadow_efer |= EFER_LMA;
1487         vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
1488 }
1489
1490 static void exit_lmode(struct kvm_vcpu *vcpu)
1491 {
1492         vcpu->arch.shadow_efer &= ~EFER_LMA;
1493
1494         vmcs_write32(VM_ENTRY_CONTROLS,
1495                      vmcs_read32(VM_ENTRY_CONTROLS)
1496                      & ~VM_ENTRY_IA32E_MODE);
1497 }
1498
1499 #endif
1500
1501 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1502 {
1503         vpid_sync_vcpu_all(to_vmx(vcpu));
1504         if (enable_ept)
1505                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1506 }
1507
1508 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1509 {
1510         vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1511         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1512 }
1513
1514 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1515 {
1516         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1517                 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1518                         printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1519                         return;
1520                 }
1521                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1522                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1523                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1524                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1525         }
1526 }
1527
1528 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1529
1530 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1531                                         unsigned long cr0,
1532                                         struct kvm_vcpu *vcpu)
1533 {
1534         if (!(cr0 & X86_CR0_PG)) {
1535                 /* From paging/starting to nonpaging */
1536                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1537                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1538                              (CPU_BASED_CR3_LOAD_EXITING |
1539                               CPU_BASED_CR3_STORE_EXITING));
1540                 vcpu->arch.cr0 = cr0;
1541                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1542                 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1543                 *hw_cr0 &= ~X86_CR0_WP;
1544         } else if (!is_paging(vcpu)) {
1545                 /* From nonpaging to paging */
1546                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1547                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1548                              ~(CPU_BASED_CR3_LOAD_EXITING |
1549                                CPU_BASED_CR3_STORE_EXITING));
1550                 vcpu->arch.cr0 = cr0;
1551                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1552                 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1553                         *hw_cr0 &= ~X86_CR0_WP;
1554         }
1555 }
1556
1557 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1558                                         struct kvm_vcpu *vcpu)
1559 {
1560         if (!is_paging(vcpu)) {
1561                 *hw_cr4 &= ~X86_CR4_PAE;
1562                 *hw_cr4 |= X86_CR4_PSE;
1563         } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1564                 *hw_cr4 &= ~X86_CR4_PAE;
1565 }
1566
1567 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1568 {
1569         unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1570                                 KVM_VM_CR0_ALWAYS_ON;
1571
1572         vmx_fpu_deactivate(vcpu);
1573
1574         if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
1575                 enter_pmode(vcpu);
1576
1577         if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
1578                 enter_rmode(vcpu);
1579
1580 #ifdef CONFIG_X86_64
1581         if (vcpu->arch.shadow_efer & EFER_LME) {
1582                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1583                         enter_lmode(vcpu);
1584                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1585                         exit_lmode(vcpu);
1586         }
1587 #endif
1588
1589         if (enable_ept)
1590                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1591
1592         vmcs_writel(CR0_READ_SHADOW, cr0);
1593         vmcs_writel(GUEST_CR0, hw_cr0);
1594         vcpu->arch.cr0 = cr0;
1595
1596         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1597                 vmx_fpu_activate(vcpu);
1598 }
1599
1600 static u64 construct_eptp(unsigned long root_hpa)
1601 {
1602         u64 eptp;
1603
1604         /* TODO write the value reading from MSR */
1605         eptp = VMX_EPT_DEFAULT_MT |
1606                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1607         eptp |= (root_hpa & PAGE_MASK);
1608
1609         return eptp;
1610 }
1611
1612 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1613 {
1614         unsigned long guest_cr3;
1615         u64 eptp;
1616
1617         guest_cr3 = cr3;
1618         if (enable_ept) {
1619                 eptp = construct_eptp(cr3);
1620                 vmcs_write64(EPT_POINTER, eptp);
1621                 ept_sync_context(eptp);
1622                 ept_load_pdptrs(vcpu);
1623                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1624                         VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1625         }
1626
1627         vmx_flush_tlb(vcpu);
1628         vmcs_writel(GUEST_CR3, guest_cr3);
1629         if (vcpu->arch.cr0 & X86_CR0_PE)
1630                 vmx_fpu_deactivate(vcpu);
1631 }
1632
1633 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1634 {
1635         unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1636                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1637
1638         vcpu->arch.cr4 = cr4;
1639         if (enable_ept)
1640                 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1641
1642         vmcs_writel(CR4_READ_SHADOW, cr4);
1643         vmcs_writel(GUEST_CR4, hw_cr4);
1644 }
1645
1646 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1647 {
1648         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1649
1650         return vmcs_readl(sf->base);
1651 }
1652
1653 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1654                             struct kvm_segment *var, int seg)
1655 {
1656         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1657         u32 ar;
1658
1659         var->base = vmcs_readl(sf->base);
1660         var->limit = vmcs_read32(sf->limit);
1661         var->selector = vmcs_read16(sf->selector);
1662         ar = vmcs_read32(sf->ar_bytes);
1663         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1664                 ar = 0;
1665         var->type = ar & 15;
1666         var->s = (ar >> 4) & 1;
1667         var->dpl = (ar >> 5) & 3;
1668         var->present = (ar >> 7) & 1;
1669         var->avl = (ar >> 12) & 1;
1670         var->l = (ar >> 13) & 1;
1671         var->db = (ar >> 14) & 1;
1672         var->g = (ar >> 15) & 1;
1673         var->unusable = (ar >> 16) & 1;
1674 }
1675
1676 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1677 {
1678         struct kvm_segment kvm_seg;
1679
1680         if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1681                 return 0;
1682
1683         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1684                 return 3;
1685
1686         vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1687         return kvm_seg.selector & 3;
1688 }
1689
1690 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1691 {
1692         u32 ar;
1693
1694         if (var->unusable)
1695                 ar = 1 << 16;
1696         else {
1697                 ar = var->type & 15;
1698                 ar |= (var->s & 1) << 4;
1699                 ar |= (var->dpl & 3) << 5;
1700                 ar |= (var->present & 1) << 7;
1701                 ar |= (var->avl & 1) << 12;
1702                 ar |= (var->l & 1) << 13;
1703                 ar |= (var->db & 1) << 14;
1704                 ar |= (var->g & 1) << 15;
1705         }
1706         if (ar == 0) /* a 0 value means unusable */
1707                 ar = AR_UNUSABLE_MASK;
1708
1709         return ar;
1710 }
1711
1712 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1713                             struct kvm_segment *var, int seg)
1714 {
1715         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1716         u32 ar;
1717
1718         if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1719                 vcpu->arch.rmode.tr.selector = var->selector;
1720                 vcpu->arch.rmode.tr.base = var->base;
1721                 vcpu->arch.rmode.tr.limit = var->limit;
1722                 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1723                 return;
1724         }
1725         vmcs_writel(sf->base, var->base);
1726         vmcs_write32(sf->limit, var->limit);
1727         vmcs_write16(sf->selector, var->selector);
1728         if (vcpu->arch.rmode.active && var->s) {
1729                 /*
1730                  * Hack real-mode segments into vm86 compatibility.
1731                  */
1732                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1733                         vmcs_writel(sf->base, 0xf0000);
1734                 ar = 0xf3;
1735         } else
1736                 ar = vmx_segment_access_rights(var);
1737         vmcs_write32(sf->ar_bytes, ar);
1738 }
1739
1740 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1741 {
1742         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1743
1744         *db = (ar >> 14) & 1;
1745         *l = (ar >> 13) & 1;
1746 }
1747
1748 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1749 {
1750         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1751         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1752 }
1753
1754 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1755 {
1756         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1757         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1758 }
1759
1760 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1761 {
1762         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1763         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1764 }
1765
1766 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1767 {
1768         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1769         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1770 }
1771
1772 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1773 {
1774         struct kvm_segment var;
1775         u32 ar;
1776
1777         vmx_get_segment(vcpu, &var, seg);
1778         ar = vmx_segment_access_rights(&var);
1779
1780         if (var.base != (var.selector << 4))
1781                 return false;
1782         if (var.limit != 0xffff)
1783                 return false;
1784         if (ar != 0xf3)
1785                 return false;
1786
1787         return true;
1788 }
1789
1790 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1791 {
1792         struct kvm_segment cs;
1793         unsigned int cs_rpl;
1794
1795         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1796         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1797
1798         if (cs.unusable)
1799                 return false;
1800         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1801                 return false;
1802         if (!cs.s)
1803                 return false;
1804         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1805                 if (cs.dpl > cs_rpl)
1806                         return false;
1807         } else {
1808                 if (cs.dpl != cs_rpl)
1809                         return false;
1810         }
1811         if (!cs.present)
1812                 return false;
1813
1814         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1815         return true;
1816 }
1817
1818 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1819 {
1820         struct kvm_segment ss;
1821         unsigned int ss_rpl;
1822
1823         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1824         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1825
1826         if (ss.unusable)
1827                 return true;
1828         if (ss.type != 3 && ss.type != 7)
1829                 return false;
1830         if (!ss.s)
1831                 return false;
1832         if (ss.dpl != ss_rpl) /* DPL != RPL */
1833                 return false;
1834         if (!ss.present)
1835                 return false;
1836
1837         return true;
1838 }
1839
1840 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1841 {
1842         struct kvm_segment var;
1843         unsigned int rpl;
1844
1845         vmx_get_segment(vcpu, &var, seg);
1846         rpl = var.selector & SELECTOR_RPL_MASK;
1847
1848         if (var.unusable)
1849                 return true;
1850         if (!var.s)
1851                 return false;
1852         if (!var.present)
1853                 return false;
1854         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1855                 if (var.dpl < rpl) /* DPL < RPL */
1856                         return false;
1857         }
1858
1859         /* TODO: Add other members to kvm_segment_field to allow checking for other access
1860          * rights flags
1861          */
1862         return true;
1863 }
1864
1865 static bool tr_valid(struct kvm_vcpu *vcpu)
1866 {
1867         struct kvm_segment tr;
1868
1869         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1870
1871         if (tr.unusable)
1872                 return false;
1873         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
1874                 return false;
1875         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
1876                 return false;
1877         if (!tr.present)
1878                 return false;
1879
1880         return true;
1881 }
1882
1883 static bool ldtr_valid(struct kvm_vcpu *vcpu)
1884 {
1885         struct kvm_segment ldtr;
1886
1887         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1888
1889         if (ldtr.unusable)
1890                 return true;
1891         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
1892                 return false;
1893         if (ldtr.type != 2)
1894                 return false;
1895         if (!ldtr.present)
1896                 return false;
1897
1898         return true;
1899 }
1900
1901 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
1902 {
1903         struct kvm_segment cs, ss;
1904
1905         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1906         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1907
1908         return ((cs.selector & SELECTOR_RPL_MASK) ==
1909                  (ss.selector & SELECTOR_RPL_MASK));
1910 }
1911
1912 /*
1913  * Check if guest state is valid. Returns true if valid, false if
1914  * not.
1915  * We assume that registers are always usable
1916  */
1917 static bool guest_state_valid(struct kvm_vcpu *vcpu)
1918 {
1919         /* real mode guest state checks */
1920         if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
1921                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
1922                         return false;
1923                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
1924                         return false;
1925                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
1926                         return false;
1927                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
1928                         return false;
1929                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
1930                         return false;
1931                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
1932                         return false;
1933         } else {
1934         /* protected mode guest state checks */
1935                 if (!cs_ss_rpl_check(vcpu))
1936                         return false;
1937                 if (!code_segment_valid(vcpu))
1938                         return false;
1939                 if (!stack_segment_valid(vcpu))
1940                         return false;
1941                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
1942                         return false;
1943                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
1944                         return false;
1945                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
1946                         return false;
1947                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
1948                         return false;
1949                 if (!tr_valid(vcpu))
1950                         return false;
1951                 if (!ldtr_valid(vcpu))
1952                         return false;
1953         }
1954         /* TODO:
1955          * - Add checks on RIP
1956          * - Add checks on RFLAGS
1957          */
1958
1959         return true;
1960 }
1961
1962 static int init_rmode_tss(struct kvm *kvm)
1963 {
1964         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1965         u16 data = 0;
1966         int ret = 0;
1967         int r;
1968
1969         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1970         if (r < 0)
1971                 goto out;
1972         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1973         r = kvm_write_guest_page(kvm, fn++, &data,
1974                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
1975         if (r < 0)
1976                 goto out;
1977         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1978         if (r < 0)
1979                 goto out;
1980         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1981         if (r < 0)
1982                 goto out;
1983         data = ~0;
1984         r = kvm_write_guest_page(kvm, fn, &data,
1985                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1986                                  sizeof(u8));
1987         if (r < 0)
1988                 goto out;
1989
1990         ret = 1;
1991 out:
1992         return ret;
1993 }
1994
1995 static int init_rmode_identity_map(struct kvm *kvm)
1996 {
1997         int i, r, ret;
1998         pfn_t identity_map_pfn;
1999         u32 tmp;
2000
2001         if (!enable_ept)
2002                 return 1;
2003         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2004                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2005                         "haven't been allocated!\n");
2006                 return 0;
2007         }
2008         if (likely(kvm->arch.ept_identity_pagetable_done))
2009                 return 1;
2010         ret = 0;
2011         identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
2012         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2013         if (r < 0)
2014                 goto out;
2015         /* Set up identity-mapping pagetable for EPT in real mode */
2016         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2017                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2018                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2019                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2020                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2021                 if (r < 0)
2022                         goto out;
2023         }
2024         kvm->arch.ept_identity_pagetable_done = true;
2025         ret = 1;
2026 out:
2027         return ret;
2028 }
2029
2030 static void seg_setup(int seg)
2031 {
2032         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2033
2034         vmcs_write16(sf->selector, 0);
2035         vmcs_writel(sf->base, 0);
2036         vmcs_write32(sf->limit, 0xffff);
2037         vmcs_write32(sf->ar_bytes, 0xf3);
2038 }
2039
2040 static int alloc_apic_access_page(struct kvm *kvm)
2041 {
2042         struct kvm_userspace_memory_region kvm_userspace_mem;
2043         int r = 0;
2044
2045         down_write(&kvm->slots_lock);
2046         if (kvm->arch.apic_access_page)
2047                 goto out;
2048         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2049         kvm_userspace_mem.flags = 0;
2050         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2051         kvm_userspace_mem.memory_size = PAGE_SIZE;
2052         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2053         if (r)
2054                 goto out;
2055
2056         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2057 out:
2058         up_write(&kvm->slots_lock);
2059         return r;
2060 }
2061
2062 static int alloc_identity_pagetable(struct kvm *kvm)
2063 {
2064         struct kvm_userspace_memory_region kvm_userspace_mem;
2065         int r = 0;
2066
2067         down_write(&kvm->slots_lock);
2068         if (kvm->arch.ept_identity_pagetable)
2069                 goto out;
2070         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2071         kvm_userspace_mem.flags = 0;
2072         kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2073         kvm_userspace_mem.memory_size = PAGE_SIZE;
2074         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2075         if (r)
2076                 goto out;
2077
2078         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2079                         VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
2080 out:
2081         up_write(&kvm->slots_lock);
2082         return r;
2083 }
2084
2085 static void allocate_vpid(struct vcpu_vmx *vmx)
2086 {
2087         int vpid;
2088
2089         vmx->vpid = 0;
2090         if (!enable_vpid)
2091                 return;
2092         spin_lock(&vmx_vpid_lock);
2093         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2094         if (vpid < VMX_NR_VPIDS) {
2095                 vmx->vpid = vpid;
2096                 __set_bit(vpid, vmx_vpid_bitmap);
2097         }
2098         spin_unlock(&vmx_vpid_lock);
2099 }
2100
2101 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2102 {
2103         int f = sizeof(unsigned long);
2104
2105         if (!cpu_has_vmx_msr_bitmap())
2106                 return;
2107
2108         /*
2109          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2110          * have the write-low and read-high bitmap offsets the wrong way round.
2111          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2112          */
2113         if (msr <= 0x1fff) {
2114                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2115                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2116         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2117                 msr &= 0x1fff;
2118                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2119                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2120         }
2121 }
2122
2123 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2124 {
2125         if (!longmode_only)
2126                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2127         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2128 }
2129
2130 /*
2131  * Sets up the vmcs for emulated real mode.
2132  */
2133 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2134 {
2135         u32 host_sysenter_cs, msr_low, msr_high;
2136         u32 junk;
2137         u64 host_pat, tsc_this, tsc_base;
2138         unsigned long a;
2139         struct descriptor_table dt;
2140         int i;
2141         unsigned long kvm_vmx_return;
2142         u32 exec_control;
2143
2144         /* I/O */
2145         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2146         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2147
2148         if (cpu_has_vmx_msr_bitmap())
2149                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2150
2151         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2152
2153         /* Control */
2154         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2155                 vmcs_config.pin_based_exec_ctrl);
2156
2157         exec_control = vmcs_config.cpu_based_exec_ctrl;
2158         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2159                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2160 #ifdef CONFIG_X86_64
2161                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2162                                 CPU_BASED_CR8_LOAD_EXITING;
2163 #endif
2164         }
2165         if (!enable_ept)
2166                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2167                                 CPU_BASED_CR3_LOAD_EXITING  |
2168                                 CPU_BASED_INVLPG_EXITING;
2169         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2170
2171         if (cpu_has_secondary_exec_ctrls()) {
2172                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2173                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2174                         exec_control &=
2175                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2176                 if (vmx->vpid == 0)
2177                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2178                 if (!enable_ept)
2179                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2180                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2181         }
2182
2183         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2184         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2185         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2186
2187         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
2188         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2189         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2190
2191         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2192         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2193         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2194         vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs());    /* 22.2.4 */
2195         vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs());    /* 22.2.4 */
2196         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2197 #ifdef CONFIG_X86_64
2198         rdmsrl(MSR_FS_BASE, a);
2199         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2200         rdmsrl(MSR_GS_BASE, a);
2201         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2202 #else
2203         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2204         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2205 #endif
2206
2207         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2208
2209         kvm_get_idt(&dt);
2210         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
2211
2212         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2213         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2214         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2215         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2216         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2217
2218         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2219         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2220         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2221         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2222         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2223         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2224
2225         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2226                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2227                 host_pat = msr_low | ((u64) msr_high << 32);
2228                 vmcs_write64(HOST_IA32_PAT, host_pat);
2229         }
2230         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2231                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2232                 host_pat = msr_low | ((u64) msr_high << 32);
2233                 /* Write the default value follow host pat */
2234                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2235                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2236                 vmx->vcpu.arch.pat = host_pat;
2237         }
2238
2239         for (i = 0; i < NR_VMX_MSR; ++i) {
2240                 u32 index = vmx_msr_index[i];
2241                 u32 data_low, data_high;
2242                 u64 data;
2243                 int j = vmx->nmsrs;
2244
2245                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2246                         continue;
2247                 if (wrmsr_safe(index, data_low, data_high) < 0)
2248                         continue;
2249                 data = data_low | ((u64)data_high << 32);
2250                 vmx->host_msrs[j].index = index;
2251                 vmx->host_msrs[j].reserved = 0;
2252                 vmx->host_msrs[j].data = data;
2253                 vmx->guest_msrs[j] = vmx->host_msrs[j];
2254                 ++vmx->nmsrs;
2255         }
2256
2257         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2258
2259         /* 22.2.1, 20.8.1 */
2260         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2261
2262         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2263         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2264
2265         tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2266         rdtscll(tsc_this);
2267         if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2268                 tsc_base = tsc_this;
2269
2270         guest_write_tsc(0, tsc_base);
2271
2272         return 0;
2273 }
2274
2275 static int init_rmode(struct kvm *kvm)
2276 {
2277         if (!init_rmode_tss(kvm))
2278                 return 0;
2279         if (!init_rmode_identity_map(kvm))
2280                 return 0;
2281         return 1;
2282 }
2283
2284 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2285 {
2286         struct vcpu_vmx *vmx = to_vmx(vcpu);
2287         u64 msr;
2288         int ret;
2289
2290         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2291         down_read(&vcpu->kvm->slots_lock);
2292         if (!init_rmode(vmx->vcpu.kvm)) {
2293                 ret = -ENOMEM;
2294                 goto out;
2295         }
2296
2297         vmx->vcpu.arch.rmode.active = 0;
2298
2299         vmx->soft_vnmi_blocked = 0;
2300
2301         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2302         kvm_set_cr8(&vmx->vcpu, 0);
2303         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2304         if (vmx->vcpu.vcpu_id == 0)
2305                 msr |= MSR_IA32_APICBASE_BSP;
2306         kvm_set_apic_base(&vmx->vcpu, msr);
2307
2308         fx_init(&vmx->vcpu);
2309
2310         seg_setup(VCPU_SREG_CS);
2311         /*
2312          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2313          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2314          */
2315         if (vmx->vcpu.vcpu_id == 0) {
2316                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2317                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2318         } else {
2319                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2320                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2321         }
2322
2323         seg_setup(VCPU_SREG_DS);
2324         seg_setup(VCPU_SREG_ES);
2325         seg_setup(VCPU_SREG_FS);
2326         seg_setup(VCPU_SREG_GS);
2327         seg_setup(VCPU_SREG_SS);
2328
2329         vmcs_write16(GUEST_TR_SELECTOR, 0);
2330         vmcs_writel(GUEST_TR_BASE, 0);
2331         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2332         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2333
2334         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2335         vmcs_writel(GUEST_LDTR_BASE, 0);
2336         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2337         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2338
2339         vmcs_write32(GUEST_SYSENTER_CS, 0);
2340         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2341         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2342
2343         vmcs_writel(GUEST_RFLAGS, 0x02);
2344         if (vmx->vcpu.vcpu_id == 0)
2345                 kvm_rip_write(vcpu, 0xfff0);
2346         else
2347                 kvm_rip_write(vcpu, 0);
2348         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2349
2350         vmcs_writel(GUEST_DR7, 0x400);
2351
2352         vmcs_writel(GUEST_GDTR_BASE, 0);
2353         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2354
2355         vmcs_writel(GUEST_IDTR_BASE, 0);
2356         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2357
2358         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2359         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2360         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2361
2362         /* Special registers */
2363         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2364
2365         setup_msrs(vmx);
2366
2367         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2368
2369         if (cpu_has_vmx_tpr_shadow()) {
2370                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2371                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2372                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2373                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2374                 vmcs_write32(TPR_THRESHOLD, 0);
2375         }
2376
2377         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2378                 vmcs_write64(APIC_ACCESS_ADDR,
2379                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2380
2381         if (vmx->vpid != 0)
2382                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2383
2384         vmx->vcpu.arch.cr0 = 0x60000010;
2385         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2386         vmx_set_cr4(&vmx->vcpu, 0);
2387         vmx_set_efer(&vmx->vcpu, 0);
2388         vmx_fpu_activate(&vmx->vcpu);
2389         update_exception_bitmap(&vmx->vcpu);
2390
2391         vpid_sync_vcpu_all(vmx);
2392
2393         ret = 0;
2394
2395         /* HACK: Don't enable emulation on guest boot/reset */
2396         vmx->emulation_required = 0;
2397
2398 out:
2399         up_read(&vcpu->kvm->slots_lock);
2400         return ret;
2401 }
2402
2403 void vmx_drop_interrupt_shadow(struct kvm_vcpu *vcpu)
2404 {
2405         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2406                         GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2407 }
2408
2409 static void enable_irq_window(struct kvm_vcpu *vcpu)
2410 {
2411         u32 cpu_based_vm_exec_control;
2412
2413         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2414         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2415         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2416 }
2417
2418 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2419 {
2420         u32 cpu_based_vm_exec_control;
2421
2422         if (!cpu_has_virtual_nmis()) {
2423                 enable_irq_window(vcpu);
2424                 return;
2425         }
2426
2427         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2428         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2429         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2430 }
2431
2432 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2433 {
2434         struct vcpu_vmx *vmx = to_vmx(vcpu);
2435
2436         KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2437
2438         ++vcpu->stat.irq_injections;
2439         if (vcpu->arch.rmode.active) {
2440                 vmx->rmode.irq.pending = true;
2441                 vmx->rmode.irq.vector = irq;
2442                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2443                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2444                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2445                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2446                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2447                 return;
2448         }
2449         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2450                         irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2451 }
2452
2453 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2454 {
2455         struct vcpu_vmx *vmx = to_vmx(vcpu);
2456
2457         if (!cpu_has_virtual_nmis()) {
2458                 /*
2459                  * Tracking the NMI-blocked state in software is built upon
2460                  * finding the next open IRQ window. This, in turn, depends on
2461                  * well-behaving guests: They have to keep IRQs disabled at
2462                  * least as long as the NMI handler runs. Otherwise we may
2463                  * cause NMI nesting, maybe breaking the guest. But as this is
2464                  * highly unlikely, we can live with the residual risk.
2465                  */
2466                 vmx->soft_vnmi_blocked = 1;
2467                 vmx->vnmi_blocked_time = 0;
2468         }
2469
2470         ++vcpu->stat.nmi_injections;
2471         if (vcpu->arch.rmode.active) {
2472                 vmx->rmode.irq.pending = true;
2473                 vmx->rmode.irq.vector = NMI_VECTOR;
2474                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2475                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2476                              NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2477                              INTR_INFO_VALID_MASK);
2478                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2479                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2480                 return;
2481         }
2482         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2483                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2484 }
2485
2486 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2487 {
2488         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2489                 return 0;
2490
2491         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2492                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2493                                 GUEST_INTR_STATE_NMI));
2494 }
2495
2496 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2497 {
2498         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2499                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2500                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2501 }
2502
2503 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2504 {
2505         int ret;
2506         struct kvm_userspace_memory_region tss_mem = {
2507                 .slot = TSS_PRIVATE_MEMSLOT,
2508                 .guest_phys_addr = addr,
2509                 .memory_size = PAGE_SIZE * 3,
2510                 .flags = 0,
2511         };
2512
2513         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2514         if (ret)
2515                 return ret;
2516         kvm->arch.tss_addr = addr;
2517         return 0;
2518 }
2519
2520 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2521                                   int vec, u32 err_code)
2522 {
2523         /*
2524          * Instruction with address size override prefix opcode 0x67
2525          * Cause the #SS fault with 0 error code in VM86 mode.
2526          */
2527         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2528                 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2529                         return 1;
2530         /*
2531          * Forward all other exceptions that are valid in real mode.
2532          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2533          *        the required debugging infrastructure rework.
2534          */
2535         switch (vec) {
2536         case DB_VECTOR:
2537                 if (vcpu->guest_debug &
2538                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2539                         return 0;
2540                 kvm_queue_exception(vcpu, vec);
2541                 return 1;
2542         case BP_VECTOR:
2543                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2544                         return 0;
2545                 /* fall through */
2546         case DE_VECTOR:
2547         case OF_VECTOR:
2548         case BR_VECTOR:
2549         case UD_VECTOR:
2550         case DF_VECTOR:
2551         case SS_VECTOR:
2552         case GP_VECTOR:
2553         case MF_VECTOR:
2554                 kvm_queue_exception(vcpu, vec);
2555                 return 1;
2556         }
2557         return 0;
2558 }
2559
2560 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2561 {
2562         struct vcpu_vmx *vmx = to_vmx(vcpu);
2563         u32 intr_info, ex_no, error_code;
2564         unsigned long cr2, rip, dr6;
2565         u32 vect_info;
2566         enum emulation_result er;
2567
2568         vect_info = vmx->idt_vectoring_info;
2569         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2570
2571         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2572                                                 !is_page_fault(intr_info))
2573                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2574                        "intr info 0x%x\n", __func__, vect_info, intr_info);
2575
2576         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2577                 return 1;  /* already handled by vmx_vcpu_run() */
2578
2579         if (is_no_device(intr_info)) {
2580                 vmx_fpu_activate(vcpu);
2581                 return 1;
2582         }
2583
2584         if (is_invalid_opcode(intr_info)) {
2585                 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2586                 if (er != EMULATE_DONE)
2587                         kvm_queue_exception(vcpu, UD_VECTOR);
2588                 return 1;
2589         }
2590
2591         error_code = 0;
2592         rip = kvm_rip_read(vcpu);
2593         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2594                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2595         if (is_page_fault(intr_info)) {
2596                 /* EPT won't cause page fault directly */
2597                 if (enable_ept)
2598                         BUG();
2599                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2600                 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2601                             (u32)((u64)cr2 >> 32), handler);
2602                 if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending)
2603                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
2604                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2605         }
2606
2607         if (vcpu->arch.rmode.active &&
2608             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2609                                                                 error_code)) {
2610                 if (vcpu->arch.halt_request) {
2611                         vcpu->arch.halt_request = 0;
2612                         return kvm_emulate_halt(vcpu);
2613                 }
2614                 return 1;
2615         }
2616
2617         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2618         switch (ex_no) {
2619         case DB_VECTOR:
2620                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2621                 if (!(vcpu->guest_debug &
2622                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2623                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2624                         kvm_queue_exception(vcpu, DB_VECTOR);
2625                         return 1;
2626                 }
2627                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2628                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2629                 /* fall through */
2630         case BP_VECTOR:
2631                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2632                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2633                 kvm_run->debug.arch.exception = ex_no;
2634                 break;
2635         default:
2636                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2637                 kvm_run->ex.exception = ex_no;
2638                 kvm_run->ex.error_code = error_code;
2639                 break;
2640         }
2641         return 0;
2642 }
2643
2644 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2645                                      struct kvm_run *kvm_run)
2646 {
2647         ++vcpu->stat.irq_exits;
2648         KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
2649         return 1;
2650 }
2651
2652 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2653 {
2654         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2655         return 0;
2656 }
2657
2658 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2659 {
2660         unsigned long exit_qualification;
2661         int size, in, string;
2662         unsigned port;
2663
2664         ++vcpu->stat.io_exits;
2665         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2666         string = (exit_qualification & 16) != 0;
2667
2668         if (string) {
2669                 if (emulate_instruction(vcpu,
2670                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2671                         return 0;
2672                 return 1;
2673         }
2674
2675         size = (exit_qualification & 7) + 1;
2676         in = (exit_qualification & 8) != 0;
2677         port = exit_qualification >> 16;
2678
2679         skip_emulated_instruction(vcpu);
2680         return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2681 }
2682
2683 static void
2684 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2685 {
2686         /*
2687          * Patch in the VMCALL instruction:
2688          */
2689         hypercall[0] = 0x0f;
2690         hypercall[1] = 0x01;
2691         hypercall[2] = 0xc1;
2692 }
2693
2694 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2695 {
2696         unsigned long exit_qualification;
2697         int cr;
2698         int reg;
2699
2700         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2701         cr = exit_qualification & 15;
2702         reg = (exit_qualification >> 8) & 15;
2703         switch ((exit_qualification >> 4) & 3) {
2704         case 0: /* mov to cr */
2705                 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2706                             (u32)kvm_register_read(vcpu, reg),
2707                             (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2708                             handler);
2709                 switch (cr) {
2710                 case 0:
2711                         kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
2712                         skip_emulated_instruction(vcpu);
2713                         return 1;
2714                 case 3:
2715                         kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
2716                         skip_emulated_instruction(vcpu);
2717                         return 1;
2718                 case 4:
2719                         kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
2720                         skip_emulated_instruction(vcpu);
2721                         return 1;
2722                 case 8: {
2723                                 u8 cr8_prev = kvm_get_cr8(vcpu);
2724                                 u8 cr8 = kvm_register_read(vcpu, reg);
2725                                 kvm_set_cr8(vcpu, cr8);
2726                                 skip_emulated_instruction(vcpu);
2727                                 if (irqchip_in_kernel(vcpu->kvm))
2728                                         return 1;
2729                                 if (cr8_prev <= cr8)
2730                                         return 1;
2731                                 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2732                                 return 0;
2733                         }
2734                 };
2735                 break;
2736         case 2: /* clts */
2737                 vmx_fpu_deactivate(vcpu);
2738                 vcpu->arch.cr0 &= ~X86_CR0_TS;
2739                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2740                 vmx_fpu_activate(vcpu);
2741                 KVMTRACE_0D(CLTS, vcpu, handler);
2742                 skip_emulated_instruction(vcpu);
2743                 return 1;
2744         case 1: /*mov from cr*/
2745                 switch (cr) {
2746                 case 3:
2747                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2748                         KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2749                                     (u32)kvm_register_read(vcpu, reg),
2750                                     (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2751                                     handler);
2752                         skip_emulated_instruction(vcpu);
2753                         return 1;
2754                 case 8:
2755                         kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2756                         KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2757                                     (u32)kvm_register_read(vcpu, reg), handler);
2758                         skip_emulated_instruction(vcpu);
2759                         return 1;
2760                 }
2761                 break;
2762         case 3: /* lmsw */
2763                 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2764
2765                 skip_emulated_instruction(vcpu);
2766                 return 1;
2767         default:
2768                 break;
2769         }
2770         kvm_run->exit_reason = 0;
2771         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2772                (int)(exit_qualification >> 4) & 3, cr);
2773         return 0;
2774 }
2775
2776 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2777 {
2778         unsigned long exit_qualification;
2779         unsigned long val;
2780         int dr, reg;
2781
2782         dr = vmcs_readl(GUEST_DR7);
2783         if (dr & DR7_GD) {
2784                 /*
2785                  * As the vm-exit takes precedence over the debug trap, we
2786                  * need to emulate the latter, either for the host or the
2787                  * guest debugging itself.
2788                  */
2789                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2790                         kvm_run->debug.arch.dr6 = vcpu->arch.dr6;
2791                         kvm_run->debug.arch.dr7 = dr;
2792                         kvm_run->debug.arch.pc =
2793                                 vmcs_readl(GUEST_CS_BASE) +
2794                                 vmcs_readl(GUEST_RIP);
2795                         kvm_run->debug.arch.exception = DB_VECTOR;
2796                         kvm_run->exit_reason = KVM_EXIT_DEBUG;
2797                         return 0;
2798                 } else {
2799                         vcpu->arch.dr7 &= ~DR7_GD;
2800                         vcpu->arch.dr6 |= DR6_BD;
2801                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2802                         kvm_queue_exception(vcpu, DB_VECTOR);
2803                         return 1;
2804                 }
2805         }
2806
2807         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2808         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2809         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2810         if (exit_qualification & TYPE_MOV_FROM_DR) {
2811                 switch (dr) {
2812                 case 0 ... 3:
2813                         val = vcpu->arch.db[dr];
2814                         break;
2815                 case 6:
2816                         val = vcpu->arch.dr6;
2817                         break;
2818                 case 7:
2819                         val = vcpu->arch.dr7;
2820                         break;
2821                 default:
2822                         val = 0;
2823                 }
2824                 kvm_register_write(vcpu, reg, val);
2825                 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
2826         } else {
2827                 val = vcpu->arch.regs[reg];
2828                 switch (dr) {
2829                 case 0 ... 3:
2830                         vcpu->arch.db[dr] = val;
2831                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2832                                 vcpu->arch.eff_db[dr] = val;
2833                         break;
2834                 case 4 ... 5:
2835                         if (vcpu->arch.cr4 & X86_CR4_DE)
2836                                 kvm_queue_exception(vcpu, UD_VECTOR);
2837                         break;
2838                 case 6:
2839                         if (val & 0xffffffff00000000ULL) {
2840                                 kvm_queue_exception(vcpu, GP_VECTOR);
2841                                 break;
2842                         }
2843                         vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
2844                         break;
2845                 case 7:
2846                         if (val & 0xffffffff00000000ULL) {
2847                                 kvm_queue_exception(vcpu, GP_VECTOR);
2848                                 break;
2849                         }
2850                         vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
2851                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
2852                                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2853                                 vcpu->arch.switch_db_regs =
2854                                         (val & DR7_BP_EN_MASK);
2855                         }
2856                         break;
2857                 }
2858                 KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)val, handler);
2859         }
2860         skip_emulated_instruction(vcpu);
2861         return 1;
2862 }
2863
2864 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2865 {
2866         kvm_emulate_cpuid(vcpu);
2867         return 1;
2868 }
2869
2870 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2871 {
2872         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2873         u64 data;
2874
2875         if (vmx_get_msr(vcpu, ecx, &data)) {
2876                 kvm_inject_gp(vcpu, 0);
2877                 return 1;
2878         }
2879
2880         KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2881                     handler);
2882
2883         /* FIXME: handling of bits 32:63 of rax, rdx */
2884         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2885         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2886         skip_emulated_instruction(vcpu);
2887         return 1;
2888 }
2889
2890 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2891 {
2892         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2893         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2894                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2895
2896         KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2897                     handler);
2898
2899         if (vmx_set_msr(vcpu, ecx, data) != 0) {
2900                 kvm_inject_gp(vcpu, 0);
2901                 return 1;
2902         }
2903
2904         skip_emulated_instruction(vcpu);
2905         return 1;
2906 }
2907
2908 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2909                                       struct kvm_run *kvm_run)
2910 {
2911         return 1;
2912 }
2913
2914 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2915                                    struct kvm_run *kvm_run)
2916 {
2917         u32 cpu_based_vm_exec_control;
2918
2919         /* clear pending irq */
2920         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2921         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2922         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2923
2924         KVMTRACE_0D(PEND_INTR, vcpu, handler);
2925         ++vcpu->stat.irq_window_exits;
2926
2927         /*
2928          * If the user space waits to inject interrupts, exit as soon as
2929          * possible
2930          */
2931         if (!irqchip_in_kernel(vcpu->kvm) &&
2932             kvm_run->request_interrupt_window &&
2933             !kvm_cpu_has_interrupt(vcpu)) {
2934                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2935                 return 0;
2936         }
2937         return 1;
2938 }
2939
2940 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2941 {
2942         skip_emulated_instruction(vcpu);
2943         return kvm_emulate_halt(vcpu);
2944 }
2945
2946 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2947 {
2948         skip_emulated_instruction(vcpu);
2949         kvm_emulate_hypercall(vcpu);
2950         return 1;
2951 }
2952
2953 static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2954 {
2955         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2956
2957         kvm_mmu_invlpg(vcpu, exit_qualification);
2958         skip_emulated_instruction(vcpu);
2959         return 1;
2960 }
2961
2962 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2963 {
2964         skip_emulated_instruction(vcpu);
2965         /* TODO: Add support for VT-d/pass-through device */
2966         return 1;
2967 }
2968
2969 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2970 {
2971         unsigned long exit_qualification;
2972         enum emulation_result er;
2973         unsigned long offset;
2974
2975         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2976         offset = exit_qualification & 0xffful;
2977
2978         er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2979
2980         if (er !=  EMULATE_DONE) {
2981                 printk(KERN_ERR
2982                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2983                        offset);
2984                 return -ENOTSUPP;
2985         }
2986         return 1;
2987 }
2988
2989 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2990 {
2991         struct vcpu_vmx *vmx = to_vmx(vcpu);
2992         unsigned long exit_qualification;
2993         u16 tss_selector;
2994         int reason, type, idt_v;
2995
2996         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
2997         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
2998
2999         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3000
3001         reason = (u32)exit_qualification >> 30;
3002         if (reason == TASK_SWITCH_GATE && idt_v) {
3003                 switch (type) {
3004                 case INTR_TYPE_NMI_INTR:
3005                         vcpu->arch.nmi_injected = false;
3006                         if (cpu_has_virtual_nmis())
3007                                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3008                                               GUEST_INTR_STATE_NMI);
3009                         break;
3010                 case INTR_TYPE_EXT_INTR:
3011                         kvm_clear_interrupt_queue(vcpu);
3012                         break;
3013                 case INTR_TYPE_HARD_EXCEPTION:
3014                 case INTR_TYPE_SOFT_EXCEPTION:
3015                         kvm_clear_exception_queue(vcpu);
3016                         break;
3017                 default:
3018                         break;
3019                 }
3020         }
3021         tss_selector = exit_qualification;
3022
3023         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3024                        type != INTR_TYPE_EXT_INTR &&
3025                        type != INTR_TYPE_NMI_INTR))
3026                 skip_emulated_instruction(vcpu);
3027
3028         if (!kvm_task_switch(vcpu, tss_selector, reason))
3029                 return 0;
3030
3031         /* clear all local breakpoint enable flags */
3032         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3033
3034         /*
3035          * TODO: What about debug traps on tss switch?
3036          *       Are we supposed to inject them and update dr6?
3037          */
3038
3039         return 1;
3040 }
3041
3042 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3043 {
3044         unsigned long exit_qualification;
3045         gpa_t gpa;
3046         int gla_validity;
3047
3048         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3049
3050         if (exit_qualification & (1 << 6)) {
3051                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3052                 return -ENOTSUPP;
3053         }
3054
3055         gla_validity = (exit_qualification >> 7) & 0x3;
3056         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3057                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3058                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3059                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3060                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3061                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3062                         (long unsigned int)exit_qualification);
3063                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3064                 kvm_run->hw.hardware_exit_reason = 0;
3065                 return -ENOTSUPP;
3066         }
3067
3068         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3069         return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3070 }
3071
3072 static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3073 {
3074         u32 cpu_based_vm_exec_control;
3075
3076         /* clear pending NMI */
3077         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3078         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3079         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3080         ++vcpu->stat.nmi_window_exits;
3081
3082         return 1;
3083 }
3084
3085 static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3086                                 struct kvm_run *kvm_run)
3087 {
3088         struct vcpu_vmx *vmx = to_vmx(vcpu);
3089         enum emulation_result err = EMULATE_DONE;
3090
3091         preempt_enable();
3092         local_irq_enable();
3093
3094         while (!guest_state_valid(vcpu)) {
3095                 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3096
3097                 if (err == EMULATE_DO_MMIO)
3098                         break;
3099
3100                 if (err != EMULATE_DONE) {
3101                         kvm_report_emulation_failure(vcpu, "emulation failure");
3102                         return;
3103                 }
3104
3105                 if (signal_pending(current))
3106                         break;
3107                 if (need_resched())
3108                         schedule();
3109         }
3110
3111         local_irq_disable();
3112         preempt_disable();
3113
3114         vmx->invalid_state_emulation_result = err;
3115 }
3116
3117 /*
3118  * The exit handlers return 1 if the exit was handled fully and guest execution
3119  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3120  * to be done to userspace and return 0.
3121  */
3122 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3123                                       struct kvm_run *kvm_run) = {
3124         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3125         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3126         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3127         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3128         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3129         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3130         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3131         [EXIT_REASON_CPUID]                   = handle_cpuid,
3132         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3133         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3134         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3135         [EXIT_REASON_HLT]                     = handle_halt,
3136         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3137         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3138         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3139         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3140         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3141         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3142         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3143 };
3144
3145 static const int kvm_vmx_max_exit_handlers =
3146         ARRAY_SIZE(kvm_vmx_exit_handlers);
3147
3148 /*
3149  * The guest has exited.  See if we can fix it or if we need userspace
3150  * assistance.
3151  */
3152 static int vmx_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
3153 {
3154         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
3155         struct vcpu_vmx *vmx = to_vmx(vcpu);
3156         u32 vectoring_info = vmx->idt_vectoring_info;
3157
3158         KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
3159                     (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
3160
3161         /* If we need to emulate an MMIO from handle_invalid_guest_state
3162          * we just return 0 */
3163         if (vmx->emulation_required && emulate_invalid_guest_state) {
3164                 if (guest_state_valid(vcpu))
3165                         vmx->emulation_required = 0;
3166                 return vmx->invalid_state_emulation_result != EMULATE_DO_MMIO;
3167         }
3168
3169         /* Access CR3 don't cause VMExit in paging mode, so we need
3170          * to sync with guest real CR3. */
3171         if (enable_ept && is_paging(vcpu)) {
3172                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3173                 ept_load_pdptrs(vcpu);
3174         }
3175
3176         if (unlikely(vmx->fail)) {
3177                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3178                 kvm_run->fail_entry.hardware_entry_failure_reason
3179                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3180                 return 0;
3181         }
3182
3183         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3184                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3185                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3186                         exit_reason != EXIT_REASON_TASK_SWITCH))
3187                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3188                        "(0x%x) and exit reason is 0x%x\n",
3189                        __func__, vectoring_info, exit_reason);
3190
3191         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3192                 if (vmx_interrupt_allowed(vcpu)) {
3193                         vmx->soft_vnmi_blocked = 0;
3194                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3195                            vcpu->arch.nmi_pending) {
3196                         /*
3197                          * This CPU don't support us in finding the end of an
3198                          * NMI-blocked window if the guest runs with IRQs
3199                          * disabled. So we pull the trigger after 1 s of
3200                          * futile waiting, but inform the user about this.
3201                          */
3202                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3203                                "state on VCPU %d after 1 s timeout\n",
3204                                __func__, vcpu->vcpu_id);
3205                         vmx->soft_vnmi_blocked = 0;
3206                 }
3207         }
3208
3209         if (exit_reason < kvm_vmx_max_exit_handlers
3210             && kvm_vmx_exit_handlers[exit_reason])
3211                 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3212         else {
3213                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3214                 kvm_run->hw.hardware_exit_reason = exit_reason;
3215         }
3216         return 0;
3217 }
3218
3219 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3220 {
3221         if (irr == -1 || tpr < irr) {
3222                 vmcs_write32(TPR_THRESHOLD, 0);
3223                 return;
3224         }
3225
3226         vmcs_write32(TPR_THRESHOLD, irr);
3227 }
3228
3229 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3230 {
3231         u32 exit_intr_info;
3232         u32 idt_vectoring_info = vmx->idt_vectoring_info;
3233         bool unblock_nmi;
3234         u8 vector;
3235         int type;
3236         bool idtv_info_valid;
3237
3238         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3239         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3240         if (cpu_has_virtual_nmis()) {
3241                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3242                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3243                 /*
3244                  * SDM 3: 27.7.1.2 (September 2008)
3245                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3246                  * a guest IRET fault.
3247                  * SDM 3: 23.2.2 (September 2008)
3248                  * Bit 12 is undefined in any of the following cases:
3249                  *  If the VM exit sets the valid bit in the IDT-vectoring
3250                  *   information field.
3251                  *  If the VM exit is due to a double fault.
3252                  */
3253                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3254                     vector != DF_VECTOR && !idtv_info_valid)
3255                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3256                                       GUEST_INTR_STATE_NMI);
3257         } else if (unlikely(vmx->soft_vnmi_blocked))
3258                 vmx->vnmi_blocked_time +=
3259                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3260
3261         vmx->vcpu.arch.nmi_injected = false;
3262         kvm_clear_exception_queue(&vmx->vcpu);
3263         kvm_clear_interrupt_queue(&vmx->vcpu);
3264
3265         if (!idtv_info_valid)
3266                 return;
3267
3268         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3269         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3270
3271         switch (type) {
3272         case INTR_TYPE_NMI_INTR:
3273                 vmx->vcpu.arch.nmi_injected = true;
3274                 /*
3275                  * SDM 3: 27.7.1.2 (September 2008)
3276                  * Clear bit "block by NMI" before VM entry if a NMI
3277                  * delivery faulted.
3278                  */
3279                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3280                                 GUEST_INTR_STATE_NMI);
3281                 break;
3282         case INTR_TYPE_HARD_EXCEPTION:
3283         case INTR_TYPE_SOFT_EXCEPTION:
3284                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3285                         u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3286                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
3287                 } else
3288                         kvm_queue_exception(&vmx->vcpu, vector);
3289                 break;
3290         case INTR_TYPE_EXT_INTR:
3291                 kvm_queue_interrupt(&vmx->vcpu, vector);
3292                 break;
3293         default:
3294                 break;
3295         }
3296 }
3297
3298 /*
3299  * Failure to inject an interrupt should give us the information
3300  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3301  * when fetching the interrupt redirection bitmap in the real-mode
3302  * tss, this doesn't happen.  So we do it ourselves.
3303  */
3304 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3305 {
3306         vmx->rmode.irq.pending = 0;
3307         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3308                 return;
3309         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3310         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3311                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3312                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3313                 return;
3314         }
3315         vmx->idt_vectoring_info =
3316                 VECTORING_INFO_VALID_MASK
3317                 | INTR_TYPE_EXT_INTR
3318                 | vmx->rmode.irq.vector;
3319 }
3320
3321 #ifdef CONFIG_X86_64
3322 #define R "r"
3323 #define Q "q"
3324 #else
3325 #define R "e"
3326 #define Q "l"
3327 #endif
3328
3329 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3330 {
3331         struct vcpu_vmx *vmx = to_vmx(vcpu);
3332         u32 intr_info;
3333
3334         /* Record the guest's net vcpu time for enforced NMI injections. */
3335         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3336                 vmx->entry_time = ktime_get();
3337
3338         /* Handle invalid guest state instead of entering VMX */
3339         if (vmx->emulation_required && emulate_invalid_guest_state) {
3340                 handle_invalid_guest_state(vcpu, kvm_run);
3341                 return;
3342         }
3343
3344         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3345                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3346         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3347                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3348
3349         /*
3350          * Loading guest fpu may have cleared host cr0.ts
3351          */
3352         vmcs_writel(HOST_CR0, read_cr0());
3353
3354         set_debugreg(vcpu->arch.dr6, 6);
3355
3356         asm(
3357                 /* Store host registers */
3358                 "push %%"R"dx; push %%"R"bp;"
3359                 "push %%"R"cx \n\t"
3360                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3361                 "je 1f \n\t"
3362                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3363                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3364                 "1: \n\t"
3365                 /* Check if vmlaunch of vmresume is needed */
3366                 "cmpl $0, %c[launched](%0) \n\t"
3367                 /* Load guest registers.  Don't clobber flags. */
3368                 "mov %c[cr2](%0), %%"R"ax \n\t"
3369                 "mov %%"R"ax, %%cr2 \n\t"
3370                 "mov %c[rax](%0), %%"R"ax \n\t"
3371                 "mov %c[rbx](%0), %%"R"bx \n\t"
3372                 "mov %c[rdx](%0), %%"R"dx \n\t"
3373                 "mov %c[rsi](%0), %%"R"si \n\t"
3374                 "mov %c[rdi](%0), %%"R"di \n\t"
3375                 "mov %c[rbp](%0), %%"R"bp \n\t"
3376 #ifdef CONFIG_X86_64
3377                 "mov %c[r8](%0),  %%r8  \n\t"
3378                 "mov %c[r9](%0),  %%r9  \n\t"
3379                 "mov %c[r10](%0), %%r10 \n\t"
3380                 "mov %c[r11](%0), %%r11 \n\t"
3381                 "mov %c[r12](%0), %%r12 \n\t"
3382                 "mov %c[r13](%0), %%r13 \n\t"
3383                 "mov %c[r14](%0), %%r14 \n\t"
3384                 "mov %c[r15](%0), %%r15 \n\t"
3385 #endif
3386                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3387
3388                 /* Enter guest mode */
3389                 "jne .Llaunched \n\t"
3390                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3391                 "jmp .Lkvm_vmx_return \n\t"
3392                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3393                 ".Lkvm_vmx_return: "
3394                 /* Save guest registers, load host registers, keep flags */
3395                 "xchg %0,     (%%"R"sp) \n\t"
3396                 "mov %%"R"ax, %c[rax](%0) \n\t"
3397                 "mov %%"R"bx, %c[rbx](%0) \n\t"
3398                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3399                 "mov %%"R"dx, %c[rdx](%0) \n\t"
3400                 "mov %%"R"si, %c[rsi](%0) \n\t"
3401                 "mov %%"R"di, %c[rdi](%0) \n\t"
3402                 "mov %%"R"bp, %c[rbp](%0) \n\t"
3403 #ifdef CONFIG_X86_64
3404                 "mov %%r8,  %c[r8](%0) \n\t"
3405                 "mov %%r9,  %c[r9](%0) \n\t"
3406                 "mov %%r10, %c[r10](%0) \n\t"
3407                 "mov %%r11, %c[r11](%0) \n\t"
3408                 "mov %%r12, %c[r12](%0) \n\t"
3409                 "mov %%r13, %c[r13](%0) \n\t"
3410                 "mov %%r14, %c[r14](%0) \n\t"
3411                 "mov %%r15, %c[r15](%0) \n\t"
3412 #endif
3413                 "mov %%cr2, %%"R"ax   \n\t"
3414                 "mov %%"R"ax, %c[cr2](%0) \n\t"
3415
3416                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
3417                 "setbe %c[fail](%0) \n\t"
3418               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3419                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3420                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3421                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3422                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3423                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3424                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3425                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3426                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3427                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3428                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3429 #ifdef CONFIG_X86_64
3430                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3431                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3432                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3433                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3434                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3435                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3436                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3437                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3438 #endif
3439                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3440               : "cc", "memory"
3441                 , R"bx", R"di", R"si"
3442 #ifdef CONFIG_X86_64
3443                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3444 #endif
3445               );
3446
3447         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3448         vcpu->arch.regs_dirty = 0;
3449
3450         get_debugreg(vcpu->arch.dr6, 6);
3451
3452         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3453         if (vmx->rmode.irq.pending)
3454                 fixup_rmode_irq(vmx);
3455
3456         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3457         vmx->launched = 1;
3458
3459         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3460
3461         /* We need to handle NMIs before interrupts are enabled */
3462         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3463             (intr_info & INTR_INFO_VALID_MASK)) {
3464                 KVMTRACE_0D(NMI, vcpu, handler);
3465                 asm("int $2");
3466         }
3467
3468         vmx_complete_interrupts(vmx);
3469 }
3470
3471 #undef R
3472 #undef Q
3473
3474 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3475 {
3476         struct vcpu_vmx *vmx = to_vmx(vcpu);
3477
3478         if (vmx->vmcs) {
3479                 vcpu_clear(vmx);
3480                 free_vmcs(vmx->vmcs);
3481                 vmx->vmcs = NULL;
3482         }
3483 }
3484
3485 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3486 {
3487         struct vcpu_vmx *vmx = to_vmx(vcpu);
3488
3489         spin_lock(&vmx_vpid_lock);
3490         if (vmx->vpid != 0)
3491                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3492         spin_unlock(&vmx_vpid_lock);
3493         vmx_free_vmcs(vcpu);
3494         kfree(vmx->host_msrs);
3495         kfree(vmx->guest_msrs);
3496         kvm_vcpu_uninit(vcpu);
3497         kmem_cache_free(kvm_vcpu_cache, vmx);
3498 }
3499
3500 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3501 {
3502         int err;
3503         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3504         int cpu;
3505
3506         if (!vmx)
3507                 return ERR_PTR(-ENOMEM);
3508
3509         allocate_vpid(vmx);
3510
3511         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3512         if (err)
3513                 goto free_vcpu;
3514
3515         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3516         if (!vmx->guest_msrs) {
3517                 err = -ENOMEM;
3518                 goto uninit_vcpu;
3519         }
3520
3521         vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3522         if (!vmx->host_msrs)
3523                 goto free_guest_msrs;
3524
3525         vmx->vmcs = alloc_vmcs();
3526         if (!vmx->vmcs)
3527                 goto free_msrs;
3528
3529         vmcs_clear(vmx->vmcs);
3530
3531         cpu = get_cpu();
3532         vmx_vcpu_load(&vmx->vcpu, cpu);
3533         err = vmx_vcpu_setup(vmx);
3534         vmx_vcpu_put(&vmx->vcpu);
3535         put_cpu();
3536         if (err)
3537                 goto free_vmcs;
3538         if (vm_need_virtualize_apic_accesses(kvm))
3539                 if (alloc_apic_access_page(kvm) != 0)
3540                         goto free_vmcs;
3541
3542         if (enable_ept)
3543                 if (alloc_identity_pagetable(kvm) != 0)
3544                         goto free_vmcs;
3545
3546         return &vmx->vcpu;
3547
3548 free_vmcs:
3549         free_vmcs(vmx->vmcs);
3550 free_msrs:
3551         kfree(vmx->host_msrs);
3552 free_guest_msrs:
3553         kfree(vmx->guest_msrs);
3554 uninit_vcpu:
3555         kvm_vcpu_uninit(&vmx->vcpu);
3556 free_vcpu:
3557         kmem_cache_free(kvm_vcpu_cache, vmx);
3558         return ERR_PTR(err);
3559 }
3560
3561 static void __init vmx_check_processor_compat(void *rtn)
3562 {
3563         struct vmcs_config vmcs_conf;
3564
3565         *(int *)rtn = 0;
3566         if (setup_vmcs_config(&vmcs_conf) < 0)
3567                 *(int *)rtn = -EIO;
3568         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3569                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3570                                 smp_processor_id());
3571                 *(int *)rtn = -EIO;
3572         }
3573 }
3574
3575 static int get_ept_level(void)
3576 {
3577         return VMX_EPT_DEFAULT_GAW + 1;
3578 }
3579
3580 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3581 {
3582         u64 ret;
3583
3584         if (is_mmio)
3585                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
3586         else
3587                 ret = (kvm_get_guest_memory_type(vcpu, gfn) <<
3588                         VMX_EPT_MT_EPTE_SHIFT) | VMX_EPT_IGMT_BIT;
3589
3590         return ret;
3591 }
3592
3593 static struct kvm_x86_ops vmx_x86_ops = {
3594         .cpu_has_kvm_support = cpu_has_kvm_support,
3595         .disabled_by_bios = vmx_disabled_by_bios,
3596         .hardware_setup = hardware_setup,
3597         .hardware_unsetup = hardware_unsetup,
3598         .check_processor_compatibility = vmx_check_processor_compat,
3599         .hardware_enable = hardware_enable,
3600         .hardware_disable = hardware_disable,
3601         .cpu_has_accelerated_tpr = report_flexpriority,
3602
3603         .vcpu_create = vmx_create_vcpu,
3604         .vcpu_free = vmx_free_vcpu,
3605         .vcpu_reset = vmx_vcpu_reset,
3606
3607         .prepare_guest_switch = vmx_save_host_state,
3608         .vcpu_load = vmx_vcpu_load,
3609         .vcpu_put = vmx_vcpu_put,
3610
3611         .set_guest_debug = set_guest_debug,
3612         .get_msr = vmx_get_msr,
3613         .set_msr = vmx_set_msr,
3614         .get_segment_base = vmx_get_segment_base,
3615         .get_segment = vmx_get_segment,
3616         .set_segment = vmx_set_segment,
3617         .get_cpl = vmx_get_cpl,
3618         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3619         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3620         .set_cr0 = vmx_set_cr0,
3621         .set_cr3 = vmx_set_cr3,
3622         .set_cr4 = vmx_set_cr4,
3623         .set_efer = vmx_set_efer,
3624         .get_idt = vmx_get_idt,
3625         .set_idt = vmx_set_idt,
3626         .get_gdt = vmx_get_gdt,
3627         .set_gdt = vmx_set_gdt,
3628         .cache_reg = vmx_cache_reg,
3629         .get_rflags = vmx_get_rflags,
3630         .set_rflags = vmx_set_rflags,
3631
3632         .tlb_flush = vmx_flush_tlb,
3633
3634         .run = vmx_vcpu_run,
3635         .handle_exit = vmx_handle_exit,
3636         .skip_emulated_instruction = skip_emulated_instruction,
3637         .patch_hypercall = vmx_patch_hypercall,
3638         .set_irq = vmx_inject_irq,
3639         .set_nmi = vmx_inject_nmi,
3640         .queue_exception = vmx_queue_exception,
3641         .interrupt_allowed = vmx_interrupt_allowed,
3642         .nmi_allowed = vmx_nmi_allowed,
3643         .enable_nmi_window = enable_nmi_window,
3644         .enable_irq_window = enable_irq_window,
3645         .update_cr8_intercept = update_cr8_intercept,
3646         .drop_interrupt_shadow = vmx_drop_interrupt_shadow,
3647
3648         .set_tss_addr = vmx_set_tss_addr,
3649         .get_tdp_level = get_ept_level,
3650         .get_mt_mask = vmx_get_mt_mask,
3651 };
3652
3653 static int __init vmx_init(void)
3654 {
3655         int r;
3656
3657         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
3658         if (!vmx_io_bitmap_a)
3659                 return -ENOMEM;
3660
3661         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
3662         if (!vmx_io_bitmap_b) {
3663                 r = -ENOMEM;
3664                 goto out;
3665         }
3666
3667         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
3668         if (!vmx_msr_bitmap_legacy) {
3669                 r = -ENOMEM;
3670                 goto out1;
3671         }
3672
3673         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
3674         if (!vmx_msr_bitmap_longmode) {
3675                 r = -ENOMEM;
3676                 goto out2;
3677         }
3678
3679         /*
3680          * Allow direct access to the PC debug port (it is often used for I/O
3681          * delays, but the vmexits simply slow things down).
3682          */
3683         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
3684         clear_bit(0x80, vmx_io_bitmap_a);
3685
3686         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
3687
3688         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
3689         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
3690
3691         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3692
3693         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
3694         if (r)
3695                 goto out3;
3696
3697         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
3698         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
3699         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
3700         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
3701         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
3702         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
3703
3704         if (enable_ept) {
3705                 bypass_guest_pf = 0;
3706                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3707                         VMX_EPT_WRITABLE_MASK);
3708                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
3709                                 VMX_EPT_EXECUTABLE_MASK);
3710                 kvm_enable_tdp();
3711         } else
3712                 kvm_disable_tdp();
3713
3714         if (bypass_guest_pf)
3715                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3716
3717         ept_sync_global();
3718
3719         return 0;
3720
3721 out3:
3722         free_page((unsigned long)vmx_msr_bitmap_longmode);
3723 out2:
3724         free_page((unsigned long)vmx_msr_bitmap_legacy);
3725 out1:
3726         free_page((unsigned long)vmx_io_bitmap_b);
3727 out:
3728         free_page((unsigned long)vmx_io_bitmap_a);
3729         return r;
3730 }
3731
3732 static void __exit vmx_exit(void)
3733 {
3734         free_page((unsigned long)vmx_msr_bitmap_legacy);
3735         free_page((unsigned long)vmx_msr_bitmap_longmode);
3736         free_page((unsigned long)vmx_io_bitmap_b);
3737         free_page((unsigned long)vmx_io_bitmap_a);
3738
3739         kvm_exit();
3740 }
3741
3742 module_init(vmx_init)
3743 module_exit(vmx_exit)