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   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/mm.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/ftrace_event.h>
  29 #include "kvm_cache_regs.h"
  30 #include "x86.h"
  31
  32 #include <asm/io.h>
  33 #include <asm/desc.h>
  34 #include <asm/vmx.h>
  35 #include <asm/virtext.h>
  36 #include <asm/mce.h>
  37
  38 #include "trace.h"
  39
  40 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  41
  42 MODULE_AUTHOR("Qumranet");
  43 MODULE_LICENSE("GPL");
  44
  45 static int __read_mostly bypass_guest_pf = 1;
  46 module_param(bypass_guest_pf, bool, S_IRUGO);
  47
  48 static int __read_mostly enable_vpid = 1;
  49 module_param_named(vpid, enable_vpid, bool, 0444);
  50
  51 static int __read_mostly flexpriority_enabled = 1;
  52 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  53
  54 static int __read_mostly enable_ept = 1;
  55 module_param_named(ept, enable_ept, bool, S_IRUGO);
  56
  57 static int __read_mostly enable_unrestricted_guest = 1;
  58 module_param_named(unrestricted_guest,
  59                         enable_unrestricted_guest, bool, S_IRUGO);
  60
  61 static int __read_mostly emulate_invalid_guest_state = 0;
  62 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  63
  64 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  65         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  66 #define KVM_GUEST_CR0_MASK                                              \
  67         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  68 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  69         (X86_CR0_WP | X86_CR0_NE)
  70 #define KVM_VM_CR0_ALWAYS_ON                                            \
  71         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  72 #define KVM_CR4_GUEST_OWNED_BITS                                      \
  73         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
  74          | X86_CR4_OSXMMEXCPT)
  75
  76 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
  77 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
  78
  79 /*
  80  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
  81  * ple_gap:    upper bound on the amount of time between two successive
  82  *             executions of PAUSE in a loop. Also indicate if ple enabled.
  83  *             According to test, this time is usually small than 41 cycles.
  84  * ple_window: upper bound on the amount of time a guest is allowed to execute
  85  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
  86  *             less than 2^12 cycles
  87  * Time is measured based on a counter that runs at the same rate as the TSC,
  88  * refer SDM volume 3b section 21.6.13 & 22.1.3.
  89  */
  90 #define KVM_VMX_DEFAULT_PLE_GAP    41
  91 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
  92 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
  93 module_param(ple_gap, int, S_IRUGO);
  94
  95 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
  96 module_param(ple_window, int, S_IRUGO);
  97
  98 struct vmcs {
  99         u32 revision_id;
 100         u32 abort;
 101         char data[0];
 102 };
 103
 104 struct shared_msr_entry {
 105         unsigned index;
 106         u64 data;
 107         u64 mask;
 108 };
 109
 110 struct vcpu_vmx {
 111         struct kvm_vcpu       vcpu;
 112         struct list_head      local_vcpus_link;
 113         unsigned long         host_rsp;
 114         int                   launched;
 115         u8                    fail;
 116         u32                   idt_vectoring_info;
 117         struct shared_msr_entry *guest_msrs;
 118         int                   nmsrs;
 119         int                   save_nmsrs;
 120 #ifdef CONFIG_X86_64
 121         u64                   msr_host_kernel_gs_base;
 122         u64                   msr_guest_kernel_gs_base;
 123 #endif
 124         struct vmcs          *vmcs;
 125         struct {
 126                 int           loaded;
 127                 u16           fs_sel, gs_sel, ldt_sel;
 128                 int           gs_ldt_reload_needed;
 129                 int           fs_reload_needed;
 130         } host_state;
 131         struct {
 132                 int vm86_active;
 133                 u8 save_iopl;
 134                 struct kvm_save_segment {
 135                         u16 selector;
 136                         unsigned long base;
 137                         u32 limit;
 138                         u32 ar;
 139                 } tr, es, ds, fs, gs;
 140                 struct {
 141                         bool pending;
 142                         u8 vector;
 143                         unsigned rip;
 144                 } irq;
 145         } rmode;
 146         int vpid;
 147         bool emulation_required;
 148
 149         /* Support for vnmi-less CPUs */
 150         int soft_vnmi_blocked;
 151         ktime_t entry_time;
 152         s64 vnmi_blocked_time;
 153         u32 exit_reason;
 154
 155         bool rdtscp_enabled;
 156 };
 157
 158 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 159 {
 160         return container_of(vcpu, struct vcpu_vmx, vcpu);
 161 }
 162
 163 static int init_rmode(struct kvm *kvm);
 164 static u64 construct_eptp(unsigned long root_hpa);
 165
 166 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 167 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 168 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 169
 170 static unsigned long *vmx_io_bitmap_a;
 171 static unsigned long *vmx_io_bitmap_b;
 172 static unsigned long *vmx_msr_bitmap_legacy;
 173 static unsigned long *vmx_msr_bitmap_longmode;
 174
 175 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 176 static DEFINE_SPINLOCK(vmx_vpid_lock);
 177
 178 static struct vmcs_config {
 179         int size;
 180         int order;
 181         u32 revision_id;
 182         u32 pin_based_exec_ctrl;
 183         u32 cpu_based_exec_ctrl;
 184         u32 cpu_based_2nd_exec_ctrl;
 185         u32 vmexit_ctrl;
 186         u32 vmentry_ctrl;
 187 } vmcs_config;
 188
 189 static struct vmx_capability {
 190         u32 ept;
 191         u32 vpid;
 192 } vmx_capability;
 193
 194 #define VMX_SEGMENT_FIELD(seg)                                  \
 195         [VCPU_SREG_##seg] = {                                   \
 196                 .selector = GUEST_##seg##_SELECTOR,             \
 197                 .base = GUEST_##seg##_BASE,                     \
 198                 .limit = GUEST_##seg##_LIMIT,                   \
 199                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 200         }
 201
 202 static struct kvm_vmx_segment_field {
 203         unsigned selector;
 204         unsigned base;
 205         unsigned limit;
 206         unsigned ar_bytes;
 207 } kvm_vmx_segment_fields[] = {
 208         VMX_SEGMENT_FIELD(CS),
 209         VMX_SEGMENT_FIELD(DS),
 210         VMX_SEGMENT_FIELD(ES),
 211         VMX_SEGMENT_FIELD(FS),
 212         VMX_SEGMENT_FIELD(GS),
 213         VMX_SEGMENT_FIELD(SS),
 214         VMX_SEGMENT_FIELD(TR),
 215         VMX_SEGMENT_FIELD(LDTR),
 216 };
 217
 218 static u64 host_efer;
 219
 220 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 221
 222 /*
 223  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 224  * away by decrementing the array size.
 225  */
 226 static const u32 vmx_msr_index[] = {
 227 #ifdef CONFIG_X86_64
 228         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 229 #endif
 230         MSR_EFER, MSR_TSC_AUX, MSR_K6_STAR,
 231 };
 232 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 233
 234 static inline int is_page_fault(u32 intr_info)
 235 {
 236         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 237                              INTR_INFO_VALID_MASK)) ==
 238                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 239 }
 240
 241 static inline int is_no_device(u32 intr_info)
 242 {
 243         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 244                              INTR_INFO_VALID_MASK)) ==
 245                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 246 }
 247
 248 static inline int is_invalid_opcode(u32 intr_info)
 249 {
 250         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 251                              INTR_INFO_VALID_MASK)) ==
 252                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 253 }
 254
 255 static inline int is_external_interrupt(u32 intr_info)
 256 {
 257         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 258                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 259 }
 260
 261 static inline int is_machine_check(u32 intr_info)
 262 {
 263         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 264                              INTR_INFO_VALID_MASK)) ==
 265                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 266 }
 267
 268 static inline int cpu_has_vmx_msr_bitmap(void)
 269 {
 270         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 271 }
 272
 273 static inline int cpu_has_vmx_tpr_shadow(void)
 274 {
 275         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 276 }
 277
 278 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 279 {
 280         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 281 }
 282
 283 static inline int cpu_has_secondary_exec_ctrls(void)
 284 {
 285         return vmcs_config.cpu_based_exec_ctrl &
 286                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 287 }
 288
 289 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 290 {
 291         return vmcs_config.cpu_based_2nd_exec_ctrl &
 292                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 293 }
 294
 295 static inline bool cpu_has_vmx_flexpriority(void)
 296 {
 297         return cpu_has_vmx_tpr_shadow() &&
 298                 cpu_has_vmx_virtualize_apic_accesses();
 299 }
 300
 301 static inline bool cpu_has_vmx_ept_execute_only(void)
 302 {
 303         return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
 304 }
 305
 306 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 307 {
 308         return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
 309 }
 310
 311 static inline bool cpu_has_vmx_eptp_writeback(void)
 312 {
 313         return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
 314 }
 315
 316 static inline bool cpu_has_vmx_ept_2m_page(void)
 317 {
 318         return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
 319 }
 320
 321 static inline bool cpu_has_vmx_ept_1g_page(void)
 322 {
 323         return !!(vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT);
 324 }
 325
 326 static inline int cpu_has_vmx_invept_individual_addr(void)
 327 {
 328         return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
 329 }
 330
 331 static inline int cpu_has_vmx_invept_context(void)
 332 {
 333         return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
 334 }
 335
 336 static inline int cpu_has_vmx_invept_global(void)
 337 {
 338         return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
 339 }
 340
 341 static inline int cpu_has_vmx_ept(void)
 342 {
 343         return vmcs_config.cpu_based_2nd_exec_ctrl &
 344                 SECONDARY_EXEC_ENABLE_EPT;
 345 }
 346
 347 static inline int cpu_has_vmx_unrestricted_guest(void)
 348 {
 349         return vmcs_config.cpu_based_2nd_exec_ctrl &
 350                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 351 }
 352
 353 static inline int cpu_has_vmx_ple(void)
 354 {
 355         return vmcs_config.cpu_based_2nd_exec_ctrl &
 356                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 357 }
 358
 359 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 360 {
 361         return flexpriority_enabled &&
 362                 (cpu_has_vmx_virtualize_apic_accesses()) &&
 363                 (irqchip_in_kernel(kvm));
 364 }
 365
 366 static inline int cpu_has_vmx_vpid(void)
 367 {
 368         return vmcs_config.cpu_based_2nd_exec_ctrl &
 369                 SECONDARY_EXEC_ENABLE_VPID;
 370 }
 371
 372 static inline int cpu_has_vmx_rdtscp(void)
 373 {
 374         return vmcs_config.cpu_based_2nd_exec_ctrl &
 375                 SECONDARY_EXEC_RDTSCP;
 376 }
 377
 378 static inline int cpu_has_virtual_nmis(void)
 379 {
 380         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 381 }
 382
 383 static inline bool report_flexpriority(void)
 384 {
 385         return flexpriority_enabled;
 386 }
 387
 388 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 389 {
 390         int i;
 391
 392         for (i = 0; i < vmx->nmsrs; ++i)
 393                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 394                         return i;
 395         return -1;
 396 }
 397
 398 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 399 {
 400     struct {
 401         u64 vpid : 16;
 402         u64 rsvd : 48;
 403         u64 gva;
 404     } operand = { vpid, 0, gva };
 405
 406     asm volatile (__ex(ASM_VMX_INVVPID)
 407                   /* CF==1 or ZF==1 --> rc = -1 */
 408                   "; ja 1f ; ud2 ; 1:"
 409                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 410 }
 411
 412 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 413 {
 414         struct {
 415                 u64 eptp, gpa;
 416         } operand = {eptp, gpa};
 417
 418         asm volatile (__ex(ASM_VMX_INVEPT)
 419                         /* CF==1 or ZF==1 --> rc = -1 */
 420                         "; ja 1f ; ud2 ; 1:\n"
 421                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 422 }
 423
 424 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 425 {
 426         int i;
 427
 428         i = __find_msr_index(vmx, msr);
 429         if (i >= 0)
 430                 return &vmx->guest_msrs[i];
 431         return NULL;
 432 }
 433
 434 static void vmcs_clear(struct vmcs *vmcs)
 435 {
 436         u64 phys_addr = __pa(vmcs);
 437         u8 error;
 438
 439         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 440                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 441                       : "cc", "memory");
 442         if (error)
 443                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 444                        vmcs, phys_addr);
 445 }
 446
 447 static void __vcpu_clear(void *arg)
 448 {
 449         struct vcpu_vmx *vmx = arg;
 450         int cpu = raw_smp_processor_id();
 451
 452         if (vmx->vcpu.cpu == cpu)
 453                 vmcs_clear(vmx->vmcs);
 454         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 455                 per_cpu(current_vmcs, cpu) = NULL;
 456         rdtscll(vmx->vcpu.arch.host_tsc);
 457         list_del(&vmx->local_vcpus_link);
 458         vmx->vcpu.cpu = -1;
 459         vmx->launched = 0;
 460 }
 461
 462 static void vcpu_clear(struct vcpu_vmx *vmx)
 463 {
 464         if (vmx->vcpu.cpu == -1)
 465                 return;
 466         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 467 }
 468
 469 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 470 {
 471         if (vmx->vpid == 0)
 472                 return;
 473
 474         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 475 }
 476
 477 static inline void ept_sync_global(void)
 478 {
 479         if (cpu_has_vmx_invept_global())
 480                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 481 }
 482
 483 static inline void ept_sync_context(u64 eptp)
 484 {
 485         if (enable_ept) {
 486                 if (cpu_has_vmx_invept_context())
 487                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 488                 else
 489                         ept_sync_global();
 490         }
 491 }
 492
 493 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 494 {
 495         if (enable_ept) {
 496                 if (cpu_has_vmx_invept_individual_addr())
 497                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 498                                         eptp, gpa);
 499                 else
 500                         ept_sync_context(eptp);
 501         }
 502 }
 503
 504 static unsigned long vmcs_readl(unsigned long field)
 505 {
 506         unsigned long value;
 507
 508         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 509                       : "=a"(value) : "d"(field) : "cc");
 510         return value;
 511 }
 512
 513 static u16 vmcs_read16(unsigned long field)
 514 {
 515         return vmcs_readl(field);
 516 }
 517
 518 static u32 vmcs_read32(unsigned long field)
 519 {
 520         return vmcs_readl(field);
 521 }
 522
 523 static u64 vmcs_read64(unsigned long field)
 524 {
 525 #ifdef CONFIG_X86_64
 526         return vmcs_readl(field);
 527 #else
 528         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 529 #endif
 530 }
 531
 532 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 533 {
 534         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 535                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 536         dump_stack();
 537 }
 538
 539 static void vmcs_writel(unsigned long field, unsigned long value)
 540 {
 541         u8 error;
 542
 543         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 544                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 545         if (unlikely(error))
 546                 vmwrite_error(field, value);
 547 }
 548
 549 static void vmcs_write16(unsigned long field, u16 value)
 550 {
 551         vmcs_writel(field, value);
 552 }
 553
 554 static void vmcs_write32(unsigned long field, u32 value)
 555 {
 556         vmcs_writel(field, value);
 557 }
 558
 559 static void vmcs_write64(unsigned long field, u64 value)
 560 {
 561         vmcs_writel(field, value);
 562 #ifndef CONFIG_X86_64
 563         asm volatile ("");
 564         vmcs_writel(field+1, value >> 32);
 565 #endif
 566 }
 567
 568 static void vmcs_clear_bits(unsigned long field, u32 mask)
 569 {
 570         vmcs_writel(field, vmcs_readl(field) & ~mask);
 571 }
 572
 573 static void vmcs_set_bits(unsigned long field, u32 mask)
 574 {
 575         vmcs_writel(field, vmcs_readl(field) | mask);
 576 }
 577
 578 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 579 {
 580         u32 eb;
 581
 582         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 583              (1u << NM_VECTOR) | (1u << DB_VECTOR);
 584         if ((vcpu->guest_debug &
 585              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 586             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 587                 eb |= 1u << BP_VECTOR;
 588         if (to_vmx(vcpu)->rmode.vm86_active)
 589                 eb = ~0;
 590         if (enable_ept)
 591                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 592         if (vcpu->fpu_active)
 593                 eb &= ~(1u << NM_VECTOR);
 594         vmcs_write32(EXCEPTION_BITMAP, eb);
 595 }
 596
 597 static void reload_tss(void)
 598 {
 599         /*
 600          * VT restores TR but not its size.  Useless.
 601          */
 602         struct descriptor_table gdt;
 603         struct desc_struct *descs;
 604
 605         kvm_get_gdt(&gdt);
 606         descs = (void *)gdt.base;
 607         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 608         load_TR_desc();
 609 }
 610
 611 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 612 {
 613         u64 guest_efer;
 614         u64 ignore_bits;
 615
 616         guest_efer = vmx->vcpu.arch.efer;
 617
 618         /*
 619          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 620          * outside long mode
 621          */
 622         ignore_bits = EFER_NX | EFER_SCE;
 623 #ifdef CONFIG_X86_64
 624         ignore_bits |= EFER_LMA | EFER_LME;
 625         /* SCE is meaningful only in long mode on Intel */
 626         if (guest_efer & EFER_LMA)
 627                 ignore_bits &= ~(u64)EFER_SCE;
 628 #endif
 629         guest_efer &= ~ignore_bits;
 630         guest_efer |= host_efer & ignore_bits;
 631         vmx->guest_msrs[efer_offset].data = guest_efer;
 632         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
 633         return true;
 634 }
 635
 636 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 637 {
 638         struct vcpu_vmx *vmx = to_vmx(vcpu);
 639         int i;
 640
 641         if (vmx->host_state.loaded)
 642                 return;
 643
 644         vmx->host_state.loaded = 1;
 645         /*
 646          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 647          * allow segment selectors with cpl > 0 or ti == 1.
 648          */
 649         vmx->host_state.ldt_sel = kvm_read_ldt();
 650         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 651         vmx->host_state.fs_sel = kvm_read_fs();
 652         if (!(vmx->host_state.fs_sel & 7)) {
 653                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 654                 vmx->host_state.fs_reload_needed = 0;
 655         } else {
 656                 vmcs_write16(HOST_FS_SELECTOR, 0);
 657                 vmx->host_state.fs_reload_needed = 1;
 658         }
 659         vmx->host_state.gs_sel = kvm_read_gs();
 660         if (!(vmx->host_state.gs_sel & 7))
 661                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 662         else {
 663                 vmcs_write16(HOST_GS_SELECTOR, 0);
 664                 vmx->host_state.gs_ldt_reload_needed = 1;
 665         }
 666
 667 #ifdef CONFIG_X86_64
 668         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 669         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 670 #else
 671         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 672         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 673 #endif
 674
 675 #ifdef CONFIG_X86_64
 676         if (is_long_mode(&vmx->vcpu)) {
 677                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 678                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 679         }
 680 #endif
 681         for (i = 0; i < vmx->save_nmsrs; ++i)
 682                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
 683                                    vmx->guest_msrs[i].data,
 684                                    vmx->guest_msrs[i].mask);
 685 }
 686
 687 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 688 {
 689         unsigned long flags;
 690
 691         if (!vmx->host_state.loaded)
 692                 return;
 693
 694         ++vmx->vcpu.stat.host_state_reload;
 695         vmx->host_state.loaded = 0;
 696         if (vmx->host_state.fs_reload_needed)
 697                 kvm_load_fs(vmx->host_state.fs_sel);
 698         if (vmx->host_state.gs_ldt_reload_needed) {
 699                 kvm_load_ldt(vmx->host_state.ldt_sel);
 700                 /*
 701                  * If we have to reload gs, we must take care to
 702                  * preserve our gs base.
 703                  */
 704                 local_irq_save(flags);
 705                 kvm_load_gs(vmx->host_state.gs_sel);
 706 #ifdef CONFIG_X86_64
 707                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 708 #endif
 709                 local_irq_restore(flags);
 710         }
 711         reload_tss();
 712 #ifdef CONFIG_X86_64
 713         if (is_long_mode(&vmx->vcpu)) {
 714                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 715                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 716         }
 717 #endif
 718 }
 719
 720 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 721 {
 722         preempt_disable();
 723         __vmx_load_host_state(vmx);
 724         preempt_enable();
 725 }
 726
 727 /*
 728  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 729  * vcpu mutex is already taken.
 730  */
 731 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 732 {
 733         struct vcpu_vmx *vmx = to_vmx(vcpu);
 734         u64 phys_addr = __pa(vmx->vmcs);
 735         u64 tsc_this, delta, new_offset;
 736
 737         if (vcpu->cpu != cpu) {
 738                 vcpu_clear(vmx);
 739                 kvm_migrate_timers(vcpu);
 740                 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
 741                 local_irq_disable();
 742                 list_add(&vmx->local_vcpus_link,
 743                          &per_cpu(vcpus_on_cpu, cpu));
 744                 local_irq_enable();
 745         }
 746
 747         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 748                 u8 error;
 749
 750                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 751                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 752                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 753                               : "cc");
 754                 if (error)
 755                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 756                                vmx->vmcs, phys_addr);
 757         }
 758
 759         if (vcpu->cpu != cpu) {
 760                 struct descriptor_table dt;
 761                 unsigned long sysenter_esp;
 762
 763                 vcpu->cpu = cpu;
 764                 /*
 765                  * Linux uses per-cpu TSS and GDT, so set these when switching
 766                  * processors.
 767                  */
 768                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 769                 kvm_get_gdt(&dt);
 770                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 771
 772                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 773                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 774
 775                 /*
 776                  * Make sure the time stamp counter is monotonous.
 777                  */
 778                 rdtscll(tsc_this);
 779                 if (tsc_this < vcpu->arch.host_tsc) {
 780                         delta = vcpu->arch.host_tsc - tsc_this;
 781                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 782                         vmcs_write64(TSC_OFFSET, new_offset);
 783                 }
 784         }
 785 }
 786
 787 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 788 {
 789         __vmx_load_host_state(to_vmx(vcpu));
 790 }
 791
 792 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 793 {
 794         ulong cr0;
 795
 796         if (vcpu->fpu_active)
 797                 return;
 798         vcpu->fpu_active = 1;
 799         cr0 = vmcs_readl(GUEST_CR0);
 800         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
 801         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
 802         vmcs_writel(GUEST_CR0, cr0);
 803         update_exception_bitmap(vcpu);
 804         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
 805         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 806 }
 807
 808 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
 809
 810 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 811 {
 812         vmx_decache_cr0_guest_bits(vcpu);
 813         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
 814         update_exception_bitmap(vcpu);
 815         vcpu->arch.cr0_guest_owned_bits = 0;
 816         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 817         vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
 818 }
 819
 820 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 821 {
 822         unsigned long rflags;
 823
 824         rflags = vmcs_readl(GUEST_RFLAGS);
 825         if (to_vmx(vcpu)->rmode.vm86_active)
 826                 rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
 827         return rflags;
 828 }
 829
 830 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 831 {
 832         if (to_vmx(vcpu)->rmode.vm86_active)
 833                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 834         vmcs_writel(GUEST_RFLAGS, rflags);
 835 }
 836
 837 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 838 {
 839         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 840         int ret = 0;
 841
 842         if (interruptibility & GUEST_INTR_STATE_STI)
 843                 ret |= X86_SHADOW_INT_STI;
 844         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
 845                 ret |= X86_SHADOW_INT_MOV_SS;
 846
 847         return ret & mask;
 848 }
 849
 850 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 851 {
 852         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 853         u32 interruptibility = interruptibility_old;
 854
 855         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
 856
 857         if (mask & X86_SHADOW_INT_MOV_SS)
 858                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
 859         if (mask & X86_SHADOW_INT_STI)
 860                 interruptibility |= GUEST_INTR_STATE_STI;
 861
 862         if ((interruptibility != interruptibility_old))
 863                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
 864 }
 865
 866 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 867 {
 868         unsigned long rip;
 869
 870         rip = kvm_rip_read(vcpu);
 871         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 872         kvm_rip_write(vcpu, rip);
 873
 874         /* skipping an emulated instruction also counts */
 875         vmx_set_interrupt_shadow(vcpu, 0);
 876 }
 877
 878 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 879                                 bool has_error_code, u32 error_code)
 880 {
 881         struct vcpu_vmx *vmx = to_vmx(vcpu);
 882         u32 intr_info = nr | INTR_INFO_VALID_MASK;
 883
 884         if (has_error_code) {
 885                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 886                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
 887         }
 888
 889         if (vmx->rmode.vm86_active) {
 890                 vmx->rmode.irq.pending = true;
 891                 vmx->rmode.irq.vector = nr;
 892                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
 893                 if (kvm_exception_is_soft(nr))
 894                         vmx->rmode.irq.rip +=
 895                                 vmx->vcpu.arch.event_exit_inst_len;
 896                 intr_info |= INTR_TYPE_SOFT_INTR;
 897                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 898                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
 899                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
 900                 return;
 901         }
 902
 903         if (kvm_exception_is_soft(nr)) {
 904                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
 905                              vmx->vcpu.arch.event_exit_inst_len);
 906                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
 907         } else
 908                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
 909
 910         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 911 }
 912
 913 static bool vmx_rdtscp_supported(void)
 914 {
 915         return cpu_has_vmx_rdtscp();
 916 }
 917
 918 /*
 919  * Swap MSR entry in host/guest MSR entry array.
 920  */
 921 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 922 {
 923         struct shared_msr_entry tmp;
 924
 925         tmp = vmx->guest_msrs[to];
 926         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 927         vmx->guest_msrs[from] = tmp;
 928 }
 929
 930 /*
 931  * Set up the vmcs to automatically save and restore system
 932  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 933  * mode, as fiddling with msrs is very expensive.
 934  */
 935 static void setup_msrs(struct vcpu_vmx *vmx)
 936 {
 937         int save_nmsrs, index;
 938         unsigned long *msr_bitmap;
 939
 940         vmx_load_host_state(vmx);
 941         save_nmsrs = 0;
 942 #ifdef CONFIG_X86_64
 943         if (is_long_mode(&vmx->vcpu)) {
 944                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 945                 if (index >= 0)
 946                         move_msr_up(vmx, index, save_nmsrs++);
 947                 index = __find_msr_index(vmx, MSR_LSTAR);
 948                 if (index >= 0)
 949                         move_msr_up(vmx, index, save_nmsrs++);
 950                 index = __find_msr_index(vmx, MSR_CSTAR);
 951                 if (index >= 0)
 952                         move_msr_up(vmx, index, save_nmsrs++);
 953                 index = __find_msr_index(vmx, MSR_TSC_AUX);
 954                 if (index >= 0 && vmx->rdtscp_enabled)
 955                         move_msr_up(vmx, index, save_nmsrs++);
 956                 /*
 957                  * MSR_K6_STAR is only needed on long mode guests, and only
 958                  * if efer.sce is enabled.
 959                  */
 960                 index = __find_msr_index(vmx, MSR_K6_STAR);
 961                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
 962                         move_msr_up(vmx, index, save_nmsrs++);
 963         }
 964 #endif
 965         index = __find_msr_index(vmx, MSR_EFER);
 966         if (index >= 0 && update_transition_efer(vmx, index))
 967                 move_msr_up(vmx, index, save_nmsrs++);
 968
 969         vmx->save_nmsrs = save_nmsrs;
 970
 971         if (cpu_has_vmx_msr_bitmap()) {
 972                 if (is_long_mode(&vmx->vcpu))
 973                         msr_bitmap = vmx_msr_bitmap_longmode;
 974                 else
 975                         msr_bitmap = vmx_msr_bitmap_legacy;
 976
 977                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
 978         }
 979 }
 980
 981 /*
 982  * reads and returns guest's timestamp counter "register"
 983  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 984  */
 985 static u64 guest_read_tsc(void)
 986 {
 987         u64 host_tsc, tsc_offset;
 988
 989         rdtscll(host_tsc);
 990         tsc_offset = vmcs_read64(TSC_OFFSET);
 991         return host_tsc + tsc_offset;
 992 }
 993
 994 /*
 995  * writes 'guest_tsc' into guest's timestamp counter "register"
 996  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 997  */
 998 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
 999 {
1000         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
1001 }
1002
1003 /*
1004  * Reads an msr value (of 'msr_index') into 'pdata'.
1005  * Returns 0 on success, non-0 otherwise.
1006  * Assumes vcpu_load() was already called.
1007  */
1008 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1009 {
1010         u64 data;
1011         struct shared_msr_entry *msr;
1012
1013         if (!pdata) {
1014                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1015                 return -EINVAL;
1016         }
1017
1018         switch (msr_index) {
1019 #ifdef CONFIG_X86_64
1020         case MSR_FS_BASE:
1021                 data = vmcs_readl(GUEST_FS_BASE);
1022                 break;
1023         case MSR_GS_BASE:
1024                 data = vmcs_readl(GUEST_GS_BASE);
1025                 break;
1026         case MSR_KERNEL_GS_BASE:
1027                 vmx_load_host_state(to_vmx(vcpu));
1028                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1029                 break;
1030 #endif
1031         case MSR_EFER:
1032                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1033         case MSR_IA32_TSC:
1034                 data = guest_read_tsc();
1035                 break;
1036         case MSR_IA32_SYSENTER_CS:
1037                 data = vmcs_read32(GUEST_SYSENTER_CS);
1038                 break;
1039         case MSR_IA32_SYSENTER_EIP:
1040                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1041                 break;
1042         case MSR_IA32_SYSENTER_ESP:
1043                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1044                 break;
1045         case MSR_TSC_AUX:
1046                 if (!to_vmx(vcpu)->rdtscp_enabled)
1047                         return 1;
1048                 /* Otherwise falls through */
1049         default:
1050                 vmx_load_host_state(to_vmx(vcpu));
1051                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1052                 if (msr) {
1053                         vmx_load_host_state(to_vmx(vcpu));
1054                         data = msr->data;
1055                         break;
1056                 }
1057                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1058         }
1059
1060         *pdata = data;
1061         return 0;
1062 }
1063
1064 /*
1065  * Writes msr value into into the appropriate "register".
1066  * Returns 0 on success, non-0 otherwise.
1067  * Assumes vcpu_load() was already called.
1068  */
1069 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1070 {
1071         struct vcpu_vmx *vmx = to_vmx(vcpu);
1072         struct shared_msr_entry *msr;
1073         u64 host_tsc;
1074         int ret = 0;
1075
1076         switch (msr_index) {
1077         case MSR_EFER:
1078                 vmx_load_host_state(vmx);
1079                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1080                 break;
1081 #ifdef CONFIG_X86_64
1082         case MSR_FS_BASE:
1083                 vmcs_writel(GUEST_FS_BASE, data);
1084                 break;
1085         case MSR_GS_BASE:
1086                 vmcs_writel(GUEST_GS_BASE, data);
1087                 break;
1088         case MSR_KERNEL_GS_BASE:
1089                 vmx_load_host_state(vmx);
1090                 vmx->msr_guest_kernel_gs_base = data;
1091                 break;
1092 #endif
1093         case MSR_IA32_SYSENTER_CS:
1094                 vmcs_write32(GUEST_SYSENTER_CS, data);
1095                 break;
1096         case MSR_IA32_SYSENTER_EIP:
1097                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1098                 break;
1099         case MSR_IA32_SYSENTER_ESP:
1100                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1101                 break;
1102         case MSR_IA32_TSC:
1103                 rdtscll(host_tsc);
1104                 guest_write_tsc(data, host_tsc);
1105                 break;
1106         case MSR_IA32_CR_PAT:
1107                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1108                         vmcs_write64(GUEST_IA32_PAT, data);
1109                         vcpu->arch.pat = data;
1110                         break;
1111                 }
1112                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1113                 break;
1114         case MSR_TSC_AUX:
1115                 if (!vmx->rdtscp_enabled)
1116                         return 1;
1117                 /* Check reserved bit, higher 32 bits should be zero */
1118                 if ((data >> 32) != 0)
1119                         return 1;
1120                 /* Otherwise falls through */
1121         default:
1122                 msr = find_msr_entry(vmx, msr_index);
1123                 if (msr) {
1124                         vmx_load_host_state(vmx);
1125                         msr->data = data;
1126                         break;
1127                 }
1128                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1129         }
1130
1131         return ret;
1132 }
1133
1134 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1135 {
1136         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1137         switch (reg) {
1138         case VCPU_REGS_RSP:
1139                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1140                 break;
1141         case VCPU_REGS_RIP:
1142                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1143                 break;
1144         case VCPU_EXREG_PDPTR:
1145                 if (enable_ept)
1146                         ept_save_pdptrs(vcpu);
1147                 break;
1148         default:
1149                 break;
1150         }
1151 }
1152
1153 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1154 {
1155         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1156                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1157         else
1158                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1159
1160         update_exception_bitmap(vcpu);
1161 }
1162
1163 static __init int cpu_has_kvm_support(void)
1164 {
1165         return cpu_has_vmx();
1166 }
1167
1168 static __init int vmx_disabled_by_bios(void)
1169 {
1170         u64 msr;
1171
1172         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1173         return (msr & (FEATURE_CONTROL_LOCKED |
1174                        FEATURE_CONTROL_VMXON_ENABLED))
1175             == FEATURE_CONTROL_LOCKED;
1176         /* locked but not enabled */
1177 }
1178
1179 static int hardware_enable(void *garbage)
1180 {
1181         int cpu = raw_smp_processor_id();
1182         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1183         u64 old;
1184
1185         if (read_cr4() & X86_CR4_VMXE)
1186                 return -EBUSY;
1187
1188         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1189         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1190         if ((old & (FEATURE_CONTROL_LOCKED |
1191                     FEATURE_CONTROL_VMXON_ENABLED))
1192             != (FEATURE_CONTROL_LOCKED |
1193                 FEATURE_CONTROL_VMXON_ENABLED))
1194                 /* enable and lock */
1195                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1196                        FEATURE_CONTROL_LOCKED |
1197                        FEATURE_CONTROL_VMXON_ENABLED);
1198         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1199         asm volatile (ASM_VMX_VMXON_RAX
1200                       : : "a"(&phys_addr), "m"(phys_addr)
1201                       : "memory", "cc");
1202
1203         ept_sync_global();
1204
1205         return 0;
1206 }
1207
1208 static void vmclear_local_vcpus(void)
1209 {
1210         int cpu = raw_smp_processor_id();
1211         struct vcpu_vmx *vmx, *n;
1212
1213         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1214                                  local_vcpus_link)
1215                 __vcpu_clear(vmx);
1216 }
1217
1218
1219 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1220  * tricks.
1221  */
1222 static void kvm_cpu_vmxoff(void)
1223 {
1224         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1225         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1226 }
1227
1228 static void hardware_disable(void *garbage)
1229 {
1230         vmclear_local_vcpus();
1231         kvm_cpu_vmxoff();
1232 }
1233
1234 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1235                                       u32 msr, u32 *result)
1236 {
1237         u32 vmx_msr_low, vmx_msr_high;
1238         u32 ctl = ctl_min | ctl_opt;
1239
1240         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1241
1242         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1243         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1244
1245         /* Ensure minimum (required) set of control bits are supported. */
1246         if (ctl_min & ~ctl)
1247                 return -EIO;
1248
1249         *result = ctl;
1250         return 0;
1251 }
1252
1253 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1254 {
1255         u32 vmx_msr_low, vmx_msr_high;
1256         u32 min, opt, min2, opt2;
1257         u32 _pin_based_exec_control = 0;
1258         u32 _cpu_based_exec_control = 0;
1259         u32 _cpu_based_2nd_exec_control = 0;
1260         u32 _vmexit_control = 0;
1261         u32 _vmentry_control = 0;
1262
1263         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1264         opt = PIN_BASED_VIRTUAL_NMIS;
1265         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1266                                 &_pin_based_exec_control) < 0)
1267                 return -EIO;
1268
1269         min = CPU_BASED_HLT_EXITING |
1270 #ifdef CONFIG_X86_64
1271               CPU_BASED_CR8_LOAD_EXITING |
1272               CPU_BASED_CR8_STORE_EXITING |
1273 #endif
1274               CPU_BASED_CR3_LOAD_EXITING |
1275               CPU_BASED_CR3_STORE_EXITING |
1276               CPU_BASED_USE_IO_BITMAPS |
1277               CPU_BASED_MOV_DR_EXITING |
1278               CPU_BASED_USE_TSC_OFFSETING |
1279               CPU_BASED_MWAIT_EXITING |
1280               CPU_BASED_MONITOR_EXITING |
1281               CPU_BASED_INVLPG_EXITING;
1282         opt = CPU_BASED_TPR_SHADOW |
1283               CPU_BASED_USE_MSR_BITMAPS |
1284               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1285         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1286                                 &_cpu_based_exec_control) < 0)
1287                 return -EIO;
1288 #ifdef CONFIG_X86_64
1289         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1290                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1291                                            ~CPU_BASED_CR8_STORE_EXITING;
1292 #endif
1293         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1294                 min2 = 0;
1295                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1296                         SECONDARY_EXEC_WBINVD_EXITING |
1297                         SECONDARY_EXEC_ENABLE_VPID |
1298                         SECONDARY_EXEC_ENABLE_EPT |
1299                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
1300                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1301                         SECONDARY_EXEC_RDTSCP;
1302                 if (adjust_vmx_controls(min2, opt2,
1303                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1304                                         &_cpu_based_2nd_exec_control) < 0)
1305                         return -EIO;
1306         }
1307 #ifndef CONFIG_X86_64
1308         if (!(_cpu_based_2nd_exec_control &
1309                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1310                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1311 #endif
1312         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1313                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1314                    enabled */
1315                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1316                                              CPU_BASED_CR3_STORE_EXITING |
1317                                              CPU_BASED_INVLPG_EXITING);
1318                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1319                       vmx_capability.ept, vmx_capability.vpid);
1320         }
1321
1322         min = 0;
1323 #ifdef CONFIG_X86_64
1324         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1325 #endif
1326         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1327         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1328                                 &_vmexit_control) < 0)
1329                 return -EIO;
1330
1331         min = 0;
1332         opt = VM_ENTRY_LOAD_IA32_PAT;
1333         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1334                                 &_vmentry_control) < 0)
1335                 return -EIO;
1336
1337         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1338
1339         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1340         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1341                 return -EIO;
1342
1343 #ifdef CONFIG_X86_64
1344         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1345         if (vmx_msr_high & (1u<<16))
1346                 return -EIO;
1347 #endif
1348
1349         /* Require Write-Back (WB) memory type for VMCS accesses. */
1350         if (((vmx_msr_high >> 18) & 15) != 6)
1351                 return -EIO;
1352
1353         vmcs_conf->size = vmx_msr_high & 0x1fff;
1354         vmcs_conf->order = get_order(vmcs_config.size);
1355         vmcs_conf->revision_id = vmx_msr_low;
1356
1357         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1358         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1359         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1360         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1361         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1362
1363         return 0;
1364 }
1365
1366 static struct vmcs *alloc_vmcs_cpu(int cpu)
1367 {
1368         int node = cpu_to_node(cpu);
1369         struct page *pages;
1370         struct vmcs *vmcs;
1371
1372         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1373         if (!pages)
1374                 return NULL;
1375         vmcs = page_address(pages);
1376         memset(vmcs, 0, vmcs_config.size);
1377         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1378         return vmcs;
1379 }
1380
1381 static struct vmcs *alloc_vmcs(void)
1382 {
1383         return alloc_vmcs_cpu(raw_smp_processor_id());
1384 }
1385
1386 static void free_vmcs(struct vmcs *vmcs)
1387 {
1388         free_pages((unsigned long)vmcs, vmcs_config.order);
1389 }
1390
1391 static void free_kvm_area(void)
1392 {
1393         int cpu;
1394
1395         for_each_possible_cpu(cpu) {
1396                 free_vmcs(per_cpu(vmxarea, cpu));
1397                 per_cpu(vmxarea, cpu) = NULL;
1398         }
1399 }
1400
1401 static __init int alloc_kvm_area(void)
1402 {
1403         int cpu;
1404
1405         for_each_possible_cpu(cpu) {
1406                 struct vmcs *vmcs;
1407
1408                 vmcs = alloc_vmcs_cpu(cpu);
1409                 if (!vmcs) {
1410                         free_kvm_area();
1411                         return -ENOMEM;
1412                 }
1413
1414                 per_cpu(vmxarea, cpu) = vmcs;
1415         }
1416         return 0;
1417 }
1418
1419 static __init int hardware_setup(void)
1420 {
1421         if (setup_vmcs_config(&vmcs_config) < 0)
1422                 return -EIO;
1423
1424         if (boot_cpu_has(X86_FEATURE_NX))
1425                 kvm_enable_efer_bits(EFER_NX);
1426
1427         if (!cpu_has_vmx_vpid())
1428                 enable_vpid = 0;
1429
1430         if (!cpu_has_vmx_ept()) {
1431                 enable_ept = 0;
1432                 enable_unrestricted_guest = 0;
1433         }
1434
1435         if (!cpu_has_vmx_unrestricted_guest())
1436                 enable_unrestricted_guest = 0;
1437
1438         if (!cpu_has_vmx_flexpriority())
1439                 flexpriority_enabled = 0;
1440
1441         if (!cpu_has_vmx_tpr_shadow())
1442                 kvm_x86_ops->update_cr8_intercept = NULL;
1443
1444         if (enable_ept && !cpu_has_vmx_ept_2m_page())
1445                 kvm_disable_largepages();
1446
1447         if (!cpu_has_vmx_ple())
1448                 ple_gap = 0;
1449
1450         return alloc_kvm_area();
1451 }
1452
1453 static __exit void hardware_unsetup(void)
1454 {
1455         free_kvm_area();
1456 }
1457
1458 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1459 {
1460         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1461
1462         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1463                 vmcs_write16(sf->selector, save->selector);
1464                 vmcs_writel(sf->base, save->base);
1465                 vmcs_write32(sf->limit, save->limit);
1466                 vmcs_write32(sf->ar_bytes, save->ar);
1467         } else {
1468                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1469                         << AR_DPL_SHIFT;
1470                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1471         }
1472 }
1473
1474 static void enter_pmode(struct kvm_vcpu *vcpu)
1475 {
1476         unsigned long flags;
1477         struct vcpu_vmx *vmx = to_vmx(vcpu);
1478
1479         vmx->emulation_required = 1;
1480         vmx->rmode.vm86_active = 0;
1481
1482         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1483         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1484         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1485
1486         flags = vmcs_readl(GUEST_RFLAGS);
1487         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1488         flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
1489         vmcs_writel(GUEST_RFLAGS, flags);
1490
1491         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1492                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1493
1494         update_exception_bitmap(vcpu);
1495
1496         if (emulate_invalid_guest_state)
1497                 return;
1498
1499         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1500         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1501         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1502         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1503
1504         vmcs_write16(GUEST_SS_SELECTOR, 0);
1505         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1506
1507         vmcs_write16(GUEST_CS_SELECTOR,
1508                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1509         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1510 }
1511
1512 static gva_t rmode_tss_base(struct kvm *kvm)
1513 {
1514         if (!kvm->arch.tss_addr) {
1515                 struct kvm_memslots *slots;
1516                 gfn_t base_gfn;
1517
1518                 slots = rcu_dereference(kvm->memslots);
1519                 base_gfn = kvm->memslots->memslots[0].base_gfn +
1520                                  kvm->memslots->memslots[0].npages - 3;
1521                 return base_gfn << PAGE_SHIFT;
1522         }
1523         return kvm->arch.tss_addr;
1524 }
1525
1526 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1527 {
1528         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1529
1530         save->selector = vmcs_read16(sf->selector);
1531         save->base = vmcs_readl(sf->base);
1532         save->limit = vmcs_read32(sf->limit);
1533         save->ar = vmcs_read32(sf->ar_bytes);
1534         vmcs_write16(sf->selector, save->base >> 4);
1535         vmcs_write32(sf->base, save->base & 0xfffff);
1536         vmcs_write32(sf->limit, 0xffff);
1537         vmcs_write32(sf->ar_bytes, 0xf3);
1538 }
1539
1540 static void enter_rmode(struct kvm_vcpu *vcpu)
1541 {
1542         unsigned long flags;
1543         struct vcpu_vmx *vmx = to_vmx(vcpu);
1544
1545         if (enable_unrestricted_guest)
1546                 return;
1547
1548         vmx->emulation_required = 1;
1549         vmx->rmode.vm86_active = 1;
1550
1551         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1552         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1553
1554         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1555         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1556
1557         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1558         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1559
1560         flags = vmcs_readl(GUEST_RFLAGS);
1561         vmx->rmode.save_iopl
1562                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1563
1564         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1565
1566         vmcs_writel(GUEST_RFLAGS, flags);
1567         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1568         update_exception_bitmap(vcpu);
1569
1570         if (emulate_invalid_guest_state)
1571                 goto continue_rmode;
1572
1573         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1574         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1575         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1576
1577         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1578         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1579         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1580                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1581         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1582
1583         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1584         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1585         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1586         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1587
1588 continue_rmode:
1589         kvm_mmu_reset_context(vcpu);
1590         init_rmode(vcpu->kvm);
1591 }
1592
1593 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1594 {
1595         struct vcpu_vmx *vmx = to_vmx(vcpu);
1596         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1597
1598         if (!msr)
1599                 return;
1600
1601         /*
1602          * Force kernel_gs_base reloading before EFER changes, as control
1603          * of this msr depends on is_long_mode().
1604          */
1605         vmx_load_host_state(to_vmx(vcpu));
1606         vcpu->arch.efer = efer;
1607         if (!msr)
1608                 return;
1609         if (efer & EFER_LMA) {
1610                 vmcs_write32(VM_ENTRY_CONTROLS,
1611                              vmcs_read32(VM_ENTRY_CONTROLS) |
1612                              VM_ENTRY_IA32E_MODE);
1613                 msr->data = efer;
1614         } else {
1615                 vmcs_write32(VM_ENTRY_CONTROLS,
1616                              vmcs_read32(VM_ENTRY_CONTROLS) &
1617                              ~VM_ENTRY_IA32E_MODE);
1618
1619                 msr->data = efer & ~EFER_LME;
1620         }
1621         setup_msrs(vmx);
1622 }
1623
1624 #ifdef CONFIG_X86_64
1625
1626 static void enter_lmode(struct kvm_vcpu *vcpu)
1627 {
1628         u32 guest_tr_ar;
1629
1630         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1631         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1632                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1633                        __func__);
1634                 vmcs_write32(GUEST_TR_AR_BYTES,
1635                              (guest_tr_ar & ~AR_TYPE_MASK)
1636                              | AR_TYPE_BUSY_64_TSS);
1637         }
1638         vcpu->arch.efer |= EFER_LMA;
1639         vmx_set_efer(vcpu, vcpu->arch.efer);
1640 }
1641
1642 static void exit_lmode(struct kvm_vcpu *vcpu)
1643 {
1644         vcpu->arch.efer &= ~EFER_LMA;
1645
1646         vmcs_write32(VM_ENTRY_CONTROLS,
1647                      vmcs_read32(VM_ENTRY_CONTROLS)
1648                      & ~VM_ENTRY_IA32E_MODE);
1649 }
1650
1651 #endif
1652
1653 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1654 {
1655         vpid_sync_vcpu_all(to_vmx(vcpu));
1656         if (enable_ept)
1657                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1658 }
1659
1660 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1661 {
1662         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1663
1664         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1665         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1666 }
1667
1668 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1669 {
1670         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1671
1672         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1673         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1674 }
1675
1676 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1677 {
1678         if (!test_bit(VCPU_EXREG_PDPTR,
1679                       (unsigned long *)&vcpu->arch.regs_dirty))
1680                 return;
1681
1682         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1683                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1684                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1685                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1686                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1687         }
1688 }
1689
1690 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1691 {
1692         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1693                 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1694                 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1695                 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1696                 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1697         }
1698
1699         __set_bit(VCPU_EXREG_PDPTR,
1700                   (unsigned long *)&vcpu->arch.regs_avail);
1701         __set_bit(VCPU_EXREG_PDPTR,
1702                   (unsigned long *)&vcpu->arch.regs_dirty);
1703 }
1704
1705 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1706
1707 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1708                                         unsigned long cr0,
1709                                         struct kvm_vcpu *vcpu)
1710 {
1711         if (!(cr0 & X86_CR0_PG)) {
1712                 /* From paging/starting to nonpaging */
1713                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1714                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1715                              (CPU_BASED_CR3_LOAD_EXITING |
1716                               CPU_BASED_CR3_STORE_EXITING));
1717                 vcpu->arch.cr0 = cr0;
1718                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1719         } else if (!is_paging(vcpu)) {
1720                 /* From nonpaging to paging */
1721                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1722                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1723                              ~(CPU_BASED_CR3_LOAD_EXITING |
1724                                CPU_BASED_CR3_STORE_EXITING));
1725                 vcpu->arch.cr0 = cr0;
1726                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1727         }
1728
1729         if (!(cr0 & X86_CR0_WP))
1730                 *hw_cr0 &= ~X86_CR0_WP;
1731 }
1732
1733 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1734 {
1735         struct vcpu_vmx *vmx = to_vmx(vcpu);
1736         unsigned long hw_cr0;
1737
1738         if (enable_unrestricted_guest)
1739                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1740                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1741         else
1742                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1743
1744         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1745                 enter_pmode(vcpu);
1746
1747         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1748                 enter_rmode(vcpu);
1749
1750 #ifdef CONFIG_X86_64
1751         if (vcpu->arch.efer & EFER_LME) {
1752                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1753                         enter_lmode(vcpu);
1754                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1755                         exit_lmode(vcpu);
1756         }
1757 #endif
1758
1759         if (enable_ept)
1760                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1761
1762         if (!vcpu->fpu_active)
1763                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
1764
1765         vmcs_writel(CR0_READ_SHADOW, cr0);
1766         vmcs_writel(GUEST_CR0, hw_cr0);
1767         vcpu->arch.cr0 = cr0;
1768 }
1769
1770 static u64 construct_eptp(unsigned long root_hpa)
1771 {
1772         u64 eptp;
1773
1774         /* TODO write the value reading from MSR */
1775         eptp = VMX_EPT_DEFAULT_MT |
1776                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1777         eptp |= (root_hpa & PAGE_MASK);
1778
1779         return eptp;
1780 }
1781
1782 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1783 {
1784         unsigned long guest_cr3;
1785         u64 eptp;
1786
1787         guest_cr3 = cr3;
1788         if (enable_ept) {
1789                 eptp = construct_eptp(cr3);
1790                 vmcs_write64(EPT_POINTER, eptp);
1791                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1792                         vcpu->kvm->arch.ept_identity_map_addr;
1793                 ept_load_pdptrs(vcpu);
1794         }
1795
1796         vmx_flush_tlb(vcpu);
1797         vmcs_writel(GUEST_CR3, guest_cr3);
1798 }
1799
1800 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1801 {
1802         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1803                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1804
1805         vcpu->arch.cr4 = cr4;
1806         if (enable_ept) {
1807                 if (!is_paging(vcpu)) {
1808                         hw_cr4 &= ~X86_CR4_PAE;
1809                         hw_cr4 |= X86_CR4_PSE;
1810                 } else if (!(cr4 & X86_CR4_PAE)) {
1811                         hw_cr4 &= ~X86_CR4_PAE;
1812                 }
1813         }
1814
1815         vmcs_writel(CR4_READ_SHADOW, cr4);
1816         vmcs_writel(GUEST_CR4, hw_cr4);
1817 }
1818
1819 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1820 {
1821         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1822
1823         return vmcs_readl(sf->base);
1824 }
1825
1826 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1827                             struct kvm_segment *var, int seg)
1828 {
1829         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1830         u32 ar;
1831
1832         var->base = vmcs_readl(sf->base);
1833         var->limit = vmcs_read32(sf->limit);
1834         var->selector = vmcs_read16(sf->selector);
1835         ar = vmcs_read32(sf->ar_bytes);
1836         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1837                 ar = 0;
1838         var->type = ar & 15;
1839         var->s = (ar >> 4) & 1;
1840         var->dpl = (ar >> 5) & 3;
1841         var->present = (ar >> 7) & 1;
1842         var->avl = (ar >> 12) & 1;
1843         var->l = (ar >> 13) & 1;
1844         var->db = (ar >> 14) & 1;
1845         var->g = (ar >> 15) & 1;
1846         var->unusable = (ar >> 16) & 1;
1847 }
1848
1849 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1850 {
1851         if (!is_protmode(vcpu))
1852                 return 0;
1853
1854         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1855                 return 3;
1856
1857         return vmcs_read16(GUEST_CS_SELECTOR) & 3;
1858 }
1859
1860 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1861 {
1862         u32 ar;
1863
1864         if (var->unusable)
1865                 ar = 1 << 16;
1866         else {
1867                 ar = var->type & 15;
1868                 ar |= (var->s & 1) << 4;
1869                 ar |= (var->dpl & 3) << 5;
1870                 ar |= (var->present & 1) << 7;
1871                 ar |= (var->avl & 1) << 12;
1872                 ar |= (var->l & 1) << 13;
1873                 ar |= (var->db & 1) << 14;
1874                 ar |= (var->g & 1) << 15;
1875         }
1876         if (ar == 0) /* a 0 value means unusable */
1877                 ar = AR_UNUSABLE_MASK;
1878
1879         return ar;
1880 }
1881
1882 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1883                             struct kvm_segment *var, int seg)
1884 {
1885         struct vcpu_vmx *vmx = to_vmx(vcpu);
1886         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1887         u32 ar;
1888
1889         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1890                 vmx->rmode.tr.selector = var->selector;
1891                 vmx->rmode.tr.base = var->base;
1892                 vmx->rmode.tr.limit = var->limit;
1893                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
1894                 return;
1895         }
1896         vmcs_writel(sf->base, var->base);
1897         vmcs_write32(sf->limit, var->limit);
1898         vmcs_write16(sf->selector, var->selector);
1899         if (vmx->rmode.vm86_active && var->s) {
1900                 /*
1901                  * Hack real-mode segments into vm86 compatibility.
1902                  */
1903                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1904                         vmcs_writel(sf->base, 0xf0000);
1905                 ar = 0xf3;
1906         } else
1907                 ar = vmx_segment_access_rights(var);
1908
1909         /*
1910          *   Fix the "Accessed" bit in AR field of segment registers for older
1911          * qemu binaries.
1912          *   IA32 arch specifies that at the time of processor reset the
1913          * "Accessed" bit in the AR field of segment registers is 1. And qemu
1914          * is setting it to 0 in the usedland code. This causes invalid guest
1915          * state vmexit when "unrestricted guest" mode is turned on.
1916          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
1917          * tree. Newer qemu binaries with that qemu fix would not need this
1918          * kvm hack.
1919          */
1920         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1921                 ar |= 0x1; /* Accessed */
1922
1923         vmcs_write32(sf->ar_bytes, ar);
1924 }
1925
1926 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1927 {
1928         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1929
1930         *db = (ar >> 14) & 1;
1931         *l = (ar >> 13) & 1;
1932 }
1933
1934 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1935 {
1936         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1937         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1938 }
1939
1940 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1941 {
1942         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1943         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1944 }
1945
1946 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1947 {
1948         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1949         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1950 }
1951
1952 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1953 {
1954         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1955         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1956 }
1957
1958 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1959 {
1960         struct kvm_segment var;
1961         u32 ar;
1962
1963         vmx_get_segment(vcpu, &var, seg);
1964         ar = vmx_segment_access_rights(&var);
1965
1966         if (var.base != (var.selector << 4))
1967                 return false;
1968         if (var.limit != 0xffff)
1969                 return false;
1970         if (ar != 0xf3)
1971                 return false;
1972
1973         return true;
1974 }
1975
1976 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1977 {
1978         struct kvm_segment cs;
1979         unsigned int cs_rpl;
1980
1981         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1982         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1983
1984         if (cs.unusable)
1985                 return false;
1986         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1987                 return false;
1988         if (!cs.s)
1989                 return false;
1990         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1991                 if (cs.dpl > cs_rpl)
1992                         return false;
1993         } else {
1994                 if (cs.dpl != cs_rpl)
1995                         return false;
1996         }
1997         if (!cs.present)
1998                 return false;
1999
2000         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2001         return true;
2002 }
2003
2004 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2005 {
2006         struct kvm_segment ss;
2007         unsigned int ss_rpl;
2008
2009         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2010         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2011
2012         if (ss.unusable)
2013                 return true;
2014         if (ss.type != 3 && ss.type != 7)
2015                 return false;
2016         if (!ss.s)
2017                 return false;
2018         if (ss.dpl != ss_rpl) /* DPL != RPL */
2019                 return false;
2020         if (!ss.present)
2021                 return false;
2022
2023         return true;
2024 }
2025
2026 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2027 {
2028         struct kvm_segment var;
2029         unsigned int rpl;
2030
2031         vmx_get_segment(vcpu, &var, seg);
2032         rpl = var.selector & SELECTOR_RPL_MASK;
2033
2034         if (var.unusable)
2035                 return true;
2036         if (!var.s)
2037                 return false;
2038         if (!var.present)
2039                 return false;
2040         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2041                 if (var.dpl < rpl) /* DPL < RPL */
2042                         return false;
2043         }
2044
2045         /* TODO: Add other members to kvm_segment_field to allow checking for other access
2046          * rights flags
2047          */
2048         return true;
2049 }
2050
2051 static bool tr_valid(struct kvm_vcpu *vcpu)
2052 {
2053         struct kvm_segment tr;
2054
2055         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2056
2057         if (tr.unusable)
2058                 return false;
2059         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
2060                 return false;
2061         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2062                 return false;
2063         if (!tr.present)
2064                 return false;
2065
2066         return true;
2067 }
2068
2069 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2070 {
2071         struct kvm_segment ldtr;
2072
2073         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2074
2075         if (ldtr.unusable)
2076                 return true;
2077         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
2078                 return false;
2079         if (ldtr.type != 2)
2080                 return false;
2081         if (!ldtr.present)
2082                 return false;
2083
2084         return true;
2085 }
2086
2087 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2088 {
2089         struct kvm_segment cs, ss;
2090
2091         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2092         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2093
2094         return ((cs.selector & SELECTOR_RPL_MASK) ==
2095                  (ss.selector & SELECTOR_RPL_MASK));
2096 }
2097
2098 /*
2099  * Check if guest state is valid. Returns true if valid, false if
2100  * not.
2101  * We assume that registers are always usable
2102  */
2103 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2104 {
2105         /* real mode guest state checks */
2106         if (!is_protmode(vcpu)) {
2107                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2108                         return false;
2109                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2110                         return false;
2111                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2112                         return false;
2113                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2114                         return false;
2115                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2116                         return false;
2117                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2118                         return false;
2119         } else {
2120         /* protected mode guest state checks */
2121                 if (!cs_ss_rpl_check(vcpu))
2122                         return false;
2123                 if (!code_segment_valid(vcpu))
2124                         return false;
2125                 if (!stack_segment_valid(vcpu))
2126                         return false;
2127                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2128                         return false;
2129                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2130                         return false;
2131                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2132                         return false;
2133                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2134                         return false;
2135                 if (!tr_valid(vcpu))
2136                         return false;
2137                 if (!ldtr_valid(vcpu))
2138                         return false;
2139         }
2140         /* TODO:
2141          * - Add checks on RIP
2142          * - Add checks on RFLAGS
2143          */
2144
2145         return true;
2146 }
2147
2148 static int init_rmode_tss(struct kvm *kvm)
2149 {
2150         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2151         u16 data = 0;
2152         int ret = 0;
2153         int r;
2154
2155         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2156         if (r < 0)
2157                 goto out;
2158         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2159         r = kvm_write_guest_page(kvm, fn++, &data,
2160                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
2161         if (r < 0)
2162                 goto out;
2163         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2164         if (r < 0)
2165                 goto out;
2166         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2167         if (r < 0)
2168                 goto out;
2169         data = ~0;
2170         r = kvm_write_guest_page(kvm, fn, &data,
2171                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2172                                  sizeof(u8));
2173         if (r < 0)
2174                 goto out;
2175
2176         ret = 1;
2177 out:
2178         return ret;
2179 }
2180
2181 static int init_rmode_identity_map(struct kvm *kvm)
2182 {
2183         int i, r, ret;
2184         pfn_t identity_map_pfn;
2185         u32 tmp;
2186
2187         if (!enable_ept)
2188                 return 1;
2189         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2190                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2191                         "haven't been allocated!\n");
2192                 return 0;
2193         }
2194         if (likely(kvm->arch.ept_identity_pagetable_done))
2195                 return 1;
2196         ret = 0;
2197         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2198         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2199         if (r < 0)
2200                 goto out;
2201         /* Set up identity-mapping pagetable for EPT in real mode */
2202         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2203                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2204                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2205                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2206                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2207                 if (r < 0)
2208                         goto out;
2209         }
2210         kvm->arch.ept_identity_pagetable_done = true;
2211         ret = 1;
2212 out:
2213         return ret;
2214 }
2215
2216 static void seg_setup(int seg)
2217 {
2218         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2219         unsigned int ar;
2220
2221         vmcs_write16(sf->selector, 0);
2222         vmcs_writel(sf->base, 0);
2223         vmcs_write32(sf->limit, 0xffff);
2224         if (enable_unrestricted_guest) {
2225                 ar = 0x93;
2226                 if (seg == VCPU_SREG_CS)
2227                         ar |= 0x08; /* code segment */
2228         } else
2229                 ar = 0xf3;
2230
2231         vmcs_write32(sf->ar_bytes, ar);
2232 }
2233
2234 static int alloc_apic_access_page(struct kvm *kvm)
2235 {
2236         struct kvm_userspace_memory_region kvm_userspace_mem;
2237         int r = 0;
2238
2239         mutex_lock(&kvm->slots_lock);
2240         if (kvm->arch.apic_access_page)
2241                 goto out;
2242         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2243         kvm_userspace_mem.flags = 0;
2244         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2245         kvm_userspace_mem.memory_size = PAGE_SIZE;
2246         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2247         if (r)
2248                 goto out;
2249
2250         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2251 out:
2252         mutex_unlock(&kvm->slots_lock);
2253         return r;
2254 }
2255
2256 static int alloc_identity_pagetable(struct kvm *kvm)
2257 {
2258         struct kvm_userspace_memory_region kvm_userspace_mem;
2259         int r = 0;
2260
2261         mutex_lock(&kvm->slots_lock);
2262         if (kvm->arch.ept_identity_pagetable)
2263                 goto out;
2264         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2265         kvm_userspace_mem.flags = 0;
2266         kvm_userspace_mem.guest_phys_addr =
2267                 kvm->arch.ept_identity_map_addr;
2268         kvm_userspace_mem.memory_size = PAGE_SIZE;
2269         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2270         if (r)
2271                 goto out;
2272
2273         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2274                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2275 out:
2276         mutex_unlock(&kvm->slots_lock);
2277         return r;
2278 }
2279
2280 static void allocate_vpid(struct vcpu_vmx *vmx)
2281 {
2282         int vpid;
2283
2284         vmx->vpid = 0;
2285         if (!enable_vpid)
2286                 return;
2287         spin_lock(&vmx_vpid_lock);
2288         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2289         if (vpid < VMX_NR_VPIDS) {
2290                 vmx->vpid = vpid;
2291                 __set_bit(vpid, vmx_vpid_bitmap);
2292         }
2293         spin_unlock(&vmx_vpid_lock);
2294 }
2295
2296 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2297 {
2298         int f = sizeof(unsigned long);
2299
2300         if (!cpu_has_vmx_msr_bitmap())
2301                 return;
2302
2303         /*
2304          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2305          * have the write-low and read-high bitmap offsets the wrong way round.
2306          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2307          */
2308         if (msr <= 0x1fff) {
2309                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2310                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2311         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2312                 msr &= 0x1fff;
2313                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2314                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2315         }
2316 }
2317
2318 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2319 {
2320         if (!longmode_only)
2321                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2322         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2323 }
2324
2325 /*
2326  * Sets up the vmcs for emulated real mode.
2327  */
2328 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2329 {
2330         u32 host_sysenter_cs, msr_low, msr_high;
2331         u32 junk;
2332         u64 host_pat, tsc_this, tsc_base;
2333         unsigned long a;
2334         struct descriptor_table dt;
2335         int i;
2336         unsigned long kvm_vmx_return;
2337         u32 exec_control;
2338
2339         /* I/O */
2340         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2341         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2342
2343         if (cpu_has_vmx_msr_bitmap())
2344                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2345
2346         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2347
2348         /* Control */
2349         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2350                 vmcs_config.pin_based_exec_ctrl);
2351
2352         exec_control = vmcs_config.cpu_based_exec_ctrl;
2353         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2354                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2355 #ifdef CONFIG_X86_64
2356                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2357                                 CPU_BASED_CR8_LOAD_EXITING;
2358 #endif
2359         }
2360         if (!enable_ept)
2361                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2362                                 CPU_BASED_CR3_LOAD_EXITING  |
2363                                 CPU_BASED_INVLPG_EXITING;
2364         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2365
2366         if (cpu_has_secondary_exec_ctrls()) {
2367                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2368                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2369                         exec_control &=
2370                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2371                 if (vmx->vpid == 0)
2372                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2373                 if (!enable_ept) {
2374                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2375                         enable_unrestricted_guest = 0;
2376                 }
2377                 if (!enable_unrestricted_guest)
2378                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2379                 if (!ple_gap)
2380                         exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2381                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2382         }
2383
2384         if (ple_gap) {
2385                 vmcs_write32(PLE_GAP, ple_gap);
2386                 vmcs_write32(PLE_WINDOW, ple_window);
2387         }
2388
2389         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2390         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2391         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2392
2393         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
2394         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2395         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2396
2397         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2398         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2399         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2400         vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs());    /* 22.2.4 */
2401         vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs());    /* 22.2.4 */
2402         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2403 #ifdef CONFIG_X86_64
2404         rdmsrl(MSR_FS_BASE, a);
2405         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2406         rdmsrl(MSR_GS_BASE, a);
2407         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2408 #else
2409         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2410         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2411 #endif
2412
2413         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2414
2415         kvm_get_idt(&dt);
2416         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
2417
2418         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2419         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2420         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2421         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2422         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2423
2424         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2425         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2426         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2427         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2428         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2429         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2430
2431         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2432                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2433                 host_pat = msr_low | ((u64) msr_high << 32);
2434                 vmcs_write64(HOST_IA32_PAT, host_pat);
2435         }
2436         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2437                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2438                 host_pat = msr_low | ((u64) msr_high << 32);
2439                 /* Write the default value follow host pat */
2440                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2441                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2442                 vmx->vcpu.arch.pat = host_pat;
2443         }
2444
2445         for (i = 0; i < NR_VMX_MSR; ++i) {
2446                 u32 index = vmx_msr_index[i];
2447                 u32 data_low, data_high;
2448                 int j = vmx->nmsrs;
2449
2450                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2451                         continue;
2452                 if (wrmsr_safe(index, data_low, data_high) < 0)
2453                         continue;
2454                 vmx->guest_msrs[j].index = i;
2455                 vmx->guest_msrs[j].data = 0;
2456                 vmx->guest_msrs[j].mask = -1ull;
2457                 ++vmx->nmsrs;
2458         }
2459
2460         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2461
2462         /* 22.2.1, 20.8.1 */
2463         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2464
2465         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2466         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2467         if (enable_ept)
2468                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2469         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2470
2471         tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2472         rdtscll(tsc_this);
2473         if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2474                 tsc_base = tsc_this;
2475
2476         guest_write_tsc(0, tsc_base);
2477
2478         return 0;
2479 }
2480
2481 static int init_rmode(struct kvm *kvm)
2482 {
2483         if (!init_rmode_tss(kvm))
2484                 return 0;
2485         if (!init_rmode_identity_map(kvm))
2486                 return 0;
2487         return 1;
2488 }
2489
2490 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2491 {
2492         struct vcpu_vmx *vmx = to_vmx(vcpu);
2493         u64 msr;
2494         int ret, idx;
2495
2496         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2497         idx = srcu_read_lock(&vcpu->kvm->srcu);
2498         if (!init_rmode(vmx->vcpu.kvm)) {
2499                 ret = -ENOMEM;
2500                 goto out;
2501         }
2502
2503         vmx->rmode.vm86_active = 0;
2504
2505         vmx->soft_vnmi_blocked = 0;
2506
2507         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2508         kvm_set_cr8(&vmx->vcpu, 0);
2509         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2510         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2511                 msr |= MSR_IA32_APICBASE_BSP;
2512         kvm_set_apic_base(&vmx->vcpu, msr);
2513
2514         fx_init(&vmx->vcpu);
2515
2516         seg_setup(VCPU_SREG_CS);
2517         /*
2518          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2519          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2520          */
2521         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2522                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2523                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2524         } else {
2525                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2526                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2527         }
2528
2529         seg_setup(VCPU_SREG_DS);
2530         seg_setup(VCPU_SREG_ES);
2531         seg_setup(VCPU_SREG_FS);
2532         seg_setup(VCPU_SREG_GS);
2533         seg_setup(VCPU_SREG_SS);
2534
2535         vmcs_write16(GUEST_TR_SELECTOR, 0);
2536         vmcs_writel(GUEST_TR_BASE, 0);
2537         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2538         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2539
2540         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2541         vmcs_writel(GUEST_LDTR_BASE, 0);
2542         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2543         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2544
2545         vmcs_write32(GUEST_SYSENTER_CS, 0);
2546         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2547         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2548
2549         vmcs_writel(GUEST_RFLAGS, 0x02);
2550         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2551                 kvm_rip_write(vcpu, 0xfff0);
2552         else
2553                 kvm_rip_write(vcpu, 0);
2554         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2555
2556         vmcs_writel(GUEST_DR7, 0x400);
2557
2558         vmcs_writel(GUEST_GDTR_BASE, 0);
2559         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2560
2561         vmcs_writel(GUEST_IDTR_BASE, 0);
2562         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2563
2564         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2565         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2566         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2567
2568         /* Special registers */
2569         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2570
2571         setup_msrs(vmx);
2572
2573         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2574
2575         if (cpu_has_vmx_tpr_shadow()) {
2576                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2577                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2578                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2579                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2580                 vmcs_write32(TPR_THRESHOLD, 0);
2581         }
2582
2583         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2584                 vmcs_write64(APIC_ACCESS_ADDR,
2585                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2586
2587         if (vmx->vpid != 0)
2588                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2589
2590         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2591         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2592         vmx_set_cr4(&vmx->vcpu, 0);
2593         vmx_set_efer(&vmx->vcpu, 0);
2594         vmx_fpu_activate(&vmx->vcpu);
2595         update_exception_bitmap(&vmx->vcpu);
2596
2597         vpid_sync_vcpu_all(vmx);
2598
2599         ret = 0;
2600
2601         /* HACK: Don't enable emulation on guest boot/reset */
2602         vmx->emulation_required = 0;
2603
2604 out:
2605         srcu_read_unlock(&vcpu->kvm->srcu, idx);
2606         return ret;
2607 }
2608
2609 static void enable_irq_window(struct kvm_vcpu *vcpu)
2610 {
2611         u32 cpu_based_vm_exec_control;
2612
2613         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2614         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2615         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2616 }
2617
2618 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2619 {
2620         u32 cpu_based_vm_exec_control;
2621
2622         if (!cpu_has_virtual_nmis()) {
2623                 enable_irq_window(vcpu);
2624                 return;
2625         }
2626
2627         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2628         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2629         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2630 }
2631
2632 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2633 {
2634         struct vcpu_vmx *vmx = to_vmx(vcpu);
2635         uint32_t intr;
2636         int irq = vcpu->arch.interrupt.nr;
2637
2638         trace_kvm_inj_virq(irq);
2639
2640         ++vcpu->stat.irq_injections;
2641         if (vmx->rmode.vm86_active) {
2642                 vmx->rmode.irq.pending = true;
2643                 vmx->rmode.irq.vector = irq;
2644                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2645                 if (vcpu->arch.interrupt.soft)
2646                         vmx->rmode.irq.rip +=
2647                                 vmx->vcpu.arch.event_exit_inst_len;
2648                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2649                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2650                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2651                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2652                 return;
2653         }
2654         intr = irq | INTR_INFO_VALID_MASK;
2655         if (vcpu->arch.interrupt.soft) {
2656                 intr |= INTR_TYPE_SOFT_INTR;
2657                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2658                              vmx->vcpu.arch.event_exit_inst_len);
2659         } else
2660                 intr |= INTR_TYPE_EXT_INTR;
2661         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2662 }
2663
2664 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2665 {
2666         struct vcpu_vmx *vmx = to_vmx(vcpu);
2667
2668         if (!cpu_has_virtual_nmis()) {
2669                 /*
2670                  * Tracking the NMI-blocked state in software is built upon
2671                  * finding the next open IRQ window. This, in turn, depends on
2672                  * well-behaving guests: They have to keep IRQs disabled at
2673                  * least as long as the NMI handler runs. Otherwise we may
2674                  * cause NMI nesting, maybe breaking the guest. But as this is
2675                  * highly unlikely, we can live with the residual risk.
2676                  */
2677                 vmx->soft_vnmi_blocked = 1;
2678                 vmx->vnmi_blocked_time = 0;
2679         }
2680
2681         ++vcpu->stat.nmi_injections;
2682         if (vmx->rmode.vm86_active) {
2683                 vmx->rmode.irq.pending = true;
2684                 vmx->rmode.irq.vector = NMI_VECTOR;
2685                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2686                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2687                              NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2688                              INTR_INFO_VALID_MASK);
2689                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2690                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2691                 return;
2692         }
2693         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2694                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2695 }
2696
2697 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2698 {
2699         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2700                 return 0;
2701
2702         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2703                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2704                                 GUEST_INTR_STATE_NMI));
2705 }
2706
2707 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2708 {
2709         if (!cpu_has_virtual_nmis())
2710                 return to_vmx(vcpu)->soft_vnmi_blocked;
2711         else
2712                 return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2713                           GUEST_INTR_STATE_NMI);
2714 }
2715
2716 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2717 {
2718         struct vcpu_vmx *vmx = to_vmx(vcpu);
2719
2720         if (!cpu_has_virtual_nmis()) {
2721                 if (vmx->soft_vnmi_blocked != masked) {
2722                         vmx->soft_vnmi_blocked = masked;
2723                         vmx->vnmi_blocked_time = 0;
2724                 }
2725         } else {
2726                 if (masked)
2727                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2728                                       GUEST_INTR_STATE_NMI);
2729                 else
2730                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2731                                         GUEST_INTR_STATE_NMI);
2732         }
2733 }
2734
2735 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2736 {
2737         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2738                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2739                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2740 }
2741
2742 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2743 {
2744         int ret;
2745         struct kvm_userspace_memory_region tss_mem = {
2746                 .slot = TSS_PRIVATE_MEMSLOT,
2747                 .guest_phys_addr = addr,
2748                 .memory_size = PAGE_SIZE * 3,
2749                 .flags = 0,
2750         };
2751
2752         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2753         if (ret)
2754                 return ret;
2755         kvm->arch.tss_addr = addr;
2756         return 0;
2757 }
2758
2759 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2760                                   int vec, u32 err_code)
2761 {
2762         /*
2763          * Instruction with address size override prefix opcode 0x67
2764          * Cause the #SS fault with 0 error code in VM86 mode.
2765          */
2766         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2767                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2768                         return 1;
2769         /*
2770          * Forward all other exceptions that are valid in real mode.
2771          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2772          *        the required debugging infrastructure rework.
2773          */
2774         switch (vec) {
2775         case DB_VECTOR:
2776                 if (vcpu->guest_debug &
2777                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2778                         return 0;
2779                 kvm_queue_exception(vcpu, vec);
2780                 return 1;
2781         case BP_VECTOR:
2782                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2783                         return 0;
2784                 /* fall through */
2785         case DE_VECTOR:
2786         case OF_VECTOR:
2787         case BR_VECTOR:
2788         case UD_VECTOR:
2789         case DF_VECTOR:
2790         case SS_VECTOR:
2791         case GP_VECTOR:
2792         case MF_VECTOR:
2793                 kvm_queue_exception(vcpu, vec);
2794                 return 1;
2795         }
2796         return 0;
2797 }
2798
2799 /*
2800  * Trigger machine check on the host. We assume all the MSRs are already set up
2801  * by the CPU and that we still run on the same CPU as the MCE occurred on.
2802  * We pass a fake environment to the machine check handler because we want
2803  * the guest to be always treated like user space, no matter what context
2804  * it used internally.
2805  */
2806 static void kvm_machine_check(void)
2807 {
2808 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2809         struct pt_regs regs = {
2810                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2811                 .flags = X86_EFLAGS_IF,
2812         };
2813
2814         do_machine_check(&regs, 0);
2815 #endif
2816 }
2817
2818 static int handle_machine_check(struct kvm_vcpu *vcpu)
2819 {
2820         /* already handled by vcpu_run */
2821         return 1;
2822 }
2823
2824 static int handle_exception(struct kvm_vcpu *vcpu)
2825 {
2826         struct vcpu_vmx *vmx = to_vmx(vcpu);
2827         struct kvm_run *kvm_run = vcpu->run;
2828         u32 intr_info, ex_no, error_code;
2829         unsigned long cr2, rip, dr6;
2830         u32 vect_info;
2831         enum emulation_result er;
2832
2833         vect_info = vmx->idt_vectoring_info;
2834         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2835
2836         if (is_machine_check(intr_info))
2837                 return handle_machine_check(vcpu);
2838
2839         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2840             !is_page_fault(intr_info)) {
2841                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2842                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2843                 vcpu->run->internal.ndata = 2;
2844                 vcpu->run->internal.data[0] = vect_info;
2845                 vcpu->run->internal.data[1] = intr_info;
2846                 return 0;
2847         }
2848
2849         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2850                 return 1;  /* already handled by vmx_vcpu_run() */
2851
2852         if (is_no_device(intr_info)) {
2853                 vmx_fpu_activate(vcpu);
2854                 return 1;
2855         }
2856
2857         if (is_invalid_opcode(intr_info)) {
2858                 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
2859                 if (er != EMULATE_DONE)
2860                         kvm_queue_exception(vcpu, UD_VECTOR);
2861                 return 1;
2862         }
2863
2864         error_code = 0;
2865         rip = kvm_rip_read(vcpu);
2866         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2867                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2868         if (is_page_fault(intr_info)) {
2869                 /* EPT won't cause page fault directly */
2870                 if (enable_ept)
2871                         BUG();
2872                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2873                 trace_kvm_page_fault(cr2, error_code);
2874
2875                 if (kvm_event_needs_reinjection(vcpu))
2876                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
2877                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2878         }
2879
2880         if (vmx->rmode.vm86_active &&
2881             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2882                                                                 error_code)) {
2883                 if (vcpu->arch.halt_request) {
2884                         vcpu->arch.halt_request = 0;
2885                         return kvm_emulate_halt(vcpu);
2886                 }
2887                 return 1;
2888         }
2889
2890         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2891         switch (ex_no) {
2892         case DB_VECTOR:
2893                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2894                 if (!(vcpu->guest_debug &
2895                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2896                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2897                         kvm_queue_exception(vcpu, DB_VECTOR);
2898                         return 1;
2899                 }
2900                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2901                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2902                 /* fall through */
2903         case BP_VECTOR:
2904                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2905                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2906                 kvm_run->debug.arch.exception = ex_no;
2907                 break;
2908         default:
2909                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2910                 kvm_run->ex.exception = ex_no;
2911                 kvm_run->ex.error_code = error_code;
2912                 break;
2913         }
2914         return 0;
2915 }
2916
2917 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
2918 {
2919         ++vcpu->stat.irq_exits;
2920         return 1;
2921 }
2922
2923 static int handle_triple_fault(struct kvm_vcpu *vcpu)
2924 {
2925         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
2926         return 0;
2927 }
2928
2929 static int handle_io(struct kvm_vcpu *vcpu)
2930 {
2931         unsigned long exit_qualification;
2932         int size, in, string;
2933         unsigned port;
2934
2935         ++vcpu->stat.io_exits;
2936         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2937         string = (exit_qualification & 16) != 0;
2938
2939         if (string) {
2940                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO)
2941                         return 0;
2942                 return 1;
2943         }
2944
2945         size = (exit_qualification & 7) + 1;
2946         in = (exit_qualification & 8) != 0;
2947         port = exit_qualification >> 16;
2948
2949         skip_emulated_instruction(vcpu);
2950         return kvm_emulate_pio(vcpu, in, size, port);
2951 }
2952
2953 static void
2954 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2955 {
2956         /*
2957          * Patch in the VMCALL instruction:
2958          */
2959         hypercall[0] = 0x0f;
2960         hypercall[1] = 0x01;
2961         hypercall[2] = 0xc1;
2962 }
2963
2964 static int handle_cr(struct kvm_vcpu *vcpu)
2965 {
2966         unsigned long exit_qualification, val;
2967         int cr;
2968         int reg;
2969
2970         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2971         cr = exit_qualification & 15;
2972         reg = (exit_qualification >> 8) & 15;
2973         switch ((exit_qualification >> 4) & 3) {
2974         case 0: /* mov to cr */
2975                 val = kvm_register_read(vcpu, reg);
2976                 trace_kvm_cr_write(cr, val);
2977                 switch (cr) {
2978                 case 0:
2979                         kvm_set_cr0(vcpu, val);
2980                         skip_emulated_instruction(vcpu);
2981                         return 1;
2982                 case 3:
2983                         kvm_set_cr3(vcpu, val);
2984                         skip_emulated_instruction(vcpu);
2985                         return 1;
2986                 case 4:
2987                         kvm_set_cr4(vcpu, val);
2988                         skip_emulated_instruction(vcpu);
2989                         return 1;
2990                 case 8: {
2991                                 u8 cr8_prev = kvm_get_cr8(vcpu);
2992                                 u8 cr8 = kvm_register_read(vcpu, reg);
2993                                 kvm_set_cr8(vcpu, cr8);
2994                                 skip_emulated_instruction(vcpu);
2995                                 if (irqchip_in_kernel(vcpu->kvm))
2996                                         return 1;
2997                                 if (cr8_prev <= cr8)
2998                                         return 1;
2999                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3000                                 return 0;
3001                         }
3002                 };
3003                 break;
3004         case 2: /* clts */
3005                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3006                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3007                 skip_emulated_instruction(vcpu);
3008                 vmx_fpu_activate(vcpu);
3009                 return 1;
3010         case 1: /*mov from cr*/
3011                 switch (cr) {
3012                 case 3:
3013                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
3014                         trace_kvm_cr_read(cr, vcpu->arch.cr3);
3015                         skip_emulated_instruction(vcpu);
3016                         return 1;
3017                 case 8:
3018                         val = kvm_get_cr8(vcpu);
3019                         kvm_register_write(vcpu, reg, val);
3020                         trace_kvm_cr_read(cr, val);
3021                         skip_emulated_instruction(vcpu);
3022                         return 1;
3023                 }
3024                 break;
3025         case 3: /* lmsw */
3026                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3027                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3028                 kvm_lmsw(vcpu, val);
3029
3030                 skip_emulated_instruction(vcpu);
3031                 return 1;
3032         default:
3033                 break;
3034         }
3035         vcpu->run->exit_reason = 0;
3036         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3037                (int)(exit_qualification >> 4) & 3, cr);
3038         return 0;
3039 }
3040
3041 static int check_dr_alias(struct kvm_vcpu *vcpu)
3042 {
3043         if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
3044                 kvm_queue_exception(vcpu, UD_VECTOR);
3045                 return -1;
3046         }
3047         return 0;
3048 }
3049
3050 static int handle_dr(struct kvm_vcpu *vcpu)
3051 {
3052         unsigned long exit_qualification;
3053         unsigned long val;
3054         int dr, reg;
3055
3056         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3057         if (!kvm_require_cpl(vcpu, 0))
3058                 return 1;
3059         dr = vmcs_readl(GUEST_DR7);
3060         if (dr & DR7_GD) {
3061                 /*
3062                  * As the vm-exit takes precedence over the debug trap, we
3063                  * need to emulate the latter, either for the host or the
3064                  * guest debugging itself.
3065                  */
3066                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3067                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3068                         vcpu->run->debug.arch.dr7 = dr;
3069                         vcpu->run->debug.arch.pc =
3070                                 vmcs_readl(GUEST_CS_BASE) +
3071                                 vmcs_readl(GUEST_RIP);
3072                         vcpu->run->debug.arch.exception = DB_VECTOR;
3073                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3074                         return 0;
3075                 } else {
3076                         vcpu->arch.dr7 &= ~DR7_GD;
3077                         vcpu->arch.dr6 |= DR6_BD;
3078                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3079                         kvm_queue_exception(vcpu, DB_VECTOR);
3080                         return 1;
3081                 }
3082         }
3083
3084         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3085         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3086         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3087         if (exit_qualification & TYPE_MOV_FROM_DR) {
3088                 switch (dr) {
3089                 case 0 ... 3:
3090                         val = vcpu->arch.db[dr];
3091                         break;
3092                 case 4:
3093                         if (check_dr_alias(vcpu) < 0)
3094                                 return 1;
3095                         /* fall through */
3096                 case 6:
3097                         val = vcpu->arch.dr6;
3098                         break;
3099                 case 5:
3100                         if (check_dr_alias(vcpu) < 0)
3101                                 return 1;
3102                         /* fall through */
3103                 default: /* 7 */
3104                         val = vcpu->arch.dr7;
3105                         break;
3106                 }
3107                 kvm_register_write(vcpu, reg, val);
3108         } else {
3109                 val = vcpu->arch.regs[reg];
3110                 switch (dr) {
3111                 case 0 ... 3:
3112                         vcpu->arch.db[dr] = val;
3113                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
3114                                 vcpu->arch.eff_db[dr] = val;
3115                         break;
3116                 case 4:
3117                         if (check_dr_alias(vcpu) < 0)
3118                                 return 1;
3119                         /* fall through */
3120                 case 6:
3121                         if (val & 0xffffffff00000000ULL) {
3122                                 kvm_inject_gp(vcpu, 0);
3123                                 return 1;
3124                         }
3125                         vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
3126                         break;
3127                 case 5:
3128                         if (check_dr_alias(vcpu) < 0)
3129                                 return 1;
3130                         /* fall through */
3131                 default: /* 7 */
3132                         if (val & 0xffffffff00000000ULL) {
3133                                 kvm_inject_gp(vcpu, 0);
3134                                 return 1;
3135                         }
3136                         vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3137                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3138                                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3139                                 vcpu->arch.switch_db_regs =
3140                                         (val & DR7_BP_EN_MASK);
3141                         }
3142                         break;
3143                 }
3144         }
3145         skip_emulated_instruction(vcpu);
3146         return 1;
3147 }
3148
3149 static int handle_cpuid(struct kvm_vcpu *vcpu)
3150 {
3151         kvm_emulate_cpuid(vcpu);
3152         return 1;
3153 }
3154
3155 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3156 {
3157         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3158         u64 data;
3159
3160         if (vmx_get_msr(vcpu, ecx, &data)) {
3161                 trace_kvm_msr_read_ex(ecx);
3162                 kvm_inject_gp(vcpu, 0);
3163                 return 1;
3164         }
3165
3166         trace_kvm_msr_read(ecx, data);
3167
3168         /* FIXME: handling of bits 32:63 of rax, rdx */
3169         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3170         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3171         skip_emulated_instruction(vcpu);
3172         return 1;
3173 }
3174
3175 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3176 {
3177         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3178         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3179                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3180
3181         if (vmx_set_msr(vcpu, ecx, data) != 0) {
3182                 trace_kvm_msr_write_ex(ecx, data);
3183                 kvm_inject_gp(vcpu, 0);
3184                 return 1;
3185         }
3186
3187         trace_kvm_msr_write(ecx, data);
3188         skip_emulated_instruction(vcpu);
3189         return 1;
3190 }
3191
3192 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3193 {
3194         return 1;
3195 }
3196
3197 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3198 {
3199         u32 cpu_based_vm_exec_control;
3200
3201         /* clear pending irq */
3202         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3203         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3204         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3205
3206         ++vcpu->stat.irq_window_exits;
3207
3208         /*
3209          * If the user space waits to inject interrupts, exit as soon as
3210          * possible
3211          */
3212         if (!irqchip_in_kernel(vcpu->kvm) &&
3213             vcpu->run->request_interrupt_window &&
3214             !kvm_cpu_has_interrupt(vcpu)) {
3215                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3216                 return 0;
3217         }
3218         return 1;
3219 }
3220
3221 static int handle_halt(struct kvm_vcpu *vcpu)
3222 {
3223         skip_emulated_instruction(vcpu);
3224         return kvm_emulate_halt(vcpu);
3225 }
3226
3227 static int handle_vmcall(struct kvm_vcpu *vcpu)
3228 {
3229         skip_emulated_instruction(vcpu);
3230         kvm_emulate_hypercall(vcpu);
3231         return 1;
3232 }
3233
3234 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3235 {
3236         kvm_queue_exception(vcpu, UD_VECTOR);
3237         return 1;
3238 }
3239
3240 static int handle_invlpg(struct kvm_vcpu *vcpu)
3241 {
3242         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3243
3244         kvm_mmu_invlpg(vcpu, exit_qualification);
3245         skip_emulated_instruction(vcpu);
3246         return 1;
3247 }
3248
3249 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3250 {
3251         skip_emulated_instruction(vcpu);
3252         /* TODO: Add support for VT-d/pass-through device */
3253         return 1;
3254 }
3255
3256 static int handle_apic_access(struct kvm_vcpu *vcpu)
3257 {
3258         unsigned long exit_qualification;
3259         enum emulation_result er;
3260         unsigned long offset;
3261
3262         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3263         offset = exit_qualification & 0xffful;
3264
3265         er = emulate_instruction(vcpu, 0, 0, 0);
3266
3267         if (er !=  EMULATE_DONE) {
3268                 printk(KERN_ERR
3269                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3270                        offset);
3271                 return -ENOEXEC;
3272         }
3273         return 1;
3274 }
3275
3276 static int handle_task_switch(struct kvm_vcpu *vcpu)
3277 {
3278         struct vcpu_vmx *vmx = to_vmx(vcpu);
3279         unsigned long exit_qualification;
3280         u16 tss_selector;
3281         int reason, type, idt_v;
3282
3283         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3284         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3285
3286         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3287
3288         reason = (u32)exit_qualification >> 30;
3289         if (reason == TASK_SWITCH_GATE && idt_v) {
3290                 switch (type) {
3291                 case INTR_TYPE_NMI_INTR:
3292                         vcpu->arch.nmi_injected = false;
3293                         if (cpu_has_virtual_nmis())
3294                                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3295                                               GUEST_INTR_STATE_NMI);
3296                         break;
3297                 case INTR_TYPE_EXT_INTR:
3298                 case INTR_TYPE_SOFT_INTR:
3299                         kvm_clear_interrupt_queue(vcpu);
3300                         break;
3301                 case INTR_TYPE_HARD_EXCEPTION:
3302                 case INTR_TYPE_SOFT_EXCEPTION:
3303                         kvm_clear_exception_queue(vcpu);
3304                         break;
3305                 default:
3306                         break;
3307                 }
3308         }
3309         tss_selector = exit_qualification;
3310
3311         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3312                        type != INTR_TYPE_EXT_INTR &&
3313                        type != INTR_TYPE_NMI_INTR))
3314                 skip_emulated_instruction(vcpu);
3315
3316         if (!kvm_task_switch(vcpu, tss_selector, reason))
3317                 return 0;
3318
3319         /* clear all local breakpoint enable flags */
3320         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3321
3322         /*
3323          * TODO: What about debug traps on tss switch?
3324          *       Are we supposed to inject them and update dr6?
3325          */
3326
3327         return 1;
3328 }
3329
3330 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3331 {
3332         unsigned long exit_qualification;
3333         gpa_t gpa;
3334         int gla_validity;
3335
3336         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3337
3338         if (exit_qualification & (1 << 6)) {
3339                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3340                 return -EINVAL;
3341         }
3342
3343         gla_validity = (exit_qualification >> 7) & 0x3;
3344         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3345                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3346                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3347                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3348                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3349                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3350                         (long unsigned int)exit_qualification);
3351                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3352                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3353                 return 0;
3354         }
3355
3356         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3357         trace_kvm_page_fault(gpa, exit_qualification);
3358         return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3359 }
3360
3361 static u64 ept_rsvd_mask(u64 spte, int level)
3362 {
3363         int i;
3364         u64 mask = 0;
3365
3366         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3367                 mask |= (1ULL << i);
3368
3369         if (level > 2)
3370                 /* bits 7:3 reserved */
3371                 mask |= 0xf8;
3372         else if (level == 2) {
3373                 if (spte & (1ULL << 7))
3374                         /* 2MB ref, bits 20:12 reserved */
3375                         mask |= 0x1ff000;
3376                 else
3377                         /* bits 6:3 reserved */
3378                         mask |= 0x78;
3379         }
3380
3381         return mask;
3382 }
3383
3384 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3385                                        int level)
3386 {
3387         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3388
3389         /* 010b (write-only) */
3390         WARN_ON((spte & 0x7) == 0x2);
3391
3392         /* 110b (write/execute) */
3393         WARN_ON((spte & 0x7) == 0x6);
3394
3395         /* 100b (execute-only) and value not supported by logical processor */
3396         if (!cpu_has_vmx_ept_execute_only())
3397                 WARN_ON((spte & 0x7) == 0x4);
3398
3399         /* not 000b */
3400         if ((spte & 0x7)) {
3401                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3402
3403                 if (rsvd_bits != 0) {
3404                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3405                                          __func__, rsvd_bits);
3406                         WARN_ON(1);
3407                 }
3408
3409                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3410                         u64 ept_mem_type = (spte & 0x38) >> 3;
3411
3412                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
3413                             ept_mem_type == 7) {
3414                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3415                                                 __func__, ept_mem_type);
3416                                 WARN_ON(1);
3417                         }
3418                 }
3419         }
3420 }
3421
3422 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3423 {
3424         u64 sptes[4];
3425         int nr_sptes, i;
3426         gpa_t gpa;
3427
3428         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3429
3430         printk(KERN_ERR "EPT: Misconfiguration.\n");
3431         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3432
3433         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3434
3435         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3436                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3437
3438         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3439         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3440
3441         return 0;
3442 }
3443
3444 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3445 {
3446         u32 cpu_based_vm_exec_control;
3447
3448         /* clear pending NMI */
3449         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3450         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3451         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3452         ++vcpu->stat.nmi_window_exits;
3453
3454         return 1;
3455 }
3456
3457 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3458 {
3459         struct vcpu_vmx *vmx = to_vmx(vcpu);
3460         enum emulation_result err = EMULATE_DONE;
3461         int ret = 1;
3462
3463         while (!guest_state_valid(vcpu)) {
3464                 err = emulate_instruction(vcpu, 0, 0, 0);
3465
3466                 if (err == EMULATE_DO_MMIO) {
3467                         ret = 0;
3468                         goto out;
3469                 }
3470
3471                 if (err != EMULATE_DONE) {
3472                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3473                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3474                         vcpu->run->internal.ndata = 0;
3475                         ret = 0;
3476                         goto out;
3477                 }
3478
3479                 if (signal_pending(current))
3480                         goto out;
3481                 if (need_resched())
3482                         schedule();
3483         }
3484
3485         vmx->emulation_required = 0;
3486 out:
3487         return ret;
3488 }
3489
3490 /*
3491  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3492  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3493  */
3494 static int handle_pause(struct kvm_vcpu *vcpu)
3495 {
3496         skip_emulated_instruction(vcpu);
3497         kvm_vcpu_on_spin(vcpu);
3498
3499         return 1;
3500 }
3501
3502 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3503 {
3504         kvm_queue_exception(vcpu, UD_VECTOR);
3505         return 1;
3506 }
3507
3508 /*
3509  * The exit handlers return 1 if the exit was handled fully and guest execution
3510  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3511  * to be done to userspace and return 0.
3512  */
3513 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3514         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3515         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3516         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3517         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3518         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3519         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3520         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3521         [EXIT_REASON_CPUID]                   = handle_cpuid,
3522         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3523         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3524         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3525         [EXIT_REASON_HLT]                     = handle_halt,
3526         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3527         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3528         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
3529         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
3530         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
3531         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
3532         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
3533         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
3534         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
3535         [EXIT_REASON_VMOFF]                   = handle_vmx_insn,
3536         [EXIT_REASON_VMON]                    = handle_vmx_insn,
3537         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3538         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3539         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3540         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3541         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
3542         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3543         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
3544         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
3545         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
3546         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
3547 };
3548
3549 static const int kvm_vmx_max_exit_handlers =
3550         ARRAY_SIZE(kvm_vmx_exit_handlers);
3551
3552 /*
3553  * The guest has exited.  See if we can fix it or if we need userspace
3554  * assistance.
3555  */
3556 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3557 {
3558         struct vcpu_vmx *vmx = to_vmx(vcpu);
3559         u32 exit_reason = vmx->exit_reason;
3560         u32 vectoring_info = vmx->idt_vectoring_info;
3561
3562         trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
3563
3564         /* If guest state is invalid, start emulating */
3565         if (vmx->emulation_required && emulate_invalid_guest_state)
3566                 return handle_invalid_guest_state(vcpu);
3567
3568         /* Access CR3 don't cause VMExit in paging mode, so we need
3569          * to sync with guest real CR3. */
3570         if (enable_ept && is_paging(vcpu))
3571                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3572
3573         if (unlikely(vmx->fail)) {
3574                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3575                 vcpu->run->fail_entry.hardware_entry_failure_reason
3576                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3577                 return 0;
3578         }
3579
3580         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3581                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3582                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3583                         exit_reason != EXIT_REASON_TASK_SWITCH))
3584                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3585                        "(0x%x) and exit reason is 0x%x\n",
3586                        __func__, vectoring_info, exit_reason);
3587
3588         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3589                 if (vmx_interrupt_allowed(vcpu)) {
3590                         vmx->soft_vnmi_blocked = 0;
3591                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3592                            vcpu->arch.nmi_pending) {
3593                         /*
3594                          * This CPU don't support us in finding the end of an
3595                          * NMI-blocked window if the guest runs with IRQs
3596                          * disabled. So we pull the trigger after 1 s of
3597                          * futile waiting, but inform the user about this.
3598                          */
3599                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3600                                "state on VCPU %d after 1 s timeout\n",
3601                                __func__, vcpu->vcpu_id);
3602                         vmx->soft_vnmi_blocked = 0;
3603                 }
3604         }
3605
3606         if (exit_reason < kvm_vmx_max_exit_handlers
3607             && kvm_vmx_exit_handlers[exit_reason])
3608                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3609         else {
3610                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3611                 vcpu->run->hw.hardware_exit_reason = exit_reason;
3612         }
3613         return 0;
3614 }
3615
3616 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3617 {
3618         if (irr == -1 || tpr < irr) {
3619                 vmcs_write32(TPR_THRESHOLD, 0);
3620                 return;
3621         }
3622
3623         vmcs_write32(TPR_THRESHOLD, irr);
3624 }
3625
3626 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3627 {
3628         u32 exit_intr_info;
3629         u32 idt_vectoring_info = vmx->idt_vectoring_info;
3630         bool unblock_nmi;
3631         u8 vector;
3632         int type;
3633         bool idtv_info_valid;
3634
3635         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3636
3637         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3638
3639         /* Handle machine checks before interrupts are enabled */
3640         if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3641             || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3642                 && is_machine_check(exit_intr_info)))
3643                 kvm_machine_check();
3644
3645         /* We need to handle NMIs before interrupts are enabled */
3646         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3647             (exit_intr_info & INTR_INFO_VALID_MASK))
3648                 asm("int $2");
3649
3650         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3651
3652         if (cpu_has_virtual_nmis()) {
3653                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3654                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3655                 /*
3656                  * SDM 3: 27.7.1.2 (September 2008)
3657                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3658                  * a guest IRET fault.
3659                  * SDM 3: 23.2.2 (September 2008)
3660                  * Bit 12 is undefined in any of the following cases:
3661                  *  If the VM exit sets the valid bit in the IDT-vectoring
3662                  *   information field.
3663                  *  If the VM exit is due to a double fault.
3664                  */
3665                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3666                     vector != DF_VECTOR && !idtv_info_valid)
3667                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3668                                       GUEST_INTR_STATE_NMI);
3669         } else if (unlikely(vmx->soft_vnmi_blocked))
3670                 vmx->vnmi_blocked_time +=
3671                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3672
3673         vmx->vcpu.arch.nmi_injected = false;
3674         kvm_clear_exception_queue(&vmx->vcpu);
3675         kvm_clear_interrupt_queue(&vmx->vcpu);
3676
3677         if (!idtv_info_valid)
3678                 return;
3679
3680         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3681         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3682
3683         switch (type) {
3684         case INTR_TYPE_NMI_INTR:
3685                 vmx->vcpu.arch.nmi_injected = true;
3686                 /*
3687                  * SDM 3: 27.7.1.2 (September 2008)
3688                  * Clear bit "block by NMI" before VM entry if a NMI
3689                  * delivery faulted.
3690                  */
3691                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3692                                 GUEST_INTR_STATE_NMI);
3693                 break;
3694         case INTR_TYPE_SOFT_EXCEPTION:
3695                 vmx->vcpu.arch.event_exit_inst_len =
3696                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3697                 /* fall through */
3698         case INTR_TYPE_HARD_EXCEPTION:
3699                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3700                         u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3701                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
3702                 } else
3703                         kvm_queue_exception(&vmx->vcpu, vector);
3704                 break;
3705         case INTR_TYPE_SOFT_INTR:
3706                 vmx->vcpu.arch.event_exit_inst_len =
3707                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3708                 /* fall through */
3709         case INTR_TYPE_EXT_INTR:
3710                 kvm_queue_interrupt(&vmx->vcpu, vector,
3711                         type == INTR_TYPE_SOFT_INTR);
3712                 break;
3713         default:
3714                 break;
3715         }
3716 }
3717
3718 /*
3719  * Failure to inject an interrupt should give us the information
3720  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3721  * when fetching the interrupt redirection bitmap in the real-mode
3722  * tss, this doesn't happen.  So we do it ourselves.
3723  */
3724 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3725 {
3726         vmx->rmode.irq.pending = 0;
3727         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3728                 return;
3729         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3730         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3731                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3732                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3733                 return;
3734         }
3735         vmx->idt_vectoring_info =
3736                 VECTORING_INFO_VALID_MASK
3737                 | INTR_TYPE_EXT_INTR
3738                 | vmx->rmode.irq.vector;
3739 }
3740
3741 #ifdef CONFIG_X86_64
3742 #define R "r"
3743 #define Q "q"
3744 #else
3745 #define R "e"
3746 #define Q "l"
3747 #endif
3748
3749 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3750 {
3751         struct vcpu_vmx *vmx = to_vmx(vcpu);
3752
3753         /* Record the guest's net vcpu time for enforced NMI injections. */
3754         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3755                 vmx->entry_time = ktime_get();
3756
3757         /* Don't enter VMX if guest state is invalid, let the exit handler
3758            start emulation until we arrive back to a valid state */
3759         if (vmx->emulation_required && emulate_invalid_guest_state)
3760                 return;
3761
3762         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3763                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3764         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3765                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3766
3767         /* When single-stepping over STI and MOV SS, we must clear the
3768          * corresponding interruptibility bits in the guest state. Otherwise
3769          * vmentry fails as it then expects bit 14 (BS) in pending debug
3770          * exceptions being set, but that's not correct for the guest debugging
3771          * case. */
3772         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3773                 vmx_set_interrupt_shadow(vcpu, 0);
3774
3775         /*
3776          * Loading guest fpu may have cleared host cr0.ts
3777          */
3778         vmcs_writel(HOST_CR0, read_cr0());
3779
3780         asm(
3781                 /* Store host registers */
3782                 "push %%"R"dx; push %%"R"bp;"
3783                 "push %%"R"cx \n\t"
3784                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3785                 "je 1f \n\t"
3786                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3787                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3788                 "1: \n\t"
3789                 /* Reload cr2 if changed */
3790                 "mov %c[cr2](%0), %%"R"ax \n\t"
3791                 "mov %%cr2, %%"R"dx \n\t"
3792                 "cmp %%"R"ax, %%"R"dx \n\t"
3793                 "je 2f \n\t"
3794                 "mov %%"R"ax, %%cr2 \n\t"
3795                 "2: \n\t"
3796                 /* Check if vmlaunch of vmresume is needed */
3797                 "cmpl $0, %c[launched](%0) \n\t"
3798                 /* Load guest registers.  Don't clobber flags. */
3799                 "mov %c[rax](%0), %%"R"ax \n\t"
3800                 "mov %c[rbx](%0), %%"R"bx \n\t"
3801                 "mov %c[rdx](%0), %%"R"dx \n\t"
3802                 "mov %c[rsi](%0), %%"R"si \n\t"
3803                 "mov %c[rdi](%0), %%"R"di \n\t"
3804                 "mov %c[rbp](%0), %%"R"bp \n\t"
3805 #ifdef CONFIG_X86_64
3806                 "mov %c[r8](%0),  %%r8  \n\t"
3807                 "mov %c[r9](%0),  %%r9  \n\t"
3808                 "mov %c[r10](%0), %%r10 \n\t"
3809                 "mov %c[r11](%0), %%r11 \n\t"
3810                 "mov %c[r12](%0), %%r12 \n\t"
3811                 "mov %c[r13](%0), %%r13 \n\t"
3812                 "mov %c[r14](%0), %%r14 \n\t"
3813                 "mov %c[r15](%0), %%r15 \n\t"
3814 #endif
3815                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3816
3817                 /* Enter guest mode */
3818                 "jne .Llaunched \n\t"
3819                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3820                 "jmp .Lkvm_vmx_return \n\t"
3821                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3822                 ".Lkvm_vmx_return: "
3823                 /* Save guest registers, load host registers, keep flags */
3824                 "xchg %0,     (%%"R"sp) \n\t"
3825                 "mov %%"R"ax, %c[rax](%0) \n\t"
3826                 "mov %%"R"bx, %c[rbx](%0) \n\t"
3827                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3828                 "mov %%"R"dx, %c[rdx](%0) \n\t"
3829                 "mov %%"R"si, %c[rsi](%0) \n\t"
3830                 "mov %%"R"di, %c[rdi](%0) \n\t"
3831                 "mov %%"R"bp, %c[rbp](%0) \n\t"
3832 #ifdef CONFIG_X86_64
3833                 "mov %%r8,  %c[r8](%0) \n\t"
3834                 "mov %%r9,  %c[r9](%0) \n\t"
3835                 "mov %%r10, %c[r10](%0) \n\t"
3836                 "mov %%r11, %c[r11](%0) \n\t"
3837                 "mov %%r12, %c[r12](%0) \n\t"
3838                 "mov %%r13, %c[r13](%0) \n\t"
3839                 "mov %%r14, %c[r14](%0) \n\t"
3840                 "mov %%r15, %c[r15](%0) \n\t"
3841 #endif
3842                 "mov %%cr2, %%"R"ax   \n\t"
3843                 "mov %%"R"ax, %c[cr2](%0) \n\t"
3844
3845                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
3846                 "setbe %c[fail](%0) \n\t"
3847               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3848                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3849                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3850                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3851                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3852                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3853                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3854                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3855                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3856                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3857                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3858 #ifdef CONFIG_X86_64
3859                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3860                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3861                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3862                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3863                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3864                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3865                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3866                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3867 #endif
3868                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3869               : "cc", "memory"
3870                 , R"bx", R"di", R"si"
3871 #ifdef CONFIG_X86_64
3872                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3873 #endif
3874               );
3875
3876         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3877                                   | (1 << VCPU_EXREG_PDPTR));
3878         vcpu->arch.regs_dirty = 0;
3879
3880         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3881         if (vmx->rmode.irq.pending)
3882                 fixup_rmode_irq(vmx);
3883
3884         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3885         vmx->launched = 1;
3886
3887         vmx_complete_interrupts(vmx);
3888 }
3889
3890 #undef R
3891 #undef Q
3892
3893 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3894 {
3895         struct vcpu_vmx *vmx = to_vmx(vcpu);
3896
3897         if (vmx->vmcs) {
3898                 vcpu_clear(vmx);
3899                 free_vmcs(vmx->vmcs);
3900                 vmx->vmcs = NULL;
3901         }
3902 }
3903
3904 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3905 {
3906         struct vcpu_vmx *vmx = to_vmx(vcpu);
3907
3908         spin_lock(&vmx_vpid_lock);
3909         if (vmx->vpid != 0)
3910                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3911         spin_unlock(&vmx_vpid_lock);
3912         vmx_free_vmcs(vcpu);
3913         kfree(vmx->guest_msrs);
3914         kvm_vcpu_uninit(vcpu);
3915         kmem_cache_free(kvm_vcpu_cache, vmx);
3916 }
3917
3918 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3919 {
3920         int err;
3921         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3922         int cpu;
3923
3924         if (!vmx)
3925                 return ERR_PTR(-ENOMEM);
3926
3927         allocate_vpid(vmx);
3928
3929         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3930         if (err)
3931                 goto free_vcpu;
3932
3933         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3934         if (!vmx->guest_msrs) {
3935                 err = -ENOMEM;
3936                 goto uninit_vcpu;
3937         }
3938
3939         vmx->vmcs = alloc_vmcs();
3940         if (!vmx->vmcs)
3941                 goto free_msrs;
3942
3943         vmcs_clear(vmx->vmcs);
3944
3945         cpu = get_cpu();
3946         vmx_vcpu_load(&vmx->vcpu, cpu);
3947         err = vmx_vcpu_setup(vmx);
3948         vmx_vcpu_put(&vmx->vcpu);
3949         put_cpu();
3950         if (err)
3951                 goto free_vmcs;
3952         if (vm_need_virtualize_apic_accesses(kvm))
3953                 if (alloc_apic_access_page(kvm) != 0)
3954                         goto free_vmcs;
3955
3956         if (enable_ept) {
3957                 if (!kvm->arch.ept_identity_map_addr)
3958                         kvm->arch.ept_identity_map_addr =
3959                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3960                 if (alloc_identity_pagetable(kvm) != 0)
3961                         goto free_vmcs;
3962         }
3963
3964         return &vmx->vcpu;
3965
3966 free_vmcs:
3967         free_vmcs(vmx->vmcs);
3968 free_msrs:
3969         kfree(vmx->guest_msrs);
3970 uninit_vcpu:
3971         kvm_vcpu_uninit(&vmx->vcpu);
3972 free_vcpu:
3973         kmem_cache_free(kvm_vcpu_cache, vmx);
3974         return ERR_PTR(err);
3975 }
3976
3977 static void __init vmx_check_processor_compat(void *rtn)
3978 {
3979         struct vmcs_config vmcs_conf;
3980
3981         *(int *)rtn = 0;
3982         if (setup_vmcs_config(&vmcs_conf) < 0)
3983                 *(int *)rtn = -EIO;
3984         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3985                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3986                                 smp_processor_id());
3987                 *(int *)rtn = -EIO;
3988         }
3989 }
3990
3991 static int get_ept_level(void)
3992 {
3993         return VMX_EPT_DEFAULT_GAW + 1;
3994 }
3995
3996 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3997 {
3998         u64 ret;
3999
4000         /* For VT-d and EPT combination
4001          * 1. MMIO: always map as UC
4002          * 2. EPT with VT-d:
4003          *   a. VT-d without snooping control feature: can't guarantee the
4004          *      result, try to trust guest.
4005          *   b. VT-d with snooping control feature: snooping control feature of
4006          *      VT-d engine can guarantee the cache correctness. Just set it
4007          *      to WB to keep consistent with host. So the same as item 3.
4008          * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
4009          *    consistent with host MTRR
4010          */
4011         if (is_mmio)
4012                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4013         else if (vcpu->kvm->arch.iommu_domain &&
4014                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4015                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4016                       VMX_EPT_MT_EPTE_SHIFT;
4017         else
4018                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4019                         | VMX_EPT_IGMT_BIT;
4020
4021         return ret;
4022 }
4023
4024 #define _ER(x) { EXIT_REASON_##x, #x }
4025
4026 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4027         _ER(EXCEPTION_NMI),
4028         _ER(EXTERNAL_INTERRUPT),
4029         _ER(TRIPLE_FAULT),
4030         _ER(PENDING_INTERRUPT),
4031         _ER(NMI_WINDOW),
4032         _ER(TASK_SWITCH),
4033         _ER(CPUID),
4034         _ER(HLT),
4035         _ER(INVLPG),
4036         _ER(RDPMC),
4037         _ER(RDTSC),
4038         _ER(VMCALL),
4039         _ER(VMCLEAR),
4040         _ER(VMLAUNCH),
4041         _ER(VMPTRLD),
4042         _ER(VMPTRST),
4043         _ER(VMREAD),
4044         _ER(VMRESUME),
4045         _ER(VMWRITE),
4046         _ER(VMOFF),
4047         _ER(VMON),
4048         _ER(CR_ACCESS),
4049         _ER(DR_ACCESS),
4050         _ER(IO_INSTRUCTION),
4051         _ER(MSR_READ),
4052         _ER(MSR_WRITE),
4053         _ER(MWAIT_INSTRUCTION),
4054         _ER(MONITOR_INSTRUCTION),
4055         _ER(PAUSE_INSTRUCTION),
4056         _ER(MCE_DURING_VMENTRY),
4057         _ER(TPR_BELOW_THRESHOLD),
4058         _ER(APIC_ACCESS),
4059         _ER(EPT_VIOLATION),
4060         _ER(EPT_MISCONFIG),
4061         _ER(WBINVD),
4062         { -1, NULL }
4063 };
4064
4065 #undef _ER
4066
4067 static int vmx_get_lpage_level(void)
4068 {
4069         if (enable_ept && !cpu_has_vmx_ept_1g_page())
4070                 return PT_DIRECTORY_LEVEL;
4071         else
4072                 /* For shadow and EPT supported 1GB page */
4073                 return PT_PDPE_LEVEL;
4074 }
4075
4076 static inline u32 bit(int bitno)
4077 {
4078         return 1 << (bitno & 31);
4079 }
4080
4081 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4082 {
4083         struct kvm_cpuid_entry2 *best;
4084         struct vcpu_vmx *vmx = to_vmx(vcpu);
4085         u32 exec_control;
4086
4087         vmx->rdtscp_enabled = false;
4088         if (vmx_rdtscp_supported()) {
4089                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4090                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4091                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4092                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4093                                 vmx->rdtscp_enabled = true;
4094                         else {
4095                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4096                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4097                                                 exec_control);
4098                         }
4099                 }
4100         }
4101 }
4102
4103 static struct kvm_x86_ops vmx_x86_ops = {
4104         .cpu_has_kvm_support = cpu_has_kvm_support,
4105         .disabled_by_bios = vmx_disabled_by_bios,
4106         .hardware_setup = hardware_setup,
4107         .hardware_unsetup = hardware_unsetup,
4108         .check_processor_compatibility = vmx_check_processor_compat,
4109         .hardware_enable = hardware_enable,
4110         .hardware_disable = hardware_disable,
4111         .cpu_has_accelerated_tpr = report_flexpriority,
4112
4113         .vcpu_create = vmx_create_vcpu,
4114         .vcpu_free = vmx_free_vcpu,
4115         .vcpu_reset = vmx_vcpu_reset,
4116
4117         .prepare_guest_switch = vmx_save_host_state,
4118         .vcpu_load = vmx_vcpu_load,
4119         .vcpu_put = vmx_vcpu_put,
4120
4121         .set_guest_debug = set_guest_debug,
4122         .get_msr = vmx_get_msr,
4123         .set_msr = vmx_set_msr,
4124         .get_segment_base = vmx_get_segment_base,
4125         .get_segment = vmx_get_segment,
4126         .set_segment = vmx_set_segment,
4127         .get_cpl = vmx_get_cpl,
4128         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4129         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4130         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4131         .set_cr0 = vmx_set_cr0,
4132         .set_cr3 = vmx_set_cr3,
4133         .set_cr4 = vmx_set_cr4,
4134         .set_efer = vmx_set_efer,
4135         .get_idt = vmx_get_idt,
4136         .set_idt = vmx_set_idt,
4137         .get_gdt = vmx_get_gdt,
4138         .set_gdt = vmx_set_gdt,
4139         .cache_reg = vmx_cache_reg,
4140         .get_rflags = vmx_get_rflags,
4141         .set_rflags = vmx_set_rflags,
4142         .fpu_deactivate = vmx_fpu_deactivate,
4143
4144         .tlb_flush = vmx_flush_tlb,
4145
4146         .run = vmx_vcpu_run,
4147         .handle_exit = vmx_handle_exit,
4148         .skip_emulated_instruction = skip_emulated_instruction,
4149         .set_interrupt_shadow = vmx_set_interrupt_shadow,
4150         .get_interrupt_shadow = vmx_get_interrupt_shadow,
4151         .patch_hypercall = vmx_patch_hypercall,
4152         .set_irq = vmx_inject_irq,
4153         .set_nmi = vmx_inject_nmi,
4154         .queue_exception = vmx_queue_exception,
4155         .interrupt_allowed = vmx_interrupt_allowed,
4156         .nmi_allowed = vmx_nmi_allowed,
4157         .get_nmi_mask = vmx_get_nmi_mask,
4158         .set_nmi_mask = vmx_set_nmi_mask,
4159         .enable_nmi_window = enable_nmi_window,
4160         .enable_irq_window = enable_irq_window,
4161         .update_cr8_intercept = update_cr8_intercept,
4162
4163         .set_tss_addr = vmx_set_tss_addr,
4164         .get_tdp_level = get_ept_level,
4165         .get_mt_mask = vmx_get_mt_mask,
4166
4167         .exit_reasons_str = vmx_exit_reasons_str,
4168         .get_lpage_level = vmx_get_lpage_level,
4169
4170         .cpuid_update = vmx_cpuid_update,
4171
4172         .rdtscp_supported = vmx_rdtscp_supported,
4173 };
4174
4175 static int __init vmx_init(void)
4176 {
4177         int r, i;
4178
4179         rdmsrl_safe(MSR_EFER, &host_efer);
4180
4181         for (i = 0; i < NR_VMX_MSR; ++i)
4182                 kvm_define_shared_msr(i, vmx_msr_index[i]);
4183
4184         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4185         if (!vmx_io_bitmap_a)
4186                 return -ENOMEM;
4187
4188         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4189         if (!vmx_io_bitmap_b) {
4190                 r = -ENOMEM;
4191                 goto out;
4192         }
4193
4194         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4195         if (!vmx_msr_bitmap_legacy) {
4196                 r = -ENOMEM;
4197                 goto out1;
4198         }
4199
4200         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4201         if (!vmx_msr_bitmap_longmode) {
4202                 r = -ENOMEM;
4203                 goto out2;
4204         }
4205
4206         /*
4207          * Allow direct access to the PC debug port (it is often used for I/O
4208          * delays, but the vmexits simply slow things down).
4209          */
4210         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4211         clear_bit(0x80, vmx_io_bitmap_a);
4212
4213         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4214
4215         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4216         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4217
4218         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4219
4220         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
4221         if (r)
4222                 goto out3;
4223
4224         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4225         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4226         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4227         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4228         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4229         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4230
4231         if (enable_ept) {
4232                 bypass_guest_pf = 0;
4233                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4234                         VMX_EPT_WRITABLE_MASK);
4235                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4236                                 VMX_EPT_EXECUTABLE_MASK);
4237                 kvm_enable_tdp();
4238         } else
4239                 kvm_disable_tdp();
4240
4241         if (bypass_guest_pf)
4242                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4243
4244         return 0;
4245
4246 out3:
4247         free_page((unsigned long)vmx_msr_bitmap_longmode);
4248 out2:
4249         free_page((unsigned long)vmx_msr_bitmap_legacy);
4250 out1:
4251         free_page((unsigned long)vmx_io_bitmap_b);
4252 out:
4253         free_page((unsigned long)vmx_io_bitmap_a);
4254         return r;
4255 }
4256
4257 static void __exit vmx_exit(void)
4258 {
4259         free_page((unsigned long)vmx_msr_bitmap_legacy);
4260         free_page((unsigned long)vmx_msr_bitmap_longmode);
4261         free_page((unsigned long)vmx_io_bitmap_b);
4262         free_page((unsigned long)vmx_io_bitmap_a);
4263
4264         kvm_exit();
4265 }
4266
4267 module_init(vmx_init)
4268 module_exit(vmx_exit)