SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/mm.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27 #include <linux/moduleparam.h>
  28 #include "kvm_cache_regs.h"
  29 #include "x86.h"
  30
  31 #include <asm/io.h>
  32 #include <asm/desc.h>
  33 #include <asm/vmx.h>
  34 #include <asm/virtext.h>
  35
  36 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  37
  38 MODULE_AUTHOR("Qumranet");
  39 MODULE_LICENSE("GPL");
  40
  41 static int bypass_guest_pf = 1;
  42 module_param(bypass_guest_pf, bool, 0);
  43
  44 static int enable_vpid = 1;
  45 module_param(enable_vpid, bool, 0);
  46
  47 static int flexpriority_enabled = 1;
  48 module_param(flexpriority_enabled, bool, 0);
  49
  50 static int enable_ept = 1;
  51 module_param(enable_ept, bool, 0);
  52
  53 static int emulate_invalid_guest_state = 0;
  54 module_param(emulate_invalid_guest_state, bool, 0);
  55
  56 struct vmcs {
  57         u32 revision_id;
  58         u32 abort;
  59         char data[0];
  60 };
  61
  62 struct vcpu_vmx {
  63         struct kvm_vcpu       vcpu;
  64         struct list_head      local_vcpus_link;
  65         unsigned long         host_rsp;
  66         int                   launched;
  67         u8                    fail;
  68         u32                   idt_vectoring_info;
  69         struct kvm_msr_entry *guest_msrs;
  70         struct kvm_msr_entry *host_msrs;
  71         int                   nmsrs;
  72         int                   save_nmsrs;
  73         int                   msr_offset_efer;
  74 #ifdef CONFIG_X86_64
  75         int                   msr_offset_kernel_gs_base;
  76 #endif
  77         struct vmcs          *vmcs;
  78         struct {
  79                 int           loaded;
  80                 u16           fs_sel, gs_sel, ldt_sel;
  81                 int           gs_ldt_reload_needed;
  82                 int           fs_reload_needed;
  83                 int           guest_efer_loaded;
  84         } host_state;
  85         struct {
  86                 struct {
  87                         bool pending;
  88                         u8 vector;
  89                         unsigned rip;
  90                 } irq;
  91         } rmode;
  92         int vpid;
  93         bool emulation_required;
  94
  95         /* Support for vnmi-less CPUs */
  96         int soft_vnmi_blocked;
  97         ktime_t entry_time;
  98         s64 vnmi_blocked_time;
  99 };
 100
 101 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 102 {
 103         return container_of(vcpu, struct vcpu_vmx, vcpu);
 104 }
 105
 106 static int init_rmode(struct kvm *kvm);
 107 static u64 construct_eptp(unsigned long root_hpa);
 108
 109 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 110 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 111 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 112
 113 static struct page *vmx_io_bitmap_a;
 114 static struct page *vmx_io_bitmap_b;
 115 static struct page *vmx_msr_bitmap;
 116
 117 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 118 static DEFINE_SPINLOCK(vmx_vpid_lock);
 119
 120 static struct vmcs_config {
 121         int size;
 122         int order;
 123         u32 revision_id;
 124         u32 pin_based_exec_ctrl;
 125         u32 cpu_based_exec_ctrl;
 126         u32 cpu_based_2nd_exec_ctrl;
 127         u32 vmexit_ctrl;
 128         u32 vmentry_ctrl;
 129 } vmcs_config;
 130
 131 static struct vmx_capability {
 132         u32 ept;
 133         u32 vpid;
 134 } vmx_capability;
 135
 136 #define VMX_SEGMENT_FIELD(seg)                                  \
 137         [VCPU_SREG_##seg] = {                                   \
 138                 .selector = GUEST_##seg##_SELECTOR,             \
 139                 .base = GUEST_##seg##_BASE,                     \
 140                 .limit = GUEST_##seg##_LIMIT,                   \
 141                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 142         }
 143
 144 static struct kvm_vmx_segment_field {
 145         unsigned selector;
 146         unsigned base;
 147         unsigned limit;
 148         unsigned ar_bytes;
 149 } kvm_vmx_segment_fields[] = {
 150         VMX_SEGMENT_FIELD(CS),
 151         VMX_SEGMENT_FIELD(DS),
 152         VMX_SEGMENT_FIELD(ES),
 153         VMX_SEGMENT_FIELD(FS),
 154         VMX_SEGMENT_FIELD(GS),
 155         VMX_SEGMENT_FIELD(SS),
 156         VMX_SEGMENT_FIELD(TR),
 157         VMX_SEGMENT_FIELD(LDTR),
 158 };
 159
 160 /*
 161  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 162  * away by decrementing the array size.
 163  */
 164 static const u32 vmx_msr_index[] = {
 165 #ifdef CONFIG_X86_64
 166         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
 167 #endif
 168         MSR_EFER, MSR_K6_STAR,
 169 };
 170 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 171
 172 static void load_msrs(struct kvm_msr_entry *e, int n)
 173 {
 174         int i;
 175
 176         for (i = 0; i < n; ++i)
 177                 wrmsrl(e[i].index, e[i].data);
 178 }
 179
 180 static void save_msrs(struct kvm_msr_entry *e, int n)
 181 {
 182         int i;
 183
 184         for (i = 0; i < n; ++i)
 185                 rdmsrl(e[i].index, e[i].data);
 186 }
 187
 188 static inline int is_page_fault(u32 intr_info)
 189 {
 190         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 191                              INTR_INFO_VALID_MASK)) ==
 192                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 193 }
 194
 195 static inline int is_no_device(u32 intr_info)
 196 {
 197         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 198                              INTR_INFO_VALID_MASK)) ==
 199                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 200 }
 201
 202 static inline int is_invalid_opcode(u32 intr_info)
 203 {
 204         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 205                              INTR_INFO_VALID_MASK)) ==
 206                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 207 }
 208
 209 static inline int is_external_interrupt(u32 intr_info)
 210 {
 211         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 212                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 213 }
 214
 215 static inline int cpu_has_vmx_msr_bitmap(void)
 216 {
 217         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
 218 }
 219
 220 static inline int cpu_has_vmx_tpr_shadow(void)
 221 {
 222         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
 223 }
 224
 225 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 226 {
 227         return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
 228 }
 229
 230 static inline int cpu_has_secondary_exec_ctrls(void)
 231 {
 232         return (vmcs_config.cpu_based_exec_ctrl &
 233                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
 234 }
 235
 236 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 237 {
 238         return flexpriority_enabled
 239                 && (vmcs_config.cpu_based_2nd_exec_ctrl &
 240                     SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
 241 }
 242
 243 static inline int cpu_has_vmx_invept_individual_addr(void)
 244 {
 245         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
 246 }
 247
 248 static inline int cpu_has_vmx_invept_context(void)
 249 {
 250         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
 251 }
 252
 253 static inline int cpu_has_vmx_invept_global(void)
 254 {
 255         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
 256 }
 257
 258 static inline int cpu_has_vmx_ept(void)
 259 {
 260         return (vmcs_config.cpu_based_2nd_exec_ctrl &
 261                 SECONDARY_EXEC_ENABLE_EPT);
 262 }
 263
 264 static inline int vm_need_ept(void)
 265 {
 266         return (cpu_has_vmx_ept() && enable_ept);
 267 }
 268
 269 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 270 {
 271         return ((cpu_has_vmx_virtualize_apic_accesses()) &&
 272                 (irqchip_in_kernel(kvm)));
 273 }
 274
 275 static inline int cpu_has_vmx_vpid(void)
 276 {
 277         return (vmcs_config.cpu_based_2nd_exec_ctrl &
 278                 SECONDARY_EXEC_ENABLE_VPID);
 279 }
 280
 281 static inline int cpu_has_virtual_nmis(void)
 282 {
 283         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 284 }
 285
 286 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 287 {
 288         int i;
 289
 290         for (i = 0; i < vmx->nmsrs; ++i)
 291                 if (vmx->guest_msrs[i].index == msr)
 292                         return i;
 293         return -1;
 294 }
 295
 296 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 297 {
 298     struct {
 299         u64 vpid : 16;
 300         u64 rsvd : 48;
 301         u64 gva;
 302     } operand = { vpid, 0, gva };
 303
 304     asm volatile (__ex(ASM_VMX_INVVPID)
 305                   /* CF==1 or ZF==1 --> rc = -1 */
 306                   "; ja 1f ; ud2 ; 1:"
 307                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 308 }
 309
 310 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 311 {
 312         struct {
 313                 u64 eptp, gpa;
 314         } operand = {eptp, gpa};
 315
 316         asm volatile (__ex(ASM_VMX_INVEPT)
 317                         /* CF==1 or ZF==1 --> rc = -1 */
 318                         "; ja 1f ; ud2 ; 1:\n"
 319                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 320 }
 321
 322 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 323 {
 324         int i;
 325
 326         i = __find_msr_index(vmx, msr);
 327         if (i >= 0)
 328                 return &vmx->guest_msrs[i];
 329         return NULL;
 330 }
 331
 332 static void vmcs_clear(struct vmcs *vmcs)
 333 {
 334         u64 phys_addr = __pa(vmcs);
 335         u8 error;
 336
 337         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 338                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 339                       : "cc", "memory");
 340         if (error)
 341                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 342                        vmcs, phys_addr);
 343 }
 344
 345 static void __vcpu_clear(void *arg)
 346 {
 347         struct vcpu_vmx *vmx = arg;
 348         int cpu = raw_smp_processor_id();
 349
 350         if (vmx->vcpu.cpu == cpu)
 351                 vmcs_clear(vmx->vmcs);
 352         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 353                 per_cpu(current_vmcs, cpu) = NULL;
 354         rdtscll(vmx->vcpu.arch.host_tsc);
 355         list_del(&vmx->local_vcpus_link);
 356         vmx->vcpu.cpu = -1;
 357         vmx->launched = 0;
 358 }
 359
 360 static void vcpu_clear(struct vcpu_vmx *vmx)
 361 {
 362         if (vmx->vcpu.cpu == -1)
 363                 return;
 364         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 365 }
 366
 367 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 368 {
 369         if (vmx->vpid == 0)
 370                 return;
 371
 372         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 373 }
 374
 375 static inline void ept_sync_global(void)
 376 {
 377         if (cpu_has_vmx_invept_global())
 378                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 379 }
 380
 381 static inline void ept_sync_context(u64 eptp)
 382 {
 383         if (vm_need_ept()) {
 384                 if (cpu_has_vmx_invept_context())
 385                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 386                 else
 387                         ept_sync_global();
 388         }
 389 }
 390
 391 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 392 {
 393         if (vm_need_ept()) {
 394                 if (cpu_has_vmx_invept_individual_addr())
 395                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 396                                         eptp, gpa);
 397                 else
 398                         ept_sync_context(eptp);
 399         }
 400 }
 401
 402 static unsigned long vmcs_readl(unsigned long field)
 403 {
 404         unsigned long value;
 405
 406         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 407                       : "=a"(value) : "d"(field) : "cc");
 408         return value;
 409 }
 410
 411 static u16 vmcs_read16(unsigned long field)
 412 {
 413         return vmcs_readl(field);
 414 }
 415
 416 static u32 vmcs_read32(unsigned long field)
 417 {
 418         return vmcs_readl(field);
 419 }
 420
 421 static u64 vmcs_read64(unsigned long field)
 422 {
 423 #ifdef CONFIG_X86_64
 424         return vmcs_readl(field);
 425 #else
 426         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 427 #endif
 428 }
 429
 430 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 431 {
 432         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 433                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 434         dump_stack();
 435 }
 436
 437 static void vmcs_writel(unsigned long field, unsigned long value)
 438 {
 439         u8 error;
 440
 441         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 442                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 443         if (unlikely(error))
 444                 vmwrite_error(field, value);
 445 }
 446
 447 static void vmcs_write16(unsigned long field, u16 value)
 448 {
 449         vmcs_writel(field, value);
 450 }
 451
 452 static void vmcs_write32(unsigned long field, u32 value)
 453 {
 454         vmcs_writel(field, value);
 455 }
 456
 457 static void vmcs_write64(unsigned long field, u64 value)
 458 {
 459         vmcs_writel(field, value);
 460 #ifndef CONFIG_X86_64
 461         asm volatile ("");
 462         vmcs_writel(field+1, value >> 32);
 463 #endif
 464 }
 465
 466 static void vmcs_clear_bits(unsigned long field, u32 mask)
 467 {
 468         vmcs_writel(field, vmcs_readl(field) & ~mask);
 469 }
 470
 471 static void vmcs_set_bits(unsigned long field, u32 mask)
 472 {
 473         vmcs_writel(field, vmcs_readl(field) | mask);
 474 }
 475
 476 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 477 {
 478         u32 eb;
 479
 480         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
 481         if (!vcpu->fpu_active)
 482                 eb |= 1u << NM_VECTOR;
 483         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
 484                 if (vcpu->guest_debug &
 485                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
 486                         eb |= 1u << DB_VECTOR;
 487                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
 488                         eb |= 1u << BP_VECTOR;
 489         }
 490         if (vcpu->arch.rmode.active)
 491                 eb = ~0;
 492         if (vm_need_ept())
 493                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 494         vmcs_write32(EXCEPTION_BITMAP, eb);
 495 }
 496
 497 static void reload_tss(void)
 498 {
 499         /*
 500          * VT restores TR but not its size.  Useless.
 501          */
 502         struct descriptor_table gdt;
 503         struct desc_struct *descs;
 504
 505         kvm_get_gdt(&gdt);
 506         descs = (void *)gdt.base;
 507         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 508         load_TR_desc();
 509 }
 510
 511 static void load_transition_efer(struct vcpu_vmx *vmx)
 512 {
 513         int efer_offset = vmx->msr_offset_efer;
 514         u64 host_efer = vmx->host_msrs[efer_offset].data;
 515         u64 guest_efer = vmx->guest_msrs[efer_offset].data;
 516         u64 ignore_bits;
 517
 518         if (efer_offset < 0)
 519                 return;
 520         /*
 521          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 522          * outside long mode
 523          */
 524         ignore_bits = EFER_NX | EFER_SCE;
 525 #ifdef CONFIG_X86_64
 526         ignore_bits |= EFER_LMA | EFER_LME;
 527         /* SCE is meaningful only in long mode on Intel */
 528         if (guest_efer & EFER_LMA)
 529                 ignore_bits &= ~(u64)EFER_SCE;
 530 #endif
 531         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
 532                 return;
 533
 534         vmx->host_state.guest_efer_loaded = 1;
 535         guest_efer &= ~ignore_bits;
 536         guest_efer |= host_efer & ignore_bits;
 537         wrmsrl(MSR_EFER, guest_efer);
 538         vmx->vcpu.stat.efer_reload++;
 539 }
 540
 541 static void reload_host_efer(struct vcpu_vmx *vmx)
 542 {
 543         if (vmx->host_state.guest_efer_loaded) {
 544                 vmx->host_state.guest_efer_loaded = 0;
 545                 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
 546         }
 547 }
 548
 549 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 550 {
 551         struct vcpu_vmx *vmx = to_vmx(vcpu);
 552
 553         if (vmx->host_state.loaded)
 554                 return;
 555
 556         vmx->host_state.loaded = 1;
 557         /*
 558          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 559          * allow segment selectors with cpl > 0 or ti == 1.
 560          */
 561         vmx->host_state.ldt_sel = kvm_read_ldt();
 562         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 563         vmx->host_state.fs_sel = kvm_read_fs();
 564         if (!(vmx->host_state.fs_sel & 7)) {
 565                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 566                 vmx->host_state.fs_reload_needed = 0;
 567         } else {
 568                 vmcs_write16(HOST_FS_SELECTOR, 0);
 569                 vmx->host_state.fs_reload_needed = 1;
 570         }
 571         vmx->host_state.gs_sel = kvm_read_gs();
 572         if (!(vmx->host_state.gs_sel & 7))
 573                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 574         else {
 575                 vmcs_write16(HOST_GS_SELECTOR, 0);
 576                 vmx->host_state.gs_ldt_reload_needed = 1;
 577         }
 578
 579 #ifdef CONFIG_X86_64
 580         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 581         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 582 #else
 583         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 584         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 585 #endif
 586
 587 #ifdef CONFIG_X86_64
 588         if (is_long_mode(&vmx->vcpu))
 589                 save_msrs(vmx->host_msrs +
 590                           vmx->msr_offset_kernel_gs_base, 1);
 591
 592 #endif
 593         load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 594         load_transition_efer(vmx);
 595 }
 596
 597 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 598 {
 599         unsigned long flags;
 600
 601         if (!vmx->host_state.loaded)
 602                 return;
 603
 604         ++vmx->vcpu.stat.host_state_reload;
 605         vmx->host_state.loaded = 0;
 606         if (vmx->host_state.fs_reload_needed)
 607                 kvm_load_fs(vmx->host_state.fs_sel);
 608         if (vmx->host_state.gs_ldt_reload_needed) {
 609                 kvm_load_ldt(vmx->host_state.ldt_sel);
 610                 /*
 611                  * If we have to reload gs, we must take care to
 612                  * preserve our gs base.
 613                  */
 614                 local_irq_save(flags);
 615                 kvm_load_gs(vmx->host_state.gs_sel);
 616 #ifdef CONFIG_X86_64
 617                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 618 #endif
 619                 local_irq_restore(flags);
 620         }
 621         reload_tss();
 622         save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 623         load_msrs(vmx->host_msrs, vmx->save_nmsrs);
 624         reload_host_efer(vmx);
 625 }
 626
 627 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 628 {
 629         preempt_disable();
 630         __vmx_load_host_state(vmx);
 631         preempt_enable();
 632 }
 633
 634 /*
 635  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 636  * vcpu mutex is already taken.
 637  */
 638 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 639 {
 640         struct vcpu_vmx *vmx = to_vmx(vcpu);
 641         u64 phys_addr = __pa(vmx->vmcs);
 642         u64 tsc_this, delta, new_offset;
 643
 644         if (vcpu->cpu != cpu) {
 645                 vcpu_clear(vmx);
 646                 kvm_migrate_timers(vcpu);
 647                 vpid_sync_vcpu_all(vmx);
 648                 local_irq_disable();
 649                 list_add(&vmx->local_vcpus_link,
 650                          &per_cpu(vcpus_on_cpu, cpu));
 651                 local_irq_enable();
 652         }
 653
 654         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 655                 u8 error;
 656
 657                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 658                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 659                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 660                               : "cc");
 661                 if (error)
 662                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 663                                vmx->vmcs, phys_addr);
 664         }
 665
 666         if (vcpu->cpu != cpu) {
 667                 struct descriptor_table dt;
 668                 unsigned long sysenter_esp;
 669
 670                 vcpu->cpu = cpu;
 671                 /*
 672                  * Linux uses per-cpu TSS and GDT, so set these when switching
 673                  * processors.
 674                  */
 675                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 676                 kvm_get_gdt(&dt);
 677                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 678
 679                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 680                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 681
 682                 /*
 683                  * Make sure the time stamp counter is monotonous.
 684                  */
 685                 rdtscll(tsc_this);
 686                 if (tsc_this < vcpu->arch.host_tsc) {
 687                         delta = vcpu->arch.host_tsc - tsc_this;
 688                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 689                         vmcs_write64(TSC_OFFSET, new_offset);
 690                 }
 691         }
 692 }
 693
 694 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 695 {
 696         __vmx_load_host_state(to_vmx(vcpu));
 697 }
 698
 699 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 700 {
 701         if (vcpu->fpu_active)
 702                 return;
 703         vcpu->fpu_active = 1;
 704         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 705         if (vcpu->arch.cr0 & X86_CR0_TS)
 706                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 707         update_exception_bitmap(vcpu);
 708 }
 709
 710 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 711 {
 712         if (!vcpu->fpu_active)
 713                 return;
 714         vcpu->fpu_active = 0;
 715         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 716         update_exception_bitmap(vcpu);
 717 }
 718
 719 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 720 {
 721         return vmcs_readl(GUEST_RFLAGS);
 722 }
 723
 724 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 725 {
 726         if (vcpu->arch.rmode.active)
 727                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 728         vmcs_writel(GUEST_RFLAGS, rflags);
 729 }
 730
 731 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 732 {
 733         unsigned long rip;
 734         u32 interruptibility;
 735
 736         rip = kvm_rip_read(vcpu);
 737         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 738         kvm_rip_write(vcpu, rip);
 739
 740         /*
 741          * We emulated an instruction, so temporary interrupt blocking
 742          * should be removed, if set.
 743          */
 744         interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 745         if (interruptibility & 3)
 746                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
 747                              interruptibility & ~3);
 748         vcpu->arch.interrupt_window_open = 1;
 749 }
 750
 751 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 752                                 bool has_error_code, u32 error_code)
 753 {
 754         struct vcpu_vmx *vmx = to_vmx(vcpu);
 755         u32 intr_info = nr | INTR_INFO_VALID_MASK;
 756
 757         if (has_error_code) {
 758                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 759                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
 760         }
 761
 762         if (vcpu->arch.rmode.active) {
 763                 vmx->rmode.irq.pending = true;
 764                 vmx->rmode.irq.vector = nr;
 765                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
 766                 if (nr == BP_VECTOR || nr == OF_VECTOR)
 767                         vmx->rmode.irq.rip++;
 768                 intr_info |= INTR_TYPE_SOFT_INTR;
 769                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 770                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
 771                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
 772                 return;
 773         }
 774
 775         if (nr == BP_VECTOR || nr == OF_VECTOR) {
 776                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
 777                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
 778         } else
 779                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
 780
 781         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 782 }
 783
 784 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
 785 {
 786         return false;
 787 }
 788
 789 /*
 790  * Swap MSR entry in host/guest MSR entry array.
 791  */
 792 #ifdef CONFIG_X86_64
 793 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 794 {
 795         struct kvm_msr_entry tmp;
 796
 797         tmp = vmx->guest_msrs[to];
 798         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 799         vmx->guest_msrs[from] = tmp;
 800         tmp = vmx->host_msrs[to];
 801         vmx->host_msrs[to] = vmx->host_msrs[from];
 802         vmx->host_msrs[from] = tmp;
 803 }
 804 #endif
 805
 806 /*
 807  * Set up the vmcs to automatically save and restore system
 808  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 809  * mode, as fiddling with msrs is very expensive.
 810  */
 811 static void setup_msrs(struct vcpu_vmx *vmx)
 812 {
 813         int save_nmsrs;
 814
 815         vmx_load_host_state(vmx);
 816         save_nmsrs = 0;
 817 #ifdef CONFIG_X86_64
 818         if (is_long_mode(&vmx->vcpu)) {
 819                 int index;
 820
 821                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 822                 if (index >= 0)
 823                         move_msr_up(vmx, index, save_nmsrs++);
 824                 index = __find_msr_index(vmx, MSR_LSTAR);
 825                 if (index >= 0)
 826                         move_msr_up(vmx, index, save_nmsrs++);
 827                 index = __find_msr_index(vmx, MSR_CSTAR);
 828                 if (index >= 0)
 829                         move_msr_up(vmx, index, save_nmsrs++);
 830                 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 831                 if (index >= 0)
 832                         move_msr_up(vmx, index, save_nmsrs++);
 833                 /*
 834                  * MSR_K6_STAR is only needed on long mode guests, and only
 835                  * if efer.sce is enabled.
 836                  */
 837                 index = __find_msr_index(vmx, MSR_K6_STAR);
 838                 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
 839                         move_msr_up(vmx, index, save_nmsrs++);
 840         }
 841 #endif
 842         vmx->save_nmsrs = save_nmsrs;
 843
 844 #ifdef CONFIG_X86_64
 845         vmx->msr_offset_kernel_gs_base =
 846                 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 847 #endif
 848         vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
 849 }
 850
 851 /*
 852  * reads and returns guest's timestamp counter "register"
 853  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 854  */
 855 static u64 guest_read_tsc(void)
 856 {
 857         u64 host_tsc, tsc_offset;
 858
 859         rdtscll(host_tsc);
 860         tsc_offset = vmcs_read64(TSC_OFFSET);
 861         return host_tsc + tsc_offset;
 862 }
 863
 864 /*
 865  * writes 'guest_tsc' into guest's timestamp counter "register"
 866  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 867  */
 868 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
 869 {
 870         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 871 }
 872
 873 /*
 874  * Reads an msr value (of 'msr_index') into 'pdata'.
 875  * Returns 0 on success, non-0 otherwise.
 876  * Assumes vcpu_load() was already called.
 877  */
 878 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
 879 {
 880         u64 data;
 881         struct kvm_msr_entry *msr;
 882
 883         if (!pdata) {
 884                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
 885                 return -EINVAL;
 886         }
 887
 888         switch (msr_index) {
 889 #ifdef CONFIG_X86_64
 890         case MSR_FS_BASE:
 891                 data = vmcs_readl(GUEST_FS_BASE);
 892                 break;
 893         case MSR_GS_BASE:
 894                 data = vmcs_readl(GUEST_GS_BASE);
 895                 break;
 896         case MSR_EFER:
 897                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 898 #endif
 899         case MSR_IA32_TIME_STAMP_COUNTER:
 900                 data = guest_read_tsc();
 901                 break;
 902         case MSR_IA32_SYSENTER_CS:
 903                 data = vmcs_read32(GUEST_SYSENTER_CS);
 904                 break;
 905         case MSR_IA32_SYSENTER_EIP:
 906                 data = vmcs_readl(GUEST_SYSENTER_EIP);
 907                 break;
 908         case MSR_IA32_SYSENTER_ESP:
 909                 data = vmcs_readl(GUEST_SYSENTER_ESP);
 910                 break;
 911         default:
 912                 vmx_load_host_state(to_vmx(vcpu));
 913                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
 914                 if (msr) {
 915                         data = msr->data;
 916                         break;
 917                 }
 918                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 919         }
 920
 921         *pdata = data;
 922         return 0;
 923 }
 924
 925 /*
 926  * Writes msr value into into the appropriate "register".
 927  * Returns 0 on success, non-0 otherwise.
 928  * Assumes vcpu_load() was already called.
 929  */
 930 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
 931 {
 932         struct vcpu_vmx *vmx = to_vmx(vcpu);
 933         struct kvm_msr_entry *msr;
 934         u64 host_tsc;
 935         int ret = 0;
 936
 937         switch (msr_index) {
 938 #ifdef CONFIG_X86_64
 939         case MSR_EFER:
 940                 vmx_load_host_state(vmx);
 941                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 942                 break;
 943         case MSR_FS_BASE:
 944                 vmcs_writel(GUEST_FS_BASE, data);
 945                 break;
 946         case MSR_GS_BASE:
 947                 vmcs_writel(GUEST_GS_BASE, data);
 948                 break;
 949 #endif
 950         case MSR_IA32_SYSENTER_CS:
 951                 vmcs_write32(GUEST_SYSENTER_CS, data);
 952                 break;
 953         case MSR_IA32_SYSENTER_EIP:
 954                 vmcs_writel(GUEST_SYSENTER_EIP, data);
 955                 break;
 956         case MSR_IA32_SYSENTER_ESP:
 957                 vmcs_writel(GUEST_SYSENTER_ESP, data);
 958                 break;
 959         case MSR_IA32_TIME_STAMP_COUNTER:
 960                 rdtscll(host_tsc);
 961                 guest_write_tsc(data, host_tsc);
 962                 break;
 963         case MSR_P6_PERFCTR0:
 964         case MSR_P6_PERFCTR1:
 965         case MSR_P6_EVNTSEL0:
 966         case MSR_P6_EVNTSEL1:
 967                 /*
 968                  * Just discard all writes to the performance counters; this
 969                  * should keep both older linux and windows 64-bit guests
 970                  * happy
 971                  */
 972                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
 973
 974                 break;
 975         case MSR_IA32_CR_PAT:
 976                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
 977                         vmcs_write64(GUEST_IA32_PAT, data);
 978                         vcpu->arch.pat = data;
 979                         break;
 980                 }
 981                 /* Otherwise falls through to kvm_set_msr_common */
 982         default:
 983                 vmx_load_host_state(vmx);
 984                 msr = find_msr_entry(vmx, msr_index);
 985                 if (msr) {
 986                         msr->data = data;
 987                         break;
 988                 }
 989                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 990         }
 991
 992         return ret;
 993 }
 994
 995 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
 996 {
 997         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
 998         switch (reg) {
 999         case VCPU_REGS_RSP:
1000                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1001                 break;
1002         case VCPU_REGS_RIP:
1003                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1004                 break;
1005         default:
1006                 break;
1007         }
1008 }
1009
1010 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1011 {
1012         int old_debug = vcpu->guest_debug;
1013         unsigned long flags;
1014
1015         vcpu->guest_debug = dbg->control;
1016         if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
1017                 vcpu->guest_debug = 0;
1018
1019         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1020                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1021         else
1022                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1023
1024         flags = vmcs_readl(GUEST_RFLAGS);
1025         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1026                 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1027         else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1028                 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1029         vmcs_writel(GUEST_RFLAGS, flags);
1030
1031         update_exception_bitmap(vcpu);
1032
1033         return 0;
1034 }
1035
1036 static int vmx_get_irq(struct kvm_vcpu *vcpu)
1037 {
1038         if (!vcpu->arch.interrupt.pending)
1039                 return -1;
1040         return vcpu->arch.interrupt.nr;
1041 }
1042
1043 static __init int cpu_has_kvm_support(void)
1044 {
1045         return cpu_has_vmx();
1046 }
1047
1048 static __init int vmx_disabled_by_bios(void)
1049 {
1050         u64 msr;
1051
1052         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1053         return (msr & (FEATURE_CONTROL_LOCKED |
1054                        FEATURE_CONTROL_VMXON_ENABLED))
1055             == FEATURE_CONTROL_LOCKED;
1056         /* locked but not enabled */
1057 }
1058
1059 static void hardware_enable(void *garbage)
1060 {
1061         int cpu = raw_smp_processor_id();
1062         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1063         u64 old;
1064
1065         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1066         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1067         if ((old & (FEATURE_CONTROL_LOCKED |
1068                     FEATURE_CONTROL_VMXON_ENABLED))
1069             != (FEATURE_CONTROL_LOCKED |
1070                 FEATURE_CONTROL_VMXON_ENABLED))
1071                 /* enable and lock */
1072                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1073                        FEATURE_CONTROL_LOCKED |
1074                        FEATURE_CONTROL_VMXON_ENABLED);
1075         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1076         asm volatile (ASM_VMX_VMXON_RAX
1077                       : : "a"(&phys_addr), "m"(phys_addr)
1078                       : "memory", "cc");
1079 }
1080
1081 static void vmclear_local_vcpus(void)
1082 {
1083         int cpu = raw_smp_processor_id();
1084         struct vcpu_vmx *vmx, *n;
1085
1086         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1087                                  local_vcpus_link)
1088                 __vcpu_clear(vmx);
1089 }
1090
1091
1092 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1093  * tricks.
1094  */
1095 static void kvm_cpu_vmxoff(void)
1096 {
1097         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1098         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1099 }
1100
1101 static void hardware_disable(void *garbage)
1102 {
1103         vmclear_local_vcpus();
1104         kvm_cpu_vmxoff();
1105 }
1106
1107 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1108                                       u32 msr, u32 *result)
1109 {
1110         u32 vmx_msr_low, vmx_msr_high;
1111         u32 ctl = ctl_min | ctl_opt;
1112
1113         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1114
1115         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1116         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1117
1118         /* Ensure minimum (required) set of control bits are supported. */
1119         if (ctl_min & ~ctl)
1120                 return -EIO;
1121
1122         *result = ctl;
1123         return 0;
1124 }
1125
1126 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1127 {
1128         u32 vmx_msr_low, vmx_msr_high;
1129         u32 min, opt, min2, opt2;
1130         u32 _pin_based_exec_control = 0;
1131         u32 _cpu_based_exec_control = 0;
1132         u32 _cpu_based_2nd_exec_control = 0;
1133         u32 _vmexit_control = 0;
1134         u32 _vmentry_control = 0;
1135
1136         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1137         opt = PIN_BASED_VIRTUAL_NMIS;
1138         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1139                                 &_pin_based_exec_control) < 0)
1140                 return -EIO;
1141
1142         min = CPU_BASED_HLT_EXITING |
1143 #ifdef CONFIG_X86_64
1144               CPU_BASED_CR8_LOAD_EXITING |
1145               CPU_BASED_CR8_STORE_EXITING |
1146 #endif
1147               CPU_BASED_CR3_LOAD_EXITING |
1148               CPU_BASED_CR3_STORE_EXITING |
1149               CPU_BASED_USE_IO_BITMAPS |
1150               CPU_BASED_MOV_DR_EXITING |
1151               CPU_BASED_USE_TSC_OFFSETING |
1152               CPU_BASED_INVLPG_EXITING;
1153         opt = CPU_BASED_TPR_SHADOW |
1154               CPU_BASED_USE_MSR_BITMAPS |
1155               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1156         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1157                                 &_cpu_based_exec_control) < 0)
1158                 return -EIO;
1159 #ifdef CONFIG_X86_64
1160         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1161                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1162                                            ~CPU_BASED_CR8_STORE_EXITING;
1163 #endif
1164         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1165                 min2 = 0;
1166                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1167                         SECONDARY_EXEC_WBINVD_EXITING |
1168                         SECONDARY_EXEC_ENABLE_VPID |
1169                         SECONDARY_EXEC_ENABLE_EPT;
1170                 if (adjust_vmx_controls(min2, opt2,
1171                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1172                                         &_cpu_based_2nd_exec_control) < 0)
1173                         return -EIO;
1174         }
1175 #ifndef CONFIG_X86_64
1176         if (!(_cpu_based_2nd_exec_control &
1177                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1178                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1179 #endif
1180         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1181                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1182                    enabled */
1183                 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1184                          CPU_BASED_CR3_STORE_EXITING |
1185                          CPU_BASED_INVLPG_EXITING);
1186                 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1187                                         &_cpu_based_exec_control) < 0)
1188                         return -EIO;
1189                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1190                       vmx_capability.ept, vmx_capability.vpid);
1191         }
1192
1193         min = 0;
1194 #ifdef CONFIG_X86_64
1195         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1196 #endif
1197         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1198         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1199                                 &_vmexit_control) < 0)
1200                 return -EIO;
1201
1202         min = 0;
1203         opt = VM_ENTRY_LOAD_IA32_PAT;
1204         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1205                                 &_vmentry_control) < 0)
1206                 return -EIO;
1207
1208         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1209
1210         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1211         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1212                 return -EIO;
1213
1214 #ifdef CONFIG_X86_64
1215         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1216         if (vmx_msr_high & (1u<<16))
1217                 return -EIO;
1218 #endif
1219
1220         /* Require Write-Back (WB) memory type for VMCS accesses. */
1221         if (((vmx_msr_high >> 18) & 15) != 6)
1222                 return -EIO;
1223
1224         vmcs_conf->size = vmx_msr_high & 0x1fff;
1225         vmcs_conf->order = get_order(vmcs_config.size);
1226         vmcs_conf->revision_id = vmx_msr_low;
1227
1228         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1229         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1230         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1231         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1232         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1233
1234         return 0;
1235 }
1236
1237 static struct vmcs *alloc_vmcs_cpu(int cpu)
1238 {
1239         int node = cpu_to_node(cpu);
1240         struct page *pages;
1241         struct vmcs *vmcs;
1242
1243         pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1244         if (!pages)
1245                 return NULL;
1246         vmcs = page_address(pages);
1247         memset(vmcs, 0, vmcs_config.size);
1248         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1249         return vmcs;
1250 }
1251
1252 static struct vmcs *alloc_vmcs(void)
1253 {
1254         return alloc_vmcs_cpu(raw_smp_processor_id());
1255 }
1256
1257 static void free_vmcs(struct vmcs *vmcs)
1258 {
1259         free_pages((unsigned long)vmcs, vmcs_config.order);
1260 }
1261
1262 static void free_kvm_area(void)
1263 {
1264         int cpu;
1265
1266         for_each_online_cpu(cpu)
1267                 free_vmcs(per_cpu(vmxarea, cpu));
1268 }
1269
1270 static __init int alloc_kvm_area(void)
1271 {
1272         int cpu;
1273
1274         for_each_online_cpu(cpu) {
1275                 struct vmcs *vmcs;
1276
1277                 vmcs = alloc_vmcs_cpu(cpu);
1278                 if (!vmcs) {
1279                         free_kvm_area();
1280                         return -ENOMEM;
1281                 }
1282
1283                 per_cpu(vmxarea, cpu) = vmcs;
1284         }
1285         return 0;
1286 }
1287
1288 static __init int hardware_setup(void)
1289 {
1290         if (setup_vmcs_config(&vmcs_config) < 0)
1291                 return -EIO;
1292
1293         if (boot_cpu_has(X86_FEATURE_NX))
1294                 kvm_enable_efer_bits(EFER_NX);
1295
1296         return alloc_kvm_area();
1297 }
1298
1299 static __exit void hardware_unsetup(void)
1300 {
1301         free_kvm_area();
1302 }
1303
1304 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1305 {
1306         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1307
1308         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1309                 vmcs_write16(sf->selector, save->selector);
1310                 vmcs_writel(sf->base, save->base);
1311                 vmcs_write32(sf->limit, save->limit);
1312                 vmcs_write32(sf->ar_bytes, save->ar);
1313         } else {
1314                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1315                         << AR_DPL_SHIFT;
1316                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1317         }
1318 }
1319
1320 static void enter_pmode(struct kvm_vcpu *vcpu)
1321 {
1322         unsigned long flags;
1323         struct vcpu_vmx *vmx = to_vmx(vcpu);
1324
1325         vmx->emulation_required = 1;
1326         vcpu->arch.rmode.active = 0;
1327
1328         vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1329         vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1330         vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1331
1332         flags = vmcs_readl(GUEST_RFLAGS);
1333         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1334         flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1335         vmcs_writel(GUEST_RFLAGS, flags);
1336
1337         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1338                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1339
1340         update_exception_bitmap(vcpu);
1341
1342         if (emulate_invalid_guest_state)
1343                 return;
1344
1345         fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1346         fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1347         fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1348         fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1349
1350         vmcs_write16(GUEST_SS_SELECTOR, 0);
1351         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1352
1353         vmcs_write16(GUEST_CS_SELECTOR,
1354                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1355         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1356 }
1357
1358 static gva_t rmode_tss_base(struct kvm *kvm)
1359 {
1360         if (!kvm->arch.tss_addr) {
1361                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1362                                  kvm->memslots[0].npages - 3;
1363                 return base_gfn << PAGE_SHIFT;
1364         }
1365         return kvm->arch.tss_addr;
1366 }
1367
1368 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1369 {
1370         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1371
1372         save->selector = vmcs_read16(sf->selector);
1373         save->base = vmcs_readl(sf->base);
1374         save->limit = vmcs_read32(sf->limit);
1375         save->ar = vmcs_read32(sf->ar_bytes);
1376         vmcs_write16(sf->selector, save->base >> 4);
1377         vmcs_write32(sf->base, save->base & 0xfffff);
1378         vmcs_write32(sf->limit, 0xffff);
1379         vmcs_write32(sf->ar_bytes, 0xf3);
1380 }
1381
1382 static void enter_rmode(struct kvm_vcpu *vcpu)
1383 {
1384         unsigned long flags;
1385         struct vcpu_vmx *vmx = to_vmx(vcpu);
1386
1387         vmx->emulation_required = 1;
1388         vcpu->arch.rmode.active = 1;
1389
1390         vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1391         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1392
1393         vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1394         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1395
1396         vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1397         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1398
1399         flags = vmcs_readl(GUEST_RFLAGS);
1400         vcpu->arch.rmode.save_iopl
1401                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1402
1403         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1404
1405         vmcs_writel(GUEST_RFLAGS, flags);
1406         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1407         update_exception_bitmap(vcpu);
1408
1409         if (emulate_invalid_guest_state)
1410                 goto continue_rmode;
1411
1412         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1413         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1414         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1415
1416         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1417         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1418         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1419                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1420         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1421
1422         fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1423         fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1424         fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1425         fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1426
1427 continue_rmode:
1428         kvm_mmu_reset_context(vcpu);
1429         init_rmode(vcpu->kvm);
1430 }
1431
1432 #ifdef CONFIG_X86_64
1433
1434 static void enter_lmode(struct kvm_vcpu *vcpu)
1435 {
1436         u32 guest_tr_ar;
1437
1438         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1439         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1440                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1441                        __func__);
1442                 vmcs_write32(GUEST_TR_AR_BYTES,
1443                              (guest_tr_ar & ~AR_TYPE_MASK)
1444                              | AR_TYPE_BUSY_64_TSS);
1445         }
1446
1447         vcpu->arch.shadow_efer |= EFER_LMA;
1448
1449         find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1450         vmcs_write32(VM_ENTRY_CONTROLS,
1451                      vmcs_read32(VM_ENTRY_CONTROLS)
1452                      | VM_ENTRY_IA32E_MODE);
1453 }
1454
1455 static void exit_lmode(struct kvm_vcpu *vcpu)
1456 {
1457         vcpu->arch.shadow_efer &= ~EFER_LMA;
1458
1459         vmcs_write32(VM_ENTRY_CONTROLS,
1460                      vmcs_read32(VM_ENTRY_CONTROLS)
1461                      & ~VM_ENTRY_IA32E_MODE);
1462 }
1463
1464 #endif
1465
1466 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1467 {
1468         vpid_sync_vcpu_all(to_vmx(vcpu));
1469         if (vm_need_ept())
1470                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1471 }
1472
1473 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1474 {
1475         vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1476         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1477 }
1478
1479 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1480 {
1481         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1482                 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1483                         printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1484                         return;
1485                 }
1486                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1487                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1488                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1489                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1490         }
1491 }
1492
1493 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1494
1495 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1496                                         unsigned long cr0,
1497                                         struct kvm_vcpu *vcpu)
1498 {
1499         if (!(cr0 & X86_CR0_PG)) {
1500                 /* From paging/starting to nonpaging */
1501                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1502                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1503                              (CPU_BASED_CR3_LOAD_EXITING |
1504                               CPU_BASED_CR3_STORE_EXITING));
1505                 vcpu->arch.cr0 = cr0;
1506                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1507                 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1508                 *hw_cr0 &= ~X86_CR0_WP;
1509         } else if (!is_paging(vcpu)) {
1510                 /* From nonpaging to paging */
1511                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1512                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1513                              ~(CPU_BASED_CR3_LOAD_EXITING |
1514                                CPU_BASED_CR3_STORE_EXITING));
1515                 vcpu->arch.cr0 = cr0;
1516                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1517                 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1518                         *hw_cr0 &= ~X86_CR0_WP;
1519         }
1520 }
1521
1522 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1523                                         struct kvm_vcpu *vcpu)
1524 {
1525         if (!is_paging(vcpu)) {
1526                 *hw_cr4 &= ~X86_CR4_PAE;
1527                 *hw_cr4 |= X86_CR4_PSE;
1528         } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1529                 *hw_cr4 &= ~X86_CR4_PAE;
1530 }
1531
1532 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1533 {
1534         unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1535                                 KVM_VM_CR0_ALWAYS_ON;
1536
1537         vmx_fpu_deactivate(vcpu);
1538
1539         if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
1540                 enter_pmode(vcpu);
1541
1542         if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
1543                 enter_rmode(vcpu);
1544
1545 #ifdef CONFIG_X86_64
1546         if (vcpu->arch.shadow_efer & EFER_LME) {
1547                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1548                         enter_lmode(vcpu);
1549                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1550                         exit_lmode(vcpu);
1551         }
1552 #endif
1553
1554         if (vm_need_ept())
1555                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1556
1557         vmcs_writel(CR0_READ_SHADOW, cr0);
1558         vmcs_writel(GUEST_CR0, hw_cr0);
1559         vcpu->arch.cr0 = cr0;
1560
1561         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1562                 vmx_fpu_activate(vcpu);
1563 }
1564
1565 static u64 construct_eptp(unsigned long root_hpa)
1566 {
1567         u64 eptp;
1568
1569         /* TODO write the value reading from MSR */
1570         eptp = VMX_EPT_DEFAULT_MT |
1571                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1572         eptp |= (root_hpa & PAGE_MASK);
1573
1574         return eptp;
1575 }
1576
1577 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1578 {
1579         unsigned long guest_cr3;
1580         u64 eptp;
1581
1582         guest_cr3 = cr3;
1583         if (vm_need_ept()) {
1584                 eptp = construct_eptp(cr3);
1585                 vmcs_write64(EPT_POINTER, eptp);
1586                 ept_sync_context(eptp);
1587                 ept_load_pdptrs(vcpu);
1588                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1589                         VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1590         }
1591
1592         vmx_flush_tlb(vcpu);
1593         vmcs_writel(GUEST_CR3, guest_cr3);
1594         if (vcpu->arch.cr0 & X86_CR0_PE)
1595                 vmx_fpu_deactivate(vcpu);
1596 }
1597
1598 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1599 {
1600         unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1601                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1602
1603         vcpu->arch.cr4 = cr4;
1604         if (vm_need_ept())
1605                 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1606
1607         vmcs_writel(CR4_READ_SHADOW, cr4);
1608         vmcs_writel(GUEST_CR4, hw_cr4);
1609 }
1610
1611 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1612 {
1613         struct vcpu_vmx *vmx = to_vmx(vcpu);
1614         struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1615
1616         vcpu->arch.shadow_efer = efer;
1617         if (!msr)
1618                 return;
1619         if (efer & EFER_LMA) {
1620                 vmcs_write32(VM_ENTRY_CONTROLS,
1621                                      vmcs_read32(VM_ENTRY_CONTROLS) |
1622                                      VM_ENTRY_IA32E_MODE);
1623                 msr->data = efer;
1624
1625         } else {
1626                 vmcs_write32(VM_ENTRY_CONTROLS,
1627                                      vmcs_read32(VM_ENTRY_CONTROLS) &
1628                                      ~VM_ENTRY_IA32E_MODE);
1629
1630                 msr->data = efer & ~EFER_LME;
1631         }
1632         setup_msrs(vmx);
1633 }
1634
1635 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1636 {
1637         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1638
1639         return vmcs_readl(sf->base);
1640 }
1641
1642 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1643                             struct kvm_segment *var, int seg)
1644 {
1645         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1646         u32 ar;
1647
1648         var->base = vmcs_readl(sf->base);
1649         var->limit = vmcs_read32(sf->limit);
1650         var->selector = vmcs_read16(sf->selector);
1651         ar = vmcs_read32(sf->ar_bytes);
1652         if (ar & AR_UNUSABLE_MASK)
1653                 ar = 0;
1654         var->type = ar & 15;
1655         var->s = (ar >> 4) & 1;
1656         var->dpl = (ar >> 5) & 3;
1657         var->present = (ar >> 7) & 1;
1658         var->avl = (ar >> 12) & 1;
1659         var->l = (ar >> 13) & 1;
1660         var->db = (ar >> 14) & 1;
1661         var->g = (ar >> 15) & 1;
1662         var->unusable = (ar >> 16) & 1;
1663 }
1664
1665 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1666 {
1667         struct kvm_segment kvm_seg;
1668
1669         if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1670                 return 0;
1671
1672         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1673                 return 3;
1674
1675         vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1676         return kvm_seg.selector & 3;
1677 }
1678
1679 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1680 {
1681         u32 ar;
1682
1683         if (var->unusable)
1684                 ar = 1 << 16;
1685         else {
1686                 ar = var->type & 15;
1687                 ar |= (var->s & 1) << 4;
1688                 ar |= (var->dpl & 3) << 5;
1689                 ar |= (var->present & 1) << 7;
1690                 ar |= (var->avl & 1) << 12;
1691                 ar |= (var->l & 1) << 13;
1692                 ar |= (var->db & 1) << 14;
1693                 ar |= (var->g & 1) << 15;
1694         }
1695         if (ar == 0) /* a 0 value means unusable */
1696                 ar = AR_UNUSABLE_MASK;
1697
1698         return ar;
1699 }
1700
1701 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1702                             struct kvm_segment *var, int seg)
1703 {
1704         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1705         u32 ar;
1706
1707         if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1708                 vcpu->arch.rmode.tr.selector = var->selector;
1709                 vcpu->arch.rmode.tr.base = var->base;
1710                 vcpu->arch.rmode.tr.limit = var->limit;
1711                 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1712                 return;
1713         }
1714         vmcs_writel(sf->base, var->base);
1715         vmcs_write32(sf->limit, var->limit);
1716         vmcs_write16(sf->selector, var->selector);
1717         if (vcpu->arch.rmode.active && var->s) {
1718                 /*
1719                  * Hack real-mode segments into vm86 compatibility.
1720                  */
1721                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1722                         vmcs_writel(sf->base, 0xf0000);
1723                 ar = 0xf3;
1724         } else
1725                 ar = vmx_segment_access_rights(var);
1726         vmcs_write32(sf->ar_bytes, ar);
1727 }
1728
1729 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1730 {
1731         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1732
1733         *db = (ar >> 14) & 1;
1734         *l = (ar >> 13) & 1;
1735 }
1736
1737 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1738 {
1739         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1740         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1741 }
1742
1743 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1744 {
1745         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1746         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1747 }
1748
1749 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1750 {
1751         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1752         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1753 }
1754
1755 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1756 {
1757         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1758         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1759 }
1760
1761 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1762 {
1763         struct kvm_segment var;
1764         u32 ar;
1765
1766         vmx_get_segment(vcpu, &var, seg);
1767         ar = vmx_segment_access_rights(&var);
1768
1769         if (var.base != (var.selector << 4))
1770                 return false;
1771         if (var.limit != 0xffff)
1772                 return false;
1773         if (ar != 0xf3)
1774                 return false;
1775
1776         return true;
1777 }
1778
1779 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1780 {
1781         struct kvm_segment cs;
1782         unsigned int cs_rpl;
1783
1784         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1785         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1786
1787         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1788                 return false;
1789         if (!cs.s)
1790                 return false;
1791         if (!(~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK))) {
1792                 if (cs.dpl > cs_rpl)
1793                         return false;
1794         } else if (cs.type & AR_TYPE_CODE_MASK) {
1795                 if (cs.dpl != cs_rpl)
1796                         return false;
1797         }
1798         if (!cs.present)
1799                 return false;
1800
1801         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1802         return true;
1803 }
1804
1805 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1806 {
1807         struct kvm_segment ss;
1808         unsigned int ss_rpl;
1809
1810         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1811         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1812
1813         if ((ss.type != 3) || (ss.type != 7))
1814                 return false;
1815         if (!ss.s)
1816                 return false;
1817         if (ss.dpl != ss_rpl) /* DPL != RPL */
1818                 return false;
1819         if (!ss.present)
1820                 return false;
1821
1822         return true;
1823 }
1824
1825 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1826 {
1827         struct kvm_segment var;
1828         unsigned int rpl;
1829
1830         vmx_get_segment(vcpu, &var, seg);
1831         rpl = var.selector & SELECTOR_RPL_MASK;
1832
1833         if (!var.s)
1834                 return false;
1835         if (!var.present)
1836                 return false;
1837         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1838                 if (var.dpl < rpl) /* DPL < RPL */
1839                         return false;
1840         }
1841
1842         /* TODO: Add other members to kvm_segment_field to allow checking for other access
1843          * rights flags
1844          */
1845         return true;
1846 }
1847
1848 static bool tr_valid(struct kvm_vcpu *vcpu)
1849 {
1850         struct kvm_segment tr;
1851
1852         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1853
1854         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
1855                 return false;
1856         if ((tr.type != 3) || (tr.type != 11)) /* TODO: Check if guest is in IA32e mode */
1857                 return false;
1858         if (!tr.present)
1859                 return false;
1860
1861         return true;
1862 }
1863
1864 static bool ldtr_valid(struct kvm_vcpu *vcpu)
1865 {
1866         struct kvm_segment ldtr;
1867
1868         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1869
1870         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
1871                 return false;
1872         if (ldtr.type != 2)
1873                 return false;
1874         if (!ldtr.present)
1875                 return false;
1876
1877         return true;
1878 }
1879
1880 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
1881 {
1882         struct kvm_segment cs, ss;
1883
1884         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1885         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1886
1887         return ((cs.selector & SELECTOR_RPL_MASK) ==
1888                  (ss.selector & SELECTOR_RPL_MASK));
1889 }
1890
1891 /*
1892  * Check if guest state is valid. Returns true if valid, false if
1893  * not.
1894  * We assume that registers are always usable
1895  */
1896 static bool guest_state_valid(struct kvm_vcpu *vcpu)
1897 {
1898         /* real mode guest state checks */
1899         if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
1900                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
1901                         return false;
1902                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
1903                         return false;
1904                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
1905                         return false;
1906                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
1907                         return false;
1908                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
1909                         return false;
1910                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
1911                         return false;
1912         } else {
1913         /* protected mode guest state checks */
1914                 if (!cs_ss_rpl_check(vcpu))
1915                         return false;
1916                 if (!code_segment_valid(vcpu))
1917                         return false;
1918                 if (!stack_segment_valid(vcpu))
1919                         return false;
1920                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
1921                         return false;
1922                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
1923                         return false;
1924                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
1925                         return false;
1926                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
1927                         return false;
1928                 if (!tr_valid(vcpu))
1929                         return false;
1930                 if (!ldtr_valid(vcpu))
1931                         return false;
1932         }
1933         /* TODO:
1934          * - Add checks on RIP
1935          * - Add checks on RFLAGS
1936          */
1937
1938         return true;
1939 }
1940
1941 static int init_rmode_tss(struct kvm *kvm)
1942 {
1943         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1944         u16 data = 0;
1945         int ret = 0;
1946         int r;
1947
1948         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1949         if (r < 0)
1950                 goto out;
1951         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1952         r = kvm_write_guest_page(kvm, fn++, &data,
1953                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
1954         if (r < 0)
1955                 goto out;
1956         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1957         if (r < 0)
1958                 goto out;
1959         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1960         if (r < 0)
1961                 goto out;
1962         data = ~0;
1963         r = kvm_write_guest_page(kvm, fn, &data,
1964                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1965                                  sizeof(u8));
1966         if (r < 0)
1967                 goto out;
1968
1969         ret = 1;
1970 out:
1971         return ret;
1972 }
1973
1974 static int init_rmode_identity_map(struct kvm *kvm)
1975 {
1976         int i, r, ret;
1977         pfn_t identity_map_pfn;
1978         u32 tmp;
1979
1980         if (!vm_need_ept())
1981                 return 1;
1982         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
1983                 printk(KERN_ERR "EPT: identity-mapping pagetable "
1984                         "haven't been allocated!\n");
1985                 return 0;
1986         }
1987         if (likely(kvm->arch.ept_identity_pagetable_done))
1988                 return 1;
1989         ret = 0;
1990         identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
1991         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
1992         if (r < 0)
1993                 goto out;
1994         /* Set up identity-mapping pagetable for EPT in real mode */
1995         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
1996                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
1997                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
1998                 r = kvm_write_guest_page(kvm, identity_map_pfn,
1999                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2000                 if (r < 0)
2001                         goto out;
2002         }
2003         kvm->arch.ept_identity_pagetable_done = true;
2004         ret = 1;
2005 out:
2006         return ret;
2007 }
2008
2009 static void seg_setup(int seg)
2010 {
2011         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2012
2013         vmcs_write16(sf->selector, 0);
2014         vmcs_writel(sf->base, 0);
2015         vmcs_write32(sf->limit, 0xffff);
2016         vmcs_write32(sf->ar_bytes, 0xf3);
2017 }
2018
2019 static int alloc_apic_access_page(struct kvm *kvm)
2020 {
2021         struct kvm_userspace_memory_region kvm_userspace_mem;
2022         int r = 0;
2023
2024         down_write(&kvm->slots_lock);
2025         if (kvm->arch.apic_access_page)
2026                 goto out;
2027         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2028         kvm_userspace_mem.flags = 0;
2029         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2030         kvm_userspace_mem.memory_size = PAGE_SIZE;
2031         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2032         if (r)
2033                 goto out;
2034
2035         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2036 out:
2037         up_write(&kvm->slots_lock);
2038         return r;
2039 }
2040
2041 static int alloc_identity_pagetable(struct kvm *kvm)
2042 {
2043         struct kvm_userspace_memory_region kvm_userspace_mem;
2044         int r = 0;
2045
2046         down_write(&kvm->slots_lock);
2047         if (kvm->arch.ept_identity_pagetable)
2048                 goto out;
2049         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2050         kvm_userspace_mem.flags = 0;
2051         kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2052         kvm_userspace_mem.memory_size = PAGE_SIZE;
2053         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2054         if (r)
2055                 goto out;
2056
2057         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2058                         VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
2059 out:
2060         up_write(&kvm->slots_lock);
2061         return r;
2062 }
2063
2064 static void allocate_vpid(struct vcpu_vmx *vmx)
2065 {
2066         int vpid;
2067
2068         vmx->vpid = 0;
2069         if (!enable_vpid || !cpu_has_vmx_vpid())
2070                 return;
2071         spin_lock(&vmx_vpid_lock);
2072         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2073         if (vpid < VMX_NR_VPIDS) {
2074                 vmx->vpid = vpid;
2075                 __set_bit(vpid, vmx_vpid_bitmap);
2076         }
2077         spin_unlock(&vmx_vpid_lock);
2078 }
2079
2080 static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr)
2081 {
2082         void *va;
2083
2084         if (!cpu_has_vmx_msr_bitmap())
2085                 return;
2086
2087         /*
2088          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2089          * have the write-low and read-high bitmap offsets the wrong way round.
2090          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2091          */
2092         va = kmap(msr_bitmap);
2093         if (msr <= 0x1fff) {
2094                 __clear_bit(msr, va + 0x000); /* read-low */
2095                 __clear_bit(msr, va + 0x800); /* write-low */
2096         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2097                 msr &= 0x1fff;
2098                 __clear_bit(msr, va + 0x400); /* read-high */
2099                 __clear_bit(msr, va + 0xc00); /* write-high */
2100         }
2101         kunmap(msr_bitmap);
2102 }
2103
2104 /*
2105  * Sets up the vmcs for emulated real mode.
2106  */
2107 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2108 {
2109         u32 host_sysenter_cs, msr_low, msr_high;
2110         u32 junk;
2111         u64 host_pat, tsc_this, tsc_base;
2112         unsigned long a;
2113         struct descriptor_table dt;
2114         int i;
2115         unsigned long kvm_vmx_return;
2116         u32 exec_control;
2117
2118         /* I/O */
2119         vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
2120         vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
2121
2122         if (cpu_has_vmx_msr_bitmap())
2123                 vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap));
2124
2125         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2126
2127         /* Control */
2128         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2129                 vmcs_config.pin_based_exec_ctrl);
2130
2131         exec_control = vmcs_config.cpu_based_exec_ctrl;
2132         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2133                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2134 #ifdef CONFIG_X86_64
2135                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2136                                 CPU_BASED_CR8_LOAD_EXITING;
2137 #endif
2138         }
2139         if (!vm_need_ept())
2140                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2141                                 CPU_BASED_CR3_LOAD_EXITING  |
2142                                 CPU_BASED_INVLPG_EXITING;
2143         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2144
2145         if (cpu_has_secondary_exec_ctrls()) {
2146                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2147                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2148                         exec_control &=
2149                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2150                 if (vmx->vpid == 0)
2151                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2152                 if (!vm_need_ept())
2153                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2154                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2155         }
2156
2157         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2158         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2159         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2160
2161         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
2162         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2163         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2164
2165         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2166         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2167         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2168         vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs());    /* 22.2.4 */
2169         vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs());    /* 22.2.4 */
2170         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2171 #ifdef CONFIG_X86_64
2172         rdmsrl(MSR_FS_BASE, a);
2173         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2174         rdmsrl(MSR_GS_BASE, a);
2175         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2176 #else
2177         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2178         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2179 #endif
2180
2181         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2182
2183         kvm_get_idt(&dt);
2184         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
2185
2186         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2187         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2188         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2189         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2190         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2191
2192         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2193         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2194         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2195         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2196         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2197         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2198
2199         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2200                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2201                 host_pat = msr_low | ((u64) msr_high << 32);
2202                 vmcs_write64(HOST_IA32_PAT, host_pat);
2203         }
2204         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2205                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2206                 host_pat = msr_low | ((u64) msr_high << 32);
2207                 /* Write the default value follow host pat */
2208                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2209                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2210                 vmx->vcpu.arch.pat = host_pat;
2211         }
2212
2213         for (i = 0; i < NR_VMX_MSR; ++i) {
2214                 u32 index = vmx_msr_index[i];
2215                 u32 data_low, data_high;
2216                 u64 data;
2217                 int j = vmx->nmsrs;
2218
2219                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2220                         continue;
2221                 if (wrmsr_safe(index, data_low, data_high) < 0)
2222                         continue;
2223                 data = data_low | ((u64)data_high << 32);
2224                 vmx->host_msrs[j].index = index;
2225                 vmx->host_msrs[j].reserved = 0;
2226                 vmx->host_msrs[j].data = data;
2227                 vmx->guest_msrs[j] = vmx->host_msrs[j];
2228                 ++vmx->nmsrs;
2229         }
2230
2231         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2232
2233         /* 22.2.1, 20.8.1 */
2234         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2235
2236         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2237         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2238
2239         tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2240         rdtscll(tsc_this);
2241         if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2242                 tsc_base = tsc_this;
2243
2244         guest_write_tsc(0, tsc_base);
2245
2246         return 0;
2247 }
2248
2249 static int init_rmode(struct kvm *kvm)
2250 {
2251         if (!init_rmode_tss(kvm))
2252                 return 0;
2253         if (!init_rmode_identity_map(kvm))
2254                 return 0;
2255         return 1;
2256 }
2257
2258 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2259 {
2260         struct vcpu_vmx *vmx = to_vmx(vcpu);
2261         u64 msr;
2262         int ret;
2263
2264         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2265         down_read(&vcpu->kvm->slots_lock);
2266         if (!init_rmode(vmx->vcpu.kvm)) {
2267                 ret = -ENOMEM;
2268                 goto out;
2269         }
2270
2271         vmx->vcpu.arch.rmode.active = 0;
2272
2273         vmx->soft_vnmi_blocked = 0;
2274
2275         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2276         kvm_set_cr8(&vmx->vcpu, 0);
2277         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2278         if (vmx->vcpu.vcpu_id == 0)
2279                 msr |= MSR_IA32_APICBASE_BSP;
2280         kvm_set_apic_base(&vmx->vcpu, msr);
2281
2282         fx_init(&vmx->vcpu);
2283
2284         seg_setup(VCPU_SREG_CS);
2285         /*
2286          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2287          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2288          */
2289         if (vmx->vcpu.vcpu_id == 0) {
2290                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2291                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2292         } else {
2293                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2294                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2295         }
2296
2297         seg_setup(VCPU_SREG_DS);
2298         seg_setup(VCPU_SREG_ES);
2299         seg_setup(VCPU_SREG_FS);
2300         seg_setup(VCPU_SREG_GS);
2301         seg_setup(VCPU_SREG_SS);
2302
2303         vmcs_write16(GUEST_TR_SELECTOR, 0);
2304         vmcs_writel(GUEST_TR_BASE, 0);
2305         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2306         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2307
2308         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2309         vmcs_writel(GUEST_LDTR_BASE, 0);
2310         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2311         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2312
2313         vmcs_write32(GUEST_SYSENTER_CS, 0);
2314         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2315         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2316
2317         vmcs_writel(GUEST_RFLAGS, 0x02);
2318         if (vmx->vcpu.vcpu_id == 0)
2319                 kvm_rip_write(vcpu, 0xfff0);
2320         else
2321                 kvm_rip_write(vcpu, 0);
2322         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2323
2324         vmcs_writel(GUEST_DR7, 0x400);
2325
2326         vmcs_writel(GUEST_GDTR_BASE, 0);
2327         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2328
2329         vmcs_writel(GUEST_IDTR_BASE, 0);
2330         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2331
2332         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2333         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2334         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2335
2336         /* Special registers */
2337         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2338
2339         setup_msrs(vmx);
2340
2341         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2342
2343         if (cpu_has_vmx_tpr_shadow()) {
2344                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2345                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2346                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2347                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2348                 vmcs_write32(TPR_THRESHOLD, 0);
2349         }
2350
2351         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2352                 vmcs_write64(APIC_ACCESS_ADDR,
2353                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2354
2355         if (vmx->vpid != 0)
2356                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2357
2358         vmx->vcpu.arch.cr0 = 0x60000010;
2359         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2360         vmx_set_cr4(&vmx->vcpu, 0);
2361         vmx_set_efer(&vmx->vcpu, 0);
2362         vmx_fpu_activate(&vmx->vcpu);
2363         update_exception_bitmap(&vmx->vcpu);
2364
2365         vpid_sync_vcpu_all(vmx);
2366
2367         ret = 0;
2368
2369         /* HACK: Don't enable emulation on guest boot/reset */
2370         vmx->emulation_required = 0;
2371
2372 out:
2373         up_read(&vcpu->kvm->slots_lock);
2374         return ret;
2375 }
2376
2377 static void enable_irq_window(struct kvm_vcpu *vcpu)
2378 {
2379         u32 cpu_based_vm_exec_control;
2380
2381         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2382         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2383         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2384 }
2385
2386 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2387 {
2388         u32 cpu_based_vm_exec_control;
2389
2390         if (!cpu_has_virtual_nmis()) {
2391                 enable_irq_window(vcpu);
2392                 return;
2393         }
2394
2395         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2396         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2397         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2398 }
2399
2400 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2401 {
2402         struct vcpu_vmx *vmx = to_vmx(vcpu);
2403
2404         KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2405
2406         ++vcpu->stat.irq_injections;
2407         if (vcpu->arch.rmode.active) {
2408                 vmx->rmode.irq.pending = true;
2409                 vmx->rmode.irq.vector = irq;
2410                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2411                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2412                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2413                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2414                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2415                 return;
2416         }
2417         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2418                         irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2419 }
2420
2421 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2422 {
2423         struct vcpu_vmx *vmx = to_vmx(vcpu);
2424
2425         if (!cpu_has_virtual_nmis()) {
2426                 /*
2427                  * Tracking the NMI-blocked state in software is built upon
2428                  * finding the next open IRQ window. This, in turn, depends on
2429                  * well-behaving guests: They have to keep IRQs disabled at
2430                  * least as long as the NMI handler runs. Otherwise we may
2431                  * cause NMI nesting, maybe breaking the guest. But as this is
2432                  * highly unlikely, we can live with the residual risk.
2433                  */
2434                 vmx->soft_vnmi_blocked = 1;
2435                 vmx->vnmi_blocked_time = 0;
2436         }
2437
2438         ++vcpu->stat.nmi_injections;
2439         if (vcpu->arch.rmode.active) {
2440                 vmx->rmode.irq.pending = true;
2441                 vmx->rmode.irq.vector = NMI_VECTOR;
2442                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2443                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2444                              NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2445                              INTR_INFO_VALID_MASK);
2446                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2447                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2448                 return;
2449         }
2450         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2451                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2452 }
2453
2454 static void vmx_update_window_states(struct kvm_vcpu *vcpu)
2455 {
2456         u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2457
2458         vcpu->arch.nmi_window_open =
2459                 !(guest_intr & (GUEST_INTR_STATE_STI |
2460                                 GUEST_INTR_STATE_MOV_SS |
2461                                 GUEST_INTR_STATE_NMI));
2462         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2463                 vcpu->arch.nmi_window_open = 0;
2464
2465         vcpu->arch.interrupt_window_open =
2466                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2467                  !(guest_intr & (GUEST_INTR_STATE_STI |
2468                                  GUEST_INTR_STATE_MOV_SS)));
2469 }
2470
2471 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
2472 {
2473         int word_index = __ffs(vcpu->arch.irq_summary);
2474         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
2475         int irq = word_index * BITS_PER_LONG + bit_index;
2476
2477         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2478         if (!vcpu->arch.irq_pending[word_index])
2479                 clear_bit(word_index, &vcpu->arch.irq_summary);
2480         kvm_queue_interrupt(vcpu, irq);
2481 }
2482
2483 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2484                                        struct kvm_run *kvm_run)
2485 {
2486         vmx_update_window_states(vcpu);
2487
2488         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
2489                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2490                                 GUEST_INTR_STATE_STI |
2491                                 GUEST_INTR_STATE_MOV_SS);
2492
2493         if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
2494                 if (vcpu->arch.interrupt.pending) {
2495                         enable_nmi_window(vcpu);
2496                 } else if (vcpu->arch.nmi_window_open) {
2497                         vcpu->arch.nmi_pending = false;
2498                         vcpu->arch.nmi_injected = true;
2499                 } else {
2500                         enable_nmi_window(vcpu);
2501                         return;
2502                 }
2503         }
2504         if (vcpu->arch.nmi_injected) {
2505                 vmx_inject_nmi(vcpu);
2506                 if (vcpu->arch.nmi_pending)
2507                         enable_nmi_window(vcpu);
2508                 else if (vcpu->arch.irq_summary
2509                          || kvm_run->request_interrupt_window)
2510                         enable_irq_window(vcpu);
2511                 return;
2512         }
2513
2514         if (vcpu->arch.interrupt_window_open) {
2515                 if (vcpu->arch.irq_summary && !vcpu->arch.interrupt.pending)
2516                         kvm_do_inject_irq(vcpu);
2517
2518                 if (vcpu->arch.interrupt.pending)
2519                         vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
2520         }
2521         if (!vcpu->arch.interrupt_window_open &&
2522             (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
2523                 enable_irq_window(vcpu);
2524 }
2525
2526 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2527 {
2528         int ret;
2529         struct kvm_userspace_memory_region tss_mem = {
2530                 .slot = TSS_PRIVATE_MEMSLOT,
2531                 .guest_phys_addr = addr,
2532                 .memory_size = PAGE_SIZE * 3,
2533                 .flags = 0,
2534         };
2535
2536         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2537         if (ret)
2538                 return ret;
2539         kvm->arch.tss_addr = addr;
2540         return 0;
2541 }
2542
2543 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2544                                   int vec, u32 err_code)
2545 {
2546         /*
2547          * Instruction with address size override prefix opcode 0x67
2548          * Cause the #SS fault with 0 error code in VM86 mode.
2549          */
2550         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2551                 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2552                         return 1;
2553         /*
2554          * Forward all other exceptions that are valid in real mode.
2555          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2556          *        the required debugging infrastructure rework.
2557          */
2558         switch (vec) {
2559         case DB_VECTOR:
2560                 if (vcpu->guest_debug &
2561                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2562                         return 0;
2563                 kvm_queue_exception(vcpu, vec);
2564                 return 1;
2565         case BP_VECTOR:
2566                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2567                         return 0;
2568                 /* fall through */
2569         case DE_VECTOR:
2570         case OF_VECTOR:
2571         case BR_VECTOR:
2572         case UD_VECTOR:
2573         case DF_VECTOR:
2574         case SS_VECTOR:
2575         case GP_VECTOR:
2576         case MF_VECTOR:
2577                 kvm_queue_exception(vcpu, vec);
2578                 return 1;
2579         }
2580         return 0;
2581 }
2582
2583 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2584 {
2585         struct vcpu_vmx *vmx = to_vmx(vcpu);
2586         u32 intr_info, ex_no, error_code;
2587         unsigned long cr2, rip, dr6;
2588         u32 vect_info;
2589         enum emulation_result er;
2590
2591         vect_info = vmx->idt_vectoring_info;
2592         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2593
2594         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2595                                                 !is_page_fault(intr_info))
2596                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2597                        "intr info 0x%x\n", __func__, vect_info, intr_info);
2598
2599         if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
2600                 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
2601                 set_bit(irq, vcpu->arch.irq_pending);
2602                 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
2603         }
2604
2605         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2606                 return 1;  /* already handled by vmx_vcpu_run() */
2607
2608         if (is_no_device(intr_info)) {
2609                 vmx_fpu_activate(vcpu);
2610                 return 1;
2611         }
2612
2613         if (is_invalid_opcode(intr_info)) {
2614                 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2615                 if (er != EMULATE_DONE)
2616                         kvm_queue_exception(vcpu, UD_VECTOR);
2617                 return 1;
2618         }
2619
2620         error_code = 0;
2621         rip = kvm_rip_read(vcpu);
2622         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2623                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2624         if (is_page_fault(intr_info)) {
2625                 /* EPT won't cause page fault directly */
2626                 if (vm_need_ept())
2627                         BUG();
2628                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2629                 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2630                             (u32)((u64)cr2 >> 32), handler);
2631                 if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending)
2632                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
2633                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2634         }
2635
2636         if (vcpu->arch.rmode.active &&
2637             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2638                                                                 error_code)) {
2639                 if (vcpu->arch.halt_request) {
2640                         vcpu->arch.halt_request = 0;
2641                         return kvm_emulate_halt(vcpu);
2642                 }
2643                 return 1;
2644         }
2645
2646         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2647         switch (ex_no) {
2648         case DB_VECTOR:
2649                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2650                 if (!(vcpu->guest_debug &
2651                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2652                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2653                         kvm_queue_exception(vcpu, DB_VECTOR);
2654                         return 1;
2655                 }
2656                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2657                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2658                 /* fall through */
2659         case BP_VECTOR:
2660                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2661                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2662                 kvm_run->debug.arch.exception = ex_no;
2663                 break;
2664         default:
2665                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2666                 kvm_run->ex.exception = ex_no;
2667                 kvm_run->ex.error_code = error_code;
2668                 break;
2669         }
2670         return 0;
2671 }
2672
2673 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2674                                      struct kvm_run *kvm_run)
2675 {
2676         ++vcpu->stat.irq_exits;
2677         KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
2678         return 1;
2679 }
2680
2681 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2682 {
2683         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2684         return 0;
2685 }
2686
2687 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2688 {
2689         unsigned long exit_qualification;
2690         int size, down, in, string, rep;
2691         unsigned port;
2692
2693         ++vcpu->stat.io_exits;
2694         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2695         string = (exit_qualification & 16) != 0;
2696
2697         if (string) {
2698                 if (emulate_instruction(vcpu,
2699                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2700                         return 0;
2701                 return 1;
2702         }
2703
2704         size = (exit_qualification & 7) + 1;
2705         in = (exit_qualification & 8) != 0;
2706         down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
2707         rep = (exit_qualification & 32) != 0;
2708         port = exit_qualification >> 16;
2709
2710         skip_emulated_instruction(vcpu);
2711         return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2712 }
2713
2714 static void
2715 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2716 {
2717         /*
2718          * Patch in the VMCALL instruction:
2719          */
2720         hypercall[0] = 0x0f;
2721         hypercall[1] = 0x01;
2722         hypercall[2] = 0xc1;
2723 }
2724
2725 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2726 {
2727         unsigned long exit_qualification;
2728         int cr;
2729         int reg;
2730
2731         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2732         cr = exit_qualification & 15;
2733         reg = (exit_qualification >> 8) & 15;
2734         switch ((exit_qualification >> 4) & 3) {
2735         case 0: /* mov to cr */
2736                 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2737                             (u32)kvm_register_read(vcpu, reg),
2738                             (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2739                             handler);
2740                 switch (cr) {
2741                 case 0:
2742                         kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
2743                         skip_emulated_instruction(vcpu);
2744                         return 1;
2745                 case 3:
2746                         kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
2747                         skip_emulated_instruction(vcpu);
2748                         return 1;
2749                 case 4:
2750                         kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
2751                         skip_emulated_instruction(vcpu);
2752                         return 1;
2753                 case 8:
2754                         kvm_set_cr8(vcpu, kvm_register_read(vcpu, reg));
2755                         skip_emulated_instruction(vcpu);
2756                         if (irqchip_in_kernel(vcpu->kvm))
2757                                 return 1;
2758                         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2759                         return 0;
2760                 };
2761                 break;
2762         case 2: /* clts */
2763                 vmx_fpu_deactivate(vcpu);
2764                 vcpu->arch.cr0 &= ~X86_CR0_TS;
2765                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2766                 vmx_fpu_activate(vcpu);
2767                 KVMTRACE_0D(CLTS, vcpu, handler);
2768                 skip_emulated_instruction(vcpu);
2769                 return 1;
2770         case 1: /*mov from cr*/
2771                 switch (cr) {
2772                 case 3:
2773                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2774                         KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2775                                     (u32)kvm_register_read(vcpu, reg),
2776                                     (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2777                                     handler);
2778                         skip_emulated_instruction(vcpu);
2779                         return 1;
2780                 case 8:
2781                         kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2782                         KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2783                                     (u32)kvm_register_read(vcpu, reg), handler);
2784                         skip_emulated_instruction(vcpu);
2785                         return 1;
2786                 }
2787                 break;
2788         case 3: /* lmsw */
2789                 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2790
2791                 skip_emulated_instruction(vcpu);
2792                 return 1;
2793         default:
2794                 break;
2795         }
2796         kvm_run->exit_reason = 0;
2797         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2798                (int)(exit_qualification >> 4) & 3, cr);
2799         return 0;
2800 }
2801
2802 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2803 {
2804         unsigned long exit_qualification;
2805         unsigned long val;
2806         int dr, reg;
2807
2808         dr = vmcs_readl(GUEST_DR7);
2809         if (dr & DR7_GD) {
2810                 /*
2811                  * As the vm-exit takes precedence over the debug trap, we
2812                  * need to emulate the latter, either for the host or the
2813                  * guest debugging itself.
2814                  */
2815                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2816                         kvm_run->debug.arch.dr6 = vcpu->arch.dr6;
2817                         kvm_run->debug.arch.dr7 = dr;
2818                         kvm_run->debug.arch.pc =
2819                                 vmcs_readl(GUEST_CS_BASE) +
2820                                 vmcs_readl(GUEST_RIP);
2821                         kvm_run->debug.arch.exception = DB_VECTOR;
2822                         kvm_run->exit_reason = KVM_EXIT_DEBUG;
2823                         return 0;
2824                 } else {
2825                         vcpu->arch.dr7 &= ~DR7_GD;
2826                         vcpu->arch.dr6 |= DR6_BD;
2827                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2828                         kvm_queue_exception(vcpu, DB_VECTOR);
2829                         return 1;
2830                 }
2831         }
2832
2833         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2834         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2835         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2836         if (exit_qualification & TYPE_MOV_FROM_DR) {
2837                 switch (dr) {
2838                 case 0 ... 3:
2839                         val = vcpu->arch.db[dr];
2840                         break;
2841                 case 6:
2842                         val = vcpu->arch.dr6;
2843                         break;
2844                 case 7:
2845                         val = vcpu->arch.dr7;
2846                         break;
2847                 default:
2848                         val = 0;
2849                 }
2850                 kvm_register_write(vcpu, reg, val);
2851                 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
2852         } else {
2853                 val = vcpu->arch.regs[reg];
2854                 switch (dr) {
2855                 case 0 ... 3:
2856                         vcpu->arch.db[dr] = val;
2857                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2858                                 vcpu->arch.eff_db[dr] = val;
2859                         break;
2860                 case 4 ... 5:
2861                         if (vcpu->arch.cr4 & X86_CR4_DE)
2862                                 kvm_queue_exception(vcpu, UD_VECTOR);
2863                         break;
2864                 case 6:
2865                         if (val & 0xffffffff00000000ULL) {
2866                                 kvm_queue_exception(vcpu, GP_VECTOR);
2867                                 break;
2868                         }
2869                         vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
2870                         break;
2871                 case 7:
2872                         if (val & 0xffffffff00000000ULL) {
2873                                 kvm_queue_exception(vcpu, GP_VECTOR);
2874                                 break;
2875                         }
2876                         vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
2877                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
2878                                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2879                                 vcpu->arch.switch_db_regs =
2880                                         (val & DR7_BP_EN_MASK);
2881                         }
2882                         break;
2883                 }
2884                 KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)val, handler);
2885         }
2886         skip_emulated_instruction(vcpu);
2887         return 1;
2888 }
2889
2890 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2891 {
2892         kvm_emulate_cpuid(vcpu);
2893         return 1;
2894 }
2895
2896 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2897 {
2898         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2899         u64 data;
2900
2901         if (vmx_get_msr(vcpu, ecx, &data)) {
2902                 kvm_inject_gp(vcpu, 0);
2903                 return 1;
2904         }
2905
2906         KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2907                     handler);
2908
2909         /* FIXME: handling of bits 32:63 of rax, rdx */
2910         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2911         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2912         skip_emulated_instruction(vcpu);
2913         return 1;
2914 }
2915
2916 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2917 {
2918         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2919         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2920                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2921
2922         KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2923                     handler);
2924
2925         if (vmx_set_msr(vcpu, ecx, data) != 0) {
2926                 kvm_inject_gp(vcpu, 0);
2927                 return 1;
2928         }
2929
2930         skip_emulated_instruction(vcpu);
2931         return 1;
2932 }
2933
2934 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2935                                       struct kvm_run *kvm_run)
2936 {
2937         return 1;
2938 }
2939
2940 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2941                                    struct kvm_run *kvm_run)
2942 {
2943         u32 cpu_based_vm_exec_control;
2944
2945         /* clear pending irq */
2946         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2947         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2948         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2949
2950         KVMTRACE_0D(PEND_INTR, vcpu, handler);
2951         ++vcpu->stat.irq_window_exits;
2952
2953         /*
2954          * If the user space waits to inject interrupts, exit as soon as
2955          * possible
2956          */
2957         if (kvm_run->request_interrupt_window &&
2958             !vcpu->arch.irq_summary) {
2959                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2960                 return 0;
2961         }
2962         return 1;
2963 }
2964
2965 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2966 {
2967         skip_emulated_instruction(vcpu);
2968         return kvm_emulate_halt(vcpu);
2969 }
2970
2971 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2972 {
2973         skip_emulated_instruction(vcpu);
2974         kvm_emulate_hypercall(vcpu);
2975         return 1;
2976 }
2977
2978 static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2979 {
2980         u64 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2981
2982         kvm_mmu_invlpg(vcpu, exit_qualification);
2983         skip_emulated_instruction(vcpu);
2984         return 1;
2985 }
2986
2987 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2988 {
2989         skip_emulated_instruction(vcpu);
2990         /* TODO: Add support for VT-d/pass-through device */
2991         return 1;
2992 }
2993
2994 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2995 {
2996         u64 exit_qualification;
2997         enum emulation_result er;
2998         unsigned long offset;
2999
3000         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
3001         offset = exit_qualification & 0xffful;
3002
3003         er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3004
3005         if (er !=  EMULATE_DONE) {
3006                 printk(KERN_ERR
3007                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3008                        offset);
3009                 return -ENOTSUPP;
3010         }
3011         return 1;
3012 }
3013
3014 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3015 {
3016         struct vcpu_vmx *vmx = to_vmx(vcpu);
3017         unsigned long exit_qualification;
3018         u16 tss_selector;
3019         int reason;
3020
3021         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3022
3023         reason = (u32)exit_qualification >> 30;
3024         if (reason == TASK_SWITCH_GATE && vmx->vcpu.arch.nmi_injected &&
3025             (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
3026             (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK)
3027             == INTR_TYPE_NMI_INTR) {
3028                 vcpu->arch.nmi_injected = false;
3029                 if (cpu_has_virtual_nmis())
3030                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3031                                       GUEST_INTR_STATE_NMI);
3032         }
3033         tss_selector = exit_qualification;
3034
3035         if (!kvm_task_switch(vcpu, tss_selector, reason))
3036                 return 0;
3037
3038         /* clear all local breakpoint enable flags */
3039         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3040
3041         /*
3042          * TODO: What about debug traps on tss switch?
3043          *       Are we supposed to inject them and update dr6?
3044          */
3045
3046         return 1;
3047 }
3048
3049 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3050 {
3051         u64 exit_qualification;
3052         enum emulation_result er;
3053         gpa_t gpa;
3054         unsigned long hva;
3055         int gla_validity;
3056         int r;
3057
3058         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
3059
3060         if (exit_qualification & (1 << 6)) {
3061                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3062                 return -ENOTSUPP;
3063         }
3064
3065         gla_validity = (exit_qualification >> 7) & 0x3;
3066         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3067                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3068                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3069                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3070                         (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
3071                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3072                         (long unsigned int)exit_qualification);
3073                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3074                 kvm_run->hw.hardware_exit_reason = 0;
3075                 return -ENOTSUPP;
3076         }
3077
3078         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3079         hva = gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT);
3080         if (!kvm_is_error_hva(hva)) {
3081                 r = kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3082                 if (r < 0) {
3083                         printk(KERN_ERR "EPT: Not enough memory!\n");
3084                         return -ENOMEM;
3085                 }
3086                 return 1;
3087         } else {
3088                 /* must be MMIO */
3089                 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3090
3091                 if (er == EMULATE_FAIL) {
3092                         printk(KERN_ERR
3093                          "EPT: Fail to handle EPT violation vmexit!er is %d\n",
3094                          er);
3095                         printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3096                          (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3097                          (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
3098                         printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3099                                 (long unsigned int)exit_qualification);
3100                         return -ENOTSUPP;
3101                 } else if (er == EMULATE_DO_MMIO)
3102                         return 0;
3103         }
3104         return 1;
3105 }
3106
3107 static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3108 {
3109         u32 cpu_based_vm_exec_control;
3110
3111         /* clear pending NMI */
3112         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3113         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3114         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3115         ++vcpu->stat.nmi_window_exits;
3116
3117         return 1;
3118 }
3119
3120 static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3121                                 struct kvm_run *kvm_run)
3122 {
3123         struct vcpu_vmx *vmx = to_vmx(vcpu);
3124         int err;
3125
3126         preempt_enable();
3127         local_irq_enable();
3128
3129         while (!guest_state_valid(vcpu)) {
3130                 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3131
3132                 if (err == EMULATE_DO_MMIO)
3133                         break;
3134
3135                 if (err != EMULATE_DONE) {
3136                         kvm_report_emulation_failure(vcpu, "emulation failure");
3137                         return;
3138                 }
3139
3140                 if (signal_pending(current))
3141                         break;
3142                 if (need_resched())
3143                         schedule();
3144         }
3145
3146         local_irq_disable();
3147         preempt_disable();
3148
3149         /* Guest state should be valid now except if we need to
3150          * emulate an MMIO */
3151         if (guest_state_valid(vcpu))
3152                 vmx->emulation_required = 0;
3153 }
3154
3155 /*
3156  * The exit handlers return 1 if the exit was handled fully and guest execution
3157  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3158  * to be done to userspace and return 0.
3159  */
3160 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3161                                       struct kvm_run *kvm_run) = {
3162         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3163         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3164         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3165         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3166         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3167         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3168         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3169         [EXIT_REASON_CPUID]                   = handle_cpuid,
3170         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3171         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3172         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3173         [EXIT_REASON_HLT]                     = handle_halt,
3174         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3175         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3176         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3177         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3178         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3179         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3180         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3181 };
3182
3183 static const int kvm_vmx_max_exit_handlers =
3184         ARRAY_SIZE(kvm_vmx_exit_handlers);
3185
3186 /*
3187  * The guest has exited.  See if we can fix it or if we need userspace
3188  * assistance.
3189  */
3190 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
3191 {
3192         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
3193         struct vcpu_vmx *vmx = to_vmx(vcpu);
3194         u32 vectoring_info = vmx->idt_vectoring_info;
3195
3196         KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
3197                     (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
3198
3199         /* If we need to emulate an MMIO from handle_invalid_guest_state
3200          * we just return 0 */
3201         if (vmx->emulation_required && emulate_invalid_guest_state)
3202                 return 0;
3203
3204         /* Access CR3 don't cause VMExit in paging mode, so we need
3205          * to sync with guest real CR3. */
3206         if (vm_need_ept() && is_paging(vcpu)) {
3207                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3208                 ept_load_pdptrs(vcpu);
3209         }
3210
3211         if (unlikely(vmx->fail)) {
3212                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3213                 kvm_run->fail_entry.hardware_entry_failure_reason
3214                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3215                 return 0;
3216         }
3217
3218         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3219                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3220                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3221                         exit_reason != EXIT_REASON_TASK_SWITCH))
3222                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3223                        "(0x%x) and exit reason is 0x%x\n",
3224                        __func__, vectoring_info, exit_reason);
3225
3226         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3227                 if (vcpu->arch.interrupt_window_open) {
3228                         vmx->soft_vnmi_blocked = 0;
3229                         vcpu->arch.nmi_window_open = 1;
3230                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3231                            vcpu->arch.nmi_pending) {
3232                         /*
3233                          * This CPU don't support us in finding the end of an
3234                          * NMI-blocked window if the guest runs with IRQs
3235                          * disabled. So we pull the trigger after 1 s of
3236                          * futile waiting, but inform the user about this.
3237                          */
3238                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3239                                "state on VCPU %d after 1 s timeout\n",
3240                                __func__, vcpu->vcpu_id);
3241                         vmx->soft_vnmi_blocked = 0;
3242                         vmx->vcpu.arch.nmi_window_open = 1;
3243                 }
3244         }
3245
3246         if (exit_reason < kvm_vmx_max_exit_handlers
3247             && kvm_vmx_exit_handlers[exit_reason])
3248                 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3249         else {
3250                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3251                 kvm_run->hw.hardware_exit_reason = exit_reason;
3252         }
3253         return 0;
3254 }
3255
3256 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
3257 {
3258         int max_irr, tpr;
3259
3260         if (!vm_need_tpr_shadow(vcpu->kvm))
3261                 return;
3262
3263         if (!kvm_lapic_enabled(vcpu) ||
3264             ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
3265                 vmcs_write32(TPR_THRESHOLD, 0);
3266                 return;
3267         }
3268
3269         tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
3270         vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
3271 }
3272
3273 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3274 {
3275         u32 exit_intr_info;
3276         u32 idt_vectoring_info;
3277         bool unblock_nmi;
3278         u8 vector;
3279         int type;
3280         bool idtv_info_valid;
3281         u32 error;
3282
3283         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3284         if (cpu_has_virtual_nmis()) {
3285                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3286                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3287                 /*
3288                  * SDM 3: 25.7.1.2
3289                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3290                  * a guest IRET fault.
3291                  */
3292                 if (unblock_nmi && vector != DF_VECTOR)
3293                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3294                                       GUEST_INTR_STATE_NMI);
3295         } else if (unlikely(vmx->soft_vnmi_blocked))
3296                 vmx->vnmi_blocked_time +=
3297                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3298
3299         idt_vectoring_info = vmx->idt_vectoring_info;
3300         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3301         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3302         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3303         if (vmx->vcpu.arch.nmi_injected) {
3304                 /*
3305                  * SDM 3: 25.7.1.2
3306                  * Clear bit "block by NMI" before VM entry if a NMI delivery
3307                  * faulted.
3308                  */
3309                 if (idtv_info_valid && type == INTR_TYPE_NMI_INTR)
3310                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3311                                         GUEST_INTR_STATE_NMI);
3312                 else
3313                         vmx->vcpu.arch.nmi_injected = false;
3314         }
3315         kvm_clear_exception_queue(&vmx->vcpu);
3316         if (idtv_info_valid && (type == INTR_TYPE_HARD_EXCEPTION ||
3317                                 type == INTR_TYPE_SOFT_EXCEPTION)) {
3318                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3319                         error = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3320                         kvm_queue_exception_e(&vmx->vcpu, vector, error);
3321                 } else
3322                         kvm_queue_exception(&vmx->vcpu, vector);
3323                 vmx->idt_vectoring_info = 0;
3324         }
3325         kvm_clear_interrupt_queue(&vmx->vcpu);
3326         if (idtv_info_valid && type == INTR_TYPE_EXT_INTR) {
3327                 kvm_queue_interrupt(&vmx->vcpu, vector);
3328                 vmx->idt_vectoring_info = 0;
3329         }
3330 }
3331
3332 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
3333 {
3334         update_tpr_threshold(vcpu);
3335
3336         vmx_update_window_states(vcpu);
3337
3338         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3339                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3340                                 GUEST_INTR_STATE_STI |
3341                                 GUEST_INTR_STATE_MOV_SS);
3342
3343         if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
3344                 if (vcpu->arch.interrupt.pending) {
3345                         enable_nmi_window(vcpu);
3346                 } else if (vcpu->arch.nmi_window_open) {
3347                         vcpu->arch.nmi_pending = false;
3348                         vcpu->arch.nmi_injected = true;
3349                 } else {
3350                         enable_nmi_window(vcpu);
3351                         return;
3352                 }
3353         }
3354         if (vcpu->arch.nmi_injected) {
3355                 vmx_inject_nmi(vcpu);
3356                 if (vcpu->arch.nmi_pending)
3357                         enable_nmi_window(vcpu);
3358                 else if (kvm_cpu_has_interrupt(vcpu))
3359                         enable_irq_window(vcpu);
3360                 return;
3361         }
3362         if (!vcpu->arch.interrupt.pending && kvm_cpu_has_interrupt(vcpu)) {
3363                 if (vcpu->arch.interrupt_window_open)
3364                         kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu));
3365                 else
3366                         enable_irq_window(vcpu);
3367         }
3368         if (vcpu->arch.interrupt.pending) {
3369                 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
3370                 if (kvm_cpu_has_interrupt(vcpu))
3371                         enable_irq_window(vcpu);
3372         }
3373 }
3374
3375 /*
3376  * Failure to inject an interrupt should give us the information
3377  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3378  * when fetching the interrupt redirection bitmap in the real-mode
3379  * tss, this doesn't happen.  So we do it ourselves.
3380  */
3381 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3382 {
3383         vmx->rmode.irq.pending = 0;
3384         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3385                 return;
3386         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3387         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3388                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3389                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3390                 return;
3391         }
3392         vmx->idt_vectoring_info =
3393                 VECTORING_INFO_VALID_MASK
3394                 | INTR_TYPE_EXT_INTR
3395                 | vmx->rmode.irq.vector;
3396 }
3397
3398 #ifdef CONFIG_X86_64
3399 #define R "r"
3400 #define Q "q"
3401 #else
3402 #define R "e"
3403 #define Q "l"
3404 #endif
3405
3406 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3407 {
3408         struct vcpu_vmx *vmx = to_vmx(vcpu);
3409         u32 intr_info;
3410
3411         /* Record the guest's net vcpu time for enforced NMI injections. */
3412         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3413                 vmx->entry_time = ktime_get();
3414
3415         /* Handle invalid guest state instead of entering VMX */
3416         if (vmx->emulation_required && emulate_invalid_guest_state) {
3417                 handle_invalid_guest_state(vcpu, kvm_run);
3418                 return;
3419         }
3420
3421         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3422                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3423         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3424                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3425
3426         /*
3427          * Loading guest fpu may have cleared host cr0.ts
3428          */
3429         vmcs_writel(HOST_CR0, read_cr0());
3430
3431         set_debugreg(vcpu->arch.dr6, 6);
3432
3433         asm(
3434                 /* Store host registers */
3435                 "push %%"R"dx; push %%"R"bp;"
3436                 "push %%"R"cx \n\t"
3437                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3438                 "je 1f \n\t"
3439                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3440                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3441                 "1: \n\t"
3442                 /* Check if vmlaunch of vmresume is needed */
3443                 "cmpl $0, %c[launched](%0) \n\t"
3444                 /* Load guest registers.  Don't clobber flags. */
3445                 "mov %c[cr2](%0), %%"R"ax \n\t"
3446                 "mov %%"R"ax, %%cr2 \n\t"
3447                 "mov %c[rax](%0), %%"R"ax \n\t"
3448                 "mov %c[rbx](%0), %%"R"bx \n\t"
3449                 "mov %c[rdx](%0), %%"R"dx \n\t"
3450                 "mov %c[rsi](%0), %%"R"si \n\t"
3451                 "mov %c[rdi](%0), %%"R"di \n\t"
3452                 "mov %c[rbp](%0), %%"R"bp \n\t"
3453 #ifdef CONFIG_X86_64
3454                 "mov %c[r8](%0),  %%r8  \n\t"
3455                 "mov %c[r9](%0),  %%r9  \n\t"
3456                 "mov %c[r10](%0), %%r10 \n\t"
3457                 "mov %c[r11](%0), %%r11 \n\t"
3458                 "mov %c[r12](%0), %%r12 \n\t"
3459                 "mov %c[r13](%0), %%r13 \n\t"
3460                 "mov %c[r14](%0), %%r14 \n\t"
3461                 "mov %c[r15](%0), %%r15 \n\t"
3462 #endif
3463                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3464
3465                 /* Enter guest mode */
3466                 "jne .Llaunched \n\t"
3467                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3468                 "jmp .Lkvm_vmx_return \n\t"
3469                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3470                 ".Lkvm_vmx_return: "
3471                 /* Save guest registers, load host registers, keep flags */
3472                 "xchg %0,     (%%"R"sp) \n\t"
3473                 "mov %%"R"ax, %c[rax](%0) \n\t"
3474                 "mov %%"R"bx, %c[rbx](%0) \n\t"
3475                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3476                 "mov %%"R"dx, %c[rdx](%0) \n\t"
3477                 "mov %%"R"si, %c[rsi](%0) \n\t"
3478                 "mov %%"R"di, %c[rdi](%0) \n\t"
3479                 "mov %%"R"bp, %c[rbp](%0) \n\t"
3480 #ifdef CONFIG_X86_64
3481                 "mov %%r8,  %c[r8](%0) \n\t"
3482                 "mov %%r9,  %c[r9](%0) \n\t"
3483                 "mov %%r10, %c[r10](%0) \n\t"
3484                 "mov %%r11, %c[r11](%0) \n\t"
3485                 "mov %%r12, %c[r12](%0) \n\t"
3486                 "mov %%r13, %c[r13](%0) \n\t"
3487                 "mov %%r14, %c[r14](%0) \n\t"
3488                 "mov %%r15, %c[r15](%0) \n\t"
3489 #endif
3490                 "mov %%cr2, %%"R"ax   \n\t"
3491                 "mov %%"R"ax, %c[cr2](%0) \n\t"
3492
3493                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
3494                 "setbe %c[fail](%0) \n\t"
3495               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3496                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3497                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3498                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3499                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3500                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3501                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3502                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3503                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3504                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3505                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3506 #ifdef CONFIG_X86_64
3507                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3508                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3509                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3510                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3511                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3512                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3513                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3514                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3515 #endif
3516                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3517               : "cc", "memory"
3518                 , R"bx", R"di", R"si"
3519 #ifdef CONFIG_X86_64
3520                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3521 #endif
3522               );
3523
3524         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3525         vcpu->arch.regs_dirty = 0;
3526
3527         get_debugreg(vcpu->arch.dr6, 6);
3528
3529         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3530         if (vmx->rmode.irq.pending)
3531                 fixup_rmode_irq(vmx);
3532
3533         vmx_update_window_states(vcpu);
3534
3535         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3536         vmx->launched = 1;
3537
3538         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3539
3540         /* We need to handle NMIs before interrupts are enabled */
3541         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3542             (intr_info & INTR_INFO_VALID_MASK)) {
3543                 KVMTRACE_0D(NMI, vcpu, handler);
3544                 asm("int $2");
3545         }
3546
3547         vmx_complete_interrupts(vmx);
3548 }
3549
3550 #undef R
3551 #undef Q
3552
3553 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3554 {
3555         struct vcpu_vmx *vmx = to_vmx(vcpu);
3556
3557         if (vmx->vmcs) {
3558                 vcpu_clear(vmx);
3559                 free_vmcs(vmx->vmcs);
3560                 vmx->vmcs = NULL;
3561         }
3562 }
3563
3564 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3565 {
3566         struct vcpu_vmx *vmx = to_vmx(vcpu);
3567
3568         spin_lock(&vmx_vpid_lock);
3569         if (vmx->vpid != 0)
3570                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3571         spin_unlock(&vmx_vpid_lock);
3572         vmx_free_vmcs(vcpu);
3573         kfree(vmx->host_msrs);
3574         kfree(vmx->guest_msrs);
3575         kvm_vcpu_uninit(vcpu);
3576         kmem_cache_free(kvm_vcpu_cache, vmx);
3577 }
3578
3579 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3580 {
3581         int err;
3582         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3583         int cpu;
3584
3585         if (!vmx)
3586                 return ERR_PTR(-ENOMEM);
3587
3588         allocate_vpid(vmx);
3589
3590         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3591         if (err)
3592                 goto free_vcpu;
3593
3594         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3595         if (!vmx->guest_msrs) {
3596                 err = -ENOMEM;
3597                 goto uninit_vcpu;
3598         }
3599
3600         vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3601         if (!vmx->host_msrs)
3602                 goto free_guest_msrs;
3603
3604         vmx->vmcs = alloc_vmcs();
3605         if (!vmx->vmcs)
3606                 goto free_msrs;
3607
3608         vmcs_clear(vmx->vmcs);
3609
3610         cpu = get_cpu();
3611         vmx_vcpu_load(&vmx->vcpu, cpu);
3612         err = vmx_vcpu_setup(vmx);
3613         vmx_vcpu_put(&vmx->vcpu);
3614         put_cpu();
3615         if (err)
3616                 goto free_vmcs;
3617         if (vm_need_virtualize_apic_accesses(kvm))
3618                 if (alloc_apic_access_page(kvm) != 0)
3619                         goto free_vmcs;
3620
3621         if (vm_need_ept())
3622                 if (alloc_identity_pagetable(kvm) != 0)
3623                         goto free_vmcs;
3624
3625         return &vmx->vcpu;
3626
3627 free_vmcs:
3628         free_vmcs(vmx->vmcs);
3629 free_msrs:
3630         kfree(vmx->host_msrs);
3631 free_guest_msrs:
3632         kfree(vmx->guest_msrs);
3633 uninit_vcpu:
3634         kvm_vcpu_uninit(&vmx->vcpu);
3635 free_vcpu:
3636         kmem_cache_free(kvm_vcpu_cache, vmx);
3637         return ERR_PTR(err);
3638 }
3639
3640 static void __init vmx_check_processor_compat(void *rtn)
3641 {
3642         struct vmcs_config vmcs_conf;
3643
3644         *(int *)rtn = 0;
3645         if (setup_vmcs_config(&vmcs_conf) < 0)
3646                 *(int *)rtn = -EIO;
3647         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3648                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3649                                 smp_processor_id());
3650                 *(int *)rtn = -EIO;
3651         }
3652 }
3653
3654 static int get_ept_level(void)
3655 {
3656         return VMX_EPT_DEFAULT_GAW + 1;
3657 }
3658
3659 static int vmx_get_mt_mask_shift(void)
3660 {
3661         return VMX_EPT_MT_EPTE_SHIFT;
3662 }
3663
3664 static struct kvm_x86_ops vmx_x86_ops = {
3665         .cpu_has_kvm_support = cpu_has_kvm_support,
3666         .disabled_by_bios = vmx_disabled_by_bios,
3667         .hardware_setup = hardware_setup,
3668         .hardware_unsetup = hardware_unsetup,
3669         .check_processor_compatibility = vmx_check_processor_compat,
3670         .hardware_enable = hardware_enable,
3671         .hardware_disable = hardware_disable,
3672         .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
3673
3674         .vcpu_create = vmx_create_vcpu,
3675         .vcpu_free = vmx_free_vcpu,
3676         .vcpu_reset = vmx_vcpu_reset,
3677
3678         .prepare_guest_switch = vmx_save_host_state,
3679         .vcpu_load = vmx_vcpu_load,
3680         .vcpu_put = vmx_vcpu_put,
3681
3682         .set_guest_debug = set_guest_debug,
3683         .get_msr = vmx_get_msr,
3684         .set_msr = vmx_set_msr,
3685         .get_segment_base = vmx_get_segment_base,
3686         .get_segment = vmx_get_segment,
3687         .set_segment = vmx_set_segment,
3688         .get_cpl = vmx_get_cpl,
3689         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3690         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3691         .set_cr0 = vmx_set_cr0,
3692         .set_cr3 = vmx_set_cr3,
3693         .set_cr4 = vmx_set_cr4,
3694         .set_efer = vmx_set_efer,
3695         .get_idt = vmx_get_idt,
3696         .set_idt = vmx_set_idt,
3697         .get_gdt = vmx_get_gdt,
3698         .set_gdt = vmx_set_gdt,
3699         .cache_reg = vmx_cache_reg,
3700         .get_rflags = vmx_get_rflags,
3701         .set_rflags = vmx_set_rflags,
3702
3703         .tlb_flush = vmx_flush_tlb,
3704
3705         .run = vmx_vcpu_run,
3706         .handle_exit = kvm_handle_exit,
3707         .skip_emulated_instruction = skip_emulated_instruction,
3708         .patch_hypercall = vmx_patch_hypercall,
3709         .get_irq = vmx_get_irq,
3710         .set_irq = vmx_inject_irq,
3711         .queue_exception = vmx_queue_exception,
3712         .exception_injected = vmx_exception_injected,
3713         .inject_pending_irq = vmx_intr_assist,
3714         .inject_pending_vectors = do_interrupt_requests,
3715
3716         .set_tss_addr = vmx_set_tss_addr,
3717         .get_tdp_level = get_ept_level,
3718         .get_mt_mask_shift = vmx_get_mt_mask_shift,
3719 };
3720
3721 static int __init vmx_init(void)
3722 {
3723         void *va;
3724         int r;
3725
3726         vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3727         if (!vmx_io_bitmap_a)
3728                 return -ENOMEM;
3729
3730         vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3731         if (!vmx_io_bitmap_b) {
3732                 r = -ENOMEM;
3733                 goto out;
3734         }
3735
3736         vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3737         if (!vmx_msr_bitmap) {
3738                 r = -ENOMEM;
3739                 goto out1;
3740         }
3741
3742         /*
3743          * Allow direct access to the PC debug port (it is often used for I/O
3744          * delays, but the vmexits simply slow things down).
3745          */
3746         va = kmap(vmx_io_bitmap_a);
3747         memset(va, 0xff, PAGE_SIZE);
3748         clear_bit(0x80, va);
3749         kunmap(vmx_io_bitmap_a);
3750
3751         va = kmap(vmx_io_bitmap_b);
3752         memset(va, 0xff, PAGE_SIZE);
3753         kunmap(vmx_io_bitmap_b);
3754
3755         va = kmap(vmx_msr_bitmap);
3756         memset(va, 0xff, PAGE_SIZE);
3757         kunmap(vmx_msr_bitmap);
3758
3759         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3760
3761         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
3762         if (r)
3763                 goto out2;
3764
3765         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE);
3766         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE);
3767         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS);
3768         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP);
3769         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP);
3770
3771         if (vm_need_ept()) {
3772                 bypass_guest_pf = 0;
3773                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3774                         VMX_EPT_WRITABLE_MASK);
3775                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
3776                                 VMX_EPT_EXECUTABLE_MASK,
3777                                 VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
3778                 kvm_enable_tdp();
3779         } else
3780                 kvm_disable_tdp();
3781
3782         if (bypass_guest_pf)
3783                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3784
3785         ept_sync_global();
3786
3787         return 0;
3788
3789 out2:
3790         __free_page(vmx_msr_bitmap);
3791 out1:
3792         __free_page(vmx_io_bitmap_b);
3793 out:
3794         __free_page(vmx_io_bitmap_a);
3795         return r;
3796 }
3797
3798 static void __exit vmx_exit(void)
3799 {
3800         __free_page(vmx_msr_bitmap);
3801         __free_page(vmx_io_bitmap_b);
3802         __free_page(vmx_io_bitmap_a);
3803
3804         kvm_exit();
3805 }
3806
3807 module_init(vmx_init)
3808 module_exit(vmx_exit)