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   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/mm.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/ftrace_event.h>
  29 #include "kvm_cache_regs.h"
  30 #include "x86.h"
  31
  32 #include <asm/io.h>
  33 #include <asm/desc.h>
  34 #include <asm/vmx.h>
  35 #include <asm/virtext.h>
  36 #include <asm/mce.h>
  37
  38 #include "trace.h"
  39
  40 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  41
  42 MODULE_AUTHOR("Qumranet");
  43 MODULE_LICENSE("GPL");
  44
  45 static int __read_mostly bypass_guest_pf = 1;
  46 module_param(bypass_guest_pf, bool, S_IRUGO);
  47
  48 static int __read_mostly enable_vpid = 1;
  49 module_param_named(vpid, enable_vpid, bool, 0444);
  50
  51 static int __read_mostly flexpriority_enabled = 1;
  52 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  53
  54 static int __read_mostly enable_ept = 1;
  55 module_param_named(ept, enable_ept, bool, S_IRUGO);
  56
  57 static int __read_mostly enable_unrestricted_guest = 1;
  58 module_param_named(unrestricted_guest,
  59                         enable_unrestricted_guest, bool, S_IRUGO);
  60
  61 static int __read_mostly emulate_invalid_guest_state = 0;
  62 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  63
  64 /*
  65  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
  66  * ple_gap:    upper bound on the amount of time between two successive
  67  *             executions of PAUSE in a loop. Also indicate if ple enabled.
  68  *             According to test, this time is usually small than 41 cycles.
  69  * ple_window: upper bound on the amount of time a guest is allowed to execute
  70  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
  71  *             less than 2^12 cycles
  72  * Time is measured based on a counter that runs at the same rate as the TSC,
  73  * refer SDM volume 3b section 21.6.13 & 22.1.3.
  74  */
  75 #define KVM_VMX_DEFAULT_PLE_GAP    41
  76 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
  77 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
  78 module_param(ple_gap, int, S_IRUGO);
  79
  80 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
  81 module_param(ple_window, int, S_IRUGO);
  82
  83 struct vmcs {
  84         u32 revision_id;
  85         u32 abort;
  86         char data[0];
  87 };
  88
  89 struct vcpu_vmx {
  90         struct kvm_vcpu       vcpu;
  91         struct list_head      local_vcpus_link;
  92         unsigned long         host_rsp;
  93         int                   launched;
  94         u8                    fail;
  95         u32                   idt_vectoring_info;
  96         struct kvm_msr_entry *guest_msrs;
  97         struct kvm_msr_entry *host_msrs;
  98         int                   nmsrs;
  99         int                   save_nmsrs;
 100         int                   msr_offset_efer;
 101 #ifdef CONFIG_X86_64
 102         u64                   msr_host_kernel_gs_base;
 103         u64                   msr_guest_kernel_gs_base;
 104 #endif
 105         struct vmcs          *vmcs;
 106         struct {
 107                 int           loaded;
 108                 u16           fs_sel, gs_sel, ldt_sel;
 109                 int           gs_ldt_reload_needed;
 110                 int           fs_reload_needed;
 111                 int           guest_efer_loaded;
 112         } host_state;
 113         struct {
 114                 int vm86_active;
 115                 u8 save_iopl;
 116                 struct kvm_save_segment {
 117                         u16 selector;
 118                         unsigned long base;
 119                         u32 limit;
 120                         u32 ar;
 121                 } tr, es, ds, fs, gs;
 122                 struct {
 123                         bool pending;
 124                         u8 vector;
 125                         unsigned rip;
 126                 } irq;
 127         } rmode;
 128         int vpid;
 129         bool emulation_required;
 130
 131         /* Support for vnmi-less CPUs */
 132         int soft_vnmi_blocked;
 133         ktime_t entry_time;
 134         s64 vnmi_blocked_time;
 135         u32 exit_reason;
 136 };
 137
 138 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 139 {
 140         return container_of(vcpu, struct vcpu_vmx, vcpu);
 141 }
 142
 143 static int init_rmode(struct kvm *kvm);
 144 static u64 construct_eptp(unsigned long root_hpa);
 145
 146 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 147 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 148 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 149
 150 static unsigned long *vmx_io_bitmap_a;
 151 static unsigned long *vmx_io_bitmap_b;
 152 static unsigned long *vmx_msr_bitmap_legacy;
 153 static unsigned long *vmx_msr_bitmap_longmode;
 154
 155 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 156 static DEFINE_SPINLOCK(vmx_vpid_lock);
 157
 158 static struct vmcs_config {
 159         int size;
 160         int order;
 161         u32 revision_id;
 162         u32 pin_based_exec_ctrl;
 163         u32 cpu_based_exec_ctrl;
 164         u32 cpu_based_2nd_exec_ctrl;
 165         u32 vmexit_ctrl;
 166         u32 vmentry_ctrl;
 167 } vmcs_config;
 168
 169 static struct vmx_capability {
 170         u32 ept;
 171         u32 vpid;
 172 } vmx_capability;
 173
 174 #define VMX_SEGMENT_FIELD(seg)                                  \
 175         [VCPU_SREG_##seg] = {                                   \
 176                 .selector = GUEST_##seg##_SELECTOR,             \
 177                 .base = GUEST_##seg##_BASE,                     \
 178                 .limit = GUEST_##seg##_LIMIT,                   \
 179                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 180         }
 181
 182 static struct kvm_vmx_segment_field {
 183         unsigned selector;
 184         unsigned base;
 185         unsigned limit;
 186         unsigned ar_bytes;
 187 } kvm_vmx_segment_fields[] = {
 188         VMX_SEGMENT_FIELD(CS),
 189         VMX_SEGMENT_FIELD(DS),
 190         VMX_SEGMENT_FIELD(ES),
 191         VMX_SEGMENT_FIELD(FS),
 192         VMX_SEGMENT_FIELD(GS),
 193         VMX_SEGMENT_FIELD(SS),
 194         VMX_SEGMENT_FIELD(TR),
 195         VMX_SEGMENT_FIELD(LDTR),
 196 };
 197
 198 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 199
 200 /*
 201  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 202  * away by decrementing the array size.
 203  */
 204 static const u32 vmx_msr_index[] = {
 205 #ifdef CONFIG_X86_64
 206         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 207 #endif
 208         MSR_EFER, MSR_K6_STAR,
 209 };
 210 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 211
 212 static void load_msrs(struct kvm_msr_entry *e, int n)
 213 {
 214         int i;
 215
 216         for (i = 0; i < n; ++i)
 217                 wrmsrl(e[i].index, e[i].data);
 218 }
 219
 220 static void save_msrs(struct kvm_msr_entry *e, int n)
 221 {
 222         int i;
 223
 224         for (i = 0; i < n; ++i)
 225                 rdmsrl(e[i].index, e[i].data);
 226 }
 227
 228 static inline int is_page_fault(u32 intr_info)
 229 {
 230         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 231                              INTR_INFO_VALID_MASK)) ==
 232                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 233 }
 234
 235 static inline int is_no_device(u32 intr_info)
 236 {
 237         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 238                              INTR_INFO_VALID_MASK)) ==
 239                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 240 }
 241
 242 static inline int is_invalid_opcode(u32 intr_info)
 243 {
 244         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 245                              INTR_INFO_VALID_MASK)) ==
 246                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 247 }
 248
 249 static inline int is_external_interrupt(u32 intr_info)
 250 {
 251         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 252                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 253 }
 254
 255 static inline int is_machine_check(u32 intr_info)
 256 {
 257         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 258                              INTR_INFO_VALID_MASK)) ==
 259                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 260 }
 261
 262 static inline int cpu_has_vmx_msr_bitmap(void)
 263 {
 264         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 265 }
 266
 267 static inline int cpu_has_vmx_tpr_shadow(void)
 268 {
 269         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 270 }
 271
 272 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 273 {
 274         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 275 }
 276
 277 static inline int cpu_has_secondary_exec_ctrls(void)
 278 {
 279         return vmcs_config.cpu_based_exec_ctrl &
 280                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 281 }
 282
 283 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 284 {
 285         return vmcs_config.cpu_based_2nd_exec_ctrl &
 286                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 287 }
 288
 289 static inline bool cpu_has_vmx_flexpriority(void)
 290 {
 291         return cpu_has_vmx_tpr_shadow() &&
 292                 cpu_has_vmx_virtualize_apic_accesses();
 293 }
 294
 295 static inline bool cpu_has_vmx_ept_execute_only(void)
 296 {
 297         return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
 298 }
 299
 300 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 301 {
 302         return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
 303 }
 304
 305 static inline bool cpu_has_vmx_eptp_writeback(void)
 306 {
 307         return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
 308 }
 309
 310 static inline bool cpu_has_vmx_ept_2m_page(void)
 311 {
 312         return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
 313 }
 314
 315 static inline int cpu_has_vmx_invept_individual_addr(void)
 316 {
 317         return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
 318 }
 319
 320 static inline int cpu_has_vmx_invept_context(void)
 321 {
 322         return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
 323 }
 324
 325 static inline int cpu_has_vmx_invept_global(void)
 326 {
 327         return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
 328 }
 329
 330 static inline int cpu_has_vmx_ept(void)
 331 {
 332         return vmcs_config.cpu_based_2nd_exec_ctrl &
 333                 SECONDARY_EXEC_ENABLE_EPT;
 334 }
 335
 336 static inline int cpu_has_vmx_unrestricted_guest(void)
 337 {
 338         return vmcs_config.cpu_based_2nd_exec_ctrl &
 339                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 340 }
 341
 342 static inline int cpu_has_vmx_ple(void)
 343 {
 344         return vmcs_config.cpu_based_2nd_exec_ctrl &
 345                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 346 }
 347
 348 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 349 {
 350         return flexpriority_enabled &&
 351                 (cpu_has_vmx_virtualize_apic_accesses()) &&
 352                 (irqchip_in_kernel(kvm));
 353 }
 354
 355 static inline int cpu_has_vmx_vpid(void)
 356 {
 357         return vmcs_config.cpu_based_2nd_exec_ctrl &
 358                 SECONDARY_EXEC_ENABLE_VPID;
 359 }
 360
 361 static inline int cpu_has_virtual_nmis(void)
 362 {
 363         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 364 }
 365
 366 static inline bool report_flexpriority(void)
 367 {
 368         return flexpriority_enabled;
 369 }
 370
 371 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 372 {
 373         int i;
 374
 375         for (i = 0; i < vmx->nmsrs; ++i)
 376                 if (vmx->guest_msrs[i].index == msr)
 377                         return i;
 378         return -1;
 379 }
 380
 381 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 382 {
 383     struct {
 384         u64 vpid : 16;
 385         u64 rsvd : 48;
 386         u64 gva;
 387     } operand = { vpid, 0, gva };
 388
 389     asm volatile (__ex(ASM_VMX_INVVPID)
 390                   /* CF==1 or ZF==1 --> rc = -1 */
 391                   "; ja 1f ; ud2 ; 1:"
 392                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 393 }
 394
 395 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 396 {
 397         struct {
 398                 u64 eptp, gpa;
 399         } operand = {eptp, gpa};
 400
 401         asm volatile (__ex(ASM_VMX_INVEPT)
 402                         /* CF==1 or ZF==1 --> rc = -1 */
 403                         "; ja 1f ; ud2 ; 1:\n"
 404                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 405 }
 406
 407 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 408 {
 409         int i;
 410
 411         i = __find_msr_index(vmx, msr);
 412         if (i >= 0)
 413                 return &vmx->guest_msrs[i];
 414         return NULL;
 415 }
 416
 417 static void vmcs_clear(struct vmcs *vmcs)
 418 {
 419         u64 phys_addr = __pa(vmcs);
 420         u8 error;
 421
 422         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 423                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 424                       : "cc", "memory");
 425         if (error)
 426                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 427                        vmcs, phys_addr);
 428 }
 429
 430 static void __vcpu_clear(void *arg)
 431 {
 432         struct vcpu_vmx *vmx = arg;
 433         int cpu = raw_smp_processor_id();
 434
 435         if (vmx->vcpu.cpu == cpu)
 436                 vmcs_clear(vmx->vmcs);
 437         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 438                 per_cpu(current_vmcs, cpu) = NULL;
 439         rdtscll(vmx->vcpu.arch.host_tsc);
 440         list_del(&vmx->local_vcpus_link);
 441         vmx->vcpu.cpu = -1;
 442         vmx->launched = 0;
 443 }
 444
 445 static void vcpu_clear(struct vcpu_vmx *vmx)
 446 {
 447         if (vmx->vcpu.cpu == -1)
 448                 return;
 449         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 450 }
 451
 452 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 453 {
 454         if (vmx->vpid == 0)
 455                 return;
 456
 457         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 458 }
 459
 460 static inline void ept_sync_global(void)
 461 {
 462         if (cpu_has_vmx_invept_global())
 463                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 464 }
 465
 466 static inline void ept_sync_context(u64 eptp)
 467 {
 468         if (enable_ept) {
 469                 if (cpu_has_vmx_invept_context())
 470                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 471                 else
 472                         ept_sync_global();
 473         }
 474 }
 475
 476 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 477 {
 478         if (enable_ept) {
 479                 if (cpu_has_vmx_invept_individual_addr())
 480                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 481                                         eptp, gpa);
 482                 else
 483                         ept_sync_context(eptp);
 484         }
 485 }
 486
 487 static unsigned long vmcs_readl(unsigned long field)
 488 {
 489         unsigned long value;
 490
 491         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 492                       : "=a"(value) : "d"(field) : "cc");
 493         return value;
 494 }
 495
 496 static u16 vmcs_read16(unsigned long field)
 497 {
 498         return vmcs_readl(field);
 499 }
 500
 501 static u32 vmcs_read32(unsigned long field)
 502 {
 503         return vmcs_readl(field);
 504 }
 505
 506 static u64 vmcs_read64(unsigned long field)
 507 {
 508 #ifdef CONFIG_X86_64
 509         return vmcs_readl(field);
 510 #else
 511         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 512 #endif
 513 }
 514
 515 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 516 {
 517         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 518                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 519         dump_stack();
 520 }
 521
 522 static void vmcs_writel(unsigned long field, unsigned long value)
 523 {
 524         u8 error;
 525
 526         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 527                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 528         if (unlikely(error))
 529                 vmwrite_error(field, value);
 530 }
 531
 532 static void vmcs_write16(unsigned long field, u16 value)
 533 {
 534         vmcs_writel(field, value);
 535 }
 536
 537 static void vmcs_write32(unsigned long field, u32 value)
 538 {
 539         vmcs_writel(field, value);
 540 }
 541
 542 static void vmcs_write64(unsigned long field, u64 value)
 543 {
 544         vmcs_writel(field, value);
 545 #ifndef CONFIG_X86_64
 546         asm volatile ("");
 547         vmcs_writel(field+1, value >> 32);
 548 #endif
 549 }
 550
 551 static void vmcs_clear_bits(unsigned long field, u32 mask)
 552 {
 553         vmcs_writel(field, vmcs_readl(field) & ~mask);
 554 }
 555
 556 static void vmcs_set_bits(unsigned long field, u32 mask)
 557 {
 558         vmcs_writel(field, vmcs_readl(field) | mask);
 559 }
 560
 561 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 562 {
 563         u32 eb;
 564
 565         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
 566         if (!vcpu->fpu_active)
 567                 eb |= 1u << NM_VECTOR;
 568         /*
 569          * Unconditionally intercept #DB so we can maintain dr6 without
 570          * reading it every exit.
 571          */
 572         eb |= 1u << DB_VECTOR;
 573         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
 574                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
 575                         eb |= 1u << BP_VECTOR;
 576         }
 577         if (to_vmx(vcpu)->rmode.vm86_active)
 578                 eb = ~0;
 579         if (enable_ept)
 580                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 581         vmcs_write32(EXCEPTION_BITMAP, eb);
 582 }
 583
 584 static void reload_tss(void)
 585 {
 586         /*
 587          * VT restores TR but not its size.  Useless.
 588          */
 589         struct descriptor_table gdt;
 590         struct desc_struct *descs;
 591
 592         kvm_get_gdt(&gdt);
 593         descs = (void *)gdt.base;
 594         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 595         load_TR_desc();
 596 }
 597
 598 static void load_transition_efer(struct vcpu_vmx *vmx)
 599 {
 600         int efer_offset = vmx->msr_offset_efer;
 601         u64 host_efer;
 602         u64 guest_efer;
 603         u64 ignore_bits;
 604
 605         if (efer_offset < 0)
 606                 return;
 607         host_efer = vmx->host_msrs[efer_offset].data;
 608         guest_efer = vmx->guest_msrs[efer_offset].data;
 609
 610         /*
 611          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 612          * outside long mode
 613          */
 614         ignore_bits = EFER_NX | EFER_SCE;
 615 #ifdef CONFIG_X86_64
 616         ignore_bits |= EFER_LMA | EFER_LME;
 617         /* SCE is meaningful only in long mode on Intel */
 618         if (guest_efer & EFER_LMA)
 619                 ignore_bits &= ~(u64)EFER_SCE;
 620 #endif
 621         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
 622                 return;
 623
 624         vmx->host_state.guest_efer_loaded = 1;
 625         guest_efer &= ~ignore_bits;
 626         guest_efer |= host_efer & ignore_bits;
 627         wrmsrl(MSR_EFER, guest_efer);
 628         vmx->vcpu.stat.efer_reload++;
 629 }
 630
 631 static void reload_host_efer(struct vcpu_vmx *vmx)
 632 {
 633         if (vmx->host_state.guest_efer_loaded) {
 634                 vmx->host_state.guest_efer_loaded = 0;
 635                 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
 636         }
 637 }
 638
 639 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 640 {
 641         struct vcpu_vmx *vmx = to_vmx(vcpu);
 642
 643         if (vmx->host_state.loaded)
 644                 return;
 645
 646         vmx->host_state.loaded = 1;
 647         /*
 648          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 649          * allow segment selectors with cpl > 0 or ti == 1.
 650          */
 651         vmx->host_state.ldt_sel = kvm_read_ldt();
 652         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 653         vmx->host_state.fs_sel = kvm_read_fs();
 654         if (!(vmx->host_state.fs_sel & 7)) {
 655                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 656                 vmx->host_state.fs_reload_needed = 0;
 657         } else {
 658                 vmcs_write16(HOST_FS_SELECTOR, 0);
 659                 vmx->host_state.fs_reload_needed = 1;
 660         }
 661         vmx->host_state.gs_sel = kvm_read_gs();
 662         if (!(vmx->host_state.gs_sel & 7))
 663                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 664         else {
 665                 vmcs_write16(HOST_GS_SELECTOR, 0);
 666                 vmx->host_state.gs_ldt_reload_needed = 1;
 667         }
 668
 669 #ifdef CONFIG_X86_64
 670         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 671         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 672 #else
 673         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 674         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 675 #endif
 676
 677 #ifdef CONFIG_X86_64
 678         if (is_long_mode(&vmx->vcpu)) {
 679                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 680                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 681         }
 682 #endif
 683         load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 684         load_transition_efer(vmx);
 685 }
 686
 687 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 688 {
 689         unsigned long flags;
 690
 691         if (!vmx->host_state.loaded)
 692                 return;
 693
 694         ++vmx->vcpu.stat.host_state_reload;
 695         vmx->host_state.loaded = 0;
 696         if (vmx->host_state.fs_reload_needed)
 697                 kvm_load_fs(vmx->host_state.fs_sel);
 698         if (vmx->host_state.gs_ldt_reload_needed) {
 699                 kvm_load_ldt(vmx->host_state.ldt_sel);
 700                 /*
 701                  * If we have to reload gs, we must take care to
 702                  * preserve our gs base.
 703                  */
 704                 local_irq_save(flags);
 705                 kvm_load_gs(vmx->host_state.gs_sel);
 706 #ifdef CONFIG_X86_64
 707                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 708 #endif
 709                 local_irq_restore(flags);
 710         }
 711         reload_tss();
 712         save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 713         load_msrs(vmx->host_msrs, vmx->save_nmsrs);
 714         reload_host_efer(vmx);
 715 #ifdef CONFIG_X86_64
 716         if (is_long_mode(&vmx->vcpu)) {
 717                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 718                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 719         }
 720 #endif
 721 }
 722
 723 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 724 {
 725         preempt_disable();
 726         __vmx_load_host_state(vmx);
 727         preempt_enable();
 728 }
 729
 730 /*
 731  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 732  * vcpu mutex is already taken.
 733  */
 734 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 735 {
 736         struct vcpu_vmx *vmx = to_vmx(vcpu);
 737         u64 phys_addr = __pa(vmx->vmcs);
 738         u64 tsc_this, delta, new_offset;
 739
 740         if (vcpu->cpu != cpu) {
 741                 vcpu_clear(vmx);
 742                 kvm_migrate_timers(vcpu);
 743                 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
 744                 local_irq_disable();
 745                 list_add(&vmx->local_vcpus_link,
 746                          &per_cpu(vcpus_on_cpu, cpu));
 747                 local_irq_enable();
 748         }
 749
 750         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 751                 u8 error;
 752
 753                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 754                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 755                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 756                               : "cc");
 757                 if (error)
 758                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 759                                vmx->vmcs, phys_addr);
 760         }
 761
 762         if (vcpu->cpu != cpu) {
 763                 struct descriptor_table dt;
 764                 unsigned long sysenter_esp;
 765
 766                 vcpu->cpu = cpu;
 767                 /*
 768                  * Linux uses per-cpu TSS and GDT, so set these when switching
 769                  * processors.
 770                  */
 771                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 772                 kvm_get_gdt(&dt);
 773                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 774
 775                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 776                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 777
 778                 /*
 779                  * Make sure the time stamp counter is monotonous.
 780                  */
 781                 rdtscll(tsc_this);
 782                 if (tsc_this < vcpu->arch.host_tsc) {
 783                         delta = vcpu->arch.host_tsc - tsc_this;
 784                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 785                         vmcs_write64(TSC_OFFSET, new_offset);
 786                 }
 787         }
 788 }
 789
 790 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 791 {
 792         __vmx_load_host_state(to_vmx(vcpu));
 793 }
 794
 795 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 796 {
 797         if (vcpu->fpu_active)
 798                 return;
 799         vcpu->fpu_active = 1;
 800         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 801         if (vcpu->arch.cr0 & X86_CR0_TS)
 802                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 803         update_exception_bitmap(vcpu);
 804 }
 805
 806 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 807 {
 808         if (!vcpu->fpu_active)
 809                 return;
 810         vcpu->fpu_active = 0;
 811         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 812         update_exception_bitmap(vcpu);
 813 }
 814
 815 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 816 {
 817         unsigned long rflags;
 818
 819         rflags = vmcs_readl(GUEST_RFLAGS);
 820         if (to_vmx(vcpu)->rmode.vm86_active)
 821                 rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
 822         return rflags;
 823 }
 824
 825 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 826 {
 827         if (to_vmx(vcpu)->rmode.vm86_active)
 828                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 829         vmcs_writel(GUEST_RFLAGS, rflags);
 830 }
 831
 832 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 833 {
 834         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 835         int ret = 0;
 836
 837         if (interruptibility & GUEST_INTR_STATE_STI)
 838                 ret |= X86_SHADOW_INT_STI;
 839         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
 840                 ret |= X86_SHADOW_INT_MOV_SS;
 841
 842         return ret & mask;
 843 }
 844
 845 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 846 {
 847         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 848         u32 interruptibility = interruptibility_old;
 849
 850         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
 851
 852         if (mask & X86_SHADOW_INT_MOV_SS)
 853                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
 854         if (mask & X86_SHADOW_INT_STI)
 855                 interruptibility |= GUEST_INTR_STATE_STI;
 856
 857         if ((interruptibility != interruptibility_old))
 858                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
 859 }
 860
 861 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 862 {
 863         unsigned long rip;
 864
 865         rip = kvm_rip_read(vcpu);
 866         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 867         kvm_rip_write(vcpu, rip);
 868
 869         /* skipping an emulated instruction also counts */
 870         vmx_set_interrupt_shadow(vcpu, 0);
 871 }
 872
 873 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 874                                 bool has_error_code, u32 error_code)
 875 {
 876         struct vcpu_vmx *vmx = to_vmx(vcpu);
 877         u32 intr_info = nr | INTR_INFO_VALID_MASK;
 878
 879         if (has_error_code) {
 880                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 881                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
 882         }
 883
 884         if (vmx->rmode.vm86_active) {
 885                 vmx->rmode.irq.pending = true;
 886                 vmx->rmode.irq.vector = nr;
 887                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
 888                 if (kvm_exception_is_soft(nr))
 889                         vmx->rmode.irq.rip +=
 890                                 vmx->vcpu.arch.event_exit_inst_len;
 891                 intr_info |= INTR_TYPE_SOFT_INTR;
 892                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 893                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
 894                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
 895                 return;
 896         }
 897
 898         if (kvm_exception_is_soft(nr)) {
 899                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
 900                              vmx->vcpu.arch.event_exit_inst_len);
 901                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
 902         } else
 903                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
 904
 905         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 906 }
 907
 908 /*
 909  * Swap MSR entry in host/guest MSR entry array.
 910  */
 911 #ifdef CONFIG_X86_64
 912 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 913 {
 914         struct kvm_msr_entry tmp;
 915
 916         tmp = vmx->guest_msrs[to];
 917         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 918         vmx->guest_msrs[from] = tmp;
 919         tmp = vmx->host_msrs[to];
 920         vmx->host_msrs[to] = vmx->host_msrs[from];
 921         vmx->host_msrs[from] = tmp;
 922 }
 923 #endif
 924
 925 /*
 926  * Set up the vmcs to automatically save and restore system
 927  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 928  * mode, as fiddling with msrs is very expensive.
 929  */
 930 static void setup_msrs(struct vcpu_vmx *vmx)
 931 {
 932         int save_nmsrs;
 933         unsigned long *msr_bitmap;
 934
 935         vmx_load_host_state(vmx);
 936         save_nmsrs = 0;
 937 #ifdef CONFIG_X86_64
 938         if (is_long_mode(&vmx->vcpu)) {
 939                 int index;
 940
 941                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 942                 if (index >= 0)
 943                         move_msr_up(vmx, index, save_nmsrs++);
 944                 index = __find_msr_index(vmx, MSR_LSTAR);
 945                 if (index >= 0)
 946                         move_msr_up(vmx, index, save_nmsrs++);
 947                 index = __find_msr_index(vmx, MSR_CSTAR);
 948                 if (index >= 0)
 949                         move_msr_up(vmx, index, save_nmsrs++);
 950                 /*
 951                  * MSR_K6_STAR is only needed on long mode guests, and only
 952                  * if efer.sce is enabled.
 953                  */
 954                 index = __find_msr_index(vmx, MSR_K6_STAR);
 955                 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
 956                         move_msr_up(vmx, index, save_nmsrs++);
 957         }
 958 #endif
 959         vmx->save_nmsrs = save_nmsrs;
 960
 961         vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
 962
 963         if (cpu_has_vmx_msr_bitmap()) {
 964                 if (is_long_mode(&vmx->vcpu))
 965                         msr_bitmap = vmx_msr_bitmap_longmode;
 966                 else
 967                         msr_bitmap = vmx_msr_bitmap_legacy;
 968
 969                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
 970         }
 971 }
 972
 973 /*
 974  * reads and returns guest's timestamp counter "register"
 975  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 976  */
 977 static u64 guest_read_tsc(void)
 978 {
 979         u64 host_tsc, tsc_offset;
 980
 981         rdtscll(host_tsc);
 982         tsc_offset = vmcs_read64(TSC_OFFSET);
 983         return host_tsc + tsc_offset;
 984 }
 985
 986 /*
 987  * writes 'guest_tsc' into guest's timestamp counter "register"
 988  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 989  */
 990 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
 991 {
 992         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 993 }
 994
 995 /*
 996  * Reads an msr value (of 'msr_index') into 'pdata'.
 997  * Returns 0 on success, non-0 otherwise.
 998  * Assumes vcpu_load() was already called.
 999  */
1000 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1001 {
1002         u64 data;
1003         struct kvm_msr_entry *msr;
1004
1005         if (!pdata) {
1006                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1007                 return -EINVAL;
1008         }
1009
1010         switch (msr_index) {
1011 #ifdef CONFIG_X86_64
1012         case MSR_FS_BASE:
1013                 data = vmcs_readl(GUEST_FS_BASE);
1014                 break;
1015         case MSR_GS_BASE:
1016                 data = vmcs_readl(GUEST_GS_BASE);
1017                 break;
1018         case MSR_KERNEL_GS_BASE:
1019                 vmx_load_host_state(to_vmx(vcpu));
1020                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1021                 break;
1022         case MSR_EFER:
1023                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1024 #endif
1025         case MSR_IA32_TSC:
1026                 data = guest_read_tsc();
1027                 break;
1028         case MSR_IA32_SYSENTER_CS:
1029                 data = vmcs_read32(GUEST_SYSENTER_CS);
1030                 break;
1031         case MSR_IA32_SYSENTER_EIP:
1032                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1033                 break;
1034         case MSR_IA32_SYSENTER_ESP:
1035                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1036                 break;
1037         default:
1038                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1039                 if (msr) {
1040                         vmx_load_host_state(to_vmx(vcpu));
1041                         data = msr->data;
1042                         break;
1043                 }
1044                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1045         }
1046
1047         *pdata = data;
1048         return 0;
1049 }
1050
1051 /*
1052  * Writes msr value into into the appropriate "register".
1053  * Returns 0 on success, non-0 otherwise.
1054  * Assumes vcpu_load() was already called.
1055  */
1056 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1057 {
1058         struct vcpu_vmx *vmx = to_vmx(vcpu);
1059         struct kvm_msr_entry *msr;
1060         u64 host_tsc;
1061         int ret = 0;
1062
1063         switch (msr_index) {
1064         case MSR_EFER:
1065                 vmx_load_host_state(vmx);
1066                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1067                 break;
1068 #ifdef CONFIG_X86_64
1069         case MSR_FS_BASE:
1070                 vmcs_writel(GUEST_FS_BASE, data);
1071                 break;
1072         case MSR_GS_BASE:
1073                 vmcs_writel(GUEST_GS_BASE, data);
1074                 break;
1075         case MSR_KERNEL_GS_BASE:
1076                 vmx_load_host_state(vmx);
1077                 vmx->msr_guest_kernel_gs_base = data;
1078                 break;
1079 #endif
1080         case MSR_IA32_SYSENTER_CS:
1081                 vmcs_write32(GUEST_SYSENTER_CS, data);
1082                 break;
1083         case MSR_IA32_SYSENTER_EIP:
1084                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1085                 break;
1086         case MSR_IA32_SYSENTER_ESP:
1087                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1088                 break;
1089         case MSR_IA32_TSC:
1090                 rdtscll(host_tsc);
1091                 guest_write_tsc(data, host_tsc);
1092                 break;
1093         case MSR_IA32_CR_PAT:
1094                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1095                         vmcs_write64(GUEST_IA32_PAT, data);
1096                         vcpu->arch.pat = data;
1097                         break;
1098                 }
1099                 /* Otherwise falls through to kvm_set_msr_common */
1100         default:
1101                 msr = find_msr_entry(vmx, msr_index);
1102                 if (msr) {
1103                         vmx_load_host_state(vmx);
1104                         msr->data = data;
1105                         break;
1106                 }
1107                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1108         }
1109
1110         return ret;
1111 }
1112
1113 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1114 {
1115         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1116         switch (reg) {
1117         case VCPU_REGS_RSP:
1118                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1119                 break;
1120         case VCPU_REGS_RIP:
1121                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1122                 break;
1123         case VCPU_EXREG_PDPTR:
1124                 if (enable_ept)
1125                         ept_save_pdptrs(vcpu);
1126                 break;
1127         default:
1128                 break;
1129         }
1130 }
1131
1132 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1133 {
1134         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1135                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1136         else
1137                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1138
1139         update_exception_bitmap(vcpu);
1140 }
1141
1142 static __init int cpu_has_kvm_support(void)
1143 {
1144         return cpu_has_vmx();
1145 }
1146
1147 static __init int vmx_disabled_by_bios(void)
1148 {
1149         u64 msr;
1150
1151         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1152         return (msr & (FEATURE_CONTROL_LOCKED |
1153                        FEATURE_CONTROL_VMXON_ENABLED))
1154             == FEATURE_CONTROL_LOCKED;
1155         /* locked but not enabled */
1156 }
1157
1158 static int hardware_enable(void *garbage)
1159 {
1160         int cpu = raw_smp_processor_id();
1161         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1162         u64 old;
1163
1164         if (read_cr4() & X86_CR4_VMXE)
1165                 return -EBUSY;
1166
1167         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1168         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1169         if ((old & (FEATURE_CONTROL_LOCKED |
1170                     FEATURE_CONTROL_VMXON_ENABLED))
1171             != (FEATURE_CONTROL_LOCKED |
1172                 FEATURE_CONTROL_VMXON_ENABLED))
1173                 /* enable and lock */
1174                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1175                        FEATURE_CONTROL_LOCKED |
1176                        FEATURE_CONTROL_VMXON_ENABLED);
1177         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1178         asm volatile (ASM_VMX_VMXON_RAX
1179                       : : "a"(&phys_addr), "m"(phys_addr)
1180                       : "memory", "cc");
1181
1182         ept_sync_global();
1183
1184         return 0;
1185 }
1186
1187 static void vmclear_local_vcpus(void)
1188 {
1189         int cpu = raw_smp_processor_id();
1190         struct vcpu_vmx *vmx, *n;
1191
1192         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1193                                  local_vcpus_link)
1194                 __vcpu_clear(vmx);
1195 }
1196
1197
1198 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1199  * tricks.
1200  */
1201 static void kvm_cpu_vmxoff(void)
1202 {
1203         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1204         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1205 }
1206
1207 static void hardware_disable(void *garbage)
1208 {
1209         vmclear_local_vcpus();
1210         kvm_cpu_vmxoff();
1211 }
1212
1213 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1214                                       u32 msr, u32 *result)
1215 {
1216         u32 vmx_msr_low, vmx_msr_high;
1217         u32 ctl = ctl_min | ctl_opt;
1218
1219         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1220
1221         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1222         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1223
1224         /* Ensure minimum (required) set of control bits are supported. */
1225         if (ctl_min & ~ctl)
1226                 return -EIO;
1227
1228         *result = ctl;
1229         return 0;
1230 }
1231
1232 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1233 {
1234         u32 vmx_msr_low, vmx_msr_high;
1235         u32 min, opt, min2, opt2;
1236         u32 _pin_based_exec_control = 0;
1237         u32 _cpu_based_exec_control = 0;
1238         u32 _cpu_based_2nd_exec_control = 0;
1239         u32 _vmexit_control = 0;
1240         u32 _vmentry_control = 0;
1241
1242         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1243         opt = PIN_BASED_VIRTUAL_NMIS;
1244         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1245                                 &_pin_based_exec_control) < 0)
1246                 return -EIO;
1247
1248         min = CPU_BASED_HLT_EXITING |
1249 #ifdef CONFIG_X86_64
1250               CPU_BASED_CR8_LOAD_EXITING |
1251               CPU_BASED_CR8_STORE_EXITING |
1252 #endif
1253               CPU_BASED_CR3_LOAD_EXITING |
1254               CPU_BASED_CR3_STORE_EXITING |
1255               CPU_BASED_USE_IO_BITMAPS |
1256               CPU_BASED_MOV_DR_EXITING |
1257               CPU_BASED_USE_TSC_OFFSETING |
1258               CPU_BASED_INVLPG_EXITING;
1259         opt = CPU_BASED_TPR_SHADOW |
1260               CPU_BASED_USE_MSR_BITMAPS |
1261               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1262         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1263                                 &_cpu_based_exec_control) < 0)
1264                 return -EIO;
1265 #ifdef CONFIG_X86_64
1266         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1267                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1268                                            ~CPU_BASED_CR8_STORE_EXITING;
1269 #endif
1270         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1271                 min2 = 0;
1272                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1273                         SECONDARY_EXEC_WBINVD_EXITING |
1274                         SECONDARY_EXEC_ENABLE_VPID |
1275                         SECONDARY_EXEC_ENABLE_EPT |
1276                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
1277                         SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1278                 if (adjust_vmx_controls(min2, opt2,
1279                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1280                                         &_cpu_based_2nd_exec_control) < 0)
1281                         return -EIO;
1282         }
1283 #ifndef CONFIG_X86_64
1284         if (!(_cpu_based_2nd_exec_control &
1285                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1286                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1287 #endif
1288         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1289                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1290                    enabled */
1291                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1292                                              CPU_BASED_CR3_STORE_EXITING |
1293                                              CPU_BASED_INVLPG_EXITING);
1294                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1295                       vmx_capability.ept, vmx_capability.vpid);
1296         }
1297
1298         min = 0;
1299 #ifdef CONFIG_X86_64
1300         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1301 #endif
1302         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1303         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1304                                 &_vmexit_control) < 0)
1305                 return -EIO;
1306
1307         min = 0;
1308         opt = VM_ENTRY_LOAD_IA32_PAT;
1309         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1310                                 &_vmentry_control) < 0)
1311                 return -EIO;
1312
1313         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1314
1315         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1316         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1317                 return -EIO;
1318
1319 #ifdef CONFIG_X86_64
1320         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1321         if (vmx_msr_high & (1u<<16))
1322                 return -EIO;
1323 #endif
1324
1325         /* Require Write-Back (WB) memory type for VMCS accesses. */
1326         if (((vmx_msr_high >> 18) & 15) != 6)
1327                 return -EIO;
1328
1329         vmcs_conf->size = vmx_msr_high & 0x1fff;
1330         vmcs_conf->order = get_order(vmcs_config.size);
1331         vmcs_conf->revision_id = vmx_msr_low;
1332
1333         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1334         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1335         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1336         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1337         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1338
1339         return 0;
1340 }
1341
1342 static struct vmcs *alloc_vmcs_cpu(int cpu)
1343 {
1344         int node = cpu_to_node(cpu);
1345         struct page *pages;
1346         struct vmcs *vmcs;
1347
1348         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1349         if (!pages)
1350                 return NULL;
1351         vmcs = page_address(pages);
1352         memset(vmcs, 0, vmcs_config.size);
1353         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1354         return vmcs;
1355 }
1356
1357 static struct vmcs *alloc_vmcs(void)
1358 {
1359         return alloc_vmcs_cpu(raw_smp_processor_id());
1360 }
1361
1362 static void free_vmcs(struct vmcs *vmcs)
1363 {
1364         free_pages((unsigned long)vmcs, vmcs_config.order);
1365 }
1366
1367 static void free_kvm_area(void)
1368 {
1369         int cpu;
1370
1371         for_each_possible_cpu(cpu) {
1372                 free_vmcs(per_cpu(vmxarea, cpu));
1373                 per_cpu(vmxarea, cpu) = NULL;
1374         }
1375 }
1376
1377 static __init int alloc_kvm_area(void)
1378 {
1379         int cpu;
1380
1381         for_each_possible_cpu(cpu) {
1382                 struct vmcs *vmcs;
1383
1384                 vmcs = alloc_vmcs_cpu(cpu);
1385                 if (!vmcs) {
1386                         free_kvm_area();
1387                         return -ENOMEM;
1388                 }
1389
1390                 per_cpu(vmxarea, cpu) = vmcs;
1391         }
1392         return 0;
1393 }
1394
1395 static __init int hardware_setup(void)
1396 {
1397         if (setup_vmcs_config(&vmcs_config) < 0)
1398                 return -EIO;
1399
1400         if (boot_cpu_has(X86_FEATURE_NX))
1401                 kvm_enable_efer_bits(EFER_NX);
1402
1403         if (!cpu_has_vmx_vpid())
1404                 enable_vpid = 0;
1405
1406         if (!cpu_has_vmx_ept()) {
1407                 enable_ept = 0;
1408                 enable_unrestricted_guest = 0;
1409         }
1410
1411         if (!cpu_has_vmx_unrestricted_guest())
1412                 enable_unrestricted_guest = 0;
1413
1414         if (!cpu_has_vmx_flexpriority())
1415                 flexpriority_enabled = 0;
1416
1417         if (!cpu_has_vmx_tpr_shadow())
1418                 kvm_x86_ops->update_cr8_intercept = NULL;
1419
1420         if (enable_ept && !cpu_has_vmx_ept_2m_page())
1421                 kvm_disable_largepages();
1422
1423         if (!cpu_has_vmx_ple())
1424                 ple_gap = 0;
1425
1426         return alloc_kvm_area();
1427 }
1428
1429 static __exit void hardware_unsetup(void)
1430 {
1431         free_kvm_area();
1432 }
1433
1434 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1435 {
1436         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1437
1438         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1439                 vmcs_write16(sf->selector, save->selector);
1440                 vmcs_writel(sf->base, save->base);
1441                 vmcs_write32(sf->limit, save->limit);
1442                 vmcs_write32(sf->ar_bytes, save->ar);
1443         } else {
1444                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1445                         << AR_DPL_SHIFT;
1446                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1447         }
1448 }
1449
1450 static void enter_pmode(struct kvm_vcpu *vcpu)
1451 {
1452         unsigned long flags;
1453         struct vcpu_vmx *vmx = to_vmx(vcpu);
1454
1455         vmx->emulation_required = 1;
1456         vmx->rmode.vm86_active = 0;
1457
1458         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1459         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1460         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1461
1462         flags = vmcs_readl(GUEST_RFLAGS);
1463         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1464         flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
1465         vmcs_writel(GUEST_RFLAGS, flags);
1466
1467         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1468                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1469
1470         update_exception_bitmap(vcpu);
1471
1472         if (emulate_invalid_guest_state)
1473                 return;
1474
1475         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1476         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1477         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1478         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1479
1480         vmcs_write16(GUEST_SS_SELECTOR, 0);
1481         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1482
1483         vmcs_write16(GUEST_CS_SELECTOR,
1484                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1485         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1486 }
1487
1488 static gva_t rmode_tss_base(struct kvm *kvm)
1489 {
1490         if (!kvm->arch.tss_addr) {
1491                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1492                                  kvm->memslots[0].npages - 3;
1493                 return base_gfn << PAGE_SHIFT;
1494         }
1495         return kvm->arch.tss_addr;
1496 }
1497
1498 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1499 {
1500         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1501
1502         save->selector = vmcs_read16(sf->selector);
1503         save->base = vmcs_readl(sf->base);
1504         save->limit = vmcs_read32(sf->limit);
1505         save->ar = vmcs_read32(sf->ar_bytes);
1506         vmcs_write16(sf->selector, save->base >> 4);
1507         vmcs_write32(sf->base, save->base & 0xfffff);
1508         vmcs_write32(sf->limit, 0xffff);
1509         vmcs_write32(sf->ar_bytes, 0xf3);
1510 }
1511
1512 static void enter_rmode(struct kvm_vcpu *vcpu)
1513 {
1514         unsigned long flags;
1515         struct vcpu_vmx *vmx = to_vmx(vcpu);
1516
1517         if (enable_unrestricted_guest)
1518                 return;
1519
1520         vmx->emulation_required = 1;
1521         vmx->rmode.vm86_active = 1;
1522
1523         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1524         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1525
1526         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1527         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1528
1529         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1530         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1531
1532         flags = vmcs_readl(GUEST_RFLAGS);
1533         vmx->rmode.save_iopl
1534                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1535
1536         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1537
1538         vmcs_writel(GUEST_RFLAGS, flags);
1539         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1540         update_exception_bitmap(vcpu);
1541
1542         if (emulate_invalid_guest_state)
1543                 goto continue_rmode;
1544
1545         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1546         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1547         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1548
1549         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1550         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1551         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1552                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1553         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1554
1555         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1556         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1557         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1558         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1559
1560 continue_rmode:
1561         kvm_mmu_reset_context(vcpu);
1562         init_rmode(vcpu->kvm);
1563 }
1564
1565 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1566 {
1567         struct vcpu_vmx *vmx = to_vmx(vcpu);
1568         struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1569
1570         /*
1571          * Force kernel_gs_base reloading before EFER changes, as control
1572          * of this msr depends on is_long_mode().
1573          */
1574         vmx_load_host_state(to_vmx(vcpu));
1575         vcpu->arch.shadow_efer = efer;
1576         if (!msr)
1577                 return;
1578         if (efer & EFER_LMA) {
1579                 vmcs_write32(VM_ENTRY_CONTROLS,
1580                              vmcs_read32(VM_ENTRY_CONTROLS) |
1581                              VM_ENTRY_IA32E_MODE);
1582                 msr->data = efer;
1583         } else {
1584                 vmcs_write32(VM_ENTRY_CONTROLS,
1585                              vmcs_read32(VM_ENTRY_CONTROLS) &
1586                              ~VM_ENTRY_IA32E_MODE);
1587
1588                 msr->data = efer & ~EFER_LME;
1589         }
1590         setup_msrs(vmx);
1591 }
1592
1593 #ifdef CONFIG_X86_64
1594
1595 static void enter_lmode(struct kvm_vcpu *vcpu)
1596 {
1597         u32 guest_tr_ar;
1598
1599         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1600         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1601                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1602                        __func__);
1603                 vmcs_write32(GUEST_TR_AR_BYTES,
1604                              (guest_tr_ar & ~AR_TYPE_MASK)
1605                              | AR_TYPE_BUSY_64_TSS);
1606         }
1607         vcpu->arch.shadow_efer |= EFER_LMA;
1608         vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
1609 }
1610
1611 static void exit_lmode(struct kvm_vcpu *vcpu)
1612 {
1613         vcpu->arch.shadow_efer &= ~EFER_LMA;
1614
1615         vmcs_write32(VM_ENTRY_CONTROLS,
1616                      vmcs_read32(VM_ENTRY_CONTROLS)
1617                      & ~VM_ENTRY_IA32E_MODE);
1618 }
1619
1620 #endif
1621
1622 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1623 {
1624         vpid_sync_vcpu_all(to_vmx(vcpu));
1625         if (enable_ept)
1626                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1627 }
1628
1629 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1630 {
1631         vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1632         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1633 }
1634
1635 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1636 {
1637         if (!test_bit(VCPU_EXREG_PDPTR,
1638                       (unsigned long *)&vcpu->arch.regs_dirty))
1639                 return;
1640
1641         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1642                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1643                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1644                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1645                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1646         }
1647 }
1648
1649 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1650 {
1651         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1652                 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1653                 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1654                 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1655                 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1656         }
1657
1658         __set_bit(VCPU_EXREG_PDPTR,
1659                   (unsigned long *)&vcpu->arch.regs_avail);
1660         __set_bit(VCPU_EXREG_PDPTR,
1661                   (unsigned long *)&vcpu->arch.regs_dirty);
1662 }
1663
1664 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1665
1666 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1667                                         unsigned long cr0,
1668                                         struct kvm_vcpu *vcpu)
1669 {
1670         if (!(cr0 & X86_CR0_PG)) {
1671                 /* From paging/starting to nonpaging */
1672                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1673                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1674                              (CPU_BASED_CR3_LOAD_EXITING |
1675                               CPU_BASED_CR3_STORE_EXITING));
1676                 vcpu->arch.cr0 = cr0;
1677                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1678         } else if (!is_paging(vcpu)) {
1679                 /* From nonpaging to paging */
1680                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1681                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1682                              ~(CPU_BASED_CR3_LOAD_EXITING |
1683                                CPU_BASED_CR3_STORE_EXITING));
1684                 vcpu->arch.cr0 = cr0;
1685                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1686         }
1687
1688         if (!(cr0 & X86_CR0_WP))
1689                 *hw_cr0 &= ~X86_CR0_WP;
1690 }
1691
1692 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1693                                         struct kvm_vcpu *vcpu)
1694 {
1695         if (!is_paging(vcpu)) {
1696                 *hw_cr4 &= ~X86_CR4_PAE;
1697                 *hw_cr4 |= X86_CR4_PSE;
1698         } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1699                 *hw_cr4 &= ~X86_CR4_PAE;
1700 }
1701
1702 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1703 {
1704         struct vcpu_vmx *vmx = to_vmx(vcpu);
1705         unsigned long hw_cr0;
1706
1707         if (enable_unrestricted_guest)
1708                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1709                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1710         else
1711                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1712
1713         vmx_fpu_deactivate(vcpu);
1714
1715         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1716                 enter_pmode(vcpu);
1717
1718         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1719                 enter_rmode(vcpu);
1720
1721 #ifdef CONFIG_X86_64
1722         if (vcpu->arch.shadow_efer & EFER_LME) {
1723                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1724                         enter_lmode(vcpu);
1725                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1726                         exit_lmode(vcpu);
1727         }
1728 #endif
1729
1730         if (enable_ept)
1731                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1732
1733         vmcs_writel(CR0_READ_SHADOW, cr0);
1734         vmcs_writel(GUEST_CR0, hw_cr0);
1735         vcpu->arch.cr0 = cr0;
1736
1737         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1738                 vmx_fpu_activate(vcpu);
1739 }
1740
1741 static u64 construct_eptp(unsigned long root_hpa)
1742 {
1743         u64 eptp;
1744
1745         /* TODO write the value reading from MSR */
1746         eptp = VMX_EPT_DEFAULT_MT |
1747                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1748         eptp |= (root_hpa & PAGE_MASK);
1749
1750         return eptp;
1751 }
1752
1753 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1754 {
1755         unsigned long guest_cr3;
1756         u64 eptp;
1757
1758         guest_cr3 = cr3;
1759         if (enable_ept) {
1760                 eptp = construct_eptp(cr3);
1761                 vmcs_write64(EPT_POINTER, eptp);
1762                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1763                         vcpu->kvm->arch.ept_identity_map_addr;
1764         }
1765
1766         vmx_flush_tlb(vcpu);
1767         vmcs_writel(GUEST_CR3, guest_cr3);
1768         if (vcpu->arch.cr0 & X86_CR0_PE)
1769                 vmx_fpu_deactivate(vcpu);
1770 }
1771
1772 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1773 {
1774         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1775                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1776
1777         vcpu->arch.cr4 = cr4;
1778         if (enable_ept)
1779                 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1780
1781         vmcs_writel(CR4_READ_SHADOW, cr4);
1782         vmcs_writel(GUEST_CR4, hw_cr4);
1783 }
1784
1785 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1786 {
1787         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1788
1789         return vmcs_readl(sf->base);
1790 }
1791
1792 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1793                             struct kvm_segment *var, int seg)
1794 {
1795         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1796         u32 ar;
1797
1798         var->base = vmcs_readl(sf->base);
1799         var->limit = vmcs_read32(sf->limit);
1800         var->selector = vmcs_read16(sf->selector);
1801         ar = vmcs_read32(sf->ar_bytes);
1802         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1803                 ar = 0;
1804         var->type = ar & 15;
1805         var->s = (ar >> 4) & 1;
1806         var->dpl = (ar >> 5) & 3;
1807         var->present = (ar >> 7) & 1;
1808         var->avl = (ar >> 12) & 1;
1809         var->l = (ar >> 13) & 1;
1810         var->db = (ar >> 14) & 1;
1811         var->g = (ar >> 15) & 1;
1812         var->unusable = (ar >> 16) & 1;
1813 }
1814
1815 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1816 {
1817         if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1818                 return 0;
1819
1820         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1821                 return 3;
1822
1823         return vmcs_read16(GUEST_CS_SELECTOR) & 3;
1824 }
1825
1826 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1827 {
1828         u32 ar;
1829
1830         if (var->unusable)
1831                 ar = 1 << 16;
1832         else {
1833                 ar = var->type & 15;
1834                 ar |= (var->s & 1) << 4;
1835                 ar |= (var->dpl & 3) << 5;
1836                 ar |= (var->present & 1) << 7;
1837                 ar |= (var->avl & 1) << 12;
1838                 ar |= (var->l & 1) << 13;
1839                 ar |= (var->db & 1) << 14;
1840                 ar |= (var->g & 1) << 15;
1841         }
1842         if (ar == 0) /* a 0 value means unusable */
1843                 ar = AR_UNUSABLE_MASK;
1844
1845         return ar;
1846 }
1847
1848 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1849                             struct kvm_segment *var, int seg)
1850 {
1851         struct vcpu_vmx *vmx = to_vmx(vcpu);
1852         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1853         u32 ar;
1854
1855         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1856                 vmx->rmode.tr.selector = var->selector;
1857                 vmx->rmode.tr.base = var->base;
1858                 vmx->rmode.tr.limit = var->limit;
1859                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
1860                 return;
1861         }
1862         vmcs_writel(sf->base, var->base);
1863         vmcs_write32(sf->limit, var->limit);
1864         vmcs_write16(sf->selector, var->selector);
1865         if (vmx->rmode.vm86_active && var->s) {
1866                 /*
1867                  * Hack real-mode segments into vm86 compatibility.
1868                  */
1869                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1870                         vmcs_writel(sf->base, 0xf0000);
1871                 ar = 0xf3;
1872         } else
1873                 ar = vmx_segment_access_rights(var);
1874
1875         /*
1876          *   Fix the "Accessed" bit in AR field of segment registers for older
1877          * qemu binaries.
1878          *   IA32 arch specifies that at the time of processor reset the
1879          * "Accessed" bit in the AR field of segment registers is 1. And qemu
1880          * is setting it to 0 in the usedland code. This causes invalid guest
1881          * state vmexit when "unrestricted guest" mode is turned on.
1882          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
1883          * tree. Newer qemu binaries with that qemu fix would not need this
1884          * kvm hack.
1885          */
1886         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1887                 ar |= 0x1; /* Accessed */
1888
1889         vmcs_write32(sf->ar_bytes, ar);
1890 }
1891
1892 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1893 {
1894         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1895
1896         *db = (ar >> 14) & 1;
1897         *l = (ar >> 13) & 1;
1898 }
1899
1900 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1901 {
1902         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1903         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1904 }
1905
1906 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1907 {
1908         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1909         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1910 }
1911
1912 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1913 {
1914         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1915         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1916 }
1917
1918 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1919 {
1920         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1921         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1922 }
1923
1924 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1925 {
1926         struct kvm_segment var;
1927         u32 ar;
1928
1929         vmx_get_segment(vcpu, &var, seg);
1930         ar = vmx_segment_access_rights(&var);
1931
1932         if (var.base != (var.selector << 4))
1933                 return false;
1934         if (var.limit != 0xffff)
1935                 return false;
1936         if (ar != 0xf3)
1937                 return false;
1938
1939         return true;
1940 }
1941
1942 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1943 {
1944         struct kvm_segment cs;
1945         unsigned int cs_rpl;
1946
1947         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1948         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1949
1950         if (cs.unusable)
1951                 return false;
1952         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1953                 return false;
1954         if (!cs.s)
1955                 return false;
1956         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1957                 if (cs.dpl > cs_rpl)
1958                         return false;
1959         } else {
1960                 if (cs.dpl != cs_rpl)
1961                         return false;
1962         }
1963         if (!cs.present)
1964                 return false;
1965
1966         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1967         return true;
1968 }
1969
1970 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1971 {
1972         struct kvm_segment ss;
1973         unsigned int ss_rpl;
1974
1975         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1976         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1977
1978         if (ss.unusable)
1979                 return true;
1980         if (ss.type != 3 && ss.type != 7)
1981                 return false;
1982         if (!ss.s)
1983                 return false;
1984         if (ss.dpl != ss_rpl) /* DPL != RPL */
1985                 return false;
1986         if (!ss.present)
1987                 return false;
1988
1989         return true;
1990 }
1991
1992 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1993 {
1994         struct kvm_segment var;
1995         unsigned int rpl;
1996
1997         vmx_get_segment(vcpu, &var, seg);
1998         rpl = var.selector & SELECTOR_RPL_MASK;
1999
2000         if (var.unusable)
2001                 return true;
2002         if (!var.s)
2003                 return false;
2004         if (!var.present)
2005                 return false;
2006         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2007                 if (var.dpl < rpl) /* DPL < RPL */
2008                         return false;
2009         }
2010
2011         /* TODO: Add other members to kvm_segment_field to allow checking for other access
2012          * rights flags
2013          */
2014         return true;
2015 }
2016
2017 static bool tr_valid(struct kvm_vcpu *vcpu)
2018 {
2019         struct kvm_segment tr;
2020
2021         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2022
2023         if (tr.unusable)
2024                 return false;
2025         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
2026                 return false;
2027         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2028                 return false;
2029         if (!tr.present)
2030                 return false;
2031
2032         return true;
2033 }
2034
2035 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2036 {
2037         struct kvm_segment ldtr;
2038
2039         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2040
2041         if (ldtr.unusable)
2042                 return true;
2043         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
2044                 return false;
2045         if (ldtr.type != 2)
2046                 return false;
2047         if (!ldtr.present)
2048                 return false;
2049
2050         return true;
2051 }
2052
2053 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2054 {
2055         struct kvm_segment cs, ss;
2056
2057         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2058         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2059
2060         return ((cs.selector & SELECTOR_RPL_MASK) ==
2061                  (ss.selector & SELECTOR_RPL_MASK));
2062 }
2063
2064 /*
2065  * Check if guest state is valid. Returns true if valid, false if
2066  * not.
2067  * We assume that registers are always usable
2068  */
2069 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2070 {
2071         /* real mode guest state checks */
2072         if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
2073                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2074                         return false;
2075                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2076                         return false;
2077                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2078                         return false;
2079                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2080                         return false;
2081                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2082                         return false;
2083                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2084                         return false;
2085         } else {
2086         /* protected mode guest state checks */
2087                 if (!cs_ss_rpl_check(vcpu))
2088                         return false;
2089                 if (!code_segment_valid(vcpu))
2090                         return false;
2091                 if (!stack_segment_valid(vcpu))
2092                         return false;
2093                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2094                         return false;
2095                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2096                         return false;
2097                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2098                         return false;
2099                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2100                         return false;
2101                 if (!tr_valid(vcpu))
2102                         return false;
2103                 if (!ldtr_valid(vcpu))
2104                         return false;
2105         }
2106         /* TODO:
2107          * - Add checks on RIP
2108          * - Add checks on RFLAGS
2109          */
2110
2111         return true;
2112 }
2113
2114 static int init_rmode_tss(struct kvm *kvm)
2115 {
2116         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2117         u16 data = 0;
2118         int ret = 0;
2119         int r;
2120
2121         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2122         if (r < 0)
2123                 goto out;
2124         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2125         r = kvm_write_guest_page(kvm, fn++, &data,
2126                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
2127         if (r < 0)
2128                 goto out;
2129         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2130         if (r < 0)
2131                 goto out;
2132         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2133         if (r < 0)
2134                 goto out;
2135         data = ~0;
2136         r = kvm_write_guest_page(kvm, fn, &data,
2137                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2138                                  sizeof(u8));
2139         if (r < 0)
2140                 goto out;
2141
2142         ret = 1;
2143 out:
2144         return ret;
2145 }
2146
2147 static int init_rmode_identity_map(struct kvm *kvm)
2148 {
2149         int i, r, ret;
2150         pfn_t identity_map_pfn;
2151         u32 tmp;
2152
2153         if (!enable_ept)
2154                 return 1;
2155         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2156                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2157                         "haven't been allocated!\n");
2158                 return 0;
2159         }
2160         if (likely(kvm->arch.ept_identity_pagetable_done))
2161                 return 1;
2162         ret = 0;
2163         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2164         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2165         if (r < 0)
2166                 goto out;
2167         /* Set up identity-mapping pagetable for EPT in real mode */
2168         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2169                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2170                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2171                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2172                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2173                 if (r < 0)
2174                         goto out;
2175         }
2176         kvm->arch.ept_identity_pagetable_done = true;
2177         ret = 1;
2178 out:
2179         return ret;
2180 }
2181
2182 static void seg_setup(int seg)
2183 {
2184         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2185         unsigned int ar;
2186
2187         vmcs_write16(sf->selector, 0);
2188         vmcs_writel(sf->base, 0);
2189         vmcs_write32(sf->limit, 0xffff);
2190         if (enable_unrestricted_guest) {
2191                 ar = 0x93;
2192                 if (seg == VCPU_SREG_CS)
2193                         ar |= 0x08; /* code segment */
2194         } else
2195                 ar = 0xf3;
2196
2197         vmcs_write32(sf->ar_bytes, ar);
2198 }
2199
2200 static int alloc_apic_access_page(struct kvm *kvm)
2201 {
2202         struct kvm_userspace_memory_region kvm_userspace_mem;
2203         int r = 0;
2204
2205         down_write(&kvm->slots_lock);
2206         if (kvm->arch.apic_access_page)
2207                 goto out;
2208         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2209         kvm_userspace_mem.flags = 0;
2210         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2211         kvm_userspace_mem.memory_size = PAGE_SIZE;
2212         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2213         if (r)
2214                 goto out;
2215
2216         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2217 out:
2218         up_write(&kvm->slots_lock);
2219         return r;
2220 }
2221
2222 static int alloc_identity_pagetable(struct kvm *kvm)
2223 {
2224         struct kvm_userspace_memory_region kvm_userspace_mem;
2225         int r = 0;
2226
2227         down_write(&kvm->slots_lock);
2228         if (kvm->arch.ept_identity_pagetable)
2229                 goto out;
2230         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2231         kvm_userspace_mem.flags = 0;
2232         kvm_userspace_mem.guest_phys_addr =
2233                 kvm->arch.ept_identity_map_addr;
2234         kvm_userspace_mem.memory_size = PAGE_SIZE;
2235         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2236         if (r)
2237                 goto out;
2238
2239         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2240                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2241 out:
2242         up_write(&kvm->slots_lock);
2243         return r;
2244 }
2245
2246 static void allocate_vpid(struct vcpu_vmx *vmx)
2247 {
2248         int vpid;
2249
2250         vmx->vpid = 0;
2251         if (!enable_vpid)
2252                 return;
2253         spin_lock(&vmx_vpid_lock);
2254         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2255         if (vpid < VMX_NR_VPIDS) {
2256                 vmx->vpid = vpid;
2257                 __set_bit(vpid, vmx_vpid_bitmap);
2258         }
2259         spin_unlock(&vmx_vpid_lock);
2260 }
2261
2262 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2263 {
2264         int f = sizeof(unsigned long);
2265
2266         if (!cpu_has_vmx_msr_bitmap())
2267                 return;
2268
2269         /*
2270          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2271          * have the write-low and read-high bitmap offsets the wrong way round.
2272          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2273          */
2274         if (msr <= 0x1fff) {
2275                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2276                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2277         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2278                 msr &= 0x1fff;
2279                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2280                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2281         }
2282 }
2283
2284 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2285 {
2286         if (!longmode_only)
2287                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2288         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2289 }
2290
2291 /*
2292  * Sets up the vmcs for emulated real mode.
2293  */
2294 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2295 {
2296         u32 host_sysenter_cs, msr_low, msr_high;
2297         u32 junk;
2298         u64 host_pat, tsc_this, tsc_base;
2299         unsigned long a;
2300         struct descriptor_table dt;
2301         int i;
2302         unsigned long kvm_vmx_return;
2303         u32 exec_control;
2304
2305         /* I/O */
2306         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2307         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2308
2309         if (cpu_has_vmx_msr_bitmap())
2310                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2311
2312         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2313
2314         /* Control */
2315         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2316                 vmcs_config.pin_based_exec_ctrl);
2317
2318         exec_control = vmcs_config.cpu_based_exec_ctrl;
2319         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2320                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2321 #ifdef CONFIG_X86_64
2322                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2323                                 CPU_BASED_CR8_LOAD_EXITING;
2324 #endif
2325         }
2326         if (!enable_ept)
2327                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2328                                 CPU_BASED_CR3_LOAD_EXITING  |
2329                                 CPU_BASED_INVLPG_EXITING;
2330         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2331
2332         if (cpu_has_secondary_exec_ctrls()) {
2333                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2334                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2335                         exec_control &=
2336                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2337                 if (vmx->vpid == 0)
2338                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2339                 if (!enable_ept)
2340                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2341                 if (!enable_unrestricted_guest)
2342                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2343                 if (!ple_gap)
2344                         exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2345                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2346         }
2347
2348         if (ple_gap) {
2349                 vmcs_write32(PLE_GAP, ple_gap);
2350                 vmcs_write32(PLE_WINDOW, ple_window);
2351         }
2352
2353         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2354         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2355         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2356
2357         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
2358         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2359         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2360
2361         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2362         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2363         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2364         vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs());    /* 22.2.4 */
2365         vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs());    /* 22.2.4 */
2366         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2367 #ifdef CONFIG_X86_64
2368         rdmsrl(MSR_FS_BASE, a);
2369         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2370         rdmsrl(MSR_GS_BASE, a);
2371         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2372 #else
2373         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2374         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2375 #endif
2376
2377         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2378
2379         kvm_get_idt(&dt);
2380         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
2381
2382         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2383         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2384         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2385         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2386         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2387
2388         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2389         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2390         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2391         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2392         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2393         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2394
2395         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2396                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2397                 host_pat = msr_low | ((u64) msr_high << 32);
2398                 vmcs_write64(HOST_IA32_PAT, host_pat);
2399         }
2400         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2401                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2402                 host_pat = msr_low | ((u64) msr_high << 32);
2403                 /* Write the default value follow host pat */
2404                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2405                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2406                 vmx->vcpu.arch.pat = host_pat;
2407         }
2408
2409         for (i = 0; i < NR_VMX_MSR; ++i) {
2410                 u32 index = vmx_msr_index[i];
2411                 u32 data_low, data_high;
2412                 u64 data;
2413                 int j = vmx->nmsrs;
2414
2415                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2416                         continue;
2417                 if (wrmsr_safe(index, data_low, data_high) < 0)
2418                         continue;
2419                 data = data_low | ((u64)data_high << 32);
2420                 vmx->host_msrs[j].index = index;
2421                 vmx->host_msrs[j].reserved = 0;
2422                 vmx->host_msrs[j].data = data;
2423                 vmx->guest_msrs[j] = vmx->host_msrs[j];
2424                 ++vmx->nmsrs;
2425         }
2426
2427         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2428
2429         /* 22.2.1, 20.8.1 */
2430         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2431
2432         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2433         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2434
2435         tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2436         rdtscll(tsc_this);
2437         if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2438                 tsc_base = tsc_this;
2439
2440         guest_write_tsc(0, tsc_base);
2441
2442         return 0;
2443 }
2444
2445 static int init_rmode(struct kvm *kvm)
2446 {
2447         if (!init_rmode_tss(kvm))
2448                 return 0;
2449         if (!init_rmode_identity_map(kvm))
2450                 return 0;
2451         return 1;
2452 }
2453
2454 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2455 {
2456         struct vcpu_vmx *vmx = to_vmx(vcpu);
2457         u64 msr;
2458         int ret;
2459
2460         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2461         down_read(&vcpu->kvm->slots_lock);
2462         if (!init_rmode(vmx->vcpu.kvm)) {
2463                 ret = -ENOMEM;
2464                 goto out;
2465         }
2466
2467         vmx->rmode.vm86_active = 0;
2468
2469         vmx->soft_vnmi_blocked = 0;
2470
2471         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2472         kvm_set_cr8(&vmx->vcpu, 0);
2473         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2474         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2475                 msr |= MSR_IA32_APICBASE_BSP;
2476         kvm_set_apic_base(&vmx->vcpu, msr);
2477
2478         fx_init(&vmx->vcpu);
2479
2480         seg_setup(VCPU_SREG_CS);
2481         /*
2482          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2483          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2484          */
2485         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2486                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2487                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2488         } else {
2489                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2490                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2491         }
2492
2493         seg_setup(VCPU_SREG_DS);
2494         seg_setup(VCPU_SREG_ES);
2495         seg_setup(VCPU_SREG_FS);
2496         seg_setup(VCPU_SREG_GS);
2497         seg_setup(VCPU_SREG_SS);
2498
2499         vmcs_write16(GUEST_TR_SELECTOR, 0);
2500         vmcs_writel(GUEST_TR_BASE, 0);
2501         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2502         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2503
2504         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2505         vmcs_writel(GUEST_LDTR_BASE, 0);
2506         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2507         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2508
2509         vmcs_write32(GUEST_SYSENTER_CS, 0);
2510         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2511         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2512
2513         vmcs_writel(GUEST_RFLAGS, 0x02);
2514         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2515                 kvm_rip_write(vcpu, 0xfff0);
2516         else
2517                 kvm_rip_write(vcpu, 0);
2518         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2519
2520         vmcs_writel(GUEST_DR7, 0x400);
2521
2522         vmcs_writel(GUEST_GDTR_BASE, 0);
2523         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2524
2525         vmcs_writel(GUEST_IDTR_BASE, 0);
2526         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2527
2528         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2529         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2530         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2531
2532         /* Special registers */
2533         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2534
2535         setup_msrs(vmx);
2536
2537         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2538
2539         if (cpu_has_vmx_tpr_shadow()) {
2540                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2541                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2542                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2543                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2544                 vmcs_write32(TPR_THRESHOLD, 0);
2545         }
2546
2547         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2548                 vmcs_write64(APIC_ACCESS_ADDR,
2549                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2550
2551         if (vmx->vpid != 0)
2552                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2553
2554         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2555         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2556         vmx_set_cr4(&vmx->vcpu, 0);
2557         vmx_set_efer(&vmx->vcpu, 0);
2558         vmx_fpu_activate(&vmx->vcpu);
2559         update_exception_bitmap(&vmx->vcpu);
2560
2561         vpid_sync_vcpu_all(vmx);
2562
2563         ret = 0;
2564
2565         /* HACK: Don't enable emulation on guest boot/reset */
2566         vmx->emulation_required = 0;
2567
2568 out:
2569         up_read(&vcpu->kvm->slots_lock);
2570         return ret;
2571 }
2572
2573 static void enable_irq_window(struct kvm_vcpu *vcpu)
2574 {
2575         u32 cpu_based_vm_exec_control;
2576
2577         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2578         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2579         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2580 }
2581
2582 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2583 {
2584         u32 cpu_based_vm_exec_control;
2585
2586         if (!cpu_has_virtual_nmis()) {
2587                 enable_irq_window(vcpu);
2588                 return;
2589         }
2590
2591         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2592         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2593         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2594 }
2595
2596 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2597 {
2598         struct vcpu_vmx *vmx = to_vmx(vcpu);
2599         uint32_t intr;
2600         int irq = vcpu->arch.interrupt.nr;
2601
2602         trace_kvm_inj_virq(irq);
2603
2604         ++vcpu->stat.irq_injections;
2605         if (vmx->rmode.vm86_active) {
2606                 vmx->rmode.irq.pending = true;
2607                 vmx->rmode.irq.vector = irq;
2608                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2609                 if (vcpu->arch.interrupt.soft)
2610                         vmx->rmode.irq.rip +=
2611                                 vmx->vcpu.arch.event_exit_inst_len;
2612                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2613                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2614                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2615                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2616                 return;
2617         }
2618         intr = irq | INTR_INFO_VALID_MASK;
2619         if (vcpu->arch.interrupt.soft) {
2620                 intr |= INTR_TYPE_SOFT_INTR;
2621                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2622                              vmx->vcpu.arch.event_exit_inst_len);
2623         } else
2624                 intr |= INTR_TYPE_EXT_INTR;
2625         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2626 }
2627
2628 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2629 {
2630         struct vcpu_vmx *vmx = to_vmx(vcpu);
2631
2632         if (!cpu_has_virtual_nmis()) {
2633                 /*
2634                  * Tracking the NMI-blocked state in software is built upon
2635                  * finding the next open IRQ window. This, in turn, depends on
2636                  * well-behaving guests: They have to keep IRQs disabled at
2637                  * least as long as the NMI handler runs. Otherwise we may
2638                  * cause NMI nesting, maybe breaking the guest. But as this is
2639                  * highly unlikely, we can live with the residual risk.
2640                  */
2641                 vmx->soft_vnmi_blocked = 1;
2642                 vmx->vnmi_blocked_time = 0;
2643         }
2644
2645         ++vcpu->stat.nmi_injections;
2646         if (vmx->rmode.vm86_active) {
2647                 vmx->rmode.irq.pending = true;
2648                 vmx->rmode.irq.vector = NMI_VECTOR;
2649                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2650                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2651                              NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2652                              INTR_INFO_VALID_MASK);
2653                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2654                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2655                 return;
2656         }
2657         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2658                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2659 }
2660
2661 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2662 {
2663         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2664                 return 0;
2665
2666         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2667                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2668                                 GUEST_INTR_STATE_NMI));
2669 }
2670
2671 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2672 {
2673         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2674                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2675                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2676 }
2677
2678 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2679 {
2680         int ret;
2681         struct kvm_userspace_memory_region tss_mem = {
2682                 .slot = TSS_PRIVATE_MEMSLOT,
2683                 .guest_phys_addr = addr,
2684                 .memory_size = PAGE_SIZE * 3,
2685                 .flags = 0,
2686         };
2687
2688         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2689         if (ret)
2690                 return ret;
2691         kvm->arch.tss_addr = addr;
2692         return 0;
2693 }
2694
2695 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2696                                   int vec, u32 err_code)
2697 {
2698         /*
2699          * Instruction with address size override prefix opcode 0x67
2700          * Cause the #SS fault with 0 error code in VM86 mode.
2701          */
2702         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2703                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2704                         return 1;
2705         /*
2706          * Forward all other exceptions that are valid in real mode.
2707          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2708          *        the required debugging infrastructure rework.
2709          */
2710         switch (vec) {
2711         case DB_VECTOR:
2712                 if (vcpu->guest_debug &
2713                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2714                         return 0;
2715                 kvm_queue_exception(vcpu, vec);
2716                 return 1;
2717         case BP_VECTOR:
2718                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2719                         return 0;
2720                 /* fall through */
2721         case DE_VECTOR:
2722         case OF_VECTOR:
2723         case BR_VECTOR:
2724         case UD_VECTOR:
2725         case DF_VECTOR:
2726         case SS_VECTOR:
2727         case GP_VECTOR:
2728         case MF_VECTOR:
2729                 kvm_queue_exception(vcpu, vec);
2730                 return 1;
2731         }
2732         return 0;
2733 }
2734
2735 /*
2736  * Trigger machine check on the host. We assume all the MSRs are already set up
2737  * by the CPU and that we still run on the same CPU as the MCE occurred on.
2738  * We pass a fake environment to the machine check handler because we want
2739  * the guest to be always treated like user space, no matter what context
2740  * it used internally.
2741  */
2742 static void kvm_machine_check(void)
2743 {
2744 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2745         struct pt_regs regs = {
2746                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2747                 .flags = X86_EFLAGS_IF,
2748         };
2749
2750         do_machine_check(&regs, 0);
2751 #endif
2752 }
2753
2754 static int handle_machine_check(struct kvm_vcpu *vcpu)
2755 {
2756         /* already handled by vcpu_run */
2757         return 1;
2758 }
2759
2760 static int handle_exception(struct kvm_vcpu *vcpu)
2761 {
2762         struct vcpu_vmx *vmx = to_vmx(vcpu);
2763         struct kvm_run *kvm_run = vcpu->run;
2764         u32 intr_info, ex_no, error_code;
2765         unsigned long cr2, rip, dr6;
2766         u32 vect_info;
2767         enum emulation_result er;
2768
2769         vect_info = vmx->idt_vectoring_info;
2770         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2771
2772         if (is_machine_check(intr_info))
2773                 return handle_machine_check(vcpu);
2774
2775         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2776                                                 !is_page_fault(intr_info))
2777                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2778                        "intr info 0x%x\n", __func__, vect_info, intr_info);
2779
2780         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2781                 return 1;  /* already handled by vmx_vcpu_run() */
2782
2783         if (is_no_device(intr_info)) {
2784                 vmx_fpu_activate(vcpu);
2785                 return 1;
2786         }
2787
2788         if (is_invalid_opcode(intr_info)) {
2789                 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
2790                 if (er != EMULATE_DONE)
2791                         kvm_queue_exception(vcpu, UD_VECTOR);
2792                 return 1;
2793         }
2794
2795         error_code = 0;
2796         rip = kvm_rip_read(vcpu);
2797         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2798                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2799         if (is_page_fault(intr_info)) {
2800                 /* EPT won't cause page fault directly */
2801                 if (enable_ept)
2802                         BUG();
2803                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2804                 trace_kvm_page_fault(cr2, error_code);
2805
2806                 if (kvm_event_needs_reinjection(vcpu))
2807                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
2808                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2809         }
2810
2811         if (vmx->rmode.vm86_active &&
2812             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2813                                                                 error_code)) {
2814                 if (vcpu->arch.halt_request) {
2815                         vcpu->arch.halt_request = 0;
2816                         return kvm_emulate_halt(vcpu);
2817                 }
2818                 return 1;
2819         }
2820
2821         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2822         switch (ex_no) {
2823         case DB_VECTOR:
2824                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2825                 if (!(vcpu->guest_debug &
2826                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2827                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2828                         kvm_queue_exception(vcpu, DB_VECTOR);
2829                         return 1;
2830                 }
2831                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2832                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2833                 /* fall through */
2834         case BP_VECTOR:
2835                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2836                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2837                 kvm_run->debug.arch.exception = ex_no;
2838                 break;
2839         default:
2840                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2841                 kvm_run->ex.exception = ex_no;
2842                 kvm_run->ex.error_code = error_code;
2843                 break;
2844         }
2845         return 0;
2846 }
2847
2848 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
2849 {
2850         ++vcpu->stat.irq_exits;
2851         return 1;
2852 }
2853
2854 static int handle_triple_fault(struct kvm_vcpu *vcpu)
2855 {
2856         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
2857         return 0;
2858 }
2859
2860 static int handle_io(struct kvm_vcpu *vcpu)
2861 {
2862         unsigned long exit_qualification;
2863         int size, in, string;
2864         unsigned port;
2865
2866         ++vcpu->stat.io_exits;
2867         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2868         string = (exit_qualification & 16) != 0;
2869
2870         if (string) {
2871                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO)
2872                         return 0;
2873                 return 1;
2874         }
2875
2876         size = (exit_qualification & 7) + 1;
2877         in = (exit_qualification & 8) != 0;
2878         port = exit_qualification >> 16;
2879
2880         skip_emulated_instruction(vcpu);
2881         return kvm_emulate_pio(vcpu, in, size, port);
2882 }
2883
2884 static void
2885 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2886 {
2887         /*
2888          * Patch in the VMCALL instruction:
2889          */
2890         hypercall[0] = 0x0f;
2891         hypercall[1] = 0x01;
2892         hypercall[2] = 0xc1;
2893 }
2894
2895 static int handle_cr(struct kvm_vcpu *vcpu)
2896 {
2897         unsigned long exit_qualification, val;
2898         int cr;
2899         int reg;
2900
2901         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2902         cr = exit_qualification & 15;
2903         reg = (exit_qualification >> 8) & 15;
2904         switch ((exit_qualification >> 4) & 3) {
2905         case 0: /* mov to cr */
2906                 val = kvm_register_read(vcpu, reg);
2907                 trace_kvm_cr_write(cr, val);
2908                 switch (cr) {
2909                 case 0:
2910                         kvm_set_cr0(vcpu, val);
2911                         skip_emulated_instruction(vcpu);
2912                         return 1;
2913                 case 3:
2914                         kvm_set_cr3(vcpu, val);
2915                         skip_emulated_instruction(vcpu);
2916                         return 1;
2917                 case 4:
2918                         kvm_set_cr4(vcpu, val);
2919                         skip_emulated_instruction(vcpu);
2920                         return 1;
2921                 case 8: {
2922                                 u8 cr8_prev = kvm_get_cr8(vcpu);
2923                                 u8 cr8 = kvm_register_read(vcpu, reg);
2924                                 kvm_set_cr8(vcpu, cr8);
2925                                 skip_emulated_instruction(vcpu);
2926                                 if (irqchip_in_kernel(vcpu->kvm))
2927                                         return 1;
2928                                 if (cr8_prev <= cr8)
2929                                         return 1;
2930                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
2931                                 return 0;
2932                         }
2933                 };
2934                 break;
2935         case 2: /* clts */
2936                 vmx_fpu_deactivate(vcpu);
2937                 vcpu->arch.cr0 &= ~X86_CR0_TS;
2938                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2939                 vmx_fpu_activate(vcpu);
2940                 skip_emulated_instruction(vcpu);
2941                 return 1;
2942         case 1: /*mov from cr*/
2943                 switch (cr) {
2944                 case 3:
2945                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2946                         trace_kvm_cr_read(cr, vcpu->arch.cr3);
2947                         skip_emulated_instruction(vcpu);
2948                         return 1;
2949                 case 8:
2950                         val = kvm_get_cr8(vcpu);
2951                         kvm_register_write(vcpu, reg, val);
2952                         trace_kvm_cr_read(cr, val);
2953                         skip_emulated_instruction(vcpu);
2954                         return 1;
2955                 }
2956                 break;
2957         case 3: /* lmsw */
2958                 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2959
2960                 skip_emulated_instruction(vcpu);
2961                 return 1;
2962         default:
2963                 break;
2964         }
2965         vcpu->run->exit_reason = 0;
2966         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2967                (int)(exit_qualification >> 4) & 3, cr);
2968         return 0;
2969 }
2970
2971 static int handle_dr(struct kvm_vcpu *vcpu)
2972 {
2973         unsigned long exit_qualification;
2974         unsigned long val;
2975         int dr, reg;
2976
2977         if (!kvm_require_cpl(vcpu, 0))
2978                 return 1;
2979         dr = vmcs_readl(GUEST_DR7);
2980         if (dr & DR7_GD) {
2981                 /*
2982                  * As the vm-exit takes precedence over the debug trap, we
2983                  * need to emulate the latter, either for the host or the
2984                  * guest debugging itself.
2985                  */
2986                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2987                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
2988                         vcpu->run->debug.arch.dr7 = dr;
2989                         vcpu->run->debug.arch.pc =
2990                                 vmcs_readl(GUEST_CS_BASE) +
2991                                 vmcs_readl(GUEST_RIP);
2992                         vcpu->run->debug.arch.exception = DB_VECTOR;
2993                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
2994                         return 0;
2995                 } else {
2996                         vcpu->arch.dr7 &= ~DR7_GD;
2997                         vcpu->arch.dr6 |= DR6_BD;
2998                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2999                         kvm_queue_exception(vcpu, DB_VECTOR);
3000                         return 1;
3001                 }
3002         }
3003
3004         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3005         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3006         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3007         if (exit_qualification & TYPE_MOV_FROM_DR) {
3008                 switch (dr) {
3009                 case 0 ... 3:
3010                         val = vcpu->arch.db[dr];
3011                         break;
3012                 case 6:
3013                         val = vcpu->arch.dr6;
3014                         break;
3015                 case 7:
3016                         val = vcpu->arch.dr7;
3017                         break;
3018                 default:
3019                         val = 0;
3020                 }
3021                 kvm_register_write(vcpu, reg, val);
3022         } else {
3023                 val = vcpu->arch.regs[reg];
3024                 switch (dr) {
3025                 case 0 ... 3:
3026                         vcpu->arch.db[dr] = val;
3027                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
3028                                 vcpu->arch.eff_db[dr] = val;
3029                         break;
3030                 case 4 ... 5:
3031                         if (vcpu->arch.cr4 & X86_CR4_DE)
3032                                 kvm_queue_exception(vcpu, UD_VECTOR);
3033                         break;
3034                 case 6:
3035                         if (val & 0xffffffff00000000ULL) {
3036                                 kvm_queue_exception(vcpu, GP_VECTOR);
3037                                 break;
3038                         }
3039                         vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
3040                         break;
3041                 case 7:
3042                         if (val & 0xffffffff00000000ULL) {
3043                                 kvm_queue_exception(vcpu, GP_VECTOR);
3044                                 break;
3045                         }
3046                         vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3047                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3048                                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3049                                 vcpu->arch.switch_db_regs =
3050                                         (val & DR7_BP_EN_MASK);
3051                         }
3052                         break;
3053                 }
3054         }
3055         skip_emulated_instruction(vcpu);
3056         return 1;
3057 }
3058
3059 static int handle_cpuid(struct kvm_vcpu *vcpu)
3060 {
3061         kvm_emulate_cpuid(vcpu);
3062         return 1;
3063 }
3064
3065 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3066 {
3067         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3068         u64 data;
3069
3070         if (vmx_get_msr(vcpu, ecx, &data)) {
3071                 kvm_inject_gp(vcpu, 0);
3072                 return 1;
3073         }
3074
3075         trace_kvm_msr_read(ecx, data);
3076
3077         /* FIXME: handling of bits 32:63 of rax, rdx */
3078         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3079         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3080         skip_emulated_instruction(vcpu);
3081         return 1;
3082 }
3083
3084 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3085 {
3086         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3087         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3088                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3089
3090         trace_kvm_msr_write(ecx, data);
3091
3092         if (vmx_set_msr(vcpu, ecx, data) != 0) {
3093                 kvm_inject_gp(vcpu, 0);
3094                 return 1;
3095         }
3096
3097         skip_emulated_instruction(vcpu);
3098         return 1;
3099 }
3100
3101 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3102 {
3103         return 1;
3104 }
3105
3106 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3107 {
3108         u32 cpu_based_vm_exec_control;
3109
3110         /* clear pending irq */
3111         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3112         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3113         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3114
3115         ++vcpu->stat.irq_window_exits;
3116
3117         /*
3118          * If the user space waits to inject interrupts, exit as soon as
3119          * possible
3120          */
3121         if (!irqchip_in_kernel(vcpu->kvm) &&
3122             vcpu->run->request_interrupt_window &&
3123             !kvm_cpu_has_interrupt(vcpu)) {
3124                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3125                 return 0;
3126         }
3127         return 1;
3128 }
3129
3130 static int handle_halt(struct kvm_vcpu *vcpu)
3131 {
3132         skip_emulated_instruction(vcpu);
3133         return kvm_emulate_halt(vcpu);
3134 }
3135
3136 static int handle_vmcall(struct kvm_vcpu *vcpu)
3137 {
3138         skip_emulated_instruction(vcpu);
3139         kvm_emulate_hypercall(vcpu);
3140         return 1;
3141 }
3142
3143 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3144 {
3145         kvm_queue_exception(vcpu, UD_VECTOR);
3146         return 1;
3147 }
3148
3149 static int handle_invlpg(struct kvm_vcpu *vcpu)
3150 {
3151         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3152
3153         kvm_mmu_invlpg(vcpu, exit_qualification);
3154         skip_emulated_instruction(vcpu);
3155         return 1;
3156 }
3157
3158 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3159 {
3160         skip_emulated_instruction(vcpu);
3161         /* TODO: Add support for VT-d/pass-through device */
3162         return 1;
3163 }
3164
3165 static int handle_apic_access(struct kvm_vcpu *vcpu)
3166 {
3167         unsigned long exit_qualification;
3168         enum emulation_result er;
3169         unsigned long offset;
3170
3171         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3172         offset = exit_qualification & 0xffful;
3173
3174         er = emulate_instruction(vcpu, 0, 0, 0);
3175
3176         if (er !=  EMULATE_DONE) {
3177                 printk(KERN_ERR
3178                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3179                        offset);
3180                 return -ENOEXEC;
3181         }
3182         return 1;
3183 }
3184
3185 static int handle_task_switch(struct kvm_vcpu *vcpu)
3186 {
3187         struct vcpu_vmx *vmx = to_vmx(vcpu);
3188         unsigned long exit_qualification;
3189         u16 tss_selector;
3190         int reason, type, idt_v;
3191
3192         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3193         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3194
3195         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3196
3197         reason = (u32)exit_qualification >> 30;
3198         if (reason == TASK_SWITCH_GATE && idt_v) {
3199                 switch (type) {
3200                 case INTR_TYPE_NMI_INTR:
3201                         vcpu->arch.nmi_injected = false;
3202                         if (cpu_has_virtual_nmis())
3203                                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3204                                               GUEST_INTR_STATE_NMI);
3205                         break;
3206                 case INTR_TYPE_EXT_INTR:
3207                 case INTR_TYPE_SOFT_INTR:
3208                         kvm_clear_interrupt_queue(vcpu);
3209                         break;
3210                 case INTR_TYPE_HARD_EXCEPTION:
3211                 case INTR_TYPE_SOFT_EXCEPTION:
3212                         kvm_clear_exception_queue(vcpu);
3213                         break;
3214                 default:
3215                         break;
3216                 }
3217         }
3218         tss_selector = exit_qualification;
3219
3220         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3221                        type != INTR_TYPE_EXT_INTR &&
3222                        type != INTR_TYPE_NMI_INTR))
3223                 skip_emulated_instruction(vcpu);
3224
3225         if (!kvm_task_switch(vcpu, tss_selector, reason))
3226                 return 0;
3227
3228         /* clear all local breakpoint enable flags */
3229         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3230
3231         /*
3232          * TODO: What about debug traps on tss switch?
3233          *       Are we supposed to inject them and update dr6?
3234          */
3235
3236         return 1;
3237 }
3238
3239 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3240 {
3241         unsigned long exit_qualification;
3242         gpa_t gpa;
3243         int gla_validity;
3244
3245         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3246
3247         if (exit_qualification & (1 << 6)) {
3248                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3249                 return -EINVAL;
3250         }
3251
3252         gla_validity = (exit_qualification >> 7) & 0x3;
3253         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3254                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3255                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3256                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3257                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3258                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3259                         (long unsigned int)exit_qualification);
3260                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3261                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3262                 return 0;
3263         }
3264
3265         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3266         trace_kvm_page_fault(gpa, exit_qualification);
3267         return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3268 }
3269
3270 static u64 ept_rsvd_mask(u64 spte, int level)
3271 {
3272         int i;
3273         u64 mask = 0;
3274
3275         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3276                 mask |= (1ULL << i);
3277
3278         if (level > 2)
3279                 /* bits 7:3 reserved */
3280                 mask |= 0xf8;
3281         else if (level == 2) {
3282                 if (spte & (1ULL << 7))
3283                         /* 2MB ref, bits 20:12 reserved */
3284                         mask |= 0x1ff000;
3285                 else
3286                         /* bits 6:3 reserved */
3287                         mask |= 0x78;
3288         }
3289
3290         return mask;
3291 }
3292
3293 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3294                                        int level)
3295 {
3296         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3297
3298         /* 010b (write-only) */
3299         WARN_ON((spte & 0x7) == 0x2);
3300
3301         /* 110b (write/execute) */
3302         WARN_ON((spte & 0x7) == 0x6);
3303
3304         /* 100b (execute-only) and value not supported by logical processor */
3305         if (!cpu_has_vmx_ept_execute_only())
3306                 WARN_ON((spte & 0x7) == 0x4);
3307
3308         /* not 000b */
3309         if ((spte & 0x7)) {
3310                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3311
3312                 if (rsvd_bits != 0) {
3313                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3314                                          __func__, rsvd_bits);
3315                         WARN_ON(1);
3316                 }
3317
3318                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3319                         u64 ept_mem_type = (spte & 0x38) >> 3;
3320
3321                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
3322                             ept_mem_type == 7) {
3323                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3324                                                 __func__, ept_mem_type);
3325                                 WARN_ON(1);
3326                         }
3327                 }
3328         }
3329 }
3330
3331 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3332 {
3333         u64 sptes[4];
3334         int nr_sptes, i;
3335         gpa_t gpa;
3336
3337         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3338
3339         printk(KERN_ERR "EPT: Misconfiguration.\n");
3340         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3341
3342         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3343
3344         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3345                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3346
3347         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3348         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3349
3350         return 0;
3351 }
3352
3353 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3354 {
3355         u32 cpu_based_vm_exec_control;
3356
3357         /* clear pending NMI */
3358         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3359         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3360         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3361         ++vcpu->stat.nmi_window_exits;
3362
3363         return 1;
3364 }
3365
3366 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3367 {
3368         struct vcpu_vmx *vmx = to_vmx(vcpu);
3369         enum emulation_result err = EMULATE_DONE;
3370         int ret = 1;
3371
3372         while (!guest_state_valid(vcpu)) {
3373                 err = emulate_instruction(vcpu, 0, 0, 0);
3374
3375                 if (err == EMULATE_DO_MMIO) {
3376                         ret = 0;
3377                         goto out;
3378                 }
3379
3380                 if (err != EMULATE_DONE) {
3381                         kvm_report_emulation_failure(vcpu, "emulation failure");
3382                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3383                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3384                         ret = 0;
3385                         goto out;
3386                 }
3387
3388                 if (signal_pending(current))
3389                         goto out;
3390                 if (need_resched())
3391                         schedule();
3392         }
3393
3394         vmx->emulation_required = 0;
3395 out:
3396         return ret;
3397 }
3398
3399 /*
3400  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3401  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3402  */
3403 static int handle_pause(struct kvm_vcpu *vcpu)
3404 {
3405         skip_emulated_instruction(vcpu);
3406         kvm_vcpu_on_spin(vcpu);
3407
3408         return 1;
3409 }
3410
3411 /*
3412  * The exit handlers return 1 if the exit was handled fully and guest execution
3413  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3414  * to be done to userspace and return 0.
3415  */
3416 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3417         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3418         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3419         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3420         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3421         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3422         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3423         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3424         [EXIT_REASON_CPUID]                   = handle_cpuid,
3425         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3426         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3427         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3428         [EXIT_REASON_HLT]                     = handle_halt,
3429         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3430         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3431         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
3432         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
3433         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
3434         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
3435         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
3436         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
3437         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
3438         [EXIT_REASON_VMOFF]                   = handle_vmx_insn,
3439         [EXIT_REASON_VMON]                    = handle_vmx_insn,
3440         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3441         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3442         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3443         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3444         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
3445         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3446         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
3447         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
3448 };
3449
3450 static const int kvm_vmx_max_exit_handlers =
3451         ARRAY_SIZE(kvm_vmx_exit_handlers);
3452
3453 /*
3454  * The guest has exited.  See if we can fix it or if we need userspace
3455  * assistance.
3456  */
3457 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3458 {
3459         struct vcpu_vmx *vmx = to_vmx(vcpu);
3460         u32 exit_reason = vmx->exit_reason;
3461         u32 vectoring_info = vmx->idt_vectoring_info;
3462
3463         trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
3464
3465         /* If guest state is invalid, start emulating */
3466         if (vmx->emulation_required && emulate_invalid_guest_state)
3467                 return handle_invalid_guest_state(vcpu);
3468
3469         /* Access CR3 don't cause VMExit in paging mode, so we need
3470          * to sync with guest real CR3. */
3471         if (enable_ept && is_paging(vcpu))
3472                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3473
3474         if (unlikely(vmx->fail)) {
3475                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3476                 vcpu->run->fail_entry.hardware_entry_failure_reason
3477                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3478                 return 0;
3479         }
3480
3481         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3482                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3483                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3484                         exit_reason != EXIT_REASON_TASK_SWITCH))
3485                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3486                        "(0x%x) and exit reason is 0x%x\n",
3487                        __func__, vectoring_info, exit_reason);
3488
3489         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3490                 if (vmx_interrupt_allowed(vcpu)) {
3491                         vmx->soft_vnmi_blocked = 0;
3492                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3493                            vcpu->arch.nmi_pending) {
3494                         /*
3495                          * This CPU don't support us in finding the end of an
3496                          * NMI-blocked window if the guest runs with IRQs
3497                          * disabled. So we pull the trigger after 1 s of
3498                          * futile waiting, but inform the user about this.
3499                          */
3500                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3501                                "state on VCPU %d after 1 s timeout\n",
3502                                __func__, vcpu->vcpu_id);
3503                         vmx->soft_vnmi_blocked = 0;
3504                 }
3505         }
3506
3507         if (exit_reason < kvm_vmx_max_exit_handlers
3508             && kvm_vmx_exit_handlers[exit_reason])
3509                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3510         else {
3511                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3512                 vcpu->run->hw.hardware_exit_reason = exit_reason;
3513         }
3514         return 0;
3515 }
3516
3517 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3518 {
3519         if (irr == -1 || tpr < irr) {
3520                 vmcs_write32(TPR_THRESHOLD, 0);
3521                 return;
3522         }
3523
3524         vmcs_write32(TPR_THRESHOLD, irr);
3525 }
3526
3527 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3528 {
3529         u32 exit_intr_info;
3530         u32 idt_vectoring_info = vmx->idt_vectoring_info;
3531         bool unblock_nmi;
3532         u8 vector;
3533         int type;
3534         bool idtv_info_valid;
3535
3536         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3537
3538         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3539
3540         /* Handle machine checks before interrupts are enabled */
3541         if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3542             || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3543                 && is_machine_check(exit_intr_info)))
3544                 kvm_machine_check();
3545
3546         /* We need to handle NMIs before interrupts are enabled */
3547         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3548             (exit_intr_info & INTR_INFO_VALID_MASK))
3549                 asm("int $2");
3550
3551         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3552
3553         if (cpu_has_virtual_nmis()) {
3554                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3555                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3556                 /*
3557                  * SDM 3: 27.7.1.2 (September 2008)
3558                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3559                  * a guest IRET fault.
3560                  * SDM 3: 23.2.2 (September 2008)
3561                  * Bit 12 is undefined in any of the following cases:
3562                  *  If the VM exit sets the valid bit in the IDT-vectoring
3563                  *   information field.
3564                  *  If the VM exit is due to a double fault.
3565                  */
3566                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3567                     vector != DF_VECTOR && !idtv_info_valid)
3568                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3569                                       GUEST_INTR_STATE_NMI);
3570         } else if (unlikely(vmx->soft_vnmi_blocked))
3571                 vmx->vnmi_blocked_time +=
3572                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3573
3574         vmx->vcpu.arch.nmi_injected = false;
3575         kvm_clear_exception_queue(&vmx->vcpu);
3576         kvm_clear_interrupt_queue(&vmx->vcpu);
3577
3578         if (!idtv_info_valid)
3579                 return;
3580
3581         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3582         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3583
3584         switch (type) {
3585         case INTR_TYPE_NMI_INTR:
3586                 vmx->vcpu.arch.nmi_injected = true;
3587                 /*
3588                  * SDM 3: 27.7.1.2 (September 2008)
3589                  * Clear bit "block by NMI" before VM entry if a NMI
3590                  * delivery faulted.
3591                  */
3592                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3593                                 GUEST_INTR_STATE_NMI);
3594                 break;
3595         case INTR_TYPE_SOFT_EXCEPTION:
3596                 vmx->vcpu.arch.event_exit_inst_len =
3597                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3598                 /* fall through */
3599         case INTR_TYPE_HARD_EXCEPTION:
3600                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3601                         u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3602                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
3603                 } else
3604                         kvm_queue_exception(&vmx->vcpu, vector);
3605                 break;
3606         case INTR_TYPE_SOFT_INTR:
3607                 vmx->vcpu.arch.event_exit_inst_len =
3608                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3609                 /* fall through */
3610         case INTR_TYPE_EXT_INTR:
3611                 kvm_queue_interrupt(&vmx->vcpu, vector,
3612                         type == INTR_TYPE_SOFT_INTR);
3613                 break;
3614         default:
3615                 break;
3616         }
3617 }
3618
3619 /*
3620  * Failure to inject an interrupt should give us the information
3621  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3622  * when fetching the interrupt redirection bitmap in the real-mode
3623  * tss, this doesn't happen.  So we do it ourselves.
3624  */
3625 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3626 {
3627         vmx->rmode.irq.pending = 0;
3628         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3629                 return;
3630         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3631         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3632                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3633                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3634                 return;
3635         }
3636         vmx->idt_vectoring_info =
3637                 VECTORING_INFO_VALID_MASK
3638                 | INTR_TYPE_EXT_INTR
3639                 | vmx->rmode.irq.vector;
3640 }
3641
3642 #ifdef CONFIG_X86_64
3643 #define R "r"
3644 #define Q "q"
3645 #else
3646 #define R "e"
3647 #define Q "l"
3648 #endif
3649
3650 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3651 {
3652         struct vcpu_vmx *vmx = to_vmx(vcpu);
3653
3654         if (enable_ept && is_paging(vcpu)) {
3655                 vmcs_writel(GUEST_CR3, vcpu->arch.cr3);
3656                 ept_load_pdptrs(vcpu);
3657         }
3658         /* Record the guest's net vcpu time for enforced NMI injections. */
3659         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3660                 vmx->entry_time = ktime_get();
3661
3662         /* Don't enter VMX if guest state is invalid, let the exit handler
3663            start emulation until we arrive back to a valid state */
3664         if (vmx->emulation_required && emulate_invalid_guest_state)
3665                 return;
3666
3667         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3668                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3669         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3670                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3671
3672         /* When single-stepping over STI and MOV SS, we must clear the
3673          * corresponding interruptibility bits in the guest state. Otherwise
3674          * vmentry fails as it then expects bit 14 (BS) in pending debug
3675          * exceptions being set, but that's not correct for the guest debugging
3676          * case. */
3677         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3678                 vmx_set_interrupt_shadow(vcpu, 0);
3679
3680         /*
3681          * Loading guest fpu may have cleared host cr0.ts
3682          */
3683         vmcs_writel(HOST_CR0, read_cr0());
3684
3685         if (vcpu->arch.switch_db_regs)
3686                 set_debugreg(vcpu->arch.dr6, 6);
3687
3688         asm(
3689                 /* Store host registers */
3690                 "push %%"R"dx; push %%"R"bp;"
3691                 "push %%"R"cx \n\t"
3692                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3693                 "je 1f \n\t"
3694                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3695                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3696                 "1: \n\t"
3697                 /* Reload cr2 if changed */
3698                 "mov %c[cr2](%0), %%"R"ax \n\t"
3699                 "mov %%cr2, %%"R"dx \n\t"
3700                 "cmp %%"R"ax, %%"R"dx \n\t"
3701                 "je 2f \n\t"
3702                 "mov %%"R"ax, %%cr2 \n\t"
3703                 "2: \n\t"
3704                 /* Check if vmlaunch of vmresume is needed */
3705                 "cmpl $0, %c[launched](%0) \n\t"
3706                 /* Load guest registers.  Don't clobber flags. */
3707                 "mov %c[rax](%0), %%"R"ax \n\t"
3708                 "mov %c[rbx](%0), %%"R"bx \n\t"
3709                 "mov %c[rdx](%0), %%"R"dx \n\t"
3710                 "mov %c[rsi](%0), %%"R"si \n\t"
3711                 "mov %c[rdi](%0), %%"R"di \n\t"
3712                 "mov %c[rbp](%0), %%"R"bp \n\t"
3713 #ifdef CONFIG_X86_64
3714                 "mov %c[r8](%0),  %%r8  \n\t"
3715                 "mov %c[r9](%0),  %%r9  \n\t"
3716                 "mov %c[r10](%0), %%r10 \n\t"
3717                 "mov %c[r11](%0), %%r11 \n\t"
3718                 "mov %c[r12](%0), %%r12 \n\t"
3719                 "mov %c[r13](%0), %%r13 \n\t"
3720                 "mov %c[r14](%0), %%r14 \n\t"
3721                 "mov %c[r15](%0), %%r15 \n\t"
3722 #endif
3723                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3724
3725                 /* Enter guest mode */
3726                 "jne .Llaunched \n\t"
3727                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3728                 "jmp .Lkvm_vmx_return \n\t"
3729                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3730                 ".Lkvm_vmx_return: "
3731                 /* Save guest registers, load host registers, keep flags */
3732                 "xchg %0,     (%%"R"sp) \n\t"
3733                 "mov %%"R"ax, %c[rax](%0) \n\t"
3734                 "mov %%"R"bx, %c[rbx](%0) \n\t"
3735                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3736                 "mov %%"R"dx, %c[rdx](%0) \n\t"
3737                 "mov %%"R"si, %c[rsi](%0) \n\t"
3738                 "mov %%"R"di, %c[rdi](%0) \n\t"
3739                 "mov %%"R"bp, %c[rbp](%0) \n\t"
3740 #ifdef CONFIG_X86_64
3741                 "mov %%r8,  %c[r8](%0) \n\t"
3742                 "mov %%r9,  %c[r9](%0) \n\t"
3743                 "mov %%r10, %c[r10](%0) \n\t"
3744                 "mov %%r11, %c[r11](%0) \n\t"
3745                 "mov %%r12, %c[r12](%0) \n\t"
3746                 "mov %%r13, %c[r13](%0) \n\t"
3747                 "mov %%r14, %c[r14](%0) \n\t"
3748                 "mov %%r15, %c[r15](%0) \n\t"
3749 #endif
3750                 "mov %%cr2, %%"R"ax   \n\t"
3751                 "mov %%"R"ax, %c[cr2](%0) \n\t"
3752
3753                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
3754                 "setbe %c[fail](%0) \n\t"
3755               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3756                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3757                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3758                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3759                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3760                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3761                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3762                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3763                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3764                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3765                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3766 #ifdef CONFIG_X86_64
3767                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3768                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3769                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3770                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3771                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3772                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3773                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3774                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3775 #endif
3776                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3777               : "cc", "memory"
3778                 , R"bx", R"di", R"si"
3779 #ifdef CONFIG_X86_64
3780                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3781 #endif
3782               );
3783
3784         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3785                                   | (1 << VCPU_EXREG_PDPTR));
3786         vcpu->arch.regs_dirty = 0;
3787
3788         if (vcpu->arch.switch_db_regs)
3789                 get_debugreg(vcpu->arch.dr6, 6);
3790
3791         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3792         if (vmx->rmode.irq.pending)
3793                 fixup_rmode_irq(vmx);
3794
3795         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3796         vmx->launched = 1;
3797
3798         vmx_complete_interrupts(vmx);
3799 }
3800
3801 #undef R
3802 #undef Q
3803
3804 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3805 {
3806         struct vcpu_vmx *vmx = to_vmx(vcpu);
3807
3808         if (vmx->vmcs) {
3809                 vcpu_clear(vmx);
3810                 free_vmcs(vmx->vmcs);
3811                 vmx->vmcs = NULL;
3812         }
3813 }
3814
3815 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3816 {
3817         struct vcpu_vmx *vmx = to_vmx(vcpu);
3818
3819         spin_lock(&vmx_vpid_lock);
3820         if (vmx->vpid != 0)
3821                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3822         spin_unlock(&vmx_vpid_lock);
3823         vmx_free_vmcs(vcpu);
3824         kfree(vmx->host_msrs);
3825         kfree(vmx->guest_msrs);
3826         kvm_vcpu_uninit(vcpu);
3827         kmem_cache_free(kvm_vcpu_cache, vmx);
3828 }
3829
3830 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3831 {
3832         int err;
3833         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3834         int cpu;
3835
3836         if (!vmx)
3837                 return ERR_PTR(-ENOMEM);
3838
3839         allocate_vpid(vmx);
3840
3841         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3842         if (err)
3843                 goto free_vcpu;
3844
3845         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3846         if (!vmx->guest_msrs) {
3847                 err = -ENOMEM;
3848                 goto uninit_vcpu;
3849         }
3850
3851         vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3852         if (!vmx->host_msrs)
3853                 goto free_guest_msrs;
3854
3855         vmx->vmcs = alloc_vmcs();
3856         if (!vmx->vmcs)
3857                 goto free_msrs;
3858
3859         vmcs_clear(vmx->vmcs);
3860
3861         cpu = get_cpu();
3862         vmx_vcpu_load(&vmx->vcpu, cpu);
3863         err = vmx_vcpu_setup(vmx);
3864         vmx_vcpu_put(&vmx->vcpu);
3865         put_cpu();
3866         if (err)
3867                 goto free_vmcs;
3868         if (vm_need_virtualize_apic_accesses(kvm))
3869                 if (alloc_apic_access_page(kvm) != 0)
3870                         goto free_vmcs;
3871
3872         if (enable_ept) {
3873                 if (!kvm->arch.ept_identity_map_addr)
3874                         kvm->arch.ept_identity_map_addr =
3875                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3876                 if (alloc_identity_pagetable(kvm) != 0)
3877                         goto free_vmcs;
3878         }
3879
3880         return &vmx->vcpu;
3881
3882 free_vmcs:
3883         free_vmcs(vmx->vmcs);
3884 free_msrs:
3885         kfree(vmx->host_msrs);
3886 free_guest_msrs:
3887         kfree(vmx->guest_msrs);
3888 uninit_vcpu:
3889         kvm_vcpu_uninit(&vmx->vcpu);
3890 free_vcpu:
3891         kmem_cache_free(kvm_vcpu_cache, vmx);
3892         return ERR_PTR(err);
3893 }
3894
3895 static void __init vmx_check_processor_compat(void *rtn)
3896 {
3897         struct vmcs_config vmcs_conf;
3898
3899         *(int *)rtn = 0;
3900         if (setup_vmcs_config(&vmcs_conf) < 0)
3901                 *(int *)rtn = -EIO;
3902         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3903                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3904                                 smp_processor_id());
3905                 *(int *)rtn = -EIO;
3906         }
3907 }
3908
3909 static int get_ept_level(void)
3910 {
3911         return VMX_EPT_DEFAULT_GAW + 1;
3912 }
3913
3914 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3915 {
3916         u64 ret;
3917
3918         /* For VT-d and EPT combination
3919          * 1. MMIO: always map as UC
3920          * 2. EPT with VT-d:
3921          *   a. VT-d without snooping control feature: can't guarantee the
3922          *      result, try to trust guest.
3923          *   b. VT-d with snooping control feature: snooping control feature of
3924          *      VT-d engine can guarantee the cache correctness. Just set it
3925          *      to WB to keep consistent with host. So the same as item 3.
3926          * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3927          *    consistent with host MTRR
3928          */
3929         if (is_mmio)
3930                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
3931         else if (vcpu->kvm->arch.iommu_domain &&
3932                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3933                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3934                       VMX_EPT_MT_EPTE_SHIFT;
3935         else
3936                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3937                         | VMX_EPT_IGMT_BIT;
3938
3939         return ret;
3940 }
3941
3942 static const struct trace_print_flags vmx_exit_reasons_str[] = {
3943         { EXIT_REASON_EXCEPTION_NMI,           "exception" },
3944         { EXIT_REASON_EXTERNAL_INTERRUPT,      "ext_irq" },
3945         { EXIT_REASON_TRIPLE_FAULT,            "triple_fault" },
3946         { EXIT_REASON_NMI_WINDOW,              "nmi_window" },
3947         { EXIT_REASON_IO_INSTRUCTION,          "io_instruction" },
3948         { EXIT_REASON_CR_ACCESS,               "cr_access" },
3949         { EXIT_REASON_DR_ACCESS,               "dr_access" },
3950         { EXIT_REASON_CPUID,                   "cpuid" },
3951         { EXIT_REASON_MSR_READ,                "rdmsr" },
3952         { EXIT_REASON_MSR_WRITE,               "wrmsr" },
3953         { EXIT_REASON_PENDING_INTERRUPT,       "interrupt_window" },
3954         { EXIT_REASON_HLT,                     "halt" },
3955         { EXIT_REASON_INVLPG,                  "invlpg" },
3956         { EXIT_REASON_VMCALL,                  "hypercall" },
3957         { EXIT_REASON_TPR_BELOW_THRESHOLD,     "tpr_below_thres" },
3958         { EXIT_REASON_APIC_ACCESS,             "apic_access" },
3959         { EXIT_REASON_WBINVD,                  "wbinvd" },
3960         { EXIT_REASON_TASK_SWITCH,             "task_switch" },
3961         { EXIT_REASON_EPT_VIOLATION,           "ept_violation" },
3962         { -1, NULL }
3963 };
3964
3965 static bool vmx_gb_page_enable(void)
3966 {
3967         return false;
3968 }
3969
3970 static struct kvm_x86_ops vmx_x86_ops = {
3971         .cpu_has_kvm_support = cpu_has_kvm_support,
3972         .disabled_by_bios = vmx_disabled_by_bios,
3973         .hardware_setup = hardware_setup,
3974         .hardware_unsetup = hardware_unsetup,
3975         .check_processor_compatibility = vmx_check_processor_compat,
3976         .hardware_enable = hardware_enable,
3977         .hardware_disable = hardware_disable,
3978         .cpu_has_accelerated_tpr = report_flexpriority,
3979
3980         .vcpu_create = vmx_create_vcpu,
3981         .vcpu_free = vmx_free_vcpu,
3982         .vcpu_reset = vmx_vcpu_reset,
3983
3984         .prepare_guest_switch = vmx_save_host_state,
3985         .vcpu_load = vmx_vcpu_load,
3986         .vcpu_put = vmx_vcpu_put,
3987
3988         .set_guest_debug = set_guest_debug,
3989         .get_msr = vmx_get_msr,
3990         .set_msr = vmx_set_msr,
3991         .get_segment_base = vmx_get_segment_base,
3992         .get_segment = vmx_get_segment,
3993         .set_segment = vmx_set_segment,
3994         .get_cpl = vmx_get_cpl,
3995         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3996         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3997         .set_cr0 = vmx_set_cr0,
3998         .set_cr3 = vmx_set_cr3,
3999         .set_cr4 = vmx_set_cr4,
4000         .set_efer = vmx_set_efer,
4001         .get_idt = vmx_get_idt,
4002         .set_idt = vmx_set_idt,
4003         .get_gdt = vmx_get_gdt,
4004         .set_gdt = vmx_set_gdt,
4005         .cache_reg = vmx_cache_reg,
4006         .get_rflags = vmx_get_rflags,
4007         .set_rflags = vmx_set_rflags,
4008
4009         .tlb_flush = vmx_flush_tlb,
4010
4011         .run = vmx_vcpu_run,
4012         .handle_exit = vmx_handle_exit,
4013         .skip_emulated_instruction = skip_emulated_instruction,
4014         .set_interrupt_shadow = vmx_set_interrupt_shadow,
4015         .get_interrupt_shadow = vmx_get_interrupt_shadow,
4016         .patch_hypercall = vmx_patch_hypercall,
4017         .set_irq = vmx_inject_irq,
4018         .set_nmi = vmx_inject_nmi,
4019         .queue_exception = vmx_queue_exception,
4020         .interrupt_allowed = vmx_interrupt_allowed,
4021         .nmi_allowed = vmx_nmi_allowed,
4022         .enable_nmi_window = enable_nmi_window,
4023         .enable_irq_window = enable_irq_window,
4024         .update_cr8_intercept = update_cr8_intercept,
4025
4026         .set_tss_addr = vmx_set_tss_addr,
4027         .get_tdp_level = get_ept_level,
4028         .get_mt_mask = vmx_get_mt_mask,
4029
4030         .exit_reasons_str = vmx_exit_reasons_str,
4031         .gb_page_enable = vmx_gb_page_enable,
4032 };
4033
4034 static int __init vmx_init(void)
4035 {
4036         int r;
4037
4038         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4039         if (!vmx_io_bitmap_a)
4040                 return -ENOMEM;
4041
4042         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4043         if (!vmx_io_bitmap_b) {
4044                 r = -ENOMEM;
4045                 goto out;
4046         }
4047
4048         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4049         if (!vmx_msr_bitmap_legacy) {
4050                 r = -ENOMEM;
4051                 goto out1;
4052         }
4053
4054         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4055         if (!vmx_msr_bitmap_longmode) {
4056                 r = -ENOMEM;
4057                 goto out2;
4058         }
4059
4060         /*
4061          * Allow direct access to the PC debug port (it is often used for I/O
4062          * delays, but the vmexits simply slow things down).
4063          */
4064         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4065         clear_bit(0x80, vmx_io_bitmap_a);
4066
4067         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4068
4069         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4070         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4071
4072         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4073
4074         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
4075         if (r)
4076                 goto out3;
4077
4078         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4079         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4080         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4081         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4082         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4083         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4084
4085         if (enable_ept) {
4086                 bypass_guest_pf = 0;
4087                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4088                         VMX_EPT_WRITABLE_MASK);
4089                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4090                                 VMX_EPT_EXECUTABLE_MASK);
4091                 kvm_enable_tdp();
4092         } else
4093                 kvm_disable_tdp();
4094
4095         if (bypass_guest_pf)
4096                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4097
4098         return 0;
4099
4100 out3:
4101         free_page((unsigned long)vmx_msr_bitmap_longmode);
4102 out2:
4103         free_page((unsigned long)vmx_msr_bitmap_legacy);
4104 out1:
4105         free_page((unsigned long)vmx_io_bitmap_b);
4106 out:
4107         free_page((unsigned long)vmx_io_bitmap_a);
4108         return r;
4109 }
4110
4111 static void __exit vmx_exit(void)
4112 {
4113         free_page((unsigned long)vmx_msr_bitmap_legacy);
4114         free_page((unsigned long)vmx_msr_bitmap_longmode);
4115         free_page((unsigned long)vmx_io_bitmap_b);
4116         free_page((unsigned long)vmx_io_bitmap_a);
4117
4118         kvm_exit();
4119 }
4120
4121 module_init(vmx_init)
4122 module_exit(vmx_exit)