SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20 #include "kvm_cache_regs.h"
  21 #include "x86.h"
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/ftrace_event.h>
  29 #include <linux/slab.h>
  30
  31 #include <asm/desc.h>
  32
  33 #include <asm/virtext.h>
  34 #include "trace.h"
  35
  36 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  37
  38 MODULE_AUTHOR("Qumranet");
  39 MODULE_LICENSE("GPL");
  40
  41 #define IOPM_ALLOC_ORDER 2
  42 #define MSRPM_ALLOC_ORDER 1
  43
  44 #define SEG_TYPE_LDT 2
  45 #define SEG_TYPE_BUSY_TSS16 3
  46
  47 #define SVM_FEATURE_NPT  (1 << 0)
  48 #define SVM_FEATURE_LBRV (1 << 1)
  49 #define SVM_FEATURE_SVML (1 << 2)
  50 #define SVM_FEATURE_NRIP (1 << 3)
  51 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
  52
  53 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  54 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  55 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  56
  57 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  58
  59 static const u32 host_save_user_msrs[] = {
  60 #ifdef CONFIG_X86_64
  61         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  62         MSR_FS_BASE,
  63 #endif
  64         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  65 };
  66
  67 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  68
  69 struct kvm_vcpu;
  70
  71 struct nested_state {
  72         struct vmcb *hsave;
  73         u64 hsave_msr;
  74         u64 vm_cr_msr;
  75         u64 vmcb;
  76
  77         /* These are the merged vectors */
  78         u32 *msrpm;
  79
  80         /* gpa pointers to the real vectors */
  81         u64 vmcb_msrpm;
  82         u64 vmcb_iopm;
  83
  84         /* A VMEXIT is required but not yet emulated */
  85         bool exit_required;
  86
  87         /* cache for intercepts of the guest */
  88         u16 intercept_cr_read;
  89         u16 intercept_cr_write;
  90         u16 intercept_dr_read;
  91         u16 intercept_dr_write;
  92         u32 intercept_exceptions;
  93         u64 intercept;
  94
  95 };
  96
  97 #define MSRPM_OFFSETS   16
  98 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
  99
 100 struct vcpu_svm {
 101         struct kvm_vcpu vcpu;
 102         struct vmcb *vmcb;
 103         unsigned long vmcb_pa;
 104         struct svm_cpu_data *svm_data;
 105         uint64_t asid_generation;
 106         uint64_t sysenter_esp;
 107         uint64_t sysenter_eip;
 108
 109         u64 next_rip;
 110
 111         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 112         u64 host_gs_base;
 113
 114         u32 *msrpm;
 115
 116         struct nested_state nested;
 117
 118         bool nmi_singlestep;
 119
 120         unsigned int3_injected;
 121         unsigned long int3_rip;
 122 };
 123
 124 #define MSR_INVALID                     0xffffffffU
 125
 126 static struct svm_direct_access_msrs {
 127         u32 index;   /* Index of the MSR */
 128         bool always; /* True if intercept is always on */
 129 } direct_access_msrs[] = {
 130         { .index = MSR_K6_STAR,                         .always = true  },
 131         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 132 #ifdef CONFIG_X86_64
 133         { .index = MSR_GS_BASE,                         .always = true  },
 134         { .index = MSR_FS_BASE,                         .always = true  },
 135         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 136         { .index = MSR_LSTAR,                           .always = true  },
 137         { .index = MSR_CSTAR,                           .always = true  },
 138         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 139 #endif
 140         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 141         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 142         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 143         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 144         { .index = MSR_INVALID,                         .always = false },
 145 };
 146
 147 /* enable NPT for AMD64 and X86 with PAE */
 148 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 149 static bool npt_enabled = true;
 150 #else
 151 static bool npt_enabled;
 152 #endif
 153 static int npt = 1;
 154
 155 module_param(npt, int, S_IRUGO);
 156
 157 static int nested = 1;
 158 module_param(nested, int, S_IRUGO);
 159
 160 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 161 static void svm_complete_interrupts(struct vcpu_svm *svm);
 162
 163 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 164 static int nested_svm_intercept(struct vcpu_svm *svm);
 165 static int nested_svm_vmexit(struct vcpu_svm *svm);
 166 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 167                                       bool has_error_code, u32 error_code);
 168
 169 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 170 {
 171         return container_of(vcpu, struct vcpu_svm, vcpu);
 172 }
 173
 174 static inline bool is_nested(struct vcpu_svm *svm)
 175 {
 176         return svm->nested.vmcb;
 177 }
 178
 179 static inline void enable_gif(struct vcpu_svm *svm)
 180 {
 181         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 182 }
 183
 184 static inline void disable_gif(struct vcpu_svm *svm)
 185 {
 186         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 187 }
 188
 189 static inline bool gif_set(struct vcpu_svm *svm)
 190 {
 191         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 192 }
 193
 194 static unsigned long iopm_base;
 195
 196 struct kvm_ldttss_desc {
 197         u16 limit0;
 198         u16 base0;
 199         unsigned base1:8, type:5, dpl:2, p:1;
 200         unsigned limit1:4, zero0:3, g:1, base2:8;
 201         u32 base3;
 202         u32 zero1;
 203 } __attribute__((packed));
 204
 205 struct svm_cpu_data {
 206         int cpu;
 207
 208         u64 asid_generation;
 209         u32 max_asid;
 210         u32 next_asid;
 211         struct kvm_ldttss_desc *tss_desc;
 212
 213         struct page *save_area;
 214 };
 215
 216 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 217 static uint32_t svm_features;
 218
 219 struct svm_init_data {
 220         int cpu;
 221         int r;
 222 };
 223
 224 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 225
 226 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 227 #define MSRS_RANGE_SIZE 2048
 228 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 229
 230 static u32 svm_msrpm_offset(u32 msr)
 231 {
 232         u32 offset;
 233         int i;
 234
 235         for (i = 0; i < NUM_MSR_MAPS; i++) {
 236                 if (msr < msrpm_ranges[i] ||
 237                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 238                         continue;
 239
 240                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 241                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 242
 243                 /* Now we have the u8 offset - but need the u32 offset */
 244                 return offset / 4;
 245         }
 246
 247         /* MSR not in any range */
 248         return MSR_INVALID;
 249 }
 250
 251 #define MAX_INST_SIZE 15
 252
 253 static inline u32 svm_has(u32 feat)
 254 {
 255         return svm_features & feat;
 256 }
 257
 258 static inline void clgi(void)
 259 {
 260         asm volatile (__ex(SVM_CLGI));
 261 }
 262
 263 static inline void stgi(void)
 264 {
 265         asm volatile (__ex(SVM_STGI));
 266 }
 267
 268 static inline void invlpga(unsigned long addr, u32 asid)
 269 {
 270         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 271 }
 272
 273 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 274 {
 275         to_svm(vcpu)->asid_generation--;
 276 }
 277
 278 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 279 {
 280         force_new_asid(vcpu);
 281 }
 282
 283 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 284 {
 285         if (!npt_enabled && !(efer & EFER_LMA))
 286                 efer &= ~EFER_LME;
 287
 288         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 289         vcpu->arch.efer = efer;
 290 }
 291
 292 static int is_external_interrupt(u32 info)
 293 {
 294         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 295         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 296 }
 297
 298 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 299 {
 300         struct vcpu_svm *svm = to_svm(vcpu);
 301         u32 ret = 0;
 302
 303         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 304                 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 305         return ret & mask;
 306 }
 307
 308 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 309 {
 310         struct vcpu_svm *svm = to_svm(vcpu);
 311
 312         if (mask == 0)
 313                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 314         else
 315                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 316
 317 }
 318
 319 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 320 {
 321         struct vcpu_svm *svm = to_svm(vcpu);
 322
 323         if (!svm->next_rip) {
 324                 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
 325                                 EMULATE_DONE)
 326                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 327                 return;
 328         }
 329         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 330                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 331                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 332
 333         kvm_rip_write(vcpu, svm->next_rip);
 334         svm_set_interrupt_shadow(vcpu, 0);
 335 }
 336
 337 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 338                                 bool has_error_code, u32 error_code)
 339 {
 340         struct vcpu_svm *svm = to_svm(vcpu);
 341
 342         /*
 343          * If we are within a nested VM we'd better #VMEXIT and let the guest
 344          * handle the exception
 345          */
 346         if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
 347                 return;
 348
 349         if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
 350                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 351
 352                 /*
 353                  * For guest debugging where we have to reinject #BP if some
 354                  * INT3 is guest-owned:
 355                  * Emulate nRIP by moving RIP forward. Will fail if injection
 356                  * raises a fault that is not intercepted. Still better than
 357                  * failing in all cases.
 358                  */
 359                 skip_emulated_instruction(&svm->vcpu);
 360                 rip = kvm_rip_read(&svm->vcpu);
 361                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 362                 svm->int3_injected = rip - old_rip;
 363         }
 364
 365         svm->vmcb->control.event_inj = nr
 366                 | SVM_EVTINJ_VALID
 367                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 368                 | SVM_EVTINJ_TYPE_EXEPT;
 369         svm->vmcb->control.event_inj_err = error_code;
 370 }
 371
 372 static int has_svm(void)
 373 {
 374         const char *msg;
 375
 376         if (!cpu_has_svm(&msg)) {
 377                 printk(KERN_INFO "has_svm: %s\n", msg);
 378                 return 0;
 379         }
 380
 381         return 1;
 382 }
 383
 384 static void svm_hardware_disable(void *garbage)
 385 {
 386         cpu_svm_disable();
 387 }
 388
 389 static int svm_hardware_enable(void *garbage)
 390 {
 391
 392         struct svm_cpu_data *sd;
 393         uint64_t efer;
 394         struct desc_ptr gdt_descr;
 395         struct desc_struct *gdt;
 396         int me = raw_smp_processor_id();
 397
 398         rdmsrl(MSR_EFER, efer);
 399         if (efer & EFER_SVME)
 400                 return -EBUSY;
 401
 402         if (!has_svm()) {
 403                 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
 404                        me);
 405                 return -EINVAL;
 406         }
 407         sd = per_cpu(svm_data, me);
 408
 409         if (!sd) {
 410                 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
 411                        me);
 412                 return -EINVAL;
 413         }
 414
 415         sd->asid_generation = 1;
 416         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 417         sd->next_asid = sd->max_asid + 1;
 418
 419         native_store_gdt(&gdt_descr);
 420         gdt = (struct desc_struct *)gdt_descr.address;
 421         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 422
 423         wrmsrl(MSR_EFER, efer | EFER_SVME);
 424
 425         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 426
 427         return 0;
 428 }
 429
 430 static void svm_cpu_uninit(int cpu)
 431 {
 432         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 433
 434         if (!sd)
 435                 return;
 436
 437         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 438         __free_page(sd->save_area);
 439         kfree(sd);
 440 }
 441
 442 static int svm_cpu_init(int cpu)
 443 {
 444         struct svm_cpu_data *sd;
 445         int r;
 446
 447         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 448         if (!sd)
 449                 return -ENOMEM;
 450         sd->cpu = cpu;
 451         sd->save_area = alloc_page(GFP_KERNEL);
 452         r = -ENOMEM;
 453         if (!sd->save_area)
 454                 goto err_1;
 455
 456         per_cpu(svm_data, cpu) = sd;
 457
 458         return 0;
 459
 460 err_1:
 461         kfree(sd);
 462         return r;
 463
 464 }
 465
 466 static bool valid_msr_intercept(u32 index)
 467 {
 468         int i;
 469
 470         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 471                 if (direct_access_msrs[i].index == index)
 472                         return true;
 473
 474         return false;
 475 }
 476
 477 static void set_msr_interception(u32 *msrpm, unsigned msr,
 478                                  int read, int write)
 479 {
 480         u8 bit_read, bit_write;
 481         unsigned long tmp;
 482         u32 offset;
 483
 484         /*
 485          * If this warning triggers extend the direct_access_msrs list at the
 486          * beginning of the file
 487          */
 488         WARN_ON(!valid_msr_intercept(msr));
 489
 490         offset    = svm_msrpm_offset(msr);
 491         bit_read  = 2 * (msr & 0x0f);
 492         bit_write = 2 * (msr & 0x0f) + 1;
 493         tmp       = msrpm[offset];
 494
 495         BUG_ON(offset == MSR_INVALID);
 496
 497         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 498         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 499
 500         msrpm[offset] = tmp;
 501 }
 502
 503 static void svm_vcpu_init_msrpm(u32 *msrpm)
 504 {
 505         int i;
 506
 507         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 508
 509         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 510                 if (!direct_access_msrs[i].always)
 511                         continue;
 512
 513                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 514         }
 515 }
 516
 517 static void add_msr_offset(u32 offset)
 518 {
 519         int i;
 520
 521         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 522
 523                 /* Offset already in list? */
 524                 if (msrpm_offsets[i] == offset)
 525                         return;
 526
 527                 /* Slot used by another offset? */
 528                 if (msrpm_offsets[i] != MSR_INVALID)
 529                         continue;
 530
 531                 /* Add offset to list */
 532                 msrpm_offsets[i] = offset;
 533
 534                 return;
 535         }
 536
 537         /*
 538          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 539          * increase MSRPM_OFFSETS in this case.
 540          */
 541         BUG();
 542 }
 543
 544 static void init_msrpm_offsets(void)
 545 {
 546         int i;
 547
 548         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 549
 550         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 551                 u32 offset;
 552
 553                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 554                 BUG_ON(offset == MSR_INVALID);
 555
 556                 add_msr_offset(offset);
 557         }
 558 }
 559
 560 static void svm_enable_lbrv(struct vcpu_svm *svm)
 561 {
 562         u32 *msrpm = svm->msrpm;
 563
 564         svm->vmcb->control.lbr_ctl = 1;
 565         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 566         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 567         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 568         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 569 }
 570
 571 static void svm_disable_lbrv(struct vcpu_svm *svm)
 572 {
 573         u32 *msrpm = svm->msrpm;
 574
 575         svm->vmcb->control.lbr_ctl = 0;
 576         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 577         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 578         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 579         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 580 }
 581
 582 static __init int svm_hardware_setup(void)
 583 {
 584         int cpu;
 585         struct page *iopm_pages;
 586         void *iopm_va;
 587         int r;
 588
 589         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 590
 591         if (!iopm_pages)
 592                 return -ENOMEM;
 593
 594         iopm_va = page_address(iopm_pages);
 595         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 596         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 597
 598         init_msrpm_offsets();
 599
 600         if (boot_cpu_has(X86_FEATURE_NX))
 601                 kvm_enable_efer_bits(EFER_NX);
 602
 603         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 604                 kvm_enable_efer_bits(EFER_FFXSR);
 605
 606         if (nested) {
 607                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 608                 kvm_enable_efer_bits(EFER_SVME);
 609         }
 610
 611         for_each_possible_cpu(cpu) {
 612                 r = svm_cpu_init(cpu);
 613                 if (r)
 614                         goto err;
 615         }
 616
 617         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 618
 619         if (!svm_has(SVM_FEATURE_NPT))
 620                 npt_enabled = false;
 621
 622         if (npt_enabled && !npt) {
 623                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 624                 npt_enabled = false;
 625         }
 626
 627         if (npt_enabled) {
 628                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 629                 kvm_enable_tdp();
 630         } else
 631                 kvm_disable_tdp();
 632
 633         return 0;
 634
 635 err:
 636         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 637         iopm_base = 0;
 638         return r;
 639 }
 640
 641 static __exit void svm_hardware_unsetup(void)
 642 {
 643         int cpu;
 644
 645         for_each_possible_cpu(cpu)
 646                 svm_cpu_uninit(cpu);
 647
 648         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 649         iopm_base = 0;
 650 }
 651
 652 static void init_seg(struct vmcb_seg *seg)
 653 {
 654         seg->selector = 0;
 655         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 656                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 657         seg->limit = 0xffff;
 658         seg->base = 0;
 659 }
 660
 661 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 662 {
 663         seg->selector = 0;
 664         seg->attrib = SVM_SELECTOR_P_MASK | type;
 665         seg->limit = 0xffff;
 666         seg->base = 0;
 667 }
 668
 669 static void init_vmcb(struct vcpu_svm *svm)
 670 {
 671         struct vmcb_control_area *control = &svm->vmcb->control;
 672         struct vmcb_save_area *save = &svm->vmcb->save;
 673
 674         svm->vcpu.fpu_active = 1;
 675
 676         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 677                                         INTERCEPT_CR3_MASK |
 678                                         INTERCEPT_CR4_MASK;
 679
 680         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 681                                         INTERCEPT_CR3_MASK |
 682                                         INTERCEPT_CR4_MASK |
 683                                         INTERCEPT_CR8_MASK;
 684
 685         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 686                                         INTERCEPT_DR1_MASK |
 687                                         INTERCEPT_DR2_MASK |
 688                                         INTERCEPT_DR3_MASK |
 689                                         INTERCEPT_DR4_MASK |
 690                                         INTERCEPT_DR5_MASK |
 691                                         INTERCEPT_DR6_MASK |
 692                                         INTERCEPT_DR7_MASK;
 693
 694         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 695                                         INTERCEPT_DR1_MASK |
 696                                         INTERCEPT_DR2_MASK |
 697                                         INTERCEPT_DR3_MASK |
 698                                         INTERCEPT_DR4_MASK |
 699                                         INTERCEPT_DR5_MASK |
 700                                         INTERCEPT_DR6_MASK |
 701                                         INTERCEPT_DR7_MASK;
 702
 703         control->intercept_exceptions = (1 << PF_VECTOR) |
 704                                         (1 << UD_VECTOR) |
 705                                         (1 << MC_VECTOR);
 706
 707
 708         control->intercept =    (1ULL << INTERCEPT_INTR) |
 709                                 (1ULL << INTERCEPT_NMI) |
 710                                 (1ULL << INTERCEPT_SMI) |
 711                                 (1ULL << INTERCEPT_SELECTIVE_CR0) |
 712                                 (1ULL << INTERCEPT_CPUID) |
 713                                 (1ULL << INTERCEPT_INVD) |
 714                                 (1ULL << INTERCEPT_HLT) |
 715                                 (1ULL << INTERCEPT_INVLPG) |
 716                                 (1ULL << INTERCEPT_INVLPGA) |
 717                                 (1ULL << INTERCEPT_IOIO_PROT) |
 718                                 (1ULL << INTERCEPT_MSR_PROT) |
 719                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 720                                 (1ULL << INTERCEPT_SHUTDOWN) |
 721                                 (1ULL << INTERCEPT_VMRUN) |
 722                                 (1ULL << INTERCEPT_VMMCALL) |
 723                                 (1ULL << INTERCEPT_VMLOAD) |
 724                                 (1ULL << INTERCEPT_VMSAVE) |
 725                                 (1ULL << INTERCEPT_STGI) |
 726                                 (1ULL << INTERCEPT_CLGI) |
 727                                 (1ULL << INTERCEPT_SKINIT) |
 728                                 (1ULL << INTERCEPT_WBINVD) |
 729                                 (1ULL << INTERCEPT_MONITOR) |
 730                                 (1ULL << INTERCEPT_MWAIT);
 731
 732         control->iopm_base_pa = iopm_base;
 733         control->msrpm_base_pa = __pa(svm->msrpm);
 734         control->tsc_offset = 0;
 735         control->int_ctl = V_INTR_MASKING_MASK;
 736
 737         init_seg(&save->es);
 738         init_seg(&save->ss);
 739         init_seg(&save->ds);
 740         init_seg(&save->fs);
 741         init_seg(&save->gs);
 742
 743         save->cs.selector = 0xf000;
 744         /* Executable/Readable Code Segment */
 745         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 746                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 747         save->cs.limit = 0xffff;
 748         /*
 749          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 750          * be consistent with it.
 751          *
 752          * Replace when we have real mode working for vmx.
 753          */
 754         save->cs.base = 0xf0000;
 755
 756         save->gdtr.limit = 0xffff;
 757         save->idtr.limit = 0xffff;
 758
 759         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 760         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 761
 762         save->efer = EFER_SVME;
 763         save->dr6 = 0xffff0ff0;
 764         save->dr7 = 0x400;
 765         save->rflags = 2;
 766         save->rip = 0x0000fff0;
 767         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 768
 769         /*
 770          * This is the guest-visible cr0 value.
 771          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
 772          */
 773         svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
 774         kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
 775
 776         save->cr4 = X86_CR4_PAE;
 777         /* rdx = ?? */
 778
 779         if (npt_enabled) {
 780                 /* Setup VMCB for Nested Paging */
 781                 control->nested_ctl = 1;
 782                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 783                                         (1ULL << INTERCEPT_INVLPG));
 784                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 785                 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
 786                 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
 787                 save->g_pat = 0x0007040600070406ULL;
 788                 save->cr3 = 0;
 789                 save->cr4 = 0;
 790         }
 791         force_new_asid(&svm->vcpu);
 792
 793         svm->nested.vmcb = 0;
 794         svm->vcpu.arch.hflags = 0;
 795
 796         if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
 797                 control->pause_filter_count = 3000;
 798                 control->intercept |= (1ULL << INTERCEPT_PAUSE);
 799         }
 800
 801         enable_gif(svm);
 802 }
 803
 804 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 805 {
 806         struct vcpu_svm *svm = to_svm(vcpu);
 807
 808         init_vmcb(svm);
 809
 810         if (!kvm_vcpu_is_bsp(vcpu)) {
 811                 kvm_rip_write(vcpu, 0);
 812                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 813                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 814         }
 815         vcpu->arch.regs_avail = ~0;
 816         vcpu->arch.regs_dirty = ~0;
 817
 818         return 0;
 819 }
 820
 821 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 822 {
 823         struct vcpu_svm *svm;
 824         struct page *page;
 825         struct page *msrpm_pages;
 826         struct page *hsave_page;
 827         struct page *nested_msrpm_pages;
 828         int err;
 829
 830         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 831         if (!svm) {
 832                 err = -ENOMEM;
 833                 goto out;
 834         }
 835
 836         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 837         if (err)
 838                 goto free_svm;
 839
 840         err = -ENOMEM;
 841         page = alloc_page(GFP_KERNEL);
 842         if (!page)
 843                 goto uninit;
 844
 845         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 846         if (!msrpm_pages)
 847                 goto free_page1;
 848
 849         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 850         if (!nested_msrpm_pages)
 851                 goto free_page2;
 852
 853         hsave_page = alloc_page(GFP_KERNEL);
 854         if (!hsave_page)
 855                 goto free_page3;
 856
 857         svm->nested.hsave = page_address(hsave_page);
 858
 859         svm->msrpm = page_address(msrpm_pages);
 860         svm_vcpu_init_msrpm(svm->msrpm);
 861
 862         svm->nested.msrpm = page_address(nested_msrpm_pages);
 863         svm_vcpu_init_msrpm(svm->nested.msrpm);
 864
 865         svm->vmcb = page_address(page);
 866         clear_page(svm->vmcb);
 867         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 868         svm->asid_generation = 0;
 869         init_vmcb(svm);
 870
 871         fx_init(&svm->vcpu);
 872         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 873         if (kvm_vcpu_is_bsp(&svm->vcpu))
 874                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 875
 876         return &svm->vcpu;
 877
 878 free_page3:
 879         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
 880 free_page2:
 881         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
 882 free_page1:
 883         __free_page(page);
 884 uninit:
 885         kvm_vcpu_uninit(&svm->vcpu);
 886 free_svm:
 887         kmem_cache_free(kvm_vcpu_cache, svm);
 888 out:
 889         return ERR_PTR(err);
 890 }
 891
 892 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 893 {
 894         struct vcpu_svm *svm = to_svm(vcpu);
 895
 896         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 897         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 898         __free_page(virt_to_page(svm->nested.hsave));
 899         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
 900         kvm_vcpu_uninit(vcpu);
 901         kmem_cache_free(kvm_vcpu_cache, svm);
 902 }
 903
 904 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 905 {
 906         struct vcpu_svm *svm = to_svm(vcpu);
 907         int i;
 908
 909         if (unlikely(cpu != vcpu->cpu)) {
 910                 u64 delta;
 911
 912                 if (check_tsc_unstable()) {
 913                         /*
 914                          * Make sure that the guest sees a monotonically
 915                          * increasing TSC.
 916                          */
 917                         delta = vcpu->arch.host_tsc - native_read_tsc();
 918                         svm->vmcb->control.tsc_offset += delta;
 919                         if (is_nested(svm))
 920                                 svm->nested.hsave->control.tsc_offset += delta;
 921                 }
 922                 vcpu->cpu = cpu;
 923                 kvm_migrate_timers(vcpu);
 924                 svm->asid_generation = 0;
 925         }
 926
 927         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 928                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 929 }
 930
 931 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 932 {
 933         struct vcpu_svm *svm = to_svm(vcpu);
 934         int i;
 935
 936         ++vcpu->stat.host_state_reload;
 937         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 938                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 939
 940         vcpu->arch.host_tsc = native_read_tsc();
 941 }
 942
 943 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 944 {
 945         return to_svm(vcpu)->vmcb->save.rflags;
 946 }
 947
 948 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 949 {
 950         to_svm(vcpu)->vmcb->save.rflags = rflags;
 951 }
 952
 953 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
 954 {
 955         switch (reg) {
 956         case VCPU_EXREG_PDPTR:
 957                 BUG_ON(!npt_enabled);
 958                 load_pdptrs(vcpu, vcpu->arch.cr3);
 959                 break;
 960         default:
 961                 BUG();
 962         }
 963 }
 964
 965 static void svm_set_vintr(struct vcpu_svm *svm)
 966 {
 967         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 968 }
 969
 970 static void svm_clear_vintr(struct vcpu_svm *svm)
 971 {
 972         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 973 }
 974
 975 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 976 {
 977         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 978
 979         switch (seg) {
 980         case VCPU_SREG_CS: return &save->cs;
 981         case VCPU_SREG_DS: return &save->ds;
 982         case VCPU_SREG_ES: return &save->es;
 983         case VCPU_SREG_FS: return &save->fs;
 984         case VCPU_SREG_GS: return &save->gs;
 985         case VCPU_SREG_SS: return &save->ss;
 986         case VCPU_SREG_TR: return &save->tr;
 987         case VCPU_SREG_LDTR: return &save->ldtr;
 988         }
 989         BUG();
 990         return NULL;
 991 }
 992
 993 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 994 {
 995         struct vmcb_seg *s = svm_seg(vcpu, seg);
 996
 997         return s->base;
 998 }
 999
1000 static void svm_get_segment(struct kvm_vcpu *vcpu,
1001                             struct kvm_segment *var, int seg)
1002 {
1003         struct vmcb_seg *s = svm_seg(vcpu, seg);
1004
1005         var->base = s->base;
1006         var->limit = s->limit;
1007         var->selector = s->selector;
1008         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1009         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1010         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1011         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1012         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1013         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1014         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1015         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1016
1017         /*
1018          * AMD's VMCB does not have an explicit unusable field, so emulate it
1019          * for cross vendor migration purposes by "not present"
1020          */
1021         var->unusable = !var->present || (var->type == 0);
1022
1023         switch (seg) {
1024         case VCPU_SREG_CS:
1025                 /*
1026                  * SVM always stores 0 for the 'G' bit in the CS selector in
1027                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1028                  * Intel's VMENTRY has a check on the 'G' bit.
1029                  */
1030                 var->g = s->limit > 0xfffff;
1031                 break;
1032         case VCPU_SREG_TR:
1033                 /*
1034                  * Work around a bug where the busy flag in the tr selector
1035                  * isn't exposed
1036                  */
1037                 var->type |= 0x2;
1038                 break;
1039         case VCPU_SREG_DS:
1040         case VCPU_SREG_ES:
1041         case VCPU_SREG_FS:
1042         case VCPU_SREG_GS:
1043                 /*
1044                  * The accessed bit must always be set in the segment
1045                  * descriptor cache, although it can be cleared in the
1046                  * descriptor, the cached bit always remains at 1. Since
1047                  * Intel has a check on this, set it here to support
1048                  * cross-vendor migration.
1049                  */
1050                 if (!var->unusable)
1051                         var->type |= 0x1;
1052                 break;
1053         case VCPU_SREG_SS:
1054                 /*
1055                  * On AMD CPUs sometimes the DB bit in the segment
1056                  * descriptor is left as 1, although the whole segment has
1057                  * been made unusable. Clear it here to pass an Intel VMX
1058                  * entry check when cross vendor migrating.
1059                  */
1060                 if (var->unusable)
1061                         var->db = 0;
1062                 break;
1063         }
1064 }
1065
1066 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1067 {
1068         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1069
1070         return save->cpl;
1071 }
1072
1073 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1074 {
1075         struct vcpu_svm *svm = to_svm(vcpu);
1076
1077         dt->size = svm->vmcb->save.idtr.limit;
1078         dt->address = svm->vmcb->save.idtr.base;
1079 }
1080
1081 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1082 {
1083         struct vcpu_svm *svm = to_svm(vcpu);
1084
1085         svm->vmcb->save.idtr.limit = dt->size;
1086         svm->vmcb->save.idtr.base = dt->address ;
1087 }
1088
1089 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1090 {
1091         struct vcpu_svm *svm = to_svm(vcpu);
1092
1093         dt->size = svm->vmcb->save.gdtr.limit;
1094         dt->address = svm->vmcb->save.gdtr.base;
1095 }
1096
1097 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1098 {
1099         struct vcpu_svm *svm = to_svm(vcpu);
1100
1101         svm->vmcb->save.gdtr.limit = dt->size;
1102         svm->vmcb->save.gdtr.base = dt->address ;
1103 }
1104
1105 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1106 {
1107 }
1108
1109 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1110 {
1111 }
1112
1113 static void update_cr0_intercept(struct vcpu_svm *svm)
1114 {
1115         struct vmcb *vmcb = svm->vmcb;
1116         ulong gcr0 = svm->vcpu.arch.cr0;
1117         u64 *hcr0 = &svm->vmcb->save.cr0;
1118
1119         if (!svm->vcpu.fpu_active)
1120                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1121         else
1122                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1123                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1124
1125
1126         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1127                 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1128                 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1129                 if (is_nested(svm)) {
1130                         struct vmcb *hsave = svm->nested.hsave;
1131
1132                         hsave->control.intercept_cr_read  &= ~INTERCEPT_CR0_MASK;
1133                         hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1134                         vmcb->control.intercept_cr_read  |= svm->nested.intercept_cr_read;
1135                         vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1136                 }
1137         } else {
1138                 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1139                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1140                 if (is_nested(svm)) {
1141                         struct vmcb *hsave = svm->nested.hsave;
1142
1143                         hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1144                         hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1145                 }
1146         }
1147 }
1148
1149 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1150 {
1151         struct vcpu_svm *svm = to_svm(vcpu);
1152
1153         if (is_nested(svm)) {
1154                 /*
1155                  * We are here because we run in nested mode, the host kvm
1156                  * intercepts cr0 writes but the l1 hypervisor does not.
1157                  * But the L1 hypervisor may intercept selective cr0 writes.
1158                  * This needs to be checked here.
1159                  */
1160                 unsigned long old, new;
1161
1162                 /* Remove bits that would trigger a real cr0 write intercept */
1163                 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1164                 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1165
1166                 if (old == new) {
1167                         /* cr0 write with ts and mp unchanged */
1168                         svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1169                         if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE)
1170                                 return;
1171                 }
1172         }
1173
1174 #ifdef CONFIG_X86_64
1175         if (vcpu->arch.efer & EFER_LME) {
1176                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1177                         vcpu->arch.efer |= EFER_LMA;
1178                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1179                 }
1180
1181                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1182                         vcpu->arch.efer &= ~EFER_LMA;
1183                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1184                 }
1185         }
1186 #endif
1187         vcpu->arch.cr0 = cr0;
1188
1189         if (!npt_enabled)
1190                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1191
1192         if (!vcpu->fpu_active)
1193                 cr0 |= X86_CR0_TS;
1194         /*
1195          * re-enable caching here because the QEMU bios
1196          * does not do it - this results in some delay at
1197          * reboot
1198          */
1199         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1200         svm->vmcb->save.cr0 = cr0;
1201         update_cr0_intercept(svm);
1202 }
1203
1204 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1205 {
1206         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1207         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1208
1209         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1210                 force_new_asid(vcpu);
1211
1212         vcpu->arch.cr4 = cr4;
1213         if (!npt_enabled)
1214                 cr4 |= X86_CR4_PAE;
1215         cr4 |= host_cr4_mce;
1216         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1217 }
1218
1219 static void svm_set_segment(struct kvm_vcpu *vcpu,
1220                             struct kvm_segment *var, int seg)
1221 {
1222         struct vcpu_svm *svm = to_svm(vcpu);
1223         struct vmcb_seg *s = svm_seg(vcpu, seg);
1224
1225         s->base = var->base;
1226         s->limit = var->limit;
1227         s->selector = var->selector;
1228         if (var->unusable)
1229                 s->attrib = 0;
1230         else {
1231                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1232                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1233                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1234                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1235                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1236                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1237                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1238                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1239         }
1240         if (seg == VCPU_SREG_CS)
1241                 svm->vmcb->save.cpl
1242                         = (svm->vmcb->save.cs.attrib
1243                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1244
1245 }
1246
1247 static void update_db_intercept(struct kvm_vcpu *vcpu)
1248 {
1249         struct vcpu_svm *svm = to_svm(vcpu);
1250
1251         svm->vmcb->control.intercept_exceptions &=
1252                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1253
1254         if (svm->nmi_singlestep)
1255                 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1256
1257         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1258                 if (vcpu->guest_debug &
1259                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1260                         svm->vmcb->control.intercept_exceptions |=
1261                                 1 << DB_VECTOR;
1262                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1263                         svm->vmcb->control.intercept_exceptions |=
1264                                 1 << BP_VECTOR;
1265         } else
1266                 vcpu->guest_debug = 0;
1267 }
1268
1269 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1270 {
1271         struct vcpu_svm *svm = to_svm(vcpu);
1272
1273         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1274                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1275         else
1276                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1277
1278         update_db_intercept(vcpu);
1279 }
1280
1281 static void load_host_msrs(struct kvm_vcpu *vcpu)
1282 {
1283 #ifdef CONFIG_X86_64
1284         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1285 #endif
1286 }
1287
1288 static void save_host_msrs(struct kvm_vcpu *vcpu)
1289 {
1290 #ifdef CONFIG_X86_64
1291         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1292 #endif
1293 }
1294
1295 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1296 {
1297         if (sd->next_asid > sd->max_asid) {
1298                 ++sd->asid_generation;
1299                 sd->next_asid = 1;
1300                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1301         }
1302
1303         svm->asid_generation = sd->asid_generation;
1304         svm->vmcb->control.asid = sd->next_asid++;
1305 }
1306
1307 static int svm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *dest)
1308 {
1309         struct vcpu_svm *svm = to_svm(vcpu);
1310
1311         switch (dr) {
1312         case 0 ... 3:
1313                 *dest = vcpu->arch.db[dr];
1314                 break;
1315         case 4:
1316                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1317                         return EMULATE_FAIL; /* will re-inject UD */
1318                 /* fall through */
1319         case 6:
1320                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1321                         *dest = vcpu->arch.dr6;
1322                 else
1323                         *dest = svm->vmcb->save.dr6;
1324                 break;
1325         case 5:
1326                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1327                         return EMULATE_FAIL; /* will re-inject UD */
1328                 /* fall through */
1329         case 7:
1330                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1331                         *dest = vcpu->arch.dr7;
1332                 else
1333                         *dest = svm->vmcb->save.dr7;
1334                 break;
1335         }
1336
1337         return EMULATE_DONE;
1338 }
1339
1340 static int svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value)
1341 {
1342         struct vcpu_svm *svm = to_svm(vcpu);
1343
1344         switch (dr) {
1345         case 0 ... 3:
1346                 vcpu->arch.db[dr] = value;
1347                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1348                         vcpu->arch.eff_db[dr] = value;
1349                 break;
1350         case 4:
1351                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1352                         return EMULATE_FAIL; /* will re-inject UD */
1353                 /* fall through */
1354         case 6:
1355                 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1356                 break;
1357         case 5:
1358                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1359                         return EMULATE_FAIL; /* will re-inject UD */
1360                 /* fall through */
1361         case 7:
1362                 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1363                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1364                         svm->vmcb->save.dr7 = vcpu->arch.dr7;
1365                         vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1366                 }
1367                 break;
1368         }
1369
1370         return EMULATE_DONE;
1371 }
1372
1373 static int pf_interception(struct vcpu_svm *svm)
1374 {
1375         u64 fault_address;
1376         u32 error_code;
1377
1378         fault_address  = svm->vmcb->control.exit_info_2;
1379         error_code = svm->vmcb->control.exit_info_1;
1380
1381         trace_kvm_page_fault(fault_address, error_code);
1382         if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1383                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1384         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1385 }
1386
1387 static int db_interception(struct vcpu_svm *svm)
1388 {
1389         struct kvm_run *kvm_run = svm->vcpu.run;
1390
1391         if (!(svm->vcpu.guest_debug &
1392               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1393                 !svm->nmi_singlestep) {
1394                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1395                 return 1;
1396         }
1397
1398         if (svm->nmi_singlestep) {
1399                 svm->nmi_singlestep = false;
1400                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1401                         svm->vmcb->save.rflags &=
1402                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1403                 update_db_intercept(&svm->vcpu);
1404         }
1405
1406         if (svm->vcpu.guest_debug &
1407             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1408                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1409                 kvm_run->debug.arch.pc =
1410                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1411                 kvm_run->debug.arch.exception = DB_VECTOR;
1412                 return 0;
1413         }
1414
1415         return 1;
1416 }
1417
1418 static int bp_interception(struct vcpu_svm *svm)
1419 {
1420         struct kvm_run *kvm_run = svm->vcpu.run;
1421
1422         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1423         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1424         kvm_run->debug.arch.exception = BP_VECTOR;
1425         return 0;
1426 }
1427
1428 static int ud_interception(struct vcpu_svm *svm)
1429 {
1430         int er;
1431
1432         er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1433         if (er != EMULATE_DONE)
1434                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1435         return 1;
1436 }
1437
1438 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1439 {
1440         struct vcpu_svm *svm = to_svm(vcpu);
1441         u32 excp;
1442
1443         if (is_nested(svm)) {
1444                 u32 h_excp, n_excp;
1445
1446                 h_excp  = svm->nested.hsave->control.intercept_exceptions;
1447                 n_excp  = svm->nested.intercept_exceptions;
1448                 h_excp &= ~(1 << NM_VECTOR);
1449                 excp    = h_excp | n_excp;
1450         } else {
1451                 excp  = svm->vmcb->control.intercept_exceptions;
1452                 excp &= ~(1 << NM_VECTOR);
1453         }
1454
1455         svm->vmcb->control.intercept_exceptions = excp;
1456
1457         svm->vcpu.fpu_active = 1;
1458         update_cr0_intercept(svm);
1459 }
1460
1461 static int nm_interception(struct vcpu_svm *svm)
1462 {
1463         svm_fpu_activate(&svm->vcpu);
1464         return 1;
1465 }
1466
1467 static int mc_interception(struct vcpu_svm *svm)
1468 {
1469         /*
1470          * On an #MC intercept the MCE handler is not called automatically in
1471          * the host. So do it by hand here.
1472          */
1473         asm volatile (
1474                 "int $0x12\n");
1475         /* not sure if we ever come back to this point */
1476
1477         return 1;
1478 }
1479
1480 static int shutdown_interception(struct vcpu_svm *svm)
1481 {
1482         struct kvm_run *kvm_run = svm->vcpu.run;
1483
1484         /*
1485          * VMCB is undefined after a SHUTDOWN intercept
1486          * so reinitialize it.
1487          */
1488         clear_page(svm->vmcb);
1489         init_vmcb(svm);
1490
1491         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1492         return 0;
1493 }
1494
1495 static int io_interception(struct vcpu_svm *svm)
1496 {
1497         struct kvm_vcpu *vcpu = &svm->vcpu;
1498         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1499         int size, in, string;
1500         unsigned port;
1501
1502         ++svm->vcpu.stat.io_exits;
1503         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1504         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1505         if (string || in)
1506                 return !(emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO);
1507
1508         port = io_info >> 16;
1509         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1510         svm->next_rip = svm->vmcb->control.exit_info_2;
1511         skip_emulated_instruction(&svm->vcpu);
1512
1513         return kvm_fast_pio_out(vcpu, size, port);
1514 }
1515
1516 static int nmi_interception(struct vcpu_svm *svm)
1517 {
1518         return 1;
1519 }
1520
1521 static int intr_interception(struct vcpu_svm *svm)
1522 {
1523         ++svm->vcpu.stat.irq_exits;
1524         return 1;
1525 }
1526
1527 static int nop_on_interception(struct vcpu_svm *svm)
1528 {
1529         return 1;
1530 }
1531
1532 static int halt_interception(struct vcpu_svm *svm)
1533 {
1534         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1535         skip_emulated_instruction(&svm->vcpu);
1536         return kvm_emulate_halt(&svm->vcpu);
1537 }
1538
1539 static int vmmcall_interception(struct vcpu_svm *svm)
1540 {
1541         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1542         skip_emulated_instruction(&svm->vcpu);
1543         kvm_emulate_hypercall(&svm->vcpu);
1544         return 1;
1545 }
1546
1547 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1548 {
1549         if (!(svm->vcpu.arch.efer & EFER_SVME)
1550             || !is_paging(&svm->vcpu)) {
1551                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1552                 return 1;
1553         }
1554
1555         if (svm->vmcb->save.cpl) {
1556                 kvm_inject_gp(&svm->vcpu, 0);
1557                 return 1;
1558         }
1559
1560        return 0;
1561 }
1562
1563 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1564                                       bool has_error_code, u32 error_code)
1565 {
1566         int vmexit;
1567
1568         if (!is_nested(svm))
1569                 return 0;
1570
1571         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1572         svm->vmcb->control.exit_code_hi = 0;
1573         svm->vmcb->control.exit_info_1 = error_code;
1574         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1575
1576         vmexit = nested_svm_intercept(svm);
1577         if (vmexit == NESTED_EXIT_DONE)
1578                 svm->nested.exit_required = true;
1579
1580         return vmexit;
1581 }
1582
1583 /* This function returns true if it is save to enable the irq window */
1584 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1585 {
1586         if (!is_nested(svm))
1587                 return true;
1588
1589         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1590                 return true;
1591
1592         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1593                 return false;
1594
1595         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
1596         svm->vmcb->control.exit_info_1 = 0;
1597         svm->vmcb->control.exit_info_2 = 0;
1598
1599         if (svm->nested.intercept & 1ULL) {
1600                 /*
1601                  * The #vmexit can't be emulated here directly because this
1602                  * code path runs with irqs and preemtion disabled. A
1603                  * #vmexit emulation might sleep. Only signal request for
1604                  * the #vmexit here.
1605                  */
1606                 svm->nested.exit_required = true;
1607                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1608                 return false;
1609         }
1610
1611         return true;
1612 }
1613
1614 /* This function returns true if it is save to enable the nmi window */
1615 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1616 {
1617         if (!is_nested(svm))
1618                 return true;
1619
1620         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1621                 return true;
1622
1623         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1624         svm->nested.exit_required = true;
1625
1626         return false;
1627 }
1628
1629 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1630 {
1631         struct page *page;
1632
1633         might_sleep();
1634
1635         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1636         if (is_error_page(page))
1637                 goto error;
1638
1639         *_page = page;
1640
1641         return kmap(page);
1642
1643 error:
1644         kvm_release_page_clean(page);
1645         kvm_inject_gp(&svm->vcpu, 0);
1646
1647         return NULL;
1648 }
1649
1650 static void nested_svm_unmap(struct page *page)
1651 {
1652         kunmap(page);
1653         kvm_release_page_dirty(page);
1654 }
1655
1656 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1657 {
1658         unsigned port;
1659         u8 val, bit;
1660         u64 gpa;
1661
1662         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1663                 return NESTED_EXIT_HOST;
1664
1665         port = svm->vmcb->control.exit_info_1 >> 16;
1666         gpa  = svm->nested.vmcb_iopm + (port / 8);
1667         bit  = port % 8;
1668         val  = 0;
1669
1670         if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1671                 val &= (1 << bit);
1672
1673         return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1674 }
1675
1676 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1677 {
1678         u32 offset, msr, value;
1679         int write, mask;
1680
1681         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1682                 return NESTED_EXIT_HOST;
1683
1684         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1685         offset = svm_msrpm_offset(msr);
1686         write  = svm->vmcb->control.exit_info_1 & 1;
1687         mask   = 1 << ((2 * (msr & 0xf)) + write);
1688
1689         if (offset == MSR_INVALID)
1690                 return NESTED_EXIT_DONE;
1691
1692         /* Offset is in 32 bit units but need in 8 bit units */
1693         offset *= 4;
1694
1695         if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1696                 return NESTED_EXIT_DONE;
1697
1698         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1699 }
1700
1701 static int nested_svm_exit_special(struct vcpu_svm *svm)
1702 {
1703         u32 exit_code = svm->vmcb->control.exit_code;
1704
1705         switch (exit_code) {
1706         case SVM_EXIT_INTR:
1707         case SVM_EXIT_NMI:
1708                 return NESTED_EXIT_HOST;
1709         case SVM_EXIT_NPF:
1710                 /* For now we are always handling NPFs when using them */
1711                 if (npt_enabled)
1712                         return NESTED_EXIT_HOST;
1713                 break;
1714         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1715                 /* When we're shadowing, trap PFs */
1716                 if (!npt_enabled)
1717                         return NESTED_EXIT_HOST;
1718                 break;
1719         case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1720                 nm_interception(svm);
1721                 break;
1722         default:
1723                 break;
1724         }
1725
1726         return NESTED_EXIT_CONTINUE;
1727 }
1728
1729 /*
1730  * If this function returns true, this #vmexit was already handled
1731  */
1732 static int nested_svm_intercept(struct vcpu_svm *svm)
1733 {
1734         u32 exit_code = svm->vmcb->control.exit_code;
1735         int vmexit = NESTED_EXIT_HOST;
1736
1737         switch (exit_code) {
1738         case SVM_EXIT_MSR:
1739                 vmexit = nested_svm_exit_handled_msr(svm);
1740                 break;
1741         case SVM_EXIT_IOIO:
1742                 vmexit = nested_svm_intercept_ioio(svm);
1743                 break;
1744         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1745                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1746                 if (svm->nested.intercept_cr_read & cr_bits)
1747                         vmexit = NESTED_EXIT_DONE;
1748                 break;
1749         }
1750         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1751                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1752                 if (svm->nested.intercept_cr_write & cr_bits)
1753                         vmexit = NESTED_EXIT_DONE;
1754                 break;
1755         }
1756         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1757                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1758                 if (svm->nested.intercept_dr_read & dr_bits)
1759                         vmexit = NESTED_EXIT_DONE;
1760                 break;
1761         }
1762         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1763                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1764                 if (svm->nested.intercept_dr_write & dr_bits)
1765                         vmexit = NESTED_EXIT_DONE;
1766                 break;
1767         }
1768         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1769                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1770                 if (svm->nested.intercept_exceptions & excp_bits)
1771                         vmexit = NESTED_EXIT_DONE;
1772                 break;
1773         }
1774         default: {
1775                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1776                 if (svm->nested.intercept & exit_bits)
1777                         vmexit = NESTED_EXIT_DONE;
1778         }
1779         }
1780
1781         return vmexit;
1782 }
1783
1784 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1785 {
1786         int vmexit;
1787
1788         vmexit = nested_svm_intercept(svm);
1789
1790         if (vmexit == NESTED_EXIT_DONE)
1791                 nested_svm_vmexit(svm);
1792
1793         return vmexit;
1794 }
1795
1796 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1797 {
1798         struct vmcb_control_area *dst  = &dst_vmcb->control;
1799         struct vmcb_control_area *from = &from_vmcb->control;
1800
1801         dst->intercept_cr_read    = from->intercept_cr_read;
1802         dst->intercept_cr_write   = from->intercept_cr_write;
1803         dst->intercept_dr_read    = from->intercept_dr_read;
1804         dst->intercept_dr_write   = from->intercept_dr_write;
1805         dst->intercept_exceptions = from->intercept_exceptions;
1806         dst->intercept            = from->intercept;
1807         dst->iopm_base_pa         = from->iopm_base_pa;
1808         dst->msrpm_base_pa        = from->msrpm_base_pa;
1809         dst->tsc_offset           = from->tsc_offset;
1810         dst->asid                 = from->asid;
1811         dst->tlb_ctl              = from->tlb_ctl;
1812         dst->int_ctl              = from->int_ctl;
1813         dst->int_vector           = from->int_vector;
1814         dst->int_state            = from->int_state;
1815         dst->exit_code            = from->exit_code;
1816         dst->exit_code_hi         = from->exit_code_hi;
1817         dst->exit_info_1          = from->exit_info_1;
1818         dst->exit_info_2          = from->exit_info_2;
1819         dst->exit_int_info        = from->exit_int_info;
1820         dst->exit_int_info_err    = from->exit_int_info_err;
1821         dst->nested_ctl           = from->nested_ctl;
1822         dst->event_inj            = from->event_inj;
1823         dst->event_inj_err        = from->event_inj_err;
1824         dst->nested_cr3           = from->nested_cr3;
1825         dst->lbr_ctl              = from->lbr_ctl;
1826 }
1827
1828 static int nested_svm_vmexit(struct vcpu_svm *svm)
1829 {
1830         struct vmcb *nested_vmcb;
1831         struct vmcb *hsave = svm->nested.hsave;
1832         struct vmcb *vmcb = svm->vmcb;
1833         struct page *page;
1834
1835         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1836                                        vmcb->control.exit_info_1,
1837                                        vmcb->control.exit_info_2,
1838                                        vmcb->control.exit_int_info,
1839                                        vmcb->control.exit_int_info_err);
1840
1841         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
1842         if (!nested_vmcb)
1843                 return 1;
1844
1845         /* Exit nested SVM mode */
1846         svm->nested.vmcb = 0;
1847
1848         /* Give the current vmcb to the guest */
1849         disable_gif(svm);
1850
1851         nested_vmcb->save.es     = vmcb->save.es;
1852         nested_vmcb->save.cs     = vmcb->save.cs;
1853         nested_vmcb->save.ss     = vmcb->save.ss;
1854         nested_vmcb->save.ds     = vmcb->save.ds;
1855         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
1856         nested_vmcb->save.idtr   = vmcb->save.idtr;
1857         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
1858         if (npt_enabled)
1859                 nested_vmcb->save.cr3    = vmcb->save.cr3;
1860         else
1861                 nested_vmcb->save.cr3    = svm->vcpu.arch.cr3;
1862         nested_vmcb->save.cr2    = vmcb->save.cr2;
1863         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
1864         nested_vmcb->save.rflags = vmcb->save.rflags;
1865         nested_vmcb->save.rip    = vmcb->save.rip;
1866         nested_vmcb->save.rsp    = vmcb->save.rsp;
1867         nested_vmcb->save.rax    = vmcb->save.rax;
1868         nested_vmcb->save.dr7    = vmcb->save.dr7;
1869         nested_vmcb->save.dr6    = vmcb->save.dr6;
1870         nested_vmcb->save.cpl    = vmcb->save.cpl;
1871
1872         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
1873         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
1874         nested_vmcb->control.int_state         = vmcb->control.int_state;
1875         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
1876         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
1877         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
1878         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
1879         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
1880         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1881
1882         /*
1883          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1884          * to make sure that we do not lose injected events. So check event_inj
1885          * here and copy it to exit_int_info if it is valid.
1886          * Exit_int_info and event_inj can't be both valid because the case
1887          * below only happens on a VMRUN instruction intercept which has
1888          * no valid exit_int_info set.
1889          */
1890         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1891                 struct vmcb_control_area *nc = &nested_vmcb->control;
1892
1893                 nc->exit_int_info     = vmcb->control.event_inj;
1894                 nc->exit_int_info_err = vmcb->control.event_inj_err;
1895         }
1896
1897         nested_vmcb->control.tlb_ctl           = 0;
1898         nested_vmcb->control.event_inj         = 0;
1899         nested_vmcb->control.event_inj_err     = 0;
1900
1901         /* We always set V_INTR_MASKING and remember the old value in hflags */
1902         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1903                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1904
1905         /* Restore the original control entries */
1906         copy_vmcb_control_area(vmcb, hsave);
1907
1908         kvm_clear_exception_queue(&svm->vcpu);
1909         kvm_clear_interrupt_queue(&svm->vcpu);
1910
1911         /* Restore selected save entries */
1912         svm->vmcb->save.es = hsave->save.es;
1913         svm->vmcb->save.cs = hsave->save.cs;
1914         svm->vmcb->save.ss = hsave->save.ss;
1915         svm->vmcb->save.ds = hsave->save.ds;
1916         svm->vmcb->save.gdtr = hsave->save.gdtr;
1917         svm->vmcb->save.idtr = hsave->save.idtr;
1918         svm->vmcb->save.rflags = hsave->save.rflags;
1919         svm_set_efer(&svm->vcpu, hsave->save.efer);
1920         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1921         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1922         if (npt_enabled) {
1923                 svm->vmcb->save.cr3 = hsave->save.cr3;
1924                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1925         } else {
1926                 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1927         }
1928         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1929         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1930         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1931         svm->vmcb->save.dr7 = 0;
1932         svm->vmcb->save.cpl = 0;
1933         svm->vmcb->control.exit_int_info = 0;
1934
1935         nested_svm_unmap(page);
1936
1937         kvm_mmu_reset_context(&svm->vcpu);
1938         kvm_mmu_load(&svm->vcpu);
1939
1940         return 0;
1941 }
1942
1943 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1944 {
1945         /*
1946          * This function merges the msr permission bitmaps of kvm and the
1947          * nested vmcb. It is omptimized in that it only merges the parts where
1948          * the kvm msr permission bitmap may contain zero bits
1949          */
1950         int i;
1951
1952         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1953                 return true;
1954
1955         for (i = 0; i < MSRPM_OFFSETS; i++) {
1956                 u32 value, p;
1957                 u64 offset;
1958
1959                 if (msrpm_offsets[i] == 0xffffffff)
1960                         break;
1961
1962                 p      = msrpm_offsets[i];
1963                 offset = svm->nested.vmcb_msrpm + (p * 4);
1964
1965                 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
1966                         return false;
1967
1968                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
1969         }
1970
1971         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
1972
1973         return true;
1974 }
1975
1976 static bool nested_svm_vmrun(struct vcpu_svm *svm)
1977 {
1978         struct vmcb *nested_vmcb;
1979         struct vmcb *hsave = svm->nested.hsave;
1980         struct vmcb *vmcb = svm->vmcb;
1981         struct page *page;
1982         u64 vmcb_gpa;
1983
1984         vmcb_gpa = svm->vmcb->save.rax;
1985
1986         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
1987         if (!nested_vmcb)
1988                 return false;
1989
1990         trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, vmcb_gpa,
1991                                nested_vmcb->save.rip,
1992                                nested_vmcb->control.int_ctl,
1993                                nested_vmcb->control.event_inj,
1994                                nested_vmcb->control.nested_ctl);
1995
1996         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
1997                                     nested_vmcb->control.intercept_cr_write,
1998                                     nested_vmcb->control.intercept_exceptions,
1999                                     nested_vmcb->control.intercept);
2000
2001         /* Clear internal status */
2002         kvm_clear_exception_queue(&svm->vcpu);
2003         kvm_clear_interrupt_queue(&svm->vcpu);
2004
2005         /*
2006          * Save the old vmcb, so we don't need to pick what we save, but can
2007          * restore everything when a VMEXIT occurs
2008          */
2009         hsave->save.es     = vmcb->save.es;
2010         hsave->save.cs     = vmcb->save.cs;
2011         hsave->save.ss     = vmcb->save.ss;
2012         hsave->save.ds     = vmcb->save.ds;
2013         hsave->save.gdtr   = vmcb->save.gdtr;
2014         hsave->save.idtr   = vmcb->save.idtr;
2015         hsave->save.efer   = svm->vcpu.arch.efer;
2016         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
2017         hsave->save.cr4    = svm->vcpu.arch.cr4;
2018         hsave->save.rflags = vmcb->save.rflags;
2019         hsave->save.rip    = svm->next_rip;
2020         hsave->save.rsp    = vmcb->save.rsp;
2021         hsave->save.rax    = vmcb->save.rax;
2022         if (npt_enabled)
2023                 hsave->save.cr3    = vmcb->save.cr3;
2024         else
2025                 hsave->save.cr3    = svm->vcpu.arch.cr3;
2026
2027         copy_vmcb_control_area(hsave, vmcb);
2028
2029         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2030                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2031         else
2032                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2033
2034         /* Load the nested guest state */
2035         svm->vmcb->save.es = nested_vmcb->save.es;
2036         svm->vmcb->save.cs = nested_vmcb->save.cs;
2037         svm->vmcb->save.ss = nested_vmcb->save.ss;
2038         svm->vmcb->save.ds = nested_vmcb->save.ds;
2039         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2040         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2041         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2042         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2043         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2044         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2045         if (npt_enabled) {
2046                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2047                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2048         } else
2049                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2050
2051         /* Guest paging mode is active - reset mmu */
2052         kvm_mmu_reset_context(&svm->vcpu);
2053
2054         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2055         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2056         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2057         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2058
2059         /* In case we don't even reach vcpu_run, the fields are not updated */
2060         svm->vmcb->save.rax = nested_vmcb->save.rax;
2061         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2062         svm->vmcb->save.rip = nested_vmcb->save.rip;
2063         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2064         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2065         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2066
2067         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2068         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2069
2070         /* cache intercepts */
2071         svm->nested.intercept_cr_read    = nested_vmcb->control.intercept_cr_read;
2072         svm->nested.intercept_cr_write   = nested_vmcb->control.intercept_cr_write;
2073         svm->nested.intercept_dr_read    = nested_vmcb->control.intercept_dr_read;
2074         svm->nested.intercept_dr_write   = nested_vmcb->control.intercept_dr_write;
2075         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2076         svm->nested.intercept            = nested_vmcb->control.intercept;
2077
2078         force_new_asid(&svm->vcpu);
2079         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2080         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2081                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2082         else
2083                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2084
2085         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2086                 /* We only want the cr8 intercept bits of the guest */
2087                 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2088                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2089         }
2090
2091         /*
2092          * We don't want a nested guest to be more powerful than the guest, so
2093          * all intercepts are ORed
2094          */
2095         svm->vmcb->control.intercept_cr_read |=
2096                 nested_vmcb->control.intercept_cr_read;
2097         svm->vmcb->control.intercept_cr_write |=
2098                 nested_vmcb->control.intercept_cr_write;
2099         svm->vmcb->control.intercept_dr_read |=
2100                 nested_vmcb->control.intercept_dr_read;
2101         svm->vmcb->control.intercept_dr_write |=
2102                 nested_vmcb->control.intercept_dr_write;
2103         svm->vmcb->control.intercept_exceptions |=
2104                 nested_vmcb->control.intercept_exceptions;
2105
2106         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2107
2108         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2109         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2110         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2111         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2112         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2113         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2114
2115         nested_svm_unmap(page);
2116
2117         /* nested_vmcb is our indicator if nested SVM is activated */
2118         svm->nested.vmcb = vmcb_gpa;
2119
2120         enable_gif(svm);
2121
2122         return true;
2123 }
2124
2125 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2126 {
2127         to_vmcb->save.fs = from_vmcb->save.fs;
2128         to_vmcb->save.gs = from_vmcb->save.gs;
2129         to_vmcb->save.tr = from_vmcb->save.tr;
2130         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2131         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2132         to_vmcb->save.star = from_vmcb->save.star;
2133         to_vmcb->save.lstar = from_vmcb->save.lstar;
2134         to_vmcb->save.cstar = from_vmcb->save.cstar;
2135         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2136         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2137         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2138         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2139 }
2140
2141 static int vmload_interception(struct vcpu_svm *svm)
2142 {
2143         struct vmcb *nested_vmcb;
2144         struct page *page;
2145
2146         if (nested_svm_check_permissions(svm))
2147                 return 1;
2148
2149         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2150         skip_emulated_instruction(&svm->vcpu);
2151
2152         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2153         if (!nested_vmcb)
2154                 return 1;
2155
2156         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2157         nested_svm_unmap(page);
2158
2159         return 1;
2160 }
2161
2162 static int vmsave_interception(struct vcpu_svm *svm)
2163 {
2164         struct vmcb *nested_vmcb;
2165         struct page *page;
2166
2167         if (nested_svm_check_permissions(svm))
2168                 return 1;
2169
2170         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2171         skip_emulated_instruction(&svm->vcpu);
2172
2173         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2174         if (!nested_vmcb)
2175                 return 1;
2176
2177         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2178         nested_svm_unmap(page);
2179
2180         return 1;
2181 }
2182
2183 static int vmrun_interception(struct vcpu_svm *svm)
2184 {
2185         if (nested_svm_check_permissions(svm))
2186                 return 1;
2187
2188         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2189         skip_emulated_instruction(&svm->vcpu);
2190
2191         if (!nested_svm_vmrun(svm))
2192                 return 1;
2193
2194         if (!nested_svm_vmrun_msrpm(svm))
2195                 goto failed;
2196
2197         return 1;
2198
2199 failed:
2200
2201         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
2202         svm->vmcb->control.exit_code_hi = 0;
2203         svm->vmcb->control.exit_info_1  = 0;
2204         svm->vmcb->control.exit_info_2  = 0;
2205
2206         nested_svm_vmexit(svm);
2207
2208         return 1;
2209 }
2210
2211 static int stgi_interception(struct vcpu_svm *svm)
2212 {
2213         if (nested_svm_check_permissions(svm))
2214                 return 1;
2215
2216         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2217         skip_emulated_instruction(&svm->vcpu);
2218
2219         enable_gif(svm);
2220
2221         return 1;
2222 }
2223
2224 static int clgi_interception(struct vcpu_svm *svm)
2225 {
2226         if (nested_svm_check_permissions(svm))
2227                 return 1;
2228
2229         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2230         skip_emulated_instruction(&svm->vcpu);
2231
2232         disable_gif(svm);
2233
2234         /* After a CLGI no interrupts should come */
2235         svm_clear_vintr(svm);
2236         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2237
2238         return 1;
2239 }
2240
2241 static int invlpga_interception(struct vcpu_svm *svm)
2242 {
2243         struct kvm_vcpu *vcpu = &svm->vcpu;
2244
2245         trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2246                           vcpu->arch.regs[VCPU_REGS_RAX]);
2247
2248         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2249         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2250
2251         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2252         skip_emulated_instruction(&svm->vcpu);
2253         return 1;
2254 }
2255
2256 static int skinit_interception(struct vcpu_svm *svm)
2257 {
2258         trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2259
2260         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2261         return 1;
2262 }
2263
2264 static int invalid_op_interception(struct vcpu_svm *svm)
2265 {
2266         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2267         return 1;
2268 }
2269
2270 static int task_switch_interception(struct vcpu_svm *svm)
2271 {
2272         u16 tss_selector;
2273         int reason;
2274         int int_type = svm->vmcb->control.exit_int_info &
2275                 SVM_EXITINTINFO_TYPE_MASK;
2276         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2277         uint32_t type =
2278                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2279         uint32_t idt_v =
2280                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2281
2282         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2283
2284         if (svm->vmcb->control.exit_info_2 &
2285             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2286                 reason = TASK_SWITCH_IRET;
2287         else if (svm->vmcb->control.exit_info_2 &
2288                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2289                 reason = TASK_SWITCH_JMP;
2290         else if (idt_v)
2291                 reason = TASK_SWITCH_GATE;
2292         else
2293                 reason = TASK_SWITCH_CALL;
2294
2295         if (reason == TASK_SWITCH_GATE) {
2296                 switch (type) {
2297                 case SVM_EXITINTINFO_TYPE_NMI:
2298                         svm->vcpu.arch.nmi_injected = false;
2299                         break;
2300                 case SVM_EXITINTINFO_TYPE_EXEPT:
2301                         kvm_clear_exception_queue(&svm->vcpu);
2302                         break;
2303                 case SVM_EXITINTINFO_TYPE_INTR:
2304                         kvm_clear_interrupt_queue(&svm->vcpu);
2305                         break;
2306                 default:
2307                         break;
2308                 }
2309         }
2310
2311         if (reason != TASK_SWITCH_GATE ||
2312             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2313             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2314              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2315                 skip_emulated_instruction(&svm->vcpu);
2316
2317         return kvm_task_switch(&svm->vcpu, tss_selector, reason);
2318 }
2319
2320 static int cpuid_interception(struct vcpu_svm *svm)
2321 {
2322         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2323         kvm_emulate_cpuid(&svm->vcpu);
2324         return 1;
2325 }
2326
2327 static int iret_interception(struct vcpu_svm *svm)
2328 {
2329         ++svm->vcpu.stat.nmi_window_exits;
2330         svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2331         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2332         return 1;
2333 }
2334
2335 static int invlpg_interception(struct vcpu_svm *svm)
2336 {
2337         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2338                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2339         return 1;
2340 }
2341
2342 static int emulate_on_interception(struct vcpu_svm *svm)
2343 {
2344         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2345                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2346         return 1;
2347 }
2348
2349 static int cr8_write_interception(struct vcpu_svm *svm)
2350 {
2351         struct kvm_run *kvm_run = svm->vcpu.run;
2352
2353         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2354         /* instruction emulation calls kvm_set_cr8() */
2355         emulate_instruction(&svm->vcpu, 0, 0, 0);
2356         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2357                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2358                 return 1;
2359         }
2360         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2361                 return 1;
2362         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2363         return 0;
2364 }
2365
2366 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2367 {
2368         struct vcpu_svm *svm = to_svm(vcpu);
2369
2370         switch (ecx) {
2371         case MSR_IA32_TSC: {
2372                 u64 tsc_offset;
2373
2374                 if (is_nested(svm))
2375                         tsc_offset = svm->nested.hsave->control.tsc_offset;
2376                 else
2377                         tsc_offset = svm->vmcb->control.tsc_offset;
2378
2379                 *data = tsc_offset + native_read_tsc();
2380                 break;
2381         }
2382         case MSR_K6_STAR:
2383                 *data = svm->vmcb->save.star;
2384                 break;
2385 #ifdef CONFIG_X86_64
2386         case MSR_LSTAR:
2387                 *data = svm->vmcb->save.lstar;
2388                 break;
2389         case MSR_CSTAR:
2390                 *data = svm->vmcb->save.cstar;
2391                 break;
2392         case MSR_KERNEL_GS_BASE:
2393                 *data = svm->vmcb->save.kernel_gs_base;
2394                 break;
2395         case MSR_SYSCALL_MASK:
2396                 *data = svm->vmcb->save.sfmask;
2397                 break;
2398 #endif
2399         case MSR_IA32_SYSENTER_CS:
2400                 *data = svm->vmcb->save.sysenter_cs;
2401                 break;
2402         case MSR_IA32_SYSENTER_EIP:
2403                 *data = svm->sysenter_eip;
2404                 break;
2405         case MSR_IA32_SYSENTER_ESP:
2406                 *data = svm->sysenter_esp;
2407                 break;
2408         /*
2409          * Nobody will change the following 5 values in the VMCB so we can
2410          * safely return them on rdmsr. They will always be 0 until LBRV is
2411          * implemented.
2412          */
2413         case MSR_IA32_DEBUGCTLMSR:
2414                 *data = svm->vmcb->save.dbgctl;
2415                 break;
2416         case MSR_IA32_LASTBRANCHFROMIP:
2417                 *data = svm->vmcb->save.br_from;
2418                 break;
2419         case MSR_IA32_LASTBRANCHTOIP:
2420                 *data = svm->vmcb->save.br_to;
2421                 break;
2422         case MSR_IA32_LASTINTFROMIP:
2423                 *data = svm->vmcb->save.last_excp_from;
2424                 break;
2425         case MSR_IA32_LASTINTTOIP:
2426                 *data = svm->vmcb->save.last_excp_to;
2427                 break;
2428         case MSR_VM_HSAVE_PA:
2429                 *data = svm->nested.hsave_msr;
2430                 break;
2431         case MSR_VM_CR:
2432                 *data = svm->nested.vm_cr_msr;
2433                 break;
2434         case MSR_IA32_UCODE_REV:
2435                 *data = 0x01000065;
2436                 break;
2437         default:
2438                 return kvm_get_msr_common(vcpu, ecx, data);
2439         }
2440         return 0;
2441 }
2442
2443 static int rdmsr_interception(struct vcpu_svm *svm)
2444 {
2445         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2446         u64 data;
2447
2448         if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2449                 trace_kvm_msr_read_ex(ecx);
2450                 kvm_inject_gp(&svm->vcpu, 0);
2451         } else {
2452                 trace_kvm_msr_read(ecx, data);
2453
2454                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2455                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2456                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2457                 skip_emulated_instruction(&svm->vcpu);
2458         }
2459         return 1;
2460 }
2461
2462 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2463 {
2464         struct vcpu_svm *svm = to_svm(vcpu);
2465         int svm_dis, chg_mask;
2466
2467         if (data & ~SVM_VM_CR_VALID_MASK)
2468                 return 1;
2469
2470         chg_mask = SVM_VM_CR_VALID_MASK;
2471
2472         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2473                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2474
2475         svm->nested.vm_cr_msr &= ~chg_mask;
2476         svm->nested.vm_cr_msr |= (data & chg_mask);
2477
2478         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2479
2480         /* check for svm_disable while efer.svme is set */
2481         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2482                 return 1;
2483
2484         return 0;
2485 }
2486
2487 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2488 {
2489         struct vcpu_svm *svm = to_svm(vcpu);
2490
2491         switch (ecx) {
2492         case MSR_IA32_TSC: {
2493                 u64 tsc_offset = data - native_read_tsc();
2494                 u64 g_tsc_offset = 0;
2495
2496                 if (is_nested(svm)) {
2497                         g_tsc_offset = svm->vmcb->control.tsc_offset -
2498                                        svm->nested.hsave->control.tsc_offset;
2499                         svm->nested.hsave->control.tsc_offset = tsc_offset;
2500                 }
2501
2502                 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2503
2504                 break;
2505         }
2506         case MSR_K6_STAR:
2507                 svm->vmcb->save.star = data;
2508                 break;
2509 #ifdef CONFIG_X86_64
2510         case MSR_LSTAR:
2511                 svm->vmcb->save.lstar = data;
2512                 break;
2513         case MSR_CSTAR:
2514                 svm->vmcb->save.cstar = data;
2515                 break;
2516         case MSR_KERNEL_GS_BASE:
2517                 svm->vmcb->save.kernel_gs_base = data;
2518                 break;
2519         case MSR_SYSCALL_MASK:
2520                 svm->vmcb->save.sfmask = data;
2521                 break;
2522 #endif
2523         case MSR_IA32_SYSENTER_CS:
2524                 svm->vmcb->save.sysenter_cs = data;
2525                 break;
2526         case MSR_IA32_SYSENTER_EIP:
2527                 svm->sysenter_eip = data;
2528                 svm->vmcb->save.sysenter_eip = data;
2529                 break;
2530         case MSR_IA32_SYSENTER_ESP:
2531                 svm->sysenter_esp = data;
2532                 svm->vmcb->save.sysenter_esp = data;
2533                 break;
2534         case MSR_IA32_DEBUGCTLMSR:
2535                 if (!svm_has(SVM_FEATURE_LBRV)) {
2536                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2537                                         __func__, data);
2538                         break;
2539                 }
2540                 if (data & DEBUGCTL_RESERVED_BITS)
2541                         return 1;
2542
2543                 svm->vmcb->save.dbgctl = data;
2544                 if (data & (1ULL<<0))
2545                         svm_enable_lbrv(svm);
2546                 else
2547                         svm_disable_lbrv(svm);
2548                 break;
2549         case MSR_VM_HSAVE_PA:
2550                 svm->nested.hsave_msr = data;
2551                 break;
2552         case MSR_VM_CR:
2553                 return svm_set_vm_cr(vcpu, data);
2554         case MSR_VM_IGNNE:
2555                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2556                 break;
2557         default:
2558                 return kvm_set_msr_common(vcpu, ecx, data);
2559         }
2560         return 0;
2561 }
2562
2563 static int wrmsr_interception(struct vcpu_svm *svm)
2564 {
2565         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2566         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2567                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2568
2569
2570         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2571         if (svm_set_msr(&svm->vcpu, ecx, data)) {
2572                 trace_kvm_msr_write_ex(ecx, data);
2573                 kvm_inject_gp(&svm->vcpu, 0);
2574         } else {
2575                 trace_kvm_msr_write(ecx, data);
2576                 skip_emulated_instruction(&svm->vcpu);
2577         }
2578         return 1;
2579 }
2580
2581 static int msr_interception(struct vcpu_svm *svm)
2582 {
2583         if (svm->vmcb->control.exit_info_1)
2584                 return wrmsr_interception(svm);
2585         else
2586                 return rdmsr_interception(svm);
2587 }
2588
2589 static int interrupt_window_interception(struct vcpu_svm *svm)
2590 {
2591         struct kvm_run *kvm_run = svm->vcpu.run;
2592
2593         svm_clear_vintr(svm);
2594         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2595         /*
2596          * If the user space waits to inject interrupts, exit as soon as
2597          * possible
2598          */
2599         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2600             kvm_run->request_interrupt_window &&
2601             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2602                 ++svm->vcpu.stat.irq_window_exits;
2603                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2604                 return 0;
2605         }
2606
2607         return 1;
2608 }
2609
2610 static int pause_interception(struct vcpu_svm *svm)
2611 {
2612         kvm_vcpu_on_spin(&(svm->vcpu));
2613         return 1;
2614 }
2615
2616 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2617         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2618         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2619         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2620         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2621         [SVM_EXIT_CR0_SEL_WRITE]                = emulate_on_interception,
2622         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2623         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2624         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2625         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2626         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2627         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2628         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2629         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2630         [SVM_EXIT_READ_DR4]                     = emulate_on_interception,
2631         [SVM_EXIT_READ_DR5]                     = emulate_on_interception,
2632         [SVM_EXIT_READ_DR6]                     = emulate_on_interception,
2633         [SVM_EXIT_READ_DR7]                     = emulate_on_interception,
2634         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2635         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2636         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2637         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2638         [SVM_EXIT_WRITE_DR4]                    = emulate_on_interception,
2639         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2640         [SVM_EXIT_WRITE_DR6]                    = emulate_on_interception,
2641         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2642         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2643         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2644         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2645         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2646         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2647         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2648         [SVM_EXIT_INTR]                         = intr_interception,
2649         [SVM_EXIT_NMI]                          = nmi_interception,
2650         [SVM_EXIT_SMI]                          = nop_on_interception,
2651         [SVM_EXIT_INIT]                         = nop_on_interception,
2652         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2653         [SVM_EXIT_CPUID]                        = cpuid_interception,
2654         [SVM_EXIT_IRET]                         = iret_interception,
2655         [SVM_EXIT_INVD]                         = emulate_on_interception,
2656         [SVM_EXIT_PAUSE]                        = pause_interception,
2657         [SVM_EXIT_HLT]                          = halt_interception,
2658         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2659         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2660         [SVM_EXIT_IOIO]                         = io_interception,
2661         [SVM_EXIT_MSR]                          = msr_interception,
2662         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2663         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2664         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2665         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2666         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2667         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2668         [SVM_EXIT_STGI]                         = stgi_interception,
2669         [SVM_EXIT_CLGI]                         = clgi_interception,
2670         [SVM_EXIT_SKINIT]                       = skinit_interception,
2671         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2672         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2673         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2674         [SVM_EXIT_NPF]                          = pf_interception,
2675 };
2676
2677 static int handle_exit(struct kvm_vcpu *vcpu)
2678 {
2679         struct vcpu_svm *svm = to_svm(vcpu);
2680         struct kvm_run *kvm_run = vcpu->run;
2681         u32 exit_code = svm->vmcb->control.exit_code;
2682
2683         trace_kvm_exit(exit_code, vcpu);
2684
2685         if (unlikely(svm->nested.exit_required)) {
2686                 nested_svm_vmexit(svm);
2687                 svm->nested.exit_required = false;
2688
2689                 return 1;
2690         }
2691
2692         if (is_nested(svm)) {
2693                 int vmexit;
2694
2695                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2696                                         svm->vmcb->control.exit_info_1,
2697                                         svm->vmcb->control.exit_info_2,
2698                                         svm->vmcb->control.exit_int_info,
2699                                         svm->vmcb->control.exit_int_info_err);
2700
2701                 vmexit = nested_svm_exit_special(svm);
2702
2703                 if (vmexit == NESTED_EXIT_CONTINUE)
2704                         vmexit = nested_svm_exit_handled(svm);
2705
2706                 if (vmexit == NESTED_EXIT_DONE)
2707                         return 1;
2708         }
2709
2710         svm_complete_interrupts(svm);
2711
2712         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2713                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2714         if (npt_enabled)
2715                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2716
2717         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2718                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2719                 kvm_run->fail_entry.hardware_entry_failure_reason
2720                         = svm->vmcb->control.exit_code;
2721                 return 0;
2722         }
2723
2724         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2725             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2726             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2727                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2728                        "exit_code 0x%x\n",
2729                        __func__, svm->vmcb->control.exit_int_info,
2730                        exit_code);
2731
2732         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2733             || !svm_exit_handlers[exit_code]) {
2734                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2735                 kvm_run->hw.hardware_exit_reason = exit_code;
2736                 return 0;
2737         }
2738
2739         return svm_exit_handlers[exit_code](svm);
2740 }
2741
2742 static void reload_tss(struct kvm_vcpu *vcpu)
2743 {
2744         int cpu = raw_smp_processor_id();
2745
2746         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2747         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
2748         load_TR_desc();
2749 }
2750
2751 static void pre_svm_run(struct vcpu_svm *svm)
2752 {
2753         int cpu = raw_smp_processor_id();
2754
2755         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2756
2757         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2758         /* FIXME: handle wraparound of asid_generation */
2759         if (svm->asid_generation != sd->asid_generation)
2760                 new_asid(svm, sd);
2761 }
2762
2763 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2764 {
2765         struct vcpu_svm *svm = to_svm(vcpu);
2766
2767         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2768         vcpu->arch.hflags |= HF_NMI_MASK;
2769         svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2770         ++vcpu->stat.nmi_injections;
2771 }
2772
2773 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2774 {
2775         struct vmcb_control_area *control;
2776
2777         trace_kvm_inj_virq(irq);
2778
2779         ++svm->vcpu.stat.irq_injections;
2780         control = &svm->vmcb->control;
2781         control->int_vector = irq;
2782         control->int_ctl &= ~V_INTR_PRIO_MASK;
2783         control->int_ctl |= V_IRQ_MASK |
2784                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2785 }
2786
2787 static void svm_set_irq(struct kvm_vcpu *vcpu)
2788 {
2789         struct vcpu_svm *svm = to_svm(vcpu);
2790
2791         BUG_ON(!(gif_set(svm)));
2792
2793         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2794                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2795 }
2796
2797 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2798 {
2799         struct vcpu_svm *svm = to_svm(vcpu);
2800
2801         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2802                 return;
2803
2804         if (irr == -1)
2805                 return;
2806
2807         if (tpr >= irr)
2808                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2809 }
2810
2811 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2812 {
2813         struct vcpu_svm *svm = to_svm(vcpu);
2814         struct vmcb *vmcb = svm->vmcb;
2815         return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2816                 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2817 }
2818
2819 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2820 {
2821         struct vcpu_svm *svm = to_svm(vcpu);
2822
2823         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2824 }
2825
2826 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2827 {
2828         struct vcpu_svm *svm = to_svm(vcpu);
2829
2830         if (masked) {
2831                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2832                 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2833         } else {
2834                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2835                 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2836         }
2837 }
2838
2839 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2840 {
2841         struct vcpu_svm *svm = to_svm(vcpu);
2842         struct vmcb *vmcb = svm->vmcb;
2843         int ret;
2844
2845         if (!gif_set(svm) ||
2846              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2847                 return 0;
2848
2849         ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2850
2851         if (is_nested(svm))
2852                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2853
2854         return ret;
2855 }
2856
2857 static void enable_irq_window(struct kvm_vcpu *vcpu)
2858 {
2859         struct vcpu_svm *svm = to_svm(vcpu);
2860
2861         /*
2862          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
2863          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
2864          * get that intercept, this function will be called again though and
2865          * we'll get the vintr intercept.
2866          */
2867         if (gif_set(svm) && nested_svm_intr(svm)) {
2868                 svm_set_vintr(svm);
2869                 svm_inject_irq(svm, 0x0);
2870         }
2871 }
2872
2873 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2874 {
2875         struct vcpu_svm *svm = to_svm(vcpu);
2876
2877         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2878             == HF_NMI_MASK)
2879                 return; /* IRET will cause a vm exit */
2880
2881         /*
2882          * Something prevents NMI from been injected. Single step over possible
2883          * problem (IRET or exception injection or interrupt shadow)
2884          */
2885         if (gif_set(svm) && nested_svm_nmi(svm)) {
2886                 svm->nmi_singlestep = true;
2887                 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2888                 update_db_intercept(vcpu);
2889         }
2890 }
2891
2892 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2893 {
2894         return 0;
2895 }
2896
2897 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2898 {
2899         force_new_asid(vcpu);
2900 }
2901
2902 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2903 {
2904 }
2905
2906 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2907 {
2908         struct vcpu_svm *svm = to_svm(vcpu);
2909
2910         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2911                 return;
2912
2913         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2914                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2915                 kvm_set_cr8(vcpu, cr8);
2916         }
2917 }
2918
2919 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2920 {
2921         struct vcpu_svm *svm = to_svm(vcpu);
2922         u64 cr8;
2923
2924         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2925                 return;
2926
2927         cr8 = kvm_get_cr8(vcpu);
2928         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2929         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2930 }
2931
2932 static void svm_complete_interrupts(struct vcpu_svm *svm)
2933 {
2934         u8 vector;
2935         int type;
2936         u32 exitintinfo = svm->vmcb->control.exit_int_info;
2937         unsigned int3_injected = svm->int3_injected;
2938
2939         svm->int3_injected = 0;
2940
2941         if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2942                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2943
2944         svm->vcpu.arch.nmi_injected = false;
2945         kvm_clear_exception_queue(&svm->vcpu);
2946         kvm_clear_interrupt_queue(&svm->vcpu);
2947
2948         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2949                 return;
2950
2951         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2952         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2953
2954         switch (type) {
2955         case SVM_EXITINTINFO_TYPE_NMI:
2956                 svm->vcpu.arch.nmi_injected = true;
2957                 break;
2958         case SVM_EXITINTINFO_TYPE_EXEPT:
2959                 if (is_nested(svm))
2960                         break;
2961                 /*
2962                  * In case of software exceptions, do not reinject the vector,
2963                  * but re-execute the instruction instead. Rewind RIP first
2964                  * if we emulated INT3 before.
2965                  */
2966                 if (kvm_exception_is_soft(vector)) {
2967                         if (vector == BP_VECTOR && int3_injected &&
2968                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
2969                                 kvm_rip_write(&svm->vcpu,
2970                                               kvm_rip_read(&svm->vcpu) -
2971                                               int3_injected);
2972                         break;
2973                 }
2974                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2975                         u32 err = svm->vmcb->control.exit_int_info_err;
2976                         kvm_queue_exception_e(&svm->vcpu, vector, err);
2977
2978                 } else
2979                         kvm_queue_exception(&svm->vcpu, vector);
2980                 break;
2981         case SVM_EXITINTINFO_TYPE_INTR:
2982                 kvm_queue_interrupt(&svm->vcpu, vector, false);
2983                 break;
2984         default:
2985                 break;
2986         }
2987 }
2988
2989 #ifdef CONFIG_X86_64
2990 #define R "r"
2991 #else
2992 #define R "e"
2993 #endif
2994
2995 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
2996 {
2997         struct vcpu_svm *svm = to_svm(vcpu);
2998         u16 fs_selector;
2999         u16 gs_selector;
3000         u16 ldt_selector;
3001
3002         /*
3003          * A vmexit emulation is required before the vcpu can be executed
3004          * again.
3005          */
3006         if (unlikely(svm->nested.exit_required))
3007                 return;
3008
3009         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3010         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3011         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3012
3013         pre_svm_run(svm);
3014
3015         sync_lapic_to_cr8(vcpu);
3016
3017         save_host_msrs(vcpu);
3018         fs_selector = kvm_read_fs();
3019         gs_selector = kvm_read_gs();
3020         ldt_selector = kvm_read_ldt();
3021         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3022         /* required for live migration with NPT */
3023         if (npt_enabled)
3024                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
3025
3026         clgi();
3027
3028         local_irq_enable();
3029
3030         asm volatile (
3031                 "push %%"R"bp; \n\t"
3032                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3033                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3034                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3035                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3036                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3037                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3038 #ifdef CONFIG_X86_64
3039                 "mov %c[r8](%[svm]),  %%r8  \n\t"
3040                 "mov %c[r9](%[svm]),  %%r9  \n\t"
3041                 "mov %c[r10](%[svm]), %%r10 \n\t"
3042                 "mov %c[r11](%[svm]), %%r11 \n\t"
3043                 "mov %c[r12](%[svm]), %%r12 \n\t"
3044                 "mov %c[r13](%[svm]), %%r13 \n\t"
3045                 "mov %c[r14](%[svm]), %%r14 \n\t"
3046                 "mov %c[r15](%[svm]), %%r15 \n\t"
3047 #endif
3048
3049                 /* Enter guest mode */
3050                 "push %%"R"ax \n\t"
3051                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3052                 __ex(SVM_VMLOAD) "\n\t"
3053                 __ex(SVM_VMRUN) "\n\t"
3054                 __ex(SVM_VMSAVE) "\n\t"
3055                 "pop %%"R"ax \n\t"
3056
3057                 /* Save guest registers, load host registers */
3058                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3059                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3060                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3061                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3062                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3063                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3064 #ifdef CONFIG_X86_64
3065                 "mov %%r8,  %c[r8](%[svm]) \n\t"
3066                 "mov %%r9,  %c[r9](%[svm]) \n\t"
3067                 "mov %%r10, %c[r10](%[svm]) \n\t"
3068                 "mov %%r11, %c[r11](%[svm]) \n\t"
3069                 "mov %%r12, %c[r12](%[svm]) \n\t"
3070                 "mov %%r13, %c[r13](%[svm]) \n\t"
3071                 "mov %%r14, %c[r14](%[svm]) \n\t"
3072                 "mov %%r15, %c[r15](%[svm]) \n\t"
3073 #endif
3074                 "pop %%"R"bp"
3075                 :
3076                 : [svm]"a"(svm),
3077                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3078                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3079                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3080                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3081                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3082                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3083                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3084 #ifdef CONFIG_X86_64
3085                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3086                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3087                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3088                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3089                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3090                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3091                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3092                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3093 #endif
3094                 : "cc", "memory"
3095                 , R"bx", R"cx", R"dx", R"si", R"di"
3096 #ifdef CONFIG_X86_64
3097                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3098 #endif
3099                 );
3100
3101         vcpu->arch.cr2 = svm->vmcb->save.cr2;
3102         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3103         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3104         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3105
3106         kvm_load_fs(fs_selector);
3107         kvm_load_gs(gs_selector);
3108         kvm_load_ldt(ldt_selector);
3109         load_host_msrs(vcpu);
3110
3111         reload_tss(vcpu);
3112
3113         local_irq_disable();
3114
3115         stgi();
3116
3117         sync_cr8_to_lapic(vcpu);
3118
3119         svm->next_rip = 0;
3120
3121         if (npt_enabled) {
3122                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3123                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3124         }
3125 }
3126
3127 #undef R
3128
3129 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3130 {
3131         struct vcpu_svm *svm = to_svm(vcpu);
3132
3133         if (npt_enabled) {
3134                 svm->vmcb->control.nested_cr3 = root;
3135                 force_new_asid(vcpu);
3136                 return;
3137         }
3138
3139         svm->vmcb->save.cr3 = root;
3140         force_new_asid(vcpu);
3141 }
3142
3143 static int is_disabled(void)
3144 {
3145         u64 vm_cr;
3146
3147         rdmsrl(MSR_VM_CR, vm_cr);
3148         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3149                 return 1;
3150
3151         return 0;
3152 }
3153
3154 static void
3155 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3156 {
3157         /*
3158          * Patch in the VMMCALL instruction:
3159          */
3160         hypercall[0] = 0x0f;
3161         hypercall[1] = 0x01;
3162         hypercall[2] = 0xd9;
3163 }
3164
3165 static void svm_check_processor_compat(void *rtn)
3166 {
3167         *(int *)rtn = 0;
3168 }
3169
3170 static bool svm_cpu_has_accelerated_tpr(void)
3171 {
3172         return false;
3173 }
3174
3175 static int get_npt_level(void)
3176 {
3177 #ifdef CONFIG_X86_64
3178         return PT64_ROOT_LEVEL;
3179 #else
3180         return PT32E_ROOT_LEVEL;
3181 #endif
3182 }
3183
3184 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3185 {
3186         return 0;
3187 }
3188
3189 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3190 {
3191 }
3192
3193 static const struct trace_print_flags svm_exit_reasons_str[] = {
3194         { SVM_EXIT_READ_CR0,                    "read_cr0" },
3195         { SVM_EXIT_READ_CR3,                    "read_cr3" },
3196         { SVM_EXIT_READ_CR4,                    "read_cr4" },
3197         { SVM_EXIT_READ_CR8,                    "read_cr8" },
3198         { SVM_EXIT_WRITE_CR0,                   "write_cr0" },
3199         { SVM_EXIT_WRITE_CR3,                   "write_cr3" },
3200         { SVM_EXIT_WRITE_CR4,                   "write_cr4" },
3201         { SVM_EXIT_WRITE_CR8,                   "write_cr8" },
3202         { SVM_EXIT_READ_DR0,                    "read_dr0" },
3203         { SVM_EXIT_READ_DR1,                    "read_dr1" },
3204         { SVM_EXIT_READ_DR2,                    "read_dr2" },
3205         { SVM_EXIT_READ_DR3,                    "read_dr3" },
3206         { SVM_EXIT_WRITE_DR0,                   "write_dr0" },
3207         { SVM_EXIT_WRITE_DR1,                   "write_dr1" },
3208         { SVM_EXIT_WRITE_DR2,                   "write_dr2" },
3209         { SVM_EXIT_WRITE_DR3,                   "write_dr3" },
3210         { SVM_EXIT_WRITE_DR5,                   "write_dr5" },
3211         { SVM_EXIT_WRITE_DR7,                   "write_dr7" },
3212         { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" },
3213         { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" },
3214         { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" },
3215         { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" },
3216         { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" },
3217         { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" },
3218         { SVM_EXIT_INTR,                        "interrupt" },
3219         { SVM_EXIT_NMI,                         "nmi" },
3220         { SVM_EXIT_SMI,                         "smi" },
3221         { SVM_EXIT_INIT,                        "init" },
3222         { SVM_EXIT_VINTR,                       "vintr" },
3223         { SVM_EXIT_CPUID,                       "cpuid" },
3224         { SVM_EXIT_INVD,                        "invd" },
3225         { SVM_EXIT_HLT,                         "hlt" },
3226         { SVM_EXIT_INVLPG,                      "invlpg" },
3227         { SVM_EXIT_INVLPGA,                     "invlpga" },
3228         { SVM_EXIT_IOIO,                        "io" },
3229         { SVM_EXIT_MSR,                         "msr" },
3230         { SVM_EXIT_TASK_SWITCH,                 "task_switch" },
3231         { SVM_EXIT_SHUTDOWN,                    "shutdown" },
3232         { SVM_EXIT_VMRUN,                       "vmrun" },
3233         { SVM_EXIT_VMMCALL,                     "hypercall" },
3234         { SVM_EXIT_VMLOAD,                      "vmload" },
3235         { SVM_EXIT_VMSAVE,                      "vmsave" },
3236         { SVM_EXIT_STGI,                        "stgi" },
3237         { SVM_EXIT_CLGI,                        "clgi" },
3238         { SVM_EXIT_SKINIT,                      "skinit" },
3239         { SVM_EXIT_WBINVD,                      "wbinvd" },
3240         { SVM_EXIT_MONITOR,                     "monitor" },
3241         { SVM_EXIT_MWAIT,                       "mwait" },
3242         { SVM_EXIT_NPF,                         "npf" },
3243         { -1, NULL }
3244 };
3245
3246 static int svm_get_lpage_level(void)
3247 {
3248         return PT_PDPE_LEVEL;
3249 }
3250
3251 static bool svm_rdtscp_supported(void)
3252 {
3253         return false;
3254 }
3255
3256 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3257 {
3258         struct vcpu_svm *svm = to_svm(vcpu);
3259
3260         svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
3261         if (is_nested(svm))
3262                 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3263         update_cr0_intercept(svm);
3264 }
3265
3266 static struct kvm_x86_ops svm_x86_ops = {
3267         .cpu_has_kvm_support = has_svm,
3268         .disabled_by_bios = is_disabled,
3269         .hardware_setup = svm_hardware_setup,
3270         .hardware_unsetup = svm_hardware_unsetup,
3271         .check_processor_compatibility = svm_check_processor_compat,
3272         .hardware_enable = svm_hardware_enable,
3273         .hardware_disable = svm_hardware_disable,
3274         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3275
3276         .vcpu_create = svm_create_vcpu,
3277         .vcpu_free = svm_free_vcpu,
3278         .vcpu_reset = svm_vcpu_reset,
3279
3280         .prepare_guest_switch = svm_prepare_guest_switch,
3281         .vcpu_load = svm_vcpu_load,
3282         .vcpu_put = svm_vcpu_put,
3283
3284         .set_guest_debug = svm_guest_debug,
3285         .get_msr = svm_get_msr,
3286         .set_msr = svm_set_msr,
3287         .get_segment_base = svm_get_segment_base,
3288         .get_segment = svm_get_segment,
3289         .set_segment = svm_set_segment,
3290         .get_cpl = svm_get_cpl,
3291         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3292         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3293         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3294         .set_cr0 = svm_set_cr0,
3295         .set_cr3 = svm_set_cr3,
3296         .set_cr4 = svm_set_cr4,
3297         .set_efer = svm_set_efer,
3298         .get_idt = svm_get_idt,
3299         .set_idt = svm_set_idt,
3300         .get_gdt = svm_get_gdt,
3301         .set_gdt = svm_set_gdt,
3302         .get_dr = svm_get_dr,
3303         .set_dr = svm_set_dr,
3304         .cache_reg = svm_cache_reg,
3305         .get_rflags = svm_get_rflags,
3306         .set_rflags = svm_set_rflags,
3307         .fpu_activate = svm_fpu_activate,
3308         .fpu_deactivate = svm_fpu_deactivate,
3309
3310         .tlb_flush = svm_flush_tlb,
3311
3312         .run = svm_vcpu_run,
3313         .handle_exit = handle_exit,
3314         .skip_emulated_instruction = skip_emulated_instruction,
3315         .set_interrupt_shadow = svm_set_interrupt_shadow,
3316         .get_interrupt_shadow = svm_get_interrupt_shadow,
3317         .patch_hypercall = svm_patch_hypercall,
3318         .set_irq = svm_set_irq,
3319         .set_nmi = svm_inject_nmi,
3320         .queue_exception = svm_queue_exception,
3321         .interrupt_allowed = svm_interrupt_allowed,
3322         .nmi_allowed = svm_nmi_allowed,
3323         .get_nmi_mask = svm_get_nmi_mask,
3324         .set_nmi_mask = svm_set_nmi_mask,
3325         .enable_nmi_window = enable_nmi_window,
3326         .enable_irq_window = enable_irq_window,
3327         .update_cr8_intercept = update_cr8_intercept,
3328
3329         .set_tss_addr = svm_set_tss_addr,
3330         .get_tdp_level = get_npt_level,
3331         .get_mt_mask = svm_get_mt_mask,
3332
3333         .exit_reasons_str = svm_exit_reasons_str,
3334         .get_lpage_level = svm_get_lpage_level,
3335
3336         .cpuid_update = svm_cpuid_update,
3337
3338         .rdtscp_supported = svm_rdtscp_supported,
3339 };
3340
3341 static int __init svm_init(void)
3342 {
3343         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3344                               THIS_MODULE);
3345 }
3346
3347 static void __exit svm_exit(void)
3348 {
3349         kvm_exit();
3350 }
3351
3352 module_init(svm_init)
3353 module_exit(svm_exit)