SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20 #include "kvm_cache_regs.h"
  21 #include "x86.h"
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/ftrace_event.h>
  29 #include <linux/slab.h>
  30
  31 #include <asm/desc.h>
  32
  33 #include <asm/virtext.h>
  34 #include "trace.h"
  35
  36 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  37
  38 MODULE_AUTHOR("Qumranet");
  39 MODULE_LICENSE("GPL");
  40
  41 #define IOPM_ALLOC_ORDER 2
  42 #define MSRPM_ALLOC_ORDER 1
  43
  44 #define SEG_TYPE_LDT 2
  45 #define SEG_TYPE_BUSY_TSS16 3
  46
  47 #define SVM_FEATURE_NPT            (1 <<  0)
  48 #define SVM_FEATURE_LBRV           (1 <<  1)
  49 #define SVM_FEATURE_SVML           (1 <<  2)
  50 #define SVM_FEATURE_NRIP           (1 <<  3)
  51 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  52
  53 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  54 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  55 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  56
  57 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  58
  59 static const u32 host_save_user_msrs[] = {
  60 #ifdef CONFIG_X86_64
  61         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  62         MSR_FS_BASE,
  63 #endif
  64         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  65 };
  66
  67 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  68
  69 struct kvm_vcpu;
  70
  71 struct nested_state {
  72         struct vmcb *hsave;
  73         u64 hsave_msr;
  74         u64 vm_cr_msr;
  75         u64 vmcb;
  76
  77         /* These are the merged vectors */
  78         u32 *msrpm;
  79
  80         /* gpa pointers to the real vectors */
  81         u64 vmcb_msrpm;
  82         u64 vmcb_iopm;
  83
  84         /* A VMEXIT is required but not yet emulated */
  85         bool exit_required;
  86
  87         /* cache for intercepts of the guest */
  88         u16 intercept_cr_read;
  89         u16 intercept_cr_write;
  90         u16 intercept_dr_read;
  91         u16 intercept_dr_write;
  92         u32 intercept_exceptions;
  93         u64 intercept;
  94
  95 };
  96
  97 #define MSRPM_OFFSETS   16
  98 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
  99
 100 struct vcpu_svm {
 101         struct kvm_vcpu vcpu;
 102         struct vmcb *vmcb;
 103         unsigned long vmcb_pa;
 104         struct svm_cpu_data *svm_data;
 105         uint64_t asid_generation;
 106         uint64_t sysenter_esp;
 107         uint64_t sysenter_eip;
 108
 109         u64 next_rip;
 110
 111         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 112         u64 host_gs_base;
 113
 114         u32 *msrpm;
 115
 116         struct nested_state nested;
 117
 118         bool nmi_singlestep;
 119
 120         unsigned int3_injected;
 121         unsigned long int3_rip;
 122 };
 123
 124 #define MSR_INVALID                     0xffffffffU
 125
 126 static struct svm_direct_access_msrs {
 127         u32 index;   /* Index of the MSR */
 128         bool always; /* True if intercept is always on */
 129 } direct_access_msrs[] = {
 130         { .index = MSR_K6_STAR,                         .always = true  },
 131         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 132 #ifdef CONFIG_X86_64
 133         { .index = MSR_GS_BASE,                         .always = true  },
 134         { .index = MSR_FS_BASE,                         .always = true  },
 135         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 136         { .index = MSR_LSTAR,                           .always = true  },
 137         { .index = MSR_CSTAR,                           .always = true  },
 138         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 139 #endif
 140         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 141         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 142         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 143         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 144         { .index = MSR_INVALID,                         .always = false },
 145 };
 146
 147 /* enable NPT for AMD64 and X86 with PAE */
 148 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 149 static bool npt_enabled = true;
 150 #else
 151 static bool npt_enabled;
 152 #endif
 153 static int npt = 1;
 154
 155 module_param(npt, int, S_IRUGO);
 156
 157 static int nested = 1;
 158 module_param(nested, int, S_IRUGO);
 159
 160 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 161 static void svm_complete_interrupts(struct vcpu_svm *svm);
 162
 163 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 164 static int nested_svm_intercept(struct vcpu_svm *svm);
 165 static int nested_svm_vmexit(struct vcpu_svm *svm);
 166 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 167                                       bool has_error_code, u32 error_code);
 168
 169 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 170 {
 171         return container_of(vcpu, struct vcpu_svm, vcpu);
 172 }
 173
 174 static inline bool is_nested(struct vcpu_svm *svm)
 175 {
 176         return svm->nested.vmcb;
 177 }
 178
 179 static inline void enable_gif(struct vcpu_svm *svm)
 180 {
 181         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 182 }
 183
 184 static inline void disable_gif(struct vcpu_svm *svm)
 185 {
 186         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 187 }
 188
 189 static inline bool gif_set(struct vcpu_svm *svm)
 190 {
 191         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 192 }
 193
 194 static unsigned long iopm_base;
 195
 196 struct kvm_ldttss_desc {
 197         u16 limit0;
 198         u16 base0;
 199         unsigned base1:8, type:5, dpl:2, p:1;
 200         unsigned limit1:4, zero0:3, g:1, base2:8;
 201         u32 base3;
 202         u32 zero1;
 203 } __attribute__((packed));
 204
 205 struct svm_cpu_data {
 206         int cpu;
 207
 208         u64 asid_generation;
 209         u32 max_asid;
 210         u32 next_asid;
 211         struct kvm_ldttss_desc *tss_desc;
 212
 213         struct page *save_area;
 214 };
 215
 216 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 217 static uint32_t svm_features;
 218
 219 struct svm_init_data {
 220         int cpu;
 221         int r;
 222 };
 223
 224 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 225
 226 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 227 #define MSRS_RANGE_SIZE 2048
 228 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 229
 230 static u32 svm_msrpm_offset(u32 msr)
 231 {
 232         u32 offset;
 233         int i;
 234
 235         for (i = 0; i < NUM_MSR_MAPS; i++) {
 236                 if (msr < msrpm_ranges[i] ||
 237                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 238                         continue;
 239
 240                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 241                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 242
 243                 /* Now we have the u8 offset - but need the u32 offset */
 244                 return offset / 4;
 245         }
 246
 247         /* MSR not in any range */
 248         return MSR_INVALID;
 249 }
 250
 251 #define MAX_INST_SIZE 15
 252
 253 static inline u32 svm_has(u32 feat)
 254 {
 255         return svm_features & feat;
 256 }
 257
 258 static inline void clgi(void)
 259 {
 260         asm volatile (__ex(SVM_CLGI));
 261 }
 262
 263 static inline void stgi(void)
 264 {
 265         asm volatile (__ex(SVM_STGI));
 266 }
 267
 268 static inline void invlpga(unsigned long addr, u32 asid)
 269 {
 270         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 271 }
 272
 273 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 274 {
 275         to_svm(vcpu)->asid_generation--;
 276 }
 277
 278 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 279 {
 280         force_new_asid(vcpu);
 281 }
 282
 283 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 284 {
 285         if (!npt_enabled && !(efer & EFER_LMA))
 286                 efer &= ~EFER_LME;
 287
 288         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 289         vcpu->arch.efer = efer;
 290 }
 291
 292 static int is_external_interrupt(u32 info)
 293 {
 294         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 295         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 296 }
 297
 298 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 299 {
 300         struct vcpu_svm *svm = to_svm(vcpu);
 301         u32 ret = 0;
 302
 303         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 304                 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 305         return ret & mask;
 306 }
 307
 308 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 309 {
 310         struct vcpu_svm *svm = to_svm(vcpu);
 311
 312         if (mask == 0)
 313                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 314         else
 315                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 316
 317 }
 318
 319 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 320 {
 321         struct vcpu_svm *svm = to_svm(vcpu);
 322
 323         if (svm->vmcb->control.next_rip != 0)
 324                 svm->next_rip = svm->vmcb->control.next_rip;
 325
 326         if (!svm->next_rip) {
 327                 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
 328                                 EMULATE_DONE)
 329                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 330                 return;
 331         }
 332         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 333                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 334                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 335
 336         kvm_rip_write(vcpu, svm->next_rip);
 337         svm_set_interrupt_shadow(vcpu, 0);
 338 }
 339
 340 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 341                                 bool has_error_code, u32 error_code)
 342 {
 343         struct vcpu_svm *svm = to_svm(vcpu);
 344
 345         /*
 346          * If we are within a nested VM we'd better #VMEXIT and let the guest
 347          * handle the exception
 348          */
 349         if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
 350                 return;
 351
 352         if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
 353                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 354
 355                 /*
 356                  * For guest debugging where we have to reinject #BP if some
 357                  * INT3 is guest-owned:
 358                  * Emulate nRIP by moving RIP forward. Will fail if injection
 359                  * raises a fault that is not intercepted. Still better than
 360                  * failing in all cases.
 361                  */
 362                 skip_emulated_instruction(&svm->vcpu);
 363                 rip = kvm_rip_read(&svm->vcpu);
 364                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 365                 svm->int3_injected = rip - old_rip;
 366         }
 367
 368         svm->vmcb->control.event_inj = nr
 369                 | SVM_EVTINJ_VALID
 370                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 371                 | SVM_EVTINJ_TYPE_EXEPT;
 372         svm->vmcb->control.event_inj_err = error_code;
 373 }
 374
 375 static int has_svm(void)
 376 {
 377         const char *msg;
 378
 379         if (!cpu_has_svm(&msg)) {
 380                 printk(KERN_INFO "has_svm: %s\n", msg);
 381                 return 0;
 382         }
 383
 384         return 1;
 385 }
 386
 387 static void svm_hardware_disable(void *garbage)
 388 {
 389         cpu_svm_disable();
 390 }
 391
 392 static int svm_hardware_enable(void *garbage)
 393 {
 394
 395         struct svm_cpu_data *sd;
 396         uint64_t efer;
 397         struct desc_ptr gdt_descr;
 398         struct desc_struct *gdt;
 399         int me = raw_smp_processor_id();
 400
 401         rdmsrl(MSR_EFER, efer);
 402         if (efer & EFER_SVME)
 403                 return -EBUSY;
 404
 405         if (!has_svm()) {
 406                 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
 407                        me);
 408                 return -EINVAL;
 409         }
 410         sd = per_cpu(svm_data, me);
 411
 412         if (!sd) {
 413                 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
 414                        me);
 415                 return -EINVAL;
 416         }
 417
 418         sd->asid_generation = 1;
 419         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 420         sd->next_asid = sd->max_asid + 1;
 421
 422         native_store_gdt(&gdt_descr);
 423         gdt = (struct desc_struct *)gdt_descr.address;
 424         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 425
 426         wrmsrl(MSR_EFER, efer | EFER_SVME);
 427
 428         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 429
 430         return 0;
 431 }
 432
 433 static void svm_cpu_uninit(int cpu)
 434 {
 435         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 436
 437         if (!sd)
 438                 return;
 439
 440         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 441         __free_page(sd->save_area);
 442         kfree(sd);
 443 }
 444
 445 static int svm_cpu_init(int cpu)
 446 {
 447         struct svm_cpu_data *sd;
 448         int r;
 449
 450         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 451         if (!sd)
 452                 return -ENOMEM;
 453         sd->cpu = cpu;
 454         sd->save_area = alloc_page(GFP_KERNEL);
 455         r = -ENOMEM;
 456         if (!sd->save_area)
 457                 goto err_1;
 458
 459         per_cpu(svm_data, cpu) = sd;
 460
 461         return 0;
 462
 463 err_1:
 464         kfree(sd);
 465         return r;
 466
 467 }
 468
 469 static bool valid_msr_intercept(u32 index)
 470 {
 471         int i;
 472
 473         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 474                 if (direct_access_msrs[i].index == index)
 475                         return true;
 476
 477         return false;
 478 }
 479
 480 static void set_msr_interception(u32 *msrpm, unsigned msr,
 481                                  int read, int write)
 482 {
 483         u8 bit_read, bit_write;
 484         unsigned long tmp;
 485         u32 offset;
 486
 487         /*
 488          * If this warning triggers extend the direct_access_msrs list at the
 489          * beginning of the file
 490          */
 491         WARN_ON(!valid_msr_intercept(msr));
 492
 493         offset    = svm_msrpm_offset(msr);
 494         bit_read  = 2 * (msr & 0x0f);
 495         bit_write = 2 * (msr & 0x0f) + 1;
 496         tmp       = msrpm[offset];
 497
 498         BUG_ON(offset == MSR_INVALID);
 499
 500         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 501         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 502
 503         msrpm[offset] = tmp;
 504 }
 505
 506 static void svm_vcpu_init_msrpm(u32 *msrpm)
 507 {
 508         int i;
 509
 510         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 511
 512         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 513                 if (!direct_access_msrs[i].always)
 514                         continue;
 515
 516                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 517         }
 518 }
 519
 520 static void add_msr_offset(u32 offset)
 521 {
 522         int i;
 523
 524         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 525
 526                 /* Offset already in list? */
 527                 if (msrpm_offsets[i] == offset)
 528                         return;
 529
 530                 /* Slot used by another offset? */
 531                 if (msrpm_offsets[i] != MSR_INVALID)
 532                         continue;
 533
 534                 /* Add offset to list */
 535                 msrpm_offsets[i] = offset;
 536
 537                 return;
 538         }
 539
 540         /*
 541          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 542          * increase MSRPM_OFFSETS in this case.
 543          */
 544         BUG();
 545 }
 546
 547 static void init_msrpm_offsets(void)
 548 {
 549         int i;
 550
 551         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 552
 553         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 554                 u32 offset;
 555
 556                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 557                 BUG_ON(offset == MSR_INVALID);
 558
 559                 add_msr_offset(offset);
 560         }
 561 }
 562
 563 static void svm_enable_lbrv(struct vcpu_svm *svm)
 564 {
 565         u32 *msrpm = svm->msrpm;
 566
 567         svm->vmcb->control.lbr_ctl = 1;
 568         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 569         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 570         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 571         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 572 }
 573
 574 static void svm_disable_lbrv(struct vcpu_svm *svm)
 575 {
 576         u32 *msrpm = svm->msrpm;
 577
 578         svm->vmcb->control.lbr_ctl = 0;
 579         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 580         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 581         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 582         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 583 }
 584
 585 static __init int svm_hardware_setup(void)
 586 {
 587         int cpu;
 588         struct page *iopm_pages;
 589         void *iopm_va;
 590         int r;
 591
 592         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 593
 594         if (!iopm_pages)
 595                 return -ENOMEM;
 596
 597         iopm_va = page_address(iopm_pages);
 598         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 599         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 600
 601         init_msrpm_offsets();
 602
 603         if (boot_cpu_has(X86_FEATURE_NX))
 604                 kvm_enable_efer_bits(EFER_NX);
 605
 606         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 607                 kvm_enable_efer_bits(EFER_FFXSR);
 608
 609         if (nested) {
 610                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 611                 kvm_enable_efer_bits(EFER_SVME);
 612         }
 613
 614         for_each_possible_cpu(cpu) {
 615                 r = svm_cpu_init(cpu);
 616                 if (r)
 617                         goto err;
 618         }
 619
 620         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 621
 622         if (!svm_has(SVM_FEATURE_NPT))
 623                 npt_enabled = false;
 624
 625         if (npt_enabled && !npt) {
 626                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 627                 npt_enabled = false;
 628         }
 629
 630         if (npt_enabled) {
 631                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 632                 kvm_enable_tdp();
 633         } else
 634                 kvm_disable_tdp();
 635
 636         return 0;
 637
 638 err:
 639         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 640         iopm_base = 0;
 641         return r;
 642 }
 643
 644 static __exit void svm_hardware_unsetup(void)
 645 {
 646         int cpu;
 647
 648         for_each_possible_cpu(cpu)
 649                 svm_cpu_uninit(cpu);
 650
 651         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 652         iopm_base = 0;
 653 }
 654
 655 static void init_seg(struct vmcb_seg *seg)
 656 {
 657         seg->selector = 0;
 658         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 659                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 660         seg->limit = 0xffff;
 661         seg->base = 0;
 662 }
 663
 664 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 665 {
 666         seg->selector = 0;
 667         seg->attrib = SVM_SELECTOR_P_MASK | type;
 668         seg->limit = 0xffff;
 669         seg->base = 0;
 670 }
 671
 672 static void init_vmcb(struct vcpu_svm *svm)
 673 {
 674         struct vmcb_control_area *control = &svm->vmcb->control;
 675         struct vmcb_save_area *save = &svm->vmcb->save;
 676
 677         svm->vcpu.fpu_active = 1;
 678
 679         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 680                                         INTERCEPT_CR3_MASK |
 681                                         INTERCEPT_CR4_MASK;
 682
 683         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 684                                         INTERCEPT_CR3_MASK |
 685                                         INTERCEPT_CR4_MASK |
 686                                         INTERCEPT_CR8_MASK;
 687
 688         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 689                                         INTERCEPT_DR1_MASK |
 690                                         INTERCEPT_DR2_MASK |
 691                                         INTERCEPT_DR3_MASK |
 692                                         INTERCEPT_DR4_MASK |
 693                                         INTERCEPT_DR5_MASK |
 694                                         INTERCEPT_DR6_MASK |
 695                                         INTERCEPT_DR7_MASK;
 696
 697         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 698                                         INTERCEPT_DR1_MASK |
 699                                         INTERCEPT_DR2_MASK |
 700                                         INTERCEPT_DR3_MASK |
 701                                         INTERCEPT_DR4_MASK |
 702                                         INTERCEPT_DR5_MASK |
 703                                         INTERCEPT_DR6_MASK |
 704                                         INTERCEPT_DR7_MASK;
 705
 706         control->intercept_exceptions = (1 << PF_VECTOR) |
 707                                         (1 << UD_VECTOR) |
 708                                         (1 << MC_VECTOR);
 709
 710
 711         control->intercept =    (1ULL << INTERCEPT_INTR) |
 712                                 (1ULL << INTERCEPT_NMI) |
 713                                 (1ULL << INTERCEPT_SMI) |
 714                                 (1ULL << INTERCEPT_SELECTIVE_CR0) |
 715                                 (1ULL << INTERCEPT_CPUID) |
 716                                 (1ULL << INTERCEPT_INVD) |
 717                                 (1ULL << INTERCEPT_HLT) |
 718                                 (1ULL << INTERCEPT_INVLPG) |
 719                                 (1ULL << INTERCEPT_INVLPGA) |
 720                                 (1ULL << INTERCEPT_IOIO_PROT) |
 721                                 (1ULL << INTERCEPT_MSR_PROT) |
 722                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 723                                 (1ULL << INTERCEPT_SHUTDOWN) |
 724                                 (1ULL << INTERCEPT_VMRUN) |
 725                                 (1ULL << INTERCEPT_VMMCALL) |
 726                                 (1ULL << INTERCEPT_VMLOAD) |
 727                                 (1ULL << INTERCEPT_VMSAVE) |
 728                                 (1ULL << INTERCEPT_STGI) |
 729                                 (1ULL << INTERCEPT_CLGI) |
 730                                 (1ULL << INTERCEPT_SKINIT) |
 731                                 (1ULL << INTERCEPT_WBINVD) |
 732                                 (1ULL << INTERCEPT_MONITOR) |
 733                                 (1ULL << INTERCEPT_MWAIT);
 734
 735         control->iopm_base_pa = iopm_base;
 736         control->msrpm_base_pa = __pa(svm->msrpm);
 737         control->tsc_offset = 0;
 738         control->int_ctl = V_INTR_MASKING_MASK;
 739
 740         init_seg(&save->es);
 741         init_seg(&save->ss);
 742         init_seg(&save->ds);
 743         init_seg(&save->fs);
 744         init_seg(&save->gs);
 745
 746         save->cs.selector = 0xf000;
 747         /* Executable/Readable Code Segment */
 748         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 749                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 750         save->cs.limit = 0xffff;
 751         /*
 752          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 753          * be consistent with it.
 754          *
 755          * Replace when we have real mode working for vmx.
 756          */
 757         save->cs.base = 0xf0000;
 758
 759         save->gdtr.limit = 0xffff;
 760         save->idtr.limit = 0xffff;
 761
 762         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 763         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 764
 765         save->efer = EFER_SVME;
 766         save->dr6 = 0xffff0ff0;
 767         save->dr7 = 0x400;
 768         save->rflags = 2;
 769         save->rip = 0x0000fff0;
 770         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 771
 772         /*
 773          * This is the guest-visible cr0 value.
 774          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
 775          */
 776         svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
 777         kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
 778
 779         save->cr4 = X86_CR4_PAE;
 780         /* rdx = ?? */
 781
 782         if (npt_enabled) {
 783                 /* Setup VMCB for Nested Paging */
 784                 control->nested_ctl = 1;
 785                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 786                                         (1ULL << INTERCEPT_INVLPG));
 787                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 788                 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
 789                 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
 790                 save->g_pat = 0x0007040600070406ULL;
 791                 save->cr3 = 0;
 792                 save->cr4 = 0;
 793         }
 794         force_new_asid(&svm->vcpu);
 795
 796         svm->nested.vmcb = 0;
 797         svm->vcpu.arch.hflags = 0;
 798
 799         if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
 800                 control->pause_filter_count = 3000;
 801                 control->intercept |= (1ULL << INTERCEPT_PAUSE);
 802         }
 803
 804         enable_gif(svm);
 805 }
 806
 807 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 808 {
 809         struct vcpu_svm *svm = to_svm(vcpu);
 810
 811         init_vmcb(svm);
 812
 813         if (!kvm_vcpu_is_bsp(vcpu)) {
 814                 kvm_rip_write(vcpu, 0);
 815                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 816                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 817         }
 818         vcpu->arch.regs_avail = ~0;
 819         vcpu->arch.regs_dirty = ~0;
 820
 821         return 0;
 822 }
 823
 824 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 825 {
 826         struct vcpu_svm *svm;
 827         struct page *page;
 828         struct page *msrpm_pages;
 829         struct page *hsave_page;
 830         struct page *nested_msrpm_pages;
 831         int err;
 832
 833         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 834         if (!svm) {
 835                 err = -ENOMEM;
 836                 goto out;
 837         }
 838
 839         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 840         if (err)
 841                 goto free_svm;
 842
 843         err = -ENOMEM;
 844         page = alloc_page(GFP_KERNEL);
 845         if (!page)
 846                 goto uninit;
 847
 848         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 849         if (!msrpm_pages)
 850                 goto free_page1;
 851
 852         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 853         if (!nested_msrpm_pages)
 854                 goto free_page2;
 855
 856         hsave_page = alloc_page(GFP_KERNEL);
 857         if (!hsave_page)
 858                 goto free_page3;
 859
 860         svm->nested.hsave = page_address(hsave_page);
 861
 862         svm->msrpm = page_address(msrpm_pages);
 863         svm_vcpu_init_msrpm(svm->msrpm);
 864
 865         svm->nested.msrpm = page_address(nested_msrpm_pages);
 866         svm_vcpu_init_msrpm(svm->nested.msrpm);
 867
 868         svm->vmcb = page_address(page);
 869         clear_page(svm->vmcb);
 870         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 871         svm->asid_generation = 0;
 872         init_vmcb(svm);
 873
 874         fx_init(&svm->vcpu);
 875         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 876         if (kvm_vcpu_is_bsp(&svm->vcpu))
 877                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 878
 879         return &svm->vcpu;
 880
 881 free_page3:
 882         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
 883 free_page2:
 884         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
 885 free_page1:
 886         __free_page(page);
 887 uninit:
 888         kvm_vcpu_uninit(&svm->vcpu);
 889 free_svm:
 890         kmem_cache_free(kvm_vcpu_cache, svm);
 891 out:
 892         return ERR_PTR(err);
 893 }
 894
 895 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 896 {
 897         struct vcpu_svm *svm = to_svm(vcpu);
 898
 899         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 900         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 901         __free_page(virt_to_page(svm->nested.hsave));
 902         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
 903         kvm_vcpu_uninit(vcpu);
 904         kmem_cache_free(kvm_vcpu_cache, svm);
 905 }
 906
 907 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 908 {
 909         struct vcpu_svm *svm = to_svm(vcpu);
 910         int i;
 911
 912         if (unlikely(cpu != vcpu->cpu)) {
 913                 u64 delta;
 914
 915                 if (check_tsc_unstable()) {
 916                         /*
 917                          * Make sure that the guest sees a monotonically
 918                          * increasing TSC.
 919                          */
 920                         delta = vcpu->arch.host_tsc - native_read_tsc();
 921                         svm->vmcb->control.tsc_offset += delta;
 922                         if (is_nested(svm))
 923                                 svm->nested.hsave->control.tsc_offset += delta;
 924                 }
 925                 vcpu->cpu = cpu;
 926                 kvm_migrate_timers(vcpu);
 927                 svm->asid_generation = 0;
 928         }
 929
 930         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 931                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 932 }
 933
 934 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 935 {
 936         struct vcpu_svm *svm = to_svm(vcpu);
 937         int i;
 938
 939         ++vcpu->stat.host_state_reload;
 940         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 941                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 942
 943         vcpu->arch.host_tsc = native_read_tsc();
 944 }
 945
 946 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 947 {
 948         return to_svm(vcpu)->vmcb->save.rflags;
 949 }
 950
 951 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 952 {
 953         to_svm(vcpu)->vmcb->save.rflags = rflags;
 954 }
 955
 956 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
 957 {
 958         switch (reg) {
 959         case VCPU_EXREG_PDPTR:
 960                 BUG_ON(!npt_enabled);
 961                 load_pdptrs(vcpu, vcpu->arch.cr3);
 962                 break;
 963         default:
 964                 BUG();
 965         }
 966 }
 967
 968 static void svm_set_vintr(struct vcpu_svm *svm)
 969 {
 970         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 971 }
 972
 973 static void svm_clear_vintr(struct vcpu_svm *svm)
 974 {
 975         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 976 }
 977
 978 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 979 {
 980         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 981
 982         switch (seg) {
 983         case VCPU_SREG_CS: return &save->cs;
 984         case VCPU_SREG_DS: return &save->ds;
 985         case VCPU_SREG_ES: return &save->es;
 986         case VCPU_SREG_FS: return &save->fs;
 987         case VCPU_SREG_GS: return &save->gs;
 988         case VCPU_SREG_SS: return &save->ss;
 989         case VCPU_SREG_TR: return &save->tr;
 990         case VCPU_SREG_LDTR: return &save->ldtr;
 991         }
 992         BUG();
 993         return NULL;
 994 }
 995
 996 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 997 {
 998         struct vmcb_seg *s = svm_seg(vcpu, seg);
 999
1000         return s->base;
1001 }
1002
1003 static void svm_get_segment(struct kvm_vcpu *vcpu,
1004                             struct kvm_segment *var, int seg)
1005 {
1006         struct vmcb_seg *s = svm_seg(vcpu, seg);
1007
1008         var->base = s->base;
1009         var->limit = s->limit;
1010         var->selector = s->selector;
1011         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1012         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1013         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1014         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1015         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1016         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1017         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1018         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1019
1020         /*
1021          * AMD's VMCB does not have an explicit unusable field, so emulate it
1022          * for cross vendor migration purposes by "not present"
1023          */
1024         var->unusable = !var->present || (var->type == 0);
1025
1026         switch (seg) {
1027         case VCPU_SREG_CS:
1028                 /*
1029                  * SVM always stores 0 for the 'G' bit in the CS selector in
1030                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1031                  * Intel's VMENTRY has a check on the 'G' bit.
1032                  */
1033                 var->g = s->limit > 0xfffff;
1034                 break;
1035         case VCPU_SREG_TR:
1036                 /*
1037                  * Work around a bug where the busy flag in the tr selector
1038                  * isn't exposed
1039                  */
1040                 var->type |= 0x2;
1041                 break;
1042         case VCPU_SREG_DS:
1043         case VCPU_SREG_ES:
1044         case VCPU_SREG_FS:
1045         case VCPU_SREG_GS:
1046                 /*
1047                  * The accessed bit must always be set in the segment
1048                  * descriptor cache, although it can be cleared in the
1049                  * descriptor, the cached bit always remains at 1. Since
1050                  * Intel has a check on this, set it here to support
1051                  * cross-vendor migration.
1052                  */
1053                 if (!var->unusable)
1054                         var->type |= 0x1;
1055                 break;
1056         case VCPU_SREG_SS:
1057                 /*
1058                  * On AMD CPUs sometimes the DB bit in the segment
1059                  * descriptor is left as 1, although the whole segment has
1060                  * been made unusable. Clear it here to pass an Intel VMX
1061                  * entry check when cross vendor migrating.
1062                  */
1063                 if (var->unusable)
1064                         var->db = 0;
1065                 break;
1066         }
1067 }
1068
1069 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1070 {
1071         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1072
1073         return save->cpl;
1074 }
1075
1076 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1077 {
1078         struct vcpu_svm *svm = to_svm(vcpu);
1079
1080         dt->size = svm->vmcb->save.idtr.limit;
1081         dt->address = svm->vmcb->save.idtr.base;
1082 }
1083
1084 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1085 {
1086         struct vcpu_svm *svm = to_svm(vcpu);
1087
1088         svm->vmcb->save.idtr.limit = dt->size;
1089         svm->vmcb->save.idtr.base = dt->address ;
1090 }
1091
1092 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1093 {
1094         struct vcpu_svm *svm = to_svm(vcpu);
1095
1096         dt->size = svm->vmcb->save.gdtr.limit;
1097         dt->address = svm->vmcb->save.gdtr.base;
1098 }
1099
1100 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1101 {
1102         struct vcpu_svm *svm = to_svm(vcpu);
1103
1104         svm->vmcb->save.gdtr.limit = dt->size;
1105         svm->vmcb->save.gdtr.base = dt->address ;
1106 }
1107
1108 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1109 {
1110 }
1111
1112 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1113 {
1114 }
1115
1116 static void update_cr0_intercept(struct vcpu_svm *svm)
1117 {
1118         struct vmcb *vmcb = svm->vmcb;
1119         ulong gcr0 = svm->vcpu.arch.cr0;
1120         u64 *hcr0 = &svm->vmcb->save.cr0;
1121
1122         if (!svm->vcpu.fpu_active)
1123                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1124         else
1125                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1126                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1127
1128
1129         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1130                 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1131                 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1132                 if (is_nested(svm)) {
1133                         struct vmcb *hsave = svm->nested.hsave;
1134
1135                         hsave->control.intercept_cr_read  &= ~INTERCEPT_CR0_MASK;
1136                         hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1137                         vmcb->control.intercept_cr_read  |= svm->nested.intercept_cr_read;
1138                         vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1139                 }
1140         } else {
1141                 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1142                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1143                 if (is_nested(svm)) {
1144                         struct vmcb *hsave = svm->nested.hsave;
1145
1146                         hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1147                         hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1148                 }
1149         }
1150 }
1151
1152 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1153 {
1154         struct vcpu_svm *svm = to_svm(vcpu);
1155
1156         if (is_nested(svm)) {
1157                 /*
1158                  * We are here because we run in nested mode, the host kvm
1159                  * intercepts cr0 writes but the l1 hypervisor does not.
1160                  * But the L1 hypervisor may intercept selective cr0 writes.
1161                  * This needs to be checked here.
1162                  */
1163                 unsigned long old, new;
1164
1165                 /* Remove bits that would trigger a real cr0 write intercept */
1166                 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1167                 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1168
1169                 if (old == new) {
1170                         /* cr0 write with ts and mp unchanged */
1171                         svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1172                         if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE)
1173                                 return;
1174                 }
1175         }
1176
1177 #ifdef CONFIG_X86_64
1178         if (vcpu->arch.efer & EFER_LME) {
1179                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1180                         vcpu->arch.efer |= EFER_LMA;
1181                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1182                 }
1183
1184                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1185                         vcpu->arch.efer &= ~EFER_LMA;
1186                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1187                 }
1188         }
1189 #endif
1190         vcpu->arch.cr0 = cr0;
1191
1192         if (!npt_enabled)
1193                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1194
1195         if (!vcpu->fpu_active)
1196                 cr0 |= X86_CR0_TS;
1197         /*
1198          * re-enable caching here because the QEMU bios
1199          * does not do it - this results in some delay at
1200          * reboot
1201          */
1202         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1203         svm->vmcb->save.cr0 = cr0;
1204         update_cr0_intercept(svm);
1205 }
1206
1207 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1208 {
1209         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1210         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1211
1212         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1213                 force_new_asid(vcpu);
1214
1215         vcpu->arch.cr4 = cr4;
1216         if (!npt_enabled)
1217                 cr4 |= X86_CR4_PAE;
1218         cr4 |= host_cr4_mce;
1219         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1220 }
1221
1222 static void svm_set_segment(struct kvm_vcpu *vcpu,
1223                             struct kvm_segment *var, int seg)
1224 {
1225         struct vcpu_svm *svm = to_svm(vcpu);
1226         struct vmcb_seg *s = svm_seg(vcpu, seg);
1227
1228         s->base = var->base;
1229         s->limit = var->limit;
1230         s->selector = var->selector;
1231         if (var->unusable)
1232                 s->attrib = 0;
1233         else {
1234                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1235                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1236                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1237                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1238                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1239                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1240                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1241                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1242         }
1243         if (seg == VCPU_SREG_CS)
1244                 svm->vmcb->save.cpl
1245                         = (svm->vmcb->save.cs.attrib
1246                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1247
1248 }
1249
1250 static void update_db_intercept(struct kvm_vcpu *vcpu)
1251 {
1252         struct vcpu_svm *svm = to_svm(vcpu);
1253
1254         svm->vmcb->control.intercept_exceptions &=
1255                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1256
1257         if (svm->nmi_singlestep)
1258                 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1259
1260         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1261                 if (vcpu->guest_debug &
1262                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1263                         svm->vmcb->control.intercept_exceptions |=
1264                                 1 << DB_VECTOR;
1265                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1266                         svm->vmcb->control.intercept_exceptions |=
1267                                 1 << BP_VECTOR;
1268         } else
1269                 vcpu->guest_debug = 0;
1270 }
1271
1272 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1273 {
1274         struct vcpu_svm *svm = to_svm(vcpu);
1275
1276         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1277                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1278         else
1279                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1280
1281         update_db_intercept(vcpu);
1282 }
1283
1284 static void load_host_msrs(struct kvm_vcpu *vcpu)
1285 {
1286 #ifdef CONFIG_X86_64
1287         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1288 #endif
1289 }
1290
1291 static void save_host_msrs(struct kvm_vcpu *vcpu)
1292 {
1293 #ifdef CONFIG_X86_64
1294         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1295 #endif
1296 }
1297
1298 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1299 {
1300         if (sd->next_asid > sd->max_asid) {
1301                 ++sd->asid_generation;
1302                 sd->next_asid = 1;
1303                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1304         }
1305
1306         svm->asid_generation = sd->asid_generation;
1307         svm->vmcb->control.asid = sd->next_asid++;
1308 }
1309
1310 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1311 {
1312         struct vcpu_svm *svm = to_svm(vcpu);
1313
1314         svm->vmcb->save.dr7 = value;
1315 }
1316
1317 static int pf_interception(struct vcpu_svm *svm)
1318 {
1319         u64 fault_address;
1320         u32 error_code;
1321
1322         fault_address  = svm->vmcb->control.exit_info_2;
1323         error_code = svm->vmcb->control.exit_info_1;
1324
1325         trace_kvm_page_fault(fault_address, error_code);
1326         if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1327                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1328         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1329 }
1330
1331 static int db_interception(struct vcpu_svm *svm)
1332 {
1333         struct kvm_run *kvm_run = svm->vcpu.run;
1334
1335         if (!(svm->vcpu.guest_debug &
1336               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1337                 !svm->nmi_singlestep) {
1338                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1339                 return 1;
1340         }
1341
1342         if (svm->nmi_singlestep) {
1343                 svm->nmi_singlestep = false;
1344                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1345                         svm->vmcb->save.rflags &=
1346                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1347                 update_db_intercept(&svm->vcpu);
1348         }
1349
1350         if (svm->vcpu.guest_debug &
1351             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1352                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1353                 kvm_run->debug.arch.pc =
1354                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1355                 kvm_run->debug.arch.exception = DB_VECTOR;
1356                 return 0;
1357         }
1358
1359         return 1;
1360 }
1361
1362 static int bp_interception(struct vcpu_svm *svm)
1363 {
1364         struct kvm_run *kvm_run = svm->vcpu.run;
1365
1366         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1367         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1368         kvm_run->debug.arch.exception = BP_VECTOR;
1369         return 0;
1370 }
1371
1372 static int ud_interception(struct vcpu_svm *svm)
1373 {
1374         int er;
1375
1376         er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1377         if (er != EMULATE_DONE)
1378                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1379         return 1;
1380 }
1381
1382 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1383 {
1384         struct vcpu_svm *svm = to_svm(vcpu);
1385         u32 excp;
1386
1387         if (is_nested(svm)) {
1388                 u32 h_excp, n_excp;
1389
1390                 h_excp  = svm->nested.hsave->control.intercept_exceptions;
1391                 n_excp  = svm->nested.intercept_exceptions;
1392                 h_excp &= ~(1 << NM_VECTOR);
1393                 excp    = h_excp | n_excp;
1394         } else {
1395                 excp  = svm->vmcb->control.intercept_exceptions;
1396                 excp &= ~(1 << NM_VECTOR);
1397         }
1398
1399         svm->vmcb->control.intercept_exceptions = excp;
1400
1401         svm->vcpu.fpu_active = 1;
1402         update_cr0_intercept(svm);
1403 }
1404
1405 static int nm_interception(struct vcpu_svm *svm)
1406 {
1407         svm_fpu_activate(&svm->vcpu);
1408         return 1;
1409 }
1410
1411 static int mc_interception(struct vcpu_svm *svm)
1412 {
1413         /*
1414          * On an #MC intercept the MCE handler is not called automatically in
1415          * the host. So do it by hand here.
1416          */
1417         asm volatile (
1418                 "int $0x12\n");
1419         /* not sure if we ever come back to this point */
1420
1421         return 1;
1422 }
1423
1424 static int shutdown_interception(struct vcpu_svm *svm)
1425 {
1426         struct kvm_run *kvm_run = svm->vcpu.run;
1427
1428         /*
1429          * VMCB is undefined after a SHUTDOWN intercept
1430          * so reinitialize it.
1431          */
1432         clear_page(svm->vmcb);
1433         init_vmcb(svm);
1434
1435         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1436         return 0;
1437 }
1438
1439 static int io_interception(struct vcpu_svm *svm)
1440 {
1441         struct kvm_vcpu *vcpu = &svm->vcpu;
1442         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1443         int size, in, string;
1444         unsigned port;
1445
1446         ++svm->vcpu.stat.io_exits;
1447         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1448         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1449         if (string || in)
1450                 return !(emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO);
1451
1452         port = io_info >> 16;
1453         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1454         svm->next_rip = svm->vmcb->control.exit_info_2;
1455         skip_emulated_instruction(&svm->vcpu);
1456
1457         return kvm_fast_pio_out(vcpu, size, port);
1458 }
1459
1460 static int nmi_interception(struct vcpu_svm *svm)
1461 {
1462         return 1;
1463 }
1464
1465 static int intr_interception(struct vcpu_svm *svm)
1466 {
1467         ++svm->vcpu.stat.irq_exits;
1468         return 1;
1469 }
1470
1471 static int nop_on_interception(struct vcpu_svm *svm)
1472 {
1473         return 1;
1474 }
1475
1476 static int halt_interception(struct vcpu_svm *svm)
1477 {
1478         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1479         skip_emulated_instruction(&svm->vcpu);
1480         return kvm_emulate_halt(&svm->vcpu);
1481 }
1482
1483 static int vmmcall_interception(struct vcpu_svm *svm)
1484 {
1485         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1486         skip_emulated_instruction(&svm->vcpu);
1487         kvm_emulate_hypercall(&svm->vcpu);
1488         return 1;
1489 }
1490
1491 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1492 {
1493         if (!(svm->vcpu.arch.efer & EFER_SVME)
1494             || !is_paging(&svm->vcpu)) {
1495                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1496                 return 1;
1497         }
1498
1499         if (svm->vmcb->save.cpl) {
1500                 kvm_inject_gp(&svm->vcpu, 0);
1501                 return 1;
1502         }
1503
1504        return 0;
1505 }
1506
1507 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1508                                       bool has_error_code, u32 error_code)
1509 {
1510         int vmexit;
1511
1512         if (!is_nested(svm))
1513                 return 0;
1514
1515         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1516         svm->vmcb->control.exit_code_hi = 0;
1517         svm->vmcb->control.exit_info_1 = error_code;
1518         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1519
1520         vmexit = nested_svm_intercept(svm);
1521         if (vmexit == NESTED_EXIT_DONE)
1522                 svm->nested.exit_required = true;
1523
1524         return vmexit;
1525 }
1526
1527 /* This function returns true if it is save to enable the irq window */
1528 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1529 {
1530         if (!is_nested(svm))
1531                 return true;
1532
1533         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1534                 return true;
1535
1536         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1537                 return false;
1538
1539         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
1540         svm->vmcb->control.exit_info_1 = 0;
1541         svm->vmcb->control.exit_info_2 = 0;
1542
1543         if (svm->nested.intercept & 1ULL) {
1544                 /*
1545                  * The #vmexit can't be emulated here directly because this
1546                  * code path runs with irqs and preemtion disabled. A
1547                  * #vmexit emulation might sleep. Only signal request for
1548                  * the #vmexit here.
1549                  */
1550                 svm->nested.exit_required = true;
1551                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1552                 return false;
1553         }
1554
1555         return true;
1556 }
1557
1558 /* This function returns true if it is save to enable the nmi window */
1559 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1560 {
1561         if (!is_nested(svm))
1562                 return true;
1563
1564         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1565                 return true;
1566
1567         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1568         svm->nested.exit_required = true;
1569
1570         return false;
1571 }
1572
1573 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1574 {
1575         struct page *page;
1576
1577         might_sleep();
1578
1579         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1580         if (is_error_page(page))
1581                 goto error;
1582
1583         *_page = page;
1584
1585         return kmap(page);
1586
1587 error:
1588         kvm_release_page_clean(page);
1589         kvm_inject_gp(&svm->vcpu, 0);
1590
1591         return NULL;
1592 }
1593
1594 static void nested_svm_unmap(struct page *page)
1595 {
1596         kunmap(page);
1597         kvm_release_page_dirty(page);
1598 }
1599
1600 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1601 {
1602         unsigned port;
1603         u8 val, bit;
1604         u64 gpa;
1605
1606         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1607                 return NESTED_EXIT_HOST;
1608
1609         port = svm->vmcb->control.exit_info_1 >> 16;
1610         gpa  = svm->nested.vmcb_iopm + (port / 8);
1611         bit  = port % 8;
1612         val  = 0;
1613
1614         if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1615                 val &= (1 << bit);
1616
1617         return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1618 }
1619
1620 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1621 {
1622         u32 offset, msr, value;
1623         int write, mask;
1624
1625         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1626                 return NESTED_EXIT_HOST;
1627
1628         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1629         offset = svm_msrpm_offset(msr);
1630         write  = svm->vmcb->control.exit_info_1 & 1;
1631         mask   = 1 << ((2 * (msr & 0xf)) + write);
1632
1633         if (offset == MSR_INVALID)
1634                 return NESTED_EXIT_DONE;
1635
1636         /* Offset is in 32 bit units but need in 8 bit units */
1637         offset *= 4;
1638
1639         if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1640                 return NESTED_EXIT_DONE;
1641
1642         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1643 }
1644
1645 static int nested_svm_exit_special(struct vcpu_svm *svm)
1646 {
1647         u32 exit_code = svm->vmcb->control.exit_code;
1648
1649         switch (exit_code) {
1650         case SVM_EXIT_INTR:
1651         case SVM_EXIT_NMI:
1652                 return NESTED_EXIT_HOST;
1653         case SVM_EXIT_NPF:
1654                 /* For now we are always handling NPFs when using them */
1655                 if (npt_enabled)
1656                         return NESTED_EXIT_HOST;
1657                 break;
1658         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1659                 /* When we're shadowing, trap PFs */
1660                 if (!npt_enabled)
1661                         return NESTED_EXIT_HOST;
1662                 break;
1663         case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1664                 nm_interception(svm);
1665                 break;
1666         default:
1667                 break;
1668         }
1669
1670         return NESTED_EXIT_CONTINUE;
1671 }
1672
1673 /*
1674  * If this function returns true, this #vmexit was already handled
1675  */
1676 static int nested_svm_intercept(struct vcpu_svm *svm)
1677 {
1678         u32 exit_code = svm->vmcb->control.exit_code;
1679         int vmexit = NESTED_EXIT_HOST;
1680
1681         switch (exit_code) {
1682         case SVM_EXIT_MSR:
1683                 vmexit = nested_svm_exit_handled_msr(svm);
1684                 break;
1685         case SVM_EXIT_IOIO:
1686                 vmexit = nested_svm_intercept_ioio(svm);
1687                 break;
1688         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1689                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1690                 if (svm->nested.intercept_cr_read & cr_bits)
1691                         vmexit = NESTED_EXIT_DONE;
1692                 break;
1693         }
1694         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1695                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1696                 if (svm->nested.intercept_cr_write & cr_bits)
1697                         vmexit = NESTED_EXIT_DONE;
1698                 break;
1699         }
1700         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1701                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1702                 if (svm->nested.intercept_dr_read & dr_bits)
1703                         vmexit = NESTED_EXIT_DONE;
1704                 break;
1705         }
1706         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1707                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1708                 if (svm->nested.intercept_dr_write & dr_bits)
1709                         vmexit = NESTED_EXIT_DONE;
1710                 break;
1711         }
1712         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1713                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1714                 if (svm->nested.intercept_exceptions & excp_bits)
1715                         vmexit = NESTED_EXIT_DONE;
1716                 break;
1717         }
1718         default: {
1719                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1720                 if (svm->nested.intercept & exit_bits)
1721                         vmexit = NESTED_EXIT_DONE;
1722         }
1723         }
1724
1725         return vmexit;
1726 }
1727
1728 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1729 {
1730         int vmexit;
1731
1732         vmexit = nested_svm_intercept(svm);
1733
1734         if (vmexit == NESTED_EXIT_DONE)
1735                 nested_svm_vmexit(svm);
1736
1737         return vmexit;
1738 }
1739
1740 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1741 {
1742         struct vmcb_control_area *dst  = &dst_vmcb->control;
1743         struct vmcb_control_area *from = &from_vmcb->control;
1744
1745         dst->intercept_cr_read    = from->intercept_cr_read;
1746         dst->intercept_cr_write   = from->intercept_cr_write;
1747         dst->intercept_dr_read    = from->intercept_dr_read;
1748         dst->intercept_dr_write   = from->intercept_dr_write;
1749         dst->intercept_exceptions = from->intercept_exceptions;
1750         dst->intercept            = from->intercept;
1751         dst->iopm_base_pa         = from->iopm_base_pa;
1752         dst->msrpm_base_pa        = from->msrpm_base_pa;
1753         dst->tsc_offset           = from->tsc_offset;
1754         dst->asid                 = from->asid;
1755         dst->tlb_ctl              = from->tlb_ctl;
1756         dst->int_ctl              = from->int_ctl;
1757         dst->int_vector           = from->int_vector;
1758         dst->int_state            = from->int_state;
1759         dst->exit_code            = from->exit_code;
1760         dst->exit_code_hi         = from->exit_code_hi;
1761         dst->exit_info_1          = from->exit_info_1;
1762         dst->exit_info_2          = from->exit_info_2;
1763         dst->exit_int_info        = from->exit_int_info;
1764         dst->exit_int_info_err    = from->exit_int_info_err;
1765         dst->nested_ctl           = from->nested_ctl;
1766         dst->event_inj            = from->event_inj;
1767         dst->event_inj_err        = from->event_inj_err;
1768         dst->nested_cr3           = from->nested_cr3;
1769         dst->lbr_ctl              = from->lbr_ctl;
1770 }
1771
1772 static int nested_svm_vmexit(struct vcpu_svm *svm)
1773 {
1774         struct vmcb *nested_vmcb;
1775         struct vmcb *hsave = svm->nested.hsave;
1776         struct vmcb *vmcb = svm->vmcb;
1777         struct page *page;
1778
1779         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1780                                        vmcb->control.exit_info_1,
1781                                        vmcb->control.exit_info_2,
1782                                        vmcb->control.exit_int_info,
1783                                        vmcb->control.exit_int_info_err);
1784
1785         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
1786         if (!nested_vmcb)
1787                 return 1;
1788
1789         /* Exit nested SVM mode */
1790         svm->nested.vmcb = 0;
1791
1792         /* Give the current vmcb to the guest */
1793         disable_gif(svm);
1794
1795         nested_vmcb->save.es     = vmcb->save.es;
1796         nested_vmcb->save.cs     = vmcb->save.cs;
1797         nested_vmcb->save.ss     = vmcb->save.ss;
1798         nested_vmcb->save.ds     = vmcb->save.ds;
1799         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
1800         nested_vmcb->save.idtr   = vmcb->save.idtr;
1801         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
1802         if (npt_enabled)
1803                 nested_vmcb->save.cr3    = vmcb->save.cr3;
1804         else
1805                 nested_vmcb->save.cr3    = svm->vcpu.arch.cr3;
1806         nested_vmcb->save.cr2    = vmcb->save.cr2;
1807         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
1808         nested_vmcb->save.rflags = vmcb->save.rflags;
1809         nested_vmcb->save.rip    = vmcb->save.rip;
1810         nested_vmcb->save.rsp    = vmcb->save.rsp;
1811         nested_vmcb->save.rax    = vmcb->save.rax;
1812         nested_vmcb->save.dr7    = vmcb->save.dr7;
1813         nested_vmcb->save.dr6    = vmcb->save.dr6;
1814         nested_vmcb->save.cpl    = vmcb->save.cpl;
1815
1816         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
1817         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
1818         nested_vmcb->control.int_state         = vmcb->control.int_state;
1819         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
1820         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
1821         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
1822         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
1823         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
1824         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1825
1826         /*
1827          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1828          * to make sure that we do not lose injected events. So check event_inj
1829          * here and copy it to exit_int_info if it is valid.
1830          * Exit_int_info and event_inj can't be both valid because the case
1831          * below only happens on a VMRUN instruction intercept which has
1832          * no valid exit_int_info set.
1833          */
1834         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1835                 struct vmcb_control_area *nc = &nested_vmcb->control;
1836
1837                 nc->exit_int_info     = vmcb->control.event_inj;
1838                 nc->exit_int_info_err = vmcb->control.event_inj_err;
1839         }
1840
1841         nested_vmcb->control.tlb_ctl           = 0;
1842         nested_vmcb->control.event_inj         = 0;
1843         nested_vmcb->control.event_inj_err     = 0;
1844
1845         /* We always set V_INTR_MASKING and remember the old value in hflags */
1846         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1847                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1848
1849         /* Restore the original control entries */
1850         copy_vmcb_control_area(vmcb, hsave);
1851
1852         kvm_clear_exception_queue(&svm->vcpu);
1853         kvm_clear_interrupt_queue(&svm->vcpu);
1854
1855         /* Restore selected save entries */
1856         svm->vmcb->save.es = hsave->save.es;
1857         svm->vmcb->save.cs = hsave->save.cs;
1858         svm->vmcb->save.ss = hsave->save.ss;
1859         svm->vmcb->save.ds = hsave->save.ds;
1860         svm->vmcb->save.gdtr = hsave->save.gdtr;
1861         svm->vmcb->save.idtr = hsave->save.idtr;
1862         svm->vmcb->save.rflags = hsave->save.rflags;
1863         svm_set_efer(&svm->vcpu, hsave->save.efer);
1864         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1865         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1866         if (npt_enabled) {
1867                 svm->vmcb->save.cr3 = hsave->save.cr3;
1868                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1869         } else {
1870                 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1871         }
1872         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1873         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1874         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1875         svm->vmcb->save.dr7 = 0;
1876         svm->vmcb->save.cpl = 0;
1877         svm->vmcb->control.exit_int_info = 0;
1878
1879         nested_svm_unmap(page);
1880
1881         kvm_mmu_reset_context(&svm->vcpu);
1882         kvm_mmu_load(&svm->vcpu);
1883
1884         return 0;
1885 }
1886
1887 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1888 {
1889         /*
1890          * This function merges the msr permission bitmaps of kvm and the
1891          * nested vmcb. It is omptimized in that it only merges the parts where
1892          * the kvm msr permission bitmap may contain zero bits
1893          */
1894         int i;
1895
1896         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1897                 return true;
1898
1899         for (i = 0; i < MSRPM_OFFSETS; i++) {
1900                 u32 value, p;
1901                 u64 offset;
1902
1903                 if (msrpm_offsets[i] == 0xffffffff)
1904                         break;
1905
1906                 p      = msrpm_offsets[i];
1907                 offset = svm->nested.vmcb_msrpm + (p * 4);
1908
1909                 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
1910                         return false;
1911
1912                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
1913         }
1914
1915         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
1916
1917         return true;
1918 }
1919
1920 static bool nested_svm_vmrun(struct vcpu_svm *svm)
1921 {
1922         struct vmcb *nested_vmcb;
1923         struct vmcb *hsave = svm->nested.hsave;
1924         struct vmcb *vmcb = svm->vmcb;
1925         struct page *page;
1926         u64 vmcb_gpa;
1927
1928         vmcb_gpa = svm->vmcb->save.rax;
1929
1930         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
1931         if (!nested_vmcb)
1932                 return false;
1933
1934         trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, vmcb_gpa,
1935                                nested_vmcb->save.rip,
1936                                nested_vmcb->control.int_ctl,
1937                                nested_vmcb->control.event_inj,
1938                                nested_vmcb->control.nested_ctl);
1939
1940         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
1941                                     nested_vmcb->control.intercept_cr_write,
1942                                     nested_vmcb->control.intercept_exceptions,
1943                                     nested_vmcb->control.intercept);
1944
1945         /* Clear internal status */
1946         kvm_clear_exception_queue(&svm->vcpu);
1947         kvm_clear_interrupt_queue(&svm->vcpu);
1948
1949         /*
1950          * Save the old vmcb, so we don't need to pick what we save, but can
1951          * restore everything when a VMEXIT occurs
1952          */
1953         hsave->save.es     = vmcb->save.es;
1954         hsave->save.cs     = vmcb->save.cs;
1955         hsave->save.ss     = vmcb->save.ss;
1956         hsave->save.ds     = vmcb->save.ds;
1957         hsave->save.gdtr   = vmcb->save.gdtr;
1958         hsave->save.idtr   = vmcb->save.idtr;
1959         hsave->save.efer   = svm->vcpu.arch.efer;
1960         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
1961         hsave->save.cr4    = svm->vcpu.arch.cr4;
1962         hsave->save.rflags = vmcb->save.rflags;
1963         hsave->save.rip    = svm->next_rip;
1964         hsave->save.rsp    = vmcb->save.rsp;
1965         hsave->save.rax    = vmcb->save.rax;
1966         if (npt_enabled)
1967                 hsave->save.cr3    = vmcb->save.cr3;
1968         else
1969                 hsave->save.cr3    = svm->vcpu.arch.cr3;
1970
1971         copy_vmcb_control_area(hsave, vmcb);
1972
1973         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1974                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1975         else
1976                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1977
1978         /* Load the nested guest state */
1979         svm->vmcb->save.es = nested_vmcb->save.es;
1980         svm->vmcb->save.cs = nested_vmcb->save.cs;
1981         svm->vmcb->save.ss = nested_vmcb->save.ss;
1982         svm->vmcb->save.ds = nested_vmcb->save.ds;
1983         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1984         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1985         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1986         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1987         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1988         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1989         if (npt_enabled) {
1990                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1991                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1992         } else
1993                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1994
1995         /* Guest paging mode is active - reset mmu */
1996         kvm_mmu_reset_context(&svm->vcpu);
1997
1998         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
1999         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2000         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2001         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2002
2003         /* In case we don't even reach vcpu_run, the fields are not updated */
2004         svm->vmcb->save.rax = nested_vmcb->save.rax;
2005         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2006         svm->vmcb->save.rip = nested_vmcb->save.rip;
2007         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2008         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2009         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2010
2011         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2012         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2013
2014         /* cache intercepts */
2015         svm->nested.intercept_cr_read    = nested_vmcb->control.intercept_cr_read;
2016         svm->nested.intercept_cr_write   = nested_vmcb->control.intercept_cr_write;
2017         svm->nested.intercept_dr_read    = nested_vmcb->control.intercept_dr_read;
2018         svm->nested.intercept_dr_write   = nested_vmcb->control.intercept_dr_write;
2019         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2020         svm->nested.intercept            = nested_vmcb->control.intercept;
2021
2022         force_new_asid(&svm->vcpu);
2023         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2024         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2025                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2026         else
2027                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2028
2029         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2030                 /* We only want the cr8 intercept bits of the guest */
2031                 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2032                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2033         }
2034
2035         /*
2036          * We don't want a nested guest to be more powerful than the guest, so
2037          * all intercepts are ORed
2038          */
2039         svm->vmcb->control.intercept_cr_read |=
2040                 nested_vmcb->control.intercept_cr_read;
2041         svm->vmcb->control.intercept_cr_write |=
2042                 nested_vmcb->control.intercept_cr_write;
2043         svm->vmcb->control.intercept_dr_read |=
2044                 nested_vmcb->control.intercept_dr_read;
2045         svm->vmcb->control.intercept_dr_write |=
2046                 nested_vmcb->control.intercept_dr_write;
2047         svm->vmcb->control.intercept_exceptions |=
2048                 nested_vmcb->control.intercept_exceptions;
2049
2050         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2051
2052         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2053         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2054         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2055         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2056         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2057         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2058
2059         nested_svm_unmap(page);
2060
2061         /* nested_vmcb is our indicator if nested SVM is activated */
2062         svm->nested.vmcb = vmcb_gpa;
2063
2064         enable_gif(svm);
2065
2066         return true;
2067 }
2068
2069 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2070 {
2071         to_vmcb->save.fs = from_vmcb->save.fs;
2072         to_vmcb->save.gs = from_vmcb->save.gs;
2073         to_vmcb->save.tr = from_vmcb->save.tr;
2074         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2075         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2076         to_vmcb->save.star = from_vmcb->save.star;
2077         to_vmcb->save.lstar = from_vmcb->save.lstar;
2078         to_vmcb->save.cstar = from_vmcb->save.cstar;
2079         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2080         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2081         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2082         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2083 }
2084
2085 static int vmload_interception(struct vcpu_svm *svm)
2086 {
2087         struct vmcb *nested_vmcb;
2088         struct page *page;
2089
2090         if (nested_svm_check_permissions(svm))
2091                 return 1;
2092
2093         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2094         skip_emulated_instruction(&svm->vcpu);
2095
2096         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2097         if (!nested_vmcb)
2098                 return 1;
2099
2100         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2101         nested_svm_unmap(page);
2102
2103         return 1;
2104 }
2105
2106 static int vmsave_interception(struct vcpu_svm *svm)
2107 {
2108         struct vmcb *nested_vmcb;
2109         struct page *page;
2110
2111         if (nested_svm_check_permissions(svm))
2112                 return 1;
2113
2114         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2115         skip_emulated_instruction(&svm->vcpu);
2116
2117         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2118         if (!nested_vmcb)
2119                 return 1;
2120
2121         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2122         nested_svm_unmap(page);
2123
2124         return 1;
2125 }
2126
2127 static int vmrun_interception(struct vcpu_svm *svm)
2128 {
2129         if (nested_svm_check_permissions(svm))
2130                 return 1;
2131
2132         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2133         skip_emulated_instruction(&svm->vcpu);
2134
2135         if (!nested_svm_vmrun(svm))
2136                 return 1;
2137
2138         if (!nested_svm_vmrun_msrpm(svm))
2139                 goto failed;
2140
2141         return 1;
2142
2143 failed:
2144
2145         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
2146         svm->vmcb->control.exit_code_hi = 0;
2147         svm->vmcb->control.exit_info_1  = 0;
2148         svm->vmcb->control.exit_info_2  = 0;
2149
2150         nested_svm_vmexit(svm);
2151
2152         return 1;
2153 }
2154
2155 static int stgi_interception(struct vcpu_svm *svm)
2156 {
2157         if (nested_svm_check_permissions(svm))
2158                 return 1;
2159
2160         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2161         skip_emulated_instruction(&svm->vcpu);
2162
2163         enable_gif(svm);
2164
2165         return 1;
2166 }
2167
2168 static int clgi_interception(struct vcpu_svm *svm)
2169 {
2170         if (nested_svm_check_permissions(svm))
2171                 return 1;
2172
2173         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2174         skip_emulated_instruction(&svm->vcpu);
2175
2176         disable_gif(svm);
2177
2178         /* After a CLGI no interrupts should come */
2179         svm_clear_vintr(svm);
2180         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2181
2182         return 1;
2183 }
2184
2185 static int invlpga_interception(struct vcpu_svm *svm)
2186 {
2187         struct kvm_vcpu *vcpu = &svm->vcpu;
2188
2189         trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2190                           vcpu->arch.regs[VCPU_REGS_RAX]);
2191
2192         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2193         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2194
2195         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2196         skip_emulated_instruction(&svm->vcpu);
2197         return 1;
2198 }
2199
2200 static int skinit_interception(struct vcpu_svm *svm)
2201 {
2202         trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2203
2204         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2205         return 1;
2206 }
2207
2208 static int invalid_op_interception(struct vcpu_svm *svm)
2209 {
2210         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2211         return 1;
2212 }
2213
2214 static int task_switch_interception(struct vcpu_svm *svm)
2215 {
2216         u16 tss_selector;
2217         int reason;
2218         int int_type = svm->vmcb->control.exit_int_info &
2219                 SVM_EXITINTINFO_TYPE_MASK;
2220         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2221         uint32_t type =
2222                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2223         uint32_t idt_v =
2224                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2225         bool has_error_code = false;
2226         u32 error_code = 0;
2227
2228         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2229
2230         if (svm->vmcb->control.exit_info_2 &
2231             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2232                 reason = TASK_SWITCH_IRET;
2233         else if (svm->vmcb->control.exit_info_2 &
2234                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2235                 reason = TASK_SWITCH_JMP;
2236         else if (idt_v)
2237                 reason = TASK_SWITCH_GATE;
2238         else
2239                 reason = TASK_SWITCH_CALL;
2240
2241         if (reason == TASK_SWITCH_GATE) {
2242                 switch (type) {
2243                 case SVM_EXITINTINFO_TYPE_NMI:
2244                         svm->vcpu.arch.nmi_injected = false;
2245                         break;
2246                 case SVM_EXITINTINFO_TYPE_EXEPT:
2247                         if (svm->vmcb->control.exit_info_2 &
2248                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2249                                 has_error_code = true;
2250                                 error_code =
2251                                         (u32)svm->vmcb->control.exit_info_2;
2252                         }
2253                         kvm_clear_exception_queue(&svm->vcpu);
2254                         break;
2255                 case SVM_EXITINTINFO_TYPE_INTR:
2256                         kvm_clear_interrupt_queue(&svm->vcpu);
2257                         break;
2258                 default:
2259                         break;
2260                 }
2261         }
2262
2263         if (reason != TASK_SWITCH_GATE ||
2264             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2265             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2266              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2267                 skip_emulated_instruction(&svm->vcpu);
2268
2269         if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2270                                 has_error_code, error_code) == EMULATE_FAIL) {
2271                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2272                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2273                 svm->vcpu.run->internal.ndata = 0;
2274                 return 0;
2275         }
2276         return 1;
2277 }
2278
2279 static int cpuid_interception(struct vcpu_svm *svm)
2280 {
2281         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2282         kvm_emulate_cpuid(&svm->vcpu);
2283         return 1;
2284 }
2285
2286 static int iret_interception(struct vcpu_svm *svm)
2287 {
2288         ++svm->vcpu.stat.nmi_window_exits;
2289         svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2290         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2291         return 1;
2292 }
2293
2294 static int invlpg_interception(struct vcpu_svm *svm)
2295 {
2296         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2297                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2298         return 1;
2299 }
2300
2301 static int emulate_on_interception(struct vcpu_svm *svm)
2302 {
2303         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2304                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2305         return 1;
2306 }
2307
2308 static int cr8_write_interception(struct vcpu_svm *svm)
2309 {
2310         struct kvm_run *kvm_run = svm->vcpu.run;
2311
2312         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2313         /* instruction emulation calls kvm_set_cr8() */
2314         emulate_instruction(&svm->vcpu, 0, 0, 0);
2315         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2316                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2317                 return 1;
2318         }
2319         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2320                 return 1;
2321         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2322         return 0;
2323 }
2324
2325 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2326 {
2327         struct vcpu_svm *svm = to_svm(vcpu);
2328
2329         switch (ecx) {
2330         case MSR_IA32_TSC: {
2331                 u64 tsc_offset;
2332
2333                 if (is_nested(svm))
2334                         tsc_offset = svm->nested.hsave->control.tsc_offset;
2335                 else
2336                         tsc_offset = svm->vmcb->control.tsc_offset;
2337
2338                 *data = tsc_offset + native_read_tsc();
2339                 break;
2340         }
2341         case MSR_K6_STAR:
2342                 *data = svm->vmcb->save.star;
2343                 break;
2344 #ifdef CONFIG_X86_64
2345         case MSR_LSTAR:
2346                 *data = svm->vmcb->save.lstar;
2347                 break;
2348         case MSR_CSTAR:
2349                 *data = svm->vmcb->save.cstar;
2350                 break;
2351         case MSR_KERNEL_GS_BASE:
2352                 *data = svm->vmcb->save.kernel_gs_base;
2353                 break;
2354         case MSR_SYSCALL_MASK:
2355                 *data = svm->vmcb->save.sfmask;
2356                 break;
2357 #endif
2358         case MSR_IA32_SYSENTER_CS:
2359                 *data = svm->vmcb->save.sysenter_cs;
2360                 break;
2361         case MSR_IA32_SYSENTER_EIP:
2362                 *data = svm->sysenter_eip;
2363                 break;
2364         case MSR_IA32_SYSENTER_ESP:
2365                 *data = svm->sysenter_esp;
2366                 break;
2367         /*
2368          * Nobody will change the following 5 values in the VMCB so we can
2369          * safely return them on rdmsr. They will always be 0 until LBRV is
2370          * implemented.
2371          */
2372         case MSR_IA32_DEBUGCTLMSR:
2373                 *data = svm->vmcb->save.dbgctl;
2374                 break;
2375         case MSR_IA32_LASTBRANCHFROMIP:
2376                 *data = svm->vmcb->save.br_from;
2377                 break;
2378         case MSR_IA32_LASTBRANCHTOIP:
2379                 *data = svm->vmcb->save.br_to;
2380                 break;
2381         case MSR_IA32_LASTINTFROMIP:
2382                 *data = svm->vmcb->save.last_excp_from;
2383                 break;
2384         case MSR_IA32_LASTINTTOIP:
2385                 *data = svm->vmcb->save.last_excp_to;
2386                 break;
2387         case MSR_VM_HSAVE_PA:
2388                 *data = svm->nested.hsave_msr;
2389                 break;
2390         case MSR_VM_CR:
2391                 *data = svm->nested.vm_cr_msr;
2392                 break;
2393         case MSR_IA32_UCODE_REV:
2394                 *data = 0x01000065;
2395                 break;
2396         default:
2397                 return kvm_get_msr_common(vcpu, ecx, data);
2398         }
2399         return 0;
2400 }
2401
2402 static int rdmsr_interception(struct vcpu_svm *svm)
2403 {
2404         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2405         u64 data;
2406
2407         if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2408                 trace_kvm_msr_read_ex(ecx);
2409                 kvm_inject_gp(&svm->vcpu, 0);
2410         } else {
2411                 trace_kvm_msr_read(ecx, data);
2412
2413                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2414                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2415                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2416                 skip_emulated_instruction(&svm->vcpu);
2417         }
2418         return 1;
2419 }
2420
2421 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2422 {
2423         struct vcpu_svm *svm = to_svm(vcpu);
2424         int svm_dis, chg_mask;
2425
2426         if (data & ~SVM_VM_CR_VALID_MASK)
2427                 return 1;
2428
2429         chg_mask = SVM_VM_CR_VALID_MASK;
2430
2431         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2432                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2433
2434         svm->nested.vm_cr_msr &= ~chg_mask;
2435         svm->nested.vm_cr_msr |= (data & chg_mask);
2436
2437         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2438
2439         /* check for svm_disable while efer.svme is set */
2440         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2441                 return 1;
2442
2443         return 0;
2444 }
2445
2446 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2447 {
2448         struct vcpu_svm *svm = to_svm(vcpu);
2449
2450         switch (ecx) {
2451         case MSR_IA32_TSC: {
2452                 u64 tsc_offset = data - native_read_tsc();
2453                 u64 g_tsc_offset = 0;
2454
2455                 if (is_nested(svm)) {
2456                         g_tsc_offset = svm->vmcb->control.tsc_offset -
2457                                        svm->nested.hsave->control.tsc_offset;
2458                         svm->nested.hsave->control.tsc_offset = tsc_offset;
2459                 }
2460
2461                 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2462
2463                 break;
2464         }
2465         case MSR_K6_STAR:
2466                 svm->vmcb->save.star = data;
2467                 break;
2468 #ifdef CONFIG_X86_64
2469         case MSR_LSTAR:
2470                 svm->vmcb->save.lstar = data;
2471                 break;
2472         case MSR_CSTAR:
2473                 svm->vmcb->save.cstar = data;
2474                 break;
2475         case MSR_KERNEL_GS_BASE:
2476                 svm->vmcb->save.kernel_gs_base = data;
2477                 break;
2478         case MSR_SYSCALL_MASK:
2479                 svm->vmcb->save.sfmask = data;
2480                 break;
2481 #endif
2482         case MSR_IA32_SYSENTER_CS:
2483                 svm->vmcb->save.sysenter_cs = data;
2484                 break;
2485         case MSR_IA32_SYSENTER_EIP:
2486                 svm->sysenter_eip = data;
2487                 svm->vmcb->save.sysenter_eip = data;
2488                 break;
2489         case MSR_IA32_SYSENTER_ESP:
2490                 svm->sysenter_esp = data;
2491                 svm->vmcb->save.sysenter_esp = data;
2492                 break;
2493         case MSR_IA32_DEBUGCTLMSR:
2494                 if (!svm_has(SVM_FEATURE_LBRV)) {
2495                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2496                                         __func__, data);
2497                         break;
2498                 }
2499                 if (data & DEBUGCTL_RESERVED_BITS)
2500                         return 1;
2501
2502                 svm->vmcb->save.dbgctl = data;
2503                 if (data & (1ULL<<0))
2504                         svm_enable_lbrv(svm);
2505                 else
2506                         svm_disable_lbrv(svm);
2507                 break;
2508         case MSR_VM_HSAVE_PA:
2509                 svm->nested.hsave_msr = data;
2510                 break;
2511         case MSR_VM_CR:
2512                 return svm_set_vm_cr(vcpu, data);
2513         case MSR_VM_IGNNE:
2514                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2515                 break;
2516         default:
2517                 return kvm_set_msr_common(vcpu, ecx, data);
2518         }
2519         return 0;
2520 }
2521
2522 static int wrmsr_interception(struct vcpu_svm *svm)
2523 {
2524         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2525         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2526                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2527
2528
2529         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2530         if (svm_set_msr(&svm->vcpu, ecx, data)) {
2531                 trace_kvm_msr_write_ex(ecx, data);
2532                 kvm_inject_gp(&svm->vcpu, 0);
2533         } else {
2534                 trace_kvm_msr_write(ecx, data);
2535                 skip_emulated_instruction(&svm->vcpu);
2536         }
2537         return 1;
2538 }
2539
2540 static int msr_interception(struct vcpu_svm *svm)
2541 {
2542         if (svm->vmcb->control.exit_info_1)
2543                 return wrmsr_interception(svm);
2544         else
2545                 return rdmsr_interception(svm);
2546 }
2547
2548 static int interrupt_window_interception(struct vcpu_svm *svm)
2549 {
2550         struct kvm_run *kvm_run = svm->vcpu.run;
2551
2552         svm_clear_vintr(svm);
2553         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2554         /*
2555          * If the user space waits to inject interrupts, exit as soon as
2556          * possible
2557          */
2558         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2559             kvm_run->request_interrupt_window &&
2560             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2561                 ++svm->vcpu.stat.irq_window_exits;
2562                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2563                 return 0;
2564         }
2565
2566         return 1;
2567 }
2568
2569 static int pause_interception(struct vcpu_svm *svm)
2570 {
2571         kvm_vcpu_on_spin(&(svm->vcpu));
2572         return 1;
2573 }
2574
2575 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2576         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2577         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2578         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2579         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2580         [SVM_EXIT_CR0_SEL_WRITE]                = emulate_on_interception,
2581         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2582         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2583         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2584         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2585         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2586         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2587         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2588         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2589         [SVM_EXIT_READ_DR4]                     = emulate_on_interception,
2590         [SVM_EXIT_READ_DR5]                     = emulate_on_interception,
2591         [SVM_EXIT_READ_DR6]                     = emulate_on_interception,
2592         [SVM_EXIT_READ_DR7]                     = emulate_on_interception,
2593         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2594         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2595         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2596         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2597         [SVM_EXIT_WRITE_DR4]                    = emulate_on_interception,
2598         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2599         [SVM_EXIT_WRITE_DR6]                    = emulate_on_interception,
2600         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2601         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2602         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2603         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2604         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2605         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2606         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2607         [SVM_EXIT_INTR]                         = intr_interception,
2608         [SVM_EXIT_NMI]                          = nmi_interception,
2609         [SVM_EXIT_SMI]                          = nop_on_interception,
2610         [SVM_EXIT_INIT]                         = nop_on_interception,
2611         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2612         [SVM_EXIT_CPUID]                        = cpuid_interception,
2613         [SVM_EXIT_IRET]                         = iret_interception,
2614         [SVM_EXIT_INVD]                         = emulate_on_interception,
2615         [SVM_EXIT_PAUSE]                        = pause_interception,
2616         [SVM_EXIT_HLT]                          = halt_interception,
2617         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2618         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2619         [SVM_EXIT_IOIO]                         = io_interception,
2620         [SVM_EXIT_MSR]                          = msr_interception,
2621         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2622         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2623         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2624         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2625         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2626         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2627         [SVM_EXIT_STGI]                         = stgi_interception,
2628         [SVM_EXIT_CLGI]                         = clgi_interception,
2629         [SVM_EXIT_SKINIT]                       = skinit_interception,
2630         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2631         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2632         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2633         [SVM_EXIT_NPF]                          = pf_interception,
2634 };
2635
2636 static int handle_exit(struct kvm_vcpu *vcpu)
2637 {
2638         struct vcpu_svm *svm = to_svm(vcpu);
2639         struct kvm_run *kvm_run = vcpu->run;
2640         u32 exit_code = svm->vmcb->control.exit_code;
2641
2642         trace_kvm_exit(exit_code, vcpu);
2643
2644         if (unlikely(svm->nested.exit_required)) {
2645                 nested_svm_vmexit(svm);
2646                 svm->nested.exit_required = false;
2647
2648                 return 1;
2649         }
2650
2651         if (is_nested(svm)) {
2652                 int vmexit;
2653
2654                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2655                                         svm->vmcb->control.exit_info_1,
2656                                         svm->vmcb->control.exit_info_2,
2657                                         svm->vmcb->control.exit_int_info,
2658                                         svm->vmcb->control.exit_int_info_err);
2659
2660                 vmexit = nested_svm_exit_special(svm);
2661
2662                 if (vmexit == NESTED_EXIT_CONTINUE)
2663                         vmexit = nested_svm_exit_handled(svm);
2664
2665                 if (vmexit == NESTED_EXIT_DONE)
2666                         return 1;
2667         }
2668
2669         svm_complete_interrupts(svm);
2670
2671         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2672                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2673         if (npt_enabled)
2674                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2675
2676         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2677                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2678                 kvm_run->fail_entry.hardware_entry_failure_reason
2679                         = svm->vmcb->control.exit_code;
2680                 return 0;
2681         }
2682
2683         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2684             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2685             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2686                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2687                        "exit_code 0x%x\n",
2688                        __func__, svm->vmcb->control.exit_int_info,
2689                        exit_code);
2690
2691         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2692             || !svm_exit_handlers[exit_code]) {
2693                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2694                 kvm_run->hw.hardware_exit_reason = exit_code;
2695                 return 0;
2696         }
2697
2698         return svm_exit_handlers[exit_code](svm);
2699 }
2700
2701 static void reload_tss(struct kvm_vcpu *vcpu)
2702 {
2703         int cpu = raw_smp_processor_id();
2704
2705         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2706         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
2707         load_TR_desc();
2708 }
2709
2710 static void pre_svm_run(struct vcpu_svm *svm)
2711 {
2712         int cpu = raw_smp_processor_id();
2713
2714         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2715
2716         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2717         /* FIXME: handle wraparound of asid_generation */
2718         if (svm->asid_generation != sd->asid_generation)
2719                 new_asid(svm, sd);
2720 }
2721
2722 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2723 {
2724         struct vcpu_svm *svm = to_svm(vcpu);
2725
2726         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2727         vcpu->arch.hflags |= HF_NMI_MASK;
2728         svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2729         ++vcpu->stat.nmi_injections;
2730 }
2731
2732 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2733 {
2734         struct vmcb_control_area *control;
2735
2736         trace_kvm_inj_virq(irq);
2737
2738         ++svm->vcpu.stat.irq_injections;
2739         control = &svm->vmcb->control;
2740         control->int_vector = irq;
2741         control->int_ctl &= ~V_INTR_PRIO_MASK;
2742         control->int_ctl |= V_IRQ_MASK |
2743                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2744 }
2745
2746 static void svm_set_irq(struct kvm_vcpu *vcpu)
2747 {
2748         struct vcpu_svm *svm = to_svm(vcpu);
2749
2750         BUG_ON(!(gif_set(svm)));
2751
2752         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2753                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2754 }
2755
2756 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2757 {
2758         struct vcpu_svm *svm = to_svm(vcpu);
2759
2760         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2761                 return;
2762
2763         if (irr == -1)
2764                 return;
2765
2766         if (tpr >= irr)
2767                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2768 }
2769
2770 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2771 {
2772         struct vcpu_svm *svm = to_svm(vcpu);
2773         struct vmcb *vmcb = svm->vmcb;
2774         int ret;
2775         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2776               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2777         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
2778
2779         return ret;
2780 }
2781
2782 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2783 {
2784         struct vcpu_svm *svm = to_svm(vcpu);
2785
2786         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2787 }
2788
2789 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2790 {
2791         struct vcpu_svm *svm = to_svm(vcpu);
2792
2793         if (masked) {
2794                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2795                 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2796         } else {
2797                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2798                 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2799         }
2800 }
2801
2802 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2803 {
2804         struct vcpu_svm *svm = to_svm(vcpu);
2805         struct vmcb *vmcb = svm->vmcb;
2806         int ret;
2807
2808         if (!gif_set(svm) ||
2809              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2810                 return 0;
2811
2812         ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2813
2814         if (is_nested(svm))
2815                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2816
2817         return ret;
2818 }
2819
2820 static void enable_irq_window(struct kvm_vcpu *vcpu)
2821 {
2822         struct vcpu_svm *svm = to_svm(vcpu);
2823
2824         /*
2825          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
2826          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
2827          * get that intercept, this function will be called again though and
2828          * we'll get the vintr intercept.
2829          */
2830         if (gif_set(svm) && nested_svm_intr(svm)) {
2831                 svm_set_vintr(svm);
2832                 svm_inject_irq(svm, 0x0);
2833         }
2834 }
2835
2836 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2837 {
2838         struct vcpu_svm *svm = to_svm(vcpu);
2839
2840         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2841             == HF_NMI_MASK)
2842                 return; /* IRET will cause a vm exit */
2843
2844         /*
2845          * Something prevents NMI from been injected. Single step over possible
2846          * problem (IRET or exception injection or interrupt shadow)
2847          */
2848         svm->nmi_singlestep = true;
2849         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2850         update_db_intercept(vcpu);
2851 }
2852
2853 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2854 {
2855         return 0;
2856 }
2857
2858 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2859 {
2860         force_new_asid(vcpu);
2861 }
2862
2863 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2864 {
2865 }
2866
2867 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2868 {
2869         struct vcpu_svm *svm = to_svm(vcpu);
2870
2871         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2872                 return;
2873
2874         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2875                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2876                 kvm_set_cr8(vcpu, cr8);
2877         }
2878 }
2879
2880 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2881 {
2882         struct vcpu_svm *svm = to_svm(vcpu);
2883         u64 cr8;
2884
2885         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2886                 return;
2887
2888         cr8 = kvm_get_cr8(vcpu);
2889         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2890         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2891 }
2892
2893 static void svm_complete_interrupts(struct vcpu_svm *svm)
2894 {
2895         u8 vector;
2896         int type;
2897         u32 exitintinfo = svm->vmcb->control.exit_int_info;
2898         unsigned int3_injected = svm->int3_injected;
2899
2900         svm->int3_injected = 0;
2901
2902         if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2903                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2904
2905         svm->vcpu.arch.nmi_injected = false;
2906         kvm_clear_exception_queue(&svm->vcpu);
2907         kvm_clear_interrupt_queue(&svm->vcpu);
2908
2909         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2910                 return;
2911
2912         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2913         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2914
2915         switch (type) {
2916         case SVM_EXITINTINFO_TYPE_NMI:
2917                 svm->vcpu.arch.nmi_injected = true;
2918                 break;
2919         case SVM_EXITINTINFO_TYPE_EXEPT:
2920                 if (is_nested(svm))
2921                         break;
2922                 /*
2923                  * In case of software exceptions, do not reinject the vector,
2924                  * but re-execute the instruction instead. Rewind RIP first
2925                  * if we emulated INT3 before.
2926                  */
2927                 if (kvm_exception_is_soft(vector)) {
2928                         if (vector == BP_VECTOR && int3_injected &&
2929                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
2930                                 kvm_rip_write(&svm->vcpu,
2931                                               kvm_rip_read(&svm->vcpu) -
2932                                               int3_injected);
2933                         break;
2934                 }
2935                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2936                         u32 err = svm->vmcb->control.exit_int_info_err;
2937                         kvm_queue_exception_e(&svm->vcpu, vector, err);
2938
2939                 } else
2940                         kvm_queue_exception(&svm->vcpu, vector);
2941                 break;
2942         case SVM_EXITINTINFO_TYPE_INTR:
2943                 kvm_queue_interrupt(&svm->vcpu, vector, false);
2944                 break;
2945         default:
2946                 break;
2947         }
2948 }
2949
2950 #ifdef CONFIG_X86_64
2951 #define R "r"
2952 #else
2953 #define R "e"
2954 #endif
2955
2956 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
2957 {
2958         struct vcpu_svm *svm = to_svm(vcpu);
2959         u16 fs_selector;
2960         u16 gs_selector;
2961         u16 ldt_selector;
2962
2963         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2964         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2965         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2966
2967         /*
2968          * A vmexit emulation is required before the vcpu can be executed
2969          * again.
2970          */
2971         if (unlikely(svm->nested.exit_required))
2972                 return;
2973
2974         pre_svm_run(svm);
2975
2976         sync_lapic_to_cr8(vcpu);
2977
2978         save_host_msrs(vcpu);
2979         fs_selector = kvm_read_fs();
2980         gs_selector = kvm_read_gs();
2981         ldt_selector = kvm_read_ldt();
2982         svm->vmcb->save.cr2 = vcpu->arch.cr2;
2983         /* required for live migration with NPT */
2984         if (npt_enabled)
2985                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2986
2987         clgi();
2988
2989         local_irq_enable();
2990
2991         asm volatile (
2992                 "push %%"R"bp; \n\t"
2993                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2994                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2995                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2996                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2997                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2998                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2999 #ifdef CONFIG_X86_64
3000                 "mov %c[r8](%[svm]),  %%r8  \n\t"
3001                 "mov %c[r9](%[svm]),  %%r9  \n\t"
3002                 "mov %c[r10](%[svm]), %%r10 \n\t"
3003                 "mov %c[r11](%[svm]), %%r11 \n\t"
3004                 "mov %c[r12](%[svm]), %%r12 \n\t"
3005                 "mov %c[r13](%[svm]), %%r13 \n\t"
3006                 "mov %c[r14](%[svm]), %%r14 \n\t"
3007                 "mov %c[r15](%[svm]), %%r15 \n\t"
3008 #endif
3009
3010                 /* Enter guest mode */
3011                 "push %%"R"ax \n\t"
3012                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3013                 __ex(SVM_VMLOAD) "\n\t"
3014                 __ex(SVM_VMRUN) "\n\t"
3015                 __ex(SVM_VMSAVE) "\n\t"
3016                 "pop %%"R"ax \n\t"
3017
3018                 /* Save guest registers, load host registers */
3019                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3020                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3021                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3022                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3023                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3024                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3025 #ifdef CONFIG_X86_64
3026                 "mov %%r8,  %c[r8](%[svm]) \n\t"
3027                 "mov %%r9,  %c[r9](%[svm]) \n\t"
3028                 "mov %%r10, %c[r10](%[svm]) \n\t"
3029                 "mov %%r11, %c[r11](%[svm]) \n\t"
3030                 "mov %%r12, %c[r12](%[svm]) \n\t"
3031                 "mov %%r13, %c[r13](%[svm]) \n\t"
3032                 "mov %%r14, %c[r14](%[svm]) \n\t"
3033                 "mov %%r15, %c[r15](%[svm]) \n\t"
3034 #endif
3035                 "pop %%"R"bp"
3036                 :
3037                 : [svm]"a"(svm),
3038                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3039                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3040                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3041                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3042                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3043                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3044                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3045 #ifdef CONFIG_X86_64
3046                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3047                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3048                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3049                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3050                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3051                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3052                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3053                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3054 #endif
3055                 : "cc", "memory"
3056                 , R"bx", R"cx", R"dx", R"si", R"di"
3057 #ifdef CONFIG_X86_64
3058                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3059 #endif
3060                 );
3061
3062         vcpu->arch.cr2 = svm->vmcb->save.cr2;
3063         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3064         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3065         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3066
3067         kvm_load_fs(fs_selector);
3068         kvm_load_gs(gs_selector);
3069         kvm_load_ldt(ldt_selector);
3070         load_host_msrs(vcpu);
3071
3072         reload_tss(vcpu);
3073
3074         local_irq_disable();
3075
3076         stgi();
3077
3078         sync_cr8_to_lapic(vcpu);
3079
3080         svm->next_rip = 0;
3081
3082         if (npt_enabled) {
3083                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3084                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3085         }
3086 }
3087
3088 #undef R
3089
3090 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3091 {
3092         struct vcpu_svm *svm = to_svm(vcpu);
3093
3094         if (npt_enabled) {
3095                 svm->vmcb->control.nested_cr3 = root;
3096                 force_new_asid(vcpu);
3097                 return;
3098         }
3099
3100         svm->vmcb->save.cr3 = root;
3101         force_new_asid(vcpu);
3102 }
3103
3104 static int is_disabled(void)
3105 {
3106         u64 vm_cr;
3107
3108         rdmsrl(MSR_VM_CR, vm_cr);
3109         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3110                 return 1;
3111
3112         return 0;
3113 }
3114
3115 static void
3116 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3117 {
3118         /*
3119          * Patch in the VMMCALL instruction:
3120          */
3121         hypercall[0] = 0x0f;
3122         hypercall[1] = 0x01;
3123         hypercall[2] = 0xd9;
3124 }
3125
3126 static void svm_check_processor_compat(void *rtn)
3127 {
3128         *(int *)rtn = 0;
3129 }
3130
3131 static bool svm_cpu_has_accelerated_tpr(void)
3132 {
3133         return false;
3134 }
3135
3136 static int get_npt_level(void)
3137 {
3138 #ifdef CONFIG_X86_64
3139         return PT64_ROOT_LEVEL;
3140 #else
3141         return PT32E_ROOT_LEVEL;
3142 #endif
3143 }
3144
3145 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3146 {
3147         return 0;
3148 }
3149
3150 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3151 {
3152 }
3153
3154 static const struct trace_print_flags svm_exit_reasons_str[] = {
3155         { SVM_EXIT_READ_CR0,                    "read_cr0" },
3156         { SVM_EXIT_READ_CR3,                    "read_cr3" },
3157         { SVM_EXIT_READ_CR4,                    "read_cr4" },
3158         { SVM_EXIT_READ_CR8,                    "read_cr8" },
3159         { SVM_EXIT_WRITE_CR0,                   "write_cr0" },
3160         { SVM_EXIT_WRITE_CR3,                   "write_cr3" },
3161         { SVM_EXIT_WRITE_CR4,                   "write_cr4" },
3162         { SVM_EXIT_WRITE_CR8,                   "write_cr8" },
3163         { SVM_EXIT_READ_DR0,                    "read_dr0" },
3164         { SVM_EXIT_READ_DR1,                    "read_dr1" },
3165         { SVM_EXIT_READ_DR2,                    "read_dr2" },
3166         { SVM_EXIT_READ_DR3,                    "read_dr3" },
3167         { SVM_EXIT_WRITE_DR0,                   "write_dr0" },
3168         { SVM_EXIT_WRITE_DR1,                   "write_dr1" },
3169         { SVM_EXIT_WRITE_DR2,                   "write_dr2" },
3170         { SVM_EXIT_WRITE_DR3,                   "write_dr3" },
3171         { SVM_EXIT_WRITE_DR5,                   "write_dr5" },
3172         { SVM_EXIT_WRITE_DR7,                   "write_dr7" },
3173         { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" },
3174         { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" },
3175         { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" },
3176         { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" },
3177         { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" },
3178         { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" },
3179         { SVM_EXIT_INTR,                        "interrupt" },
3180         { SVM_EXIT_NMI,                         "nmi" },
3181         { SVM_EXIT_SMI,                         "smi" },
3182         { SVM_EXIT_INIT,                        "init" },
3183         { SVM_EXIT_VINTR,                       "vintr" },
3184         { SVM_EXIT_CPUID,                       "cpuid" },
3185         { SVM_EXIT_INVD,                        "invd" },
3186         { SVM_EXIT_HLT,                         "hlt" },
3187         { SVM_EXIT_INVLPG,                      "invlpg" },
3188         { SVM_EXIT_INVLPGA,                     "invlpga" },
3189         { SVM_EXIT_IOIO,                        "io" },
3190         { SVM_EXIT_MSR,                         "msr" },
3191         { SVM_EXIT_TASK_SWITCH,                 "task_switch" },
3192         { SVM_EXIT_SHUTDOWN,                    "shutdown" },
3193         { SVM_EXIT_VMRUN,                       "vmrun" },
3194         { SVM_EXIT_VMMCALL,                     "hypercall" },
3195         { SVM_EXIT_VMLOAD,                      "vmload" },
3196         { SVM_EXIT_VMSAVE,                      "vmsave" },
3197         { SVM_EXIT_STGI,                        "stgi" },
3198         { SVM_EXIT_CLGI,                        "clgi" },
3199         { SVM_EXIT_SKINIT,                      "skinit" },
3200         { SVM_EXIT_WBINVD,                      "wbinvd" },
3201         { SVM_EXIT_MONITOR,                     "monitor" },
3202         { SVM_EXIT_MWAIT,                       "mwait" },
3203         { SVM_EXIT_NPF,                         "npf" },
3204         { -1, NULL }
3205 };
3206
3207 static int svm_get_lpage_level(void)
3208 {
3209         return PT_PDPE_LEVEL;
3210 }
3211
3212 static bool svm_rdtscp_supported(void)
3213 {
3214         return false;
3215 }
3216
3217 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3218 {
3219         struct vcpu_svm *svm = to_svm(vcpu);
3220
3221         svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
3222         if (is_nested(svm))
3223                 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3224         update_cr0_intercept(svm);
3225 }
3226
3227 static struct kvm_x86_ops svm_x86_ops = {
3228         .cpu_has_kvm_support = has_svm,
3229         .disabled_by_bios = is_disabled,
3230         .hardware_setup = svm_hardware_setup,
3231         .hardware_unsetup = svm_hardware_unsetup,
3232         .check_processor_compatibility = svm_check_processor_compat,
3233         .hardware_enable = svm_hardware_enable,
3234         .hardware_disable = svm_hardware_disable,
3235         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3236
3237         .vcpu_create = svm_create_vcpu,
3238         .vcpu_free = svm_free_vcpu,
3239         .vcpu_reset = svm_vcpu_reset,
3240
3241         .prepare_guest_switch = svm_prepare_guest_switch,
3242         .vcpu_load = svm_vcpu_load,
3243         .vcpu_put = svm_vcpu_put,
3244
3245         .set_guest_debug = svm_guest_debug,
3246         .get_msr = svm_get_msr,
3247         .set_msr = svm_set_msr,
3248         .get_segment_base = svm_get_segment_base,
3249         .get_segment = svm_get_segment,
3250         .set_segment = svm_set_segment,
3251         .get_cpl = svm_get_cpl,
3252         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3253         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3254         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3255         .set_cr0 = svm_set_cr0,
3256         .set_cr3 = svm_set_cr3,
3257         .set_cr4 = svm_set_cr4,
3258         .set_efer = svm_set_efer,
3259         .get_idt = svm_get_idt,
3260         .set_idt = svm_set_idt,
3261         .get_gdt = svm_get_gdt,
3262         .set_gdt = svm_set_gdt,
3263         .set_dr7 = svm_set_dr7,
3264         .cache_reg = svm_cache_reg,
3265         .get_rflags = svm_get_rflags,
3266         .set_rflags = svm_set_rflags,
3267         .fpu_activate = svm_fpu_activate,
3268         .fpu_deactivate = svm_fpu_deactivate,
3269
3270         .tlb_flush = svm_flush_tlb,
3271
3272         .run = svm_vcpu_run,
3273         .handle_exit = handle_exit,
3274         .skip_emulated_instruction = skip_emulated_instruction,
3275         .set_interrupt_shadow = svm_set_interrupt_shadow,
3276         .get_interrupt_shadow = svm_get_interrupt_shadow,
3277         .patch_hypercall = svm_patch_hypercall,
3278         .set_irq = svm_set_irq,
3279         .set_nmi = svm_inject_nmi,
3280         .queue_exception = svm_queue_exception,
3281         .interrupt_allowed = svm_interrupt_allowed,
3282         .nmi_allowed = svm_nmi_allowed,
3283         .get_nmi_mask = svm_get_nmi_mask,
3284         .set_nmi_mask = svm_set_nmi_mask,
3285         .enable_nmi_window = enable_nmi_window,
3286         .enable_irq_window = enable_irq_window,
3287         .update_cr8_intercept = update_cr8_intercept,
3288
3289         .set_tss_addr = svm_set_tss_addr,
3290         .get_tdp_level = get_npt_level,
3291         .get_mt_mask = svm_get_mt_mask,
3292
3293         .exit_reasons_str = svm_exit_reasons_str,
3294         .get_lpage_level = svm_get_lpage_level,
3295
3296         .cpuid_update = svm_cpuid_update,
3297
3298         .rdtscp_supported = svm_rdtscp_supported,
3299 };
3300
3301 static int __init svm_init(void)
3302 {
3303         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3304                               THIS_MODULE);
3305 }
3306
3307 static void __exit svm_exit(void)
3308 {
3309         kvm_exit();
3310 }
3311
3312 module_init(svm_init)
3313 module_exit(svm_exit)