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   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20 #include "kvm_cache_regs.h"
  21 #include "x86.h"
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/ftrace_event.h>
  29
  30 #include <asm/desc.h>
  31
  32 #include <asm/virtext.h>
  33 #include "trace.h"
  34
  35 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  36
  37 MODULE_AUTHOR("Qumranet");
  38 MODULE_LICENSE("GPL");
  39
  40 #define IOPM_ALLOC_ORDER 2
  41 #define MSRPM_ALLOC_ORDER 1
  42
  43 #define SEG_TYPE_LDT 2
  44 #define SEG_TYPE_BUSY_TSS16 3
  45
  46 #define SVM_FEATURE_NPT  (1 << 0)
  47 #define SVM_FEATURE_LBRV (1 << 1)
  48 #define SVM_FEATURE_SVML (1 << 2)
  49 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
  50
  51 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  52 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  53 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  54
  55 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  56
  57 static const u32 host_save_user_msrs[] = {
  58 #ifdef CONFIG_X86_64
  59         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  60         MSR_FS_BASE,
  61 #endif
  62         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  63 };
  64
  65 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  66
  67 struct kvm_vcpu;
  68
  69 struct nested_state {
  70         struct vmcb *hsave;
  71         u64 hsave_msr;
  72         u64 vmcb;
  73
  74         /* These are the merged vectors */
  75         u32 *msrpm;
  76
  77         /* gpa pointers to the real vectors */
  78         u64 vmcb_msrpm;
  79
  80         /* A VMEXIT is required but not yet emulated */
  81         bool exit_required;
  82
  83         /* cache for intercepts of the guest */
  84         u16 intercept_cr_read;
  85         u16 intercept_cr_write;
  86         u16 intercept_dr_read;
  87         u16 intercept_dr_write;
  88         u32 intercept_exceptions;
  89         u64 intercept;
  90
  91 };
  92
  93 struct vcpu_svm {
  94         struct kvm_vcpu vcpu;
  95         struct vmcb *vmcb;
  96         unsigned long vmcb_pa;
  97         struct svm_cpu_data *svm_data;
  98         uint64_t asid_generation;
  99         uint64_t sysenter_esp;
 100         uint64_t sysenter_eip;
 101
 102         u64 next_rip;
 103
 104         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 105         u64 host_gs_base;
 106
 107         u32 *msrpm;
 108
 109         struct nested_state nested;
 110
 111         bool nmi_singlestep;
 112 };
 113
 114 /* enable NPT for AMD64 and X86 with PAE */
 115 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 116 static bool npt_enabled = true;
 117 #else
 118 static bool npt_enabled = false;
 119 #endif
 120 static int npt = 1;
 121
 122 module_param(npt, int, S_IRUGO);
 123
 124 static int nested = 1;
 125 module_param(nested, int, S_IRUGO);
 126
 127 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 128 static void svm_complete_interrupts(struct vcpu_svm *svm);
 129
 130 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 131 static int nested_svm_vmexit(struct vcpu_svm *svm);
 132 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 133                                       bool has_error_code, u32 error_code);
 134
 135 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 136 {
 137         return container_of(vcpu, struct vcpu_svm, vcpu);
 138 }
 139
 140 static inline bool is_nested(struct vcpu_svm *svm)
 141 {
 142         return svm->nested.vmcb;
 143 }
 144
 145 static inline void enable_gif(struct vcpu_svm *svm)
 146 {
 147         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 148 }
 149
 150 static inline void disable_gif(struct vcpu_svm *svm)
 151 {
 152         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 153 }
 154
 155 static inline bool gif_set(struct vcpu_svm *svm)
 156 {
 157         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 158 }
 159
 160 static unsigned long iopm_base;
 161
 162 struct kvm_ldttss_desc {
 163         u16 limit0;
 164         u16 base0;
 165         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
 166         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
 167         u32 base3;
 168         u32 zero1;
 169 } __attribute__((packed));
 170
 171 struct svm_cpu_data {
 172         int cpu;
 173
 174         u64 asid_generation;
 175         u32 max_asid;
 176         u32 next_asid;
 177         struct kvm_ldttss_desc *tss_desc;
 178
 179         struct page *save_area;
 180 };
 181
 182 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 183 static uint32_t svm_features;
 184
 185 struct svm_init_data {
 186         int cpu;
 187         int r;
 188 };
 189
 190 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 191
 192 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 193 #define MSRS_RANGE_SIZE 2048
 194 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 195
 196 #define MAX_INST_SIZE 15
 197
 198 static inline u32 svm_has(u32 feat)
 199 {
 200         return svm_features & feat;
 201 }
 202
 203 static inline void clgi(void)
 204 {
 205         asm volatile (__ex(SVM_CLGI));
 206 }
 207
 208 static inline void stgi(void)
 209 {
 210         asm volatile (__ex(SVM_STGI));
 211 }
 212
 213 static inline void invlpga(unsigned long addr, u32 asid)
 214 {
 215         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 216 }
 217
 218 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 219 {
 220         to_svm(vcpu)->asid_generation--;
 221 }
 222
 223 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 224 {
 225         force_new_asid(vcpu);
 226 }
 227
 228 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 229 {
 230         if (!npt_enabled && !(efer & EFER_LMA))
 231                 efer &= ~EFER_LME;
 232
 233         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 234         vcpu->arch.shadow_efer = efer;
 235 }
 236
 237 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 238                                 bool has_error_code, u32 error_code)
 239 {
 240         struct vcpu_svm *svm = to_svm(vcpu);
 241
 242         /* If we are within a nested VM we'd better #VMEXIT and let the
 243            guest handle the exception */
 244         if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
 245                 return;
 246
 247         svm->vmcb->control.event_inj = nr
 248                 | SVM_EVTINJ_VALID
 249                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 250                 | SVM_EVTINJ_TYPE_EXEPT;
 251         svm->vmcb->control.event_inj_err = error_code;
 252 }
 253
 254 static int is_external_interrupt(u32 info)
 255 {
 256         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 257         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 258 }
 259
 260 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 261 {
 262         struct vcpu_svm *svm = to_svm(vcpu);
 263         u32 ret = 0;
 264
 265         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 266                 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
 267         return ret & mask;
 268 }
 269
 270 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 271 {
 272         struct vcpu_svm *svm = to_svm(vcpu);
 273
 274         if (mask == 0)
 275                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 276         else
 277                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 278
 279 }
 280
 281 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 282 {
 283         struct vcpu_svm *svm = to_svm(vcpu);
 284
 285         if (!svm->next_rip) {
 286                 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
 287                                 EMULATE_DONE)
 288                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 289                 return;
 290         }
 291         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 292                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 293                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 294
 295         kvm_rip_write(vcpu, svm->next_rip);
 296         svm_set_interrupt_shadow(vcpu, 0);
 297 }
 298
 299 static int has_svm(void)
 300 {
 301         const char *msg;
 302
 303         if (!cpu_has_svm(&msg)) {
 304                 printk(KERN_INFO "has_svm: %s\n", msg);
 305                 return 0;
 306         }
 307
 308         return 1;
 309 }
 310
 311 static void svm_hardware_disable(void *garbage)
 312 {
 313         cpu_svm_disable();
 314 }
 315
 316 static int svm_hardware_enable(void *garbage)
 317 {
 318
 319         struct svm_cpu_data *sd;
 320         uint64_t efer;
 321         struct descriptor_table gdt_descr;
 322         struct desc_struct *gdt;
 323         int me = raw_smp_processor_id();
 324
 325         rdmsrl(MSR_EFER, efer);
 326         if (efer & EFER_SVME)
 327                 return -EBUSY;
 328
 329         if (!has_svm()) {
 330                 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
 331                        me);
 332                 return -EINVAL;
 333         }
 334         sd = per_cpu(svm_data, me);
 335
 336         if (!sd) {
 337                 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
 338                        me);
 339                 return -EINVAL;
 340         }
 341
 342         sd->asid_generation = 1;
 343         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 344         sd->next_asid = sd->max_asid + 1;
 345
 346         kvm_get_gdt(&gdt_descr);
 347         gdt = (struct desc_struct *)gdt_descr.base;
 348         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 349
 350         wrmsrl(MSR_EFER, efer | EFER_SVME);
 351
 352         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 353
 354         return 0;
 355 }
 356
 357 static void svm_cpu_uninit(int cpu)
 358 {
 359         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 360
 361         if (!sd)
 362                 return;
 363
 364         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 365         __free_page(sd->save_area);
 366         kfree(sd);
 367 }
 368
 369 static int svm_cpu_init(int cpu)
 370 {
 371         struct svm_cpu_data *sd;
 372         int r;
 373
 374         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 375         if (!sd)
 376                 return -ENOMEM;
 377         sd->cpu = cpu;
 378         sd->save_area = alloc_page(GFP_KERNEL);
 379         r = -ENOMEM;
 380         if (!sd->save_area)
 381                 goto err_1;
 382
 383         per_cpu(svm_data, cpu) = sd;
 384
 385         return 0;
 386
 387 err_1:
 388         kfree(sd);
 389         return r;
 390
 391 }
 392
 393 static void set_msr_interception(u32 *msrpm, unsigned msr,
 394                                  int read, int write)
 395 {
 396         int i;
 397
 398         for (i = 0; i < NUM_MSR_MAPS; i++) {
 399                 if (msr >= msrpm_ranges[i] &&
 400                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 401                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 402                                           msrpm_ranges[i]) * 2;
 403
 404                         u32 *base = msrpm + (msr_offset / 32);
 405                         u32 msr_shift = msr_offset % 32;
 406                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 407                         *base = (*base & ~(0x3 << msr_shift)) |
 408                                 (mask << msr_shift);
 409                         return;
 410                 }
 411         }
 412         BUG();
 413 }
 414
 415 static void svm_vcpu_init_msrpm(u32 *msrpm)
 416 {
 417         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 418
 419 #ifdef CONFIG_X86_64
 420         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 421         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 422         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 423         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 424         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 425         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 426 #endif
 427         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 428         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 429 }
 430
 431 static void svm_enable_lbrv(struct vcpu_svm *svm)
 432 {
 433         u32 *msrpm = svm->msrpm;
 434
 435         svm->vmcb->control.lbr_ctl = 1;
 436         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 437         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 438         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 439         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 440 }
 441
 442 static void svm_disable_lbrv(struct vcpu_svm *svm)
 443 {
 444         u32 *msrpm = svm->msrpm;
 445
 446         svm->vmcb->control.lbr_ctl = 0;
 447         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 448         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 449         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 450         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 451 }
 452
 453 static __init int svm_hardware_setup(void)
 454 {
 455         int cpu;
 456         struct page *iopm_pages;
 457         void *iopm_va;
 458         int r;
 459
 460         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 461
 462         if (!iopm_pages)
 463                 return -ENOMEM;
 464
 465         iopm_va = page_address(iopm_pages);
 466         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 467         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 468
 469         if (boot_cpu_has(X86_FEATURE_NX))
 470                 kvm_enable_efer_bits(EFER_NX);
 471
 472         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 473                 kvm_enable_efer_bits(EFER_FFXSR);
 474
 475         if (nested) {
 476                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 477                 kvm_enable_efer_bits(EFER_SVME);
 478         }
 479
 480         for_each_possible_cpu(cpu) {
 481                 r = svm_cpu_init(cpu);
 482                 if (r)
 483                         goto err;
 484         }
 485
 486         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 487
 488         if (!svm_has(SVM_FEATURE_NPT))
 489                 npt_enabled = false;
 490
 491         if (npt_enabled && !npt) {
 492                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 493                 npt_enabled = false;
 494         }
 495
 496         if (npt_enabled) {
 497                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 498                 kvm_enable_tdp();
 499         } else
 500                 kvm_disable_tdp();
 501
 502         return 0;
 503
 504 err:
 505         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 506         iopm_base = 0;
 507         return r;
 508 }
 509
 510 static __exit void svm_hardware_unsetup(void)
 511 {
 512         int cpu;
 513
 514         for_each_possible_cpu(cpu)
 515                 svm_cpu_uninit(cpu);
 516
 517         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 518         iopm_base = 0;
 519 }
 520
 521 static void init_seg(struct vmcb_seg *seg)
 522 {
 523         seg->selector = 0;
 524         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 525                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 526         seg->limit = 0xffff;
 527         seg->base = 0;
 528 }
 529
 530 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 531 {
 532         seg->selector = 0;
 533         seg->attrib = SVM_SELECTOR_P_MASK | type;
 534         seg->limit = 0xffff;
 535         seg->base = 0;
 536 }
 537
 538 static void init_vmcb(struct vcpu_svm *svm)
 539 {
 540         struct vmcb_control_area *control = &svm->vmcb->control;
 541         struct vmcb_save_area *save = &svm->vmcb->save;
 542
 543         svm->vcpu.fpu_active = 1;
 544
 545         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 546                                         INTERCEPT_CR3_MASK |
 547                                         INTERCEPT_CR4_MASK;
 548
 549         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 550                                         INTERCEPT_CR3_MASK |
 551                                         INTERCEPT_CR4_MASK |
 552                                         INTERCEPT_CR8_MASK;
 553
 554         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 555                                         INTERCEPT_DR1_MASK |
 556                                         INTERCEPT_DR2_MASK |
 557                                         INTERCEPT_DR3_MASK |
 558                                         INTERCEPT_DR4_MASK |
 559                                         INTERCEPT_DR5_MASK |
 560                                         INTERCEPT_DR6_MASK |
 561                                         INTERCEPT_DR7_MASK;
 562
 563         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 564                                         INTERCEPT_DR1_MASK |
 565                                         INTERCEPT_DR2_MASK |
 566                                         INTERCEPT_DR3_MASK |
 567                                         INTERCEPT_DR4_MASK |
 568                                         INTERCEPT_DR5_MASK |
 569                                         INTERCEPT_DR6_MASK |
 570                                         INTERCEPT_DR7_MASK;
 571
 572         control->intercept_exceptions = (1 << PF_VECTOR) |
 573                                         (1 << UD_VECTOR) |
 574                                         (1 << MC_VECTOR);
 575
 576
 577         control->intercept =    (1ULL << INTERCEPT_INTR) |
 578                                 (1ULL << INTERCEPT_NMI) |
 579                                 (1ULL << INTERCEPT_SMI) |
 580                                 (1ULL << INTERCEPT_SELECTIVE_CR0) |
 581                                 (1ULL << INTERCEPT_CPUID) |
 582                                 (1ULL << INTERCEPT_INVD) |
 583                                 (1ULL << INTERCEPT_HLT) |
 584                                 (1ULL << INTERCEPT_INVLPG) |
 585                                 (1ULL << INTERCEPT_INVLPGA) |
 586                                 (1ULL << INTERCEPT_IOIO_PROT) |
 587                                 (1ULL << INTERCEPT_MSR_PROT) |
 588                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 589                                 (1ULL << INTERCEPT_SHUTDOWN) |
 590                                 (1ULL << INTERCEPT_VMRUN) |
 591                                 (1ULL << INTERCEPT_VMMCALL) |
 592                                 (1ULL << INTERCEPT_VMLOAD) |
 593                                 (1ULL << INTERCEPT_VMSAVE) |
 594                                 (1ULL << INTERCEPT_STGI) |
 595                                 (1ULL << INTERCEPT_CLGI) |
 596                                 (1ULL << INTERCEPT_SKINIT) |
 597                                 (1ULL << INTERCEPT_WBINVD) |
 598                                 (1ULL << INTERCEPT_MONITOR) |
 599                                 (1ULL << INTERCEPT_MWAIT);
 600
 601         control->iopm_base_pa = iopm_base;
 602         control->msrpm_base_pa = __pa(svm->msrpm);
 603         control->tsc_offset = 0;
 604         control->int_ctl = V_INTR_MASKING_MASK;
 605
 606         init_seg(&save->es);
 607         init_seg(&save->ss);
 608         init_seg(&save->ds);
 609         init_seg(&save->fs);
 610         init_seg(&save->gs);
 611
 612         save->cs.selector = 0xf000;
 613         /* Executable/Readable Code Segment */
 614         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 615                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 616         save->cs.limit = 0xffff;
 617         /*
 618          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 619          * be consistent with it.
 620          *
 621          * Replace when we have real mode working for vmx.
 622          */
 623         save->cs.base = 0xf0000;
 624
 625         save->gdtr.limit = 0xffff;
 626         save->idtr.limit = 0xffff;
 627
 628         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 629         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 630
 631         save->efer = EFER_SVME;
 632         save->dr6 = 0xffff0ff0;
 633         save->dr7 = 0x400;
 634         save->rflags = 2;
 635         save->rip = 0x0000fff0;
 636         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 637
 638         /* This is the guest-visible cr0 value.
 639          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
 640          */
 641         svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
 642         kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
 643
 644         save->cr4 = X86_CR4_PAE;
 645         /* rdx = ?? */
 646
 647         if (npt_enabled) {
 648                 /* Setup VMCB for Nested Paging */
 649                 control->nested_ctl = 1;
 650                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 651                                         (1ULL << INTERCEPT_INVLPG));
 652                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 653                 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
 654                 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
 655                 save->g_pat = 0x0007040600070406ULL;
 656                 save->cr3 = 0;
 657                 save->cr4 = 0;
 658         }
 659         force_new_asid(&svm->vcpu);
 660
 661         svm->nested.vmcb = 0;
 662         svm->vcpu.arch.hflags = 0;
 663
 664         if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
 665                 control->pause_filter_count = 3000;
 666                 control->intercept |= (1ULL << INTERCEPT_PAUSE);
 667         }
 668
 669         enable_gif(svm);
 670 }
 671
 672 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 673 {
 674         struct vcpu_svm *svm = to_svm(vcpu);
 675
 676         init_vmcb(svm);
 677
 678         if (!kvm_vcpu_is_bsp(vcpu)) {
 679                 kvm_rip_write(vcpu, 0);
 680                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 681                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 682         }
 683         vcpu->arch.regs_avail = ~0;
 684         vcpu->arch.regs_dirty = ~0;
 685
 686         return 0;
 687 }
 688
 689 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 690 {
 691         struct vcpu_svm *svm;
 692         struct page *page;
 693         struct page *msrpm_pages;
 694         struct page *hsave_page;
 695         struct page *nested_msrpm_pages;
 696         int err;
 697
 698         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 699         if (!svm) {
 700                 err = -ENOMEM;
 701                 goto out;
 702         }
 703
 704         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 705         if (err)
 706                 goto free_svm;
 707
 708         page = alloc_page(GFP_KERNEL);
 709         if (!page) {
 710                 err = -ENOMEM;
 711                 goto uninit;
 712         }
 713
 714         err = -ENOMEM;
 715         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 716         if (!msrpm_pages)
 717                 goto uninit;
 718
 719         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 720         if (!nested_msrpm_pages)
 721                 goto uninit;
 722
 723         svm->msrpm = page_address(msrpm_pages);
 724         svm_vcpu_init_msrpm(svm->msrpm);
 725
 726         hsave_page = alloc_page(GFP_KERNEL);
 727         if (!hsave_page)
 728                 goto uninit;
 729         svm->nested.hsave = page_address(hsave_page);
 730
 731         svm->nested.msrpm = page_address(nested_msrpm_pages);
 732
 733         svm->vmcb = page_address(page);
 734         clear_page(svm->vmcb);
 735         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 736         svm->asid_generation = 0;
 737         init_vmcb(svm);
 738
 739         fx_init(&svm->vcpu);
 740         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 741         if (kvm_vcpu_is_bsp(&svm->vcpu))
 742                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 743
 744         return &svm->vcpu;
 745
 746 uninit:
 747         kvm_vcpu_uninit(&svm->vcpu);
 748 free_svm:
 749         kmem_cache_free(kvm_vcpu_cache, svm);
 750 out:
 751         return ERR_PTR(err);
 752 }
 753
 754 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 755 {
 756         struct vcpu_svm *svm = to_svm(vcpu);
 757
 758         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 759         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 760         __free_page(virt_to_page(svm->nested.hsave));
 761         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
 762         kvm_vcpu_uninit(vcpu);
 763         kmem_cache_free(kvm_vcpu_cache, svm);
 764 }
 765
 766 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 767 {
 768         struct vcpu_svm *svm = to_svm(vcpu);
 769         int i;
 770
 771         if (unlikely(cpu != vcpu->cpu)) {
 772                 u64 delta;
 773
 774                 if (check_tsc_unstable()) {
 775                         /*
 776                          * Make sure that the guest sees a monotonically
 777                          * increasing TSC.
 778                          */
 779                         delta = vcpu->arch.host_tsc - native_read_tsc();
 780                         svm->vmcb->control.tsc_offset += delta;
 781                         if (is_nested(svm))
 782                                 svm->nested.hsave->control.tsc_offset += delta;
 783                 }
 784                 vcpu->cpu = cpu;
 785                 kvm_migrate_timers(vcpu);
 786                 svm->asid_generation = 0;
 787         }
 788
 789         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 790                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 791 }
 792
 793 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 794 {
 795         struct vcpu_svm *svm = to_svm(vcpu);
 796         int i;
 797
 798         ++vcpu->stat.host_state_reload;
 799         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 800                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 801
 802         vcpu->arch.host_tsc = native_read_tsc();
 803 }
 804
 805 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 806 {
 807         return to_svm(vcpu)->vmcb->save.rflags;
 808 }
 809
 810 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 811 {
 812         to_svm(vcpu)->vmcb->save.rflags = rflags;
 813 }
 814
 815 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
 816 {
 817         switch (reg) {
 818         case VCPU_EXREG_PDPTR:
 819                 BUG_ON(!npt_enabled);
 820                 load_pdptrs(vcpu, vcpu->arch.cr3);
 821                 break;
 822         default:
 823                 BUG();
 824         }
 825 }
 826
 827 static void svm_set_vintr(struct vcpu_svm *svm)
 828 {
 829         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 830 }
 831
 832 static void svm_clear_vintr(struct vcpu_svm *svm)
 833 {
 834         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 835 }
 836
 837 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 838 {
 839         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 840
 841         switch (seg) {
 842         case VCPU_SREG_CS: return &save->cs;
 843         case VCPU_SREG_DS: return &save->ds;
 844         case VCPU_SREG_ES: return &save->es;
 845         case VCPU_SREG_FS: return &save->fs;
 846         case VCPU_SREG_GS: return &save->gs;
 847         case VCPU_SREG_SS: return &save->ss;
 848         case VCPU_SREG_TR: return &save->tr;
 849         case VCPU_SREG_LDTR: return &save->ldtr;
 850         }
 851         BUG();
 852         return NULL;
 853 }
 854
 855 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 856 {
 857         struct vmcb_seg *s = svm_seg(vcpu, seg);
 858
 859         return s->base;
 860 }
 861
 862 static void svm_get_segment(struct kvm_vcpu *vcpu,
 863                             struct kvm_segment *var, int seg)
 864 {
 865         struct vmcb_seg *s = svm_seg(vcpu, seg);
 866
 867         var->base = s->base;
 868         var->limit = s->limit;
 869         var->selector = s->selector;
 870         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 871         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 872         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 873         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 874         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 875         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 876         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 877         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 878
 879         /* AMD's VMCB does not have an explicit unusable field, so emulate it
 880          * for cross vendor migration purposes by "not present"
 881          */
 882         var->unusable = !var->present || (var->type == 0);
 883
 884         switch (seg) {
 885         case VCPU_SREG_CS:
 886                 /*
 887                  * SVM always stores 0 for the 'G' bit in the CS selector in
 888                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 889                  * Intel's VMENTRY has a check on the 'G' bit.
 890                  */
 891                 var->g = s->limit > 0xfffff;
 892                 break;
 893         case VCPU_SREG_TR:
 894                 /*
 895                  * Work around a bug where the busy flag in the tr selector
 896                  * isn't exposed
 897                  */
 898                 var->type |= 0x2;
 899                 break;
 900         case VCPU_SREG_DS:
 901         case VCPU_SREG_ES:
 902         case VCPU_SREG_FS:
 903         case VCPU_SREG_GS:
 904                 /*
 905                  * The accessed bit must always be set in the segment
 906                  * descriptor cache, although it can be cleared in the
 907                  * descriptor, the cached bit always remains at 1. Since
 908                  * Intel has a check on this, set it here to support
 909                  * cross-vendor migration.
 910                  */
 911                 if (!var->unusable)
 912                         var->type |= 0x1;
 913                 break;
 914         case VCPU_SREG_SS:
 915                 /* On AMD CPUs sometimes the DB bit in the segment
 916                  * descriptor is left as 1, although the whole segment has
 917                  * been made unusable. Clear it here to pass an Intel VMX
 918                  * entry check when cross vendor migrating.
 919                  */
 920                 if (var->unusable)
 921                         var->db = 0;
 922                 break;
 923         }
 924 }
 925
 926 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 927 {
 928         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 929
 930         return save->cpl;
 931 }
 932
 933 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 934 {
 935         struct vcpu_svm *svm = to_svm(vcpu);
 936
 937         dt->limit = svm->vmcb->save.idtr.limit;
 938         dt->base = svm->vmcb->save.idtr.base;
 939 }
 940
 941 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 942 {
 943         struct vcpu_svm *svm = to_svm(vcpu);
 944
 945         svm->vmcb->save.idtr.limit = dt->limit;
 946         svm->vmcb->save.idtr.base = dt->base ;
 947 }
 948
 949 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 950 {
 951         struct vcpu_svm *svm = to_svm(vcpu);
 952
 953         dt->limit = svm->vmcb->save.gdtr.limit;
 954         dt->base = svm->vmcb->save.gdtr.base;
 955 }
 956
 957 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 958 {
 959         struct vcpu_svm *svm = to_svm(vcpu);
 960
 961         svm->vmcb->save.gdtr.limit = dt->limit;
 962         svm->vmcb->save.gdtr.base = dt->base ;
 963 }
 964
 965 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
 966 {
 967 }
 968
 969 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 970 {
 971 }
 972
 973 static void update_cr0_intercept(struct vcpu_svm *svm)
 974 {
 975         ulong gcr0 = svm->vcpu.arch.cr0;
 976         u64 *hcr0 = &svm->vmcb->save.cr0;
 977
 978         if (!svm->vcpu.fpu_active)
 979                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
 980         else
 981                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
 982                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
 983
 984
 985         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
 986                 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
 987                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
 988         } else {
 989                 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
 990                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
 991         }
 992 }
 993
 994 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 995 {
 996         struct vcpu_svm *svm = to_svm(vcpu);
 997
 998 #ifdef CONFIG_X86_64
 999         if (vcpu->arch.shadow_efer & EFER_LME) {
1000                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1001                         vcpu->arch.shadow_efer |= EFER_LMA;
1002                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1003                 }
1004
1005                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1006                         vcpu->arch.shadow_efer &= ~EFER_LMA;
1007                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1008                 }
1009         }
1010 #endif
1011         vcpu->arch.cr0 = cr0;
1012
1013         if (!npt_enabled)
1014                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1015
1016         if (!vcpu->fpu_active)
1017                 cr0 |= X86_CR0_TS;
1018         /*
1019          * re-enable caching here because the QEMU bios
1020          * does not do it - this results in some delay at
1021          * reboot
1022          */
1023         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1024         svm->vmcb->save.cr0 = cr0;
1025         update_cr0_intercept(svm);
1026 }
1027
1028 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1029 {
1030         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1031         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1032
1033         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1034                 force_new_asid(vcpu);
1035
1036         vcpu->arch.cr4 = cr4;
1037         if (!npt_enabled)
1038                 cr4 |= X86_CR4_PAE;
1039         cr4 |= host_cr4_mce;
1040         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1041 }
1042
1043 static void svm_set_segment(struct kvm_vcpu *vcpu,
1044                             struct kvm_segment *var, int seg)
1045 {
1046         struct vcpu_svm *svm = to_svm(vcpu);
1047         struct vmcb_seg *s = svm_seg(vcpu, seg);
1048
1049         s->base = var->base;
1050         s->limit = var->limit;
1051         s->selector = var->selector;
1052         if (var->unusable)
1053                 s->attrib = 0;
1054         else {
1055                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1056                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1057                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1058                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1059                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1060                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1061                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1062                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1063         }
1064         if (seg == VCPU_SREG_CS)
1065                 svm->vmcb->save.cpl
1066                         = (svm->vmcb->save.cs.attrib
1067                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1068
1069 }
1070
1071 static void update_db_intercept(struct kvm_vcpu *vcpu)
1072 {
1073         struct vcpu_svm *svm = to_svm(vcpu);
1074
1075         svm->vmcb->control.intercept_exceptions &=
1076                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1077
1078         if (svm->nmi_singlestep)
1079                 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1080
1081         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1082                 if (vcpu->guest_debug &
1083                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1084                         svm->vmcb->control.intercept_exceptions |=
1085                                 1 << DB_VECTOR;
1086                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1087                         svm->vmcb->control.intercept_exceptions |=
1088                                 1 << BP_VECTOR;
1089         } else
1090                 vcpu->guest_debug = 0;
1091 }
1092
1093 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1094 {
1095         struct vcpu_svm *svm = to_svm(vcpu);
1096
1097         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1098                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1099         else
1100                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1101
1102         update_db_intercept(vcpu);
1103 }
1104
1105 static void load_host_msrs(struct kvm_vcpu *vcpu)
1106 {
1107 #ifdef CONFIG_X86_64
1108         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1109 #endif
1110 }
1111
1112 static void save_host_msrs(struct kvm_vcpu *vcpu)
1113 {
1114 #ifdef CONFIG_X86_64
1115         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1116 #endif
1117 }
1118
1119 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1120 {
1121         if (sd->next_asid > sd->max_asid) {
1122                 ++sd->asid_generation;
1123                 sd->next_asid = 1;
1124                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1125         }
1126
1127         svm->asid_generation = sd->asid_generation;
1128         svm->vmcb->control.asid = sd->next_asid++;
1129 }
1130
1131 static int svm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *dest)
1132 {
1133         struct vcpu_svm *svm = to_svm(vcpu);
1134
1135         switch (dr) {
1136         case 0 ... 3:
1137                 *dest = vcpu->arch.db[dr];
1138                 break;
1139         case 4:
1140                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1141                         return EMULATE_FAIL; /* will re-inject UD */
1142                 /* fall through */
1143         case 6:
1144                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1145                         *dest = vcpu->arch.dr6;
1146                 else
1147                         *dest = svm->vmcb->save.dr6;
1148                 break;
1149         case 5:
1150                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1151                         return EMULATE_FAIL; /* will re-inject UD */
1152                 /* fall through */
1153         case 7:
1154                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1155                         *dest = vcpu->arch.dr7;
1156                 else
1157                         *dest = svm->vmcb->save.dr7;
1158                 break;
1159         }
1160
1161         return EMULATE_DONE;
1162 }
1163
1164 static int svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value)
1165 {
1166         struct vcpu_svm *svm = to_svm(vcpu);
1167
1168         switch (dr) {
1169         case 0 ... 3:
1170                 vcpu->arch.db[dr] = value;
1171                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1172                         vcpu->arch.eff_db[dr] = value;
1173                 break;
1174         case 4:
1175                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1176                         return EMULATE_FAIL; /* will re-inject UD */
1177                 /* fall through */
1178         case 6:
1179                 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1180                 break;
1181         case 5:
1182                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1183                         return EMULATE_FAIL; /* will re-inject UD */
1184                 /* fall through */
1185         case 7:
1186                 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1187                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1188                         svm->vmcb->save.dr7 = vcpu->arch.dr7;
1189                         vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1190                 }
1191                 break;
1192         }
1193
1194         return EMULATE_DONE;
1195 }
1196
1197 static int pf_interception(struct vcpu_svm *svm)
1198 {
1199         u64 fault_address;
1200         u32 error_code;
1201
1202         fault_address  = svm->vmcb->control.exit_info_2;
1203         error_code = svm->vmcb->control.exit_info_1;
1204
1205         trace_kvm_page_fault(fault_address, error_code);
1206         if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1207                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1208         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1209 }
1210
1211 static int db_interception(struct vcpu_svm *svm)
1212 {
1213         struct kvm_run *kvm_run = svm->vcpu.run;
1214
1215         if (!(svm->vcpu.guest_debug &
1216               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1217                 !svm->nmi_singlestep) {
1218                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1219                 return 1;
1220         }
1221
1222         if (svm->nmi_singlestep) {
1223                 svm->nmi_singlestep = false;
1224                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1225                         svm->vmcb->save.rflags &=
1226                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1227                 update_db_intercept(&svm->vcpu);
1228         }
1229
1230         if (svm->vcpu.guest_debug &
1231             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1232                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1233                 kvm_run->debug.arch.pc =
1234                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1235                 kvm_run->debug.arch.exception = DB_VECTOR;
1236                 return 0;
1237         }
1238
1239         return 1;
1240 }
1241
1242 static int bp_interception(struct vcpu_svm *svm)
1243 {
1244         struct kvm_run *kvm_run = svm->vcpu.run;
1245
1246         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1247         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1248         kvm_run->debug.arch.exception = BP_VECTOR;
1249         return 0;
1250 }
1251
1252 static int ud_interception(struct vcpu_svm *svm)
1253 {
1254         int er;
1255
1256         er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1257         if (er != EMULATE_DONE)
1258                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1259         return 1;
1260 }
1261
1262 static int nm_interception(struct vcpu_svm *svm)
1263 {
1264         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1265         svm->vcpu.fpu_active = 1;
1266         update_cr0_intercept(svm);
1267
1268         return 1;
1269 }
1270
1271 static int mc_interception(struct vcpu_svm *svm)
1272 {
1273         /*
1274          * On an #MC intercept the MCE handler is not called automatically in
1275          * the host. So do it by hand here.
1276          */
1277         asm volatile (
1278                 "int $0x12\n");
1279         /* not sure if we ever come back to this point */
1280
1281         return 1;
1282 }
1283
1284 static int shutdown_interception(struct vcpu_svm *svm)
1285 {
1286         struct kvm_run *kvm_run = svm->vcpu.run;
1287
1288         /*
1289          * VMCB is undefined after a SHUTDOWN intercept
1290          * so reinitialize it.
1291          */
1292         clear_page(svm->vmcb);
1293         init_vmcb(svm);
1294
1295         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1296         return 0;
1297 }
1298
1299 static int io_interception(struct vcpu_svm *svm)
1300 {
1301         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1302         int size, in, string;
1303         unsigned port;
1304
1305         ++svm->vcpu.stat.io_exits;
1306
1307         svm->next_rip = svm->vmcb->control.exit_info_2;
1308
1309         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1310
1311         if (string) {
1312                 if (emulate_instruction(&svm->vcpu,
1313                                         0, 0, 0) == EMULATE_DO_MMIO)
1314                         return 0;
1315                 return 1;
1316         }
1317
1318         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1319         port = io_info >> 16;
1320         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1321
1322         skip_emulated_instruction(&svm->vcpu);
1323         return kvm_emulate_pio(&svm->vcpu, in, size, port);
1324 }
1325
1326 static int nmi_interception(struct vcpu_svm *svm)
1327 {
1328         return 1;
1329 }
1330
1331 static int intr_interception(struct vcpu_svm *svm)
1332 {
1333         ++svm->vcpu.stat.irq_exits;
1334         return 1;
1335 }
1336
1337 static int nop_on_interception(struct vcpu_svm *svm)
1338 {
1339         return 1;
1340 }
1341
1342 static int halt_interception(struct vcpu_svm *svm)
1343 {
1344         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1345         skip_emulated_instruction(&svm->vcpu);
1346         return kvm_emulate_halt(&svm->vcpu);
1347 }
1348
1349 static int vmmcall_interception(struct vcpu_svm *svm)
1350 {
1351         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1352         skip_emulated_instruction(&svm->vcpu);
1353         kvm_emulate_hypercall(&svm->vcpu);
1354         return 1;
1355 }
1356
1357 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1358 {
1359         if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1360             || !is_paging(&svm->vcpu)) {
1361                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1362                 return 1;
1363         }
1364
1365         if (svm->vmcb->save.cpl) {
1366                 kvm_inject_gp(&svm->vcpu, 0);
1367                 return 1;
1368         }
1369
1370        return 0;
1371 }
1372
1373 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1374                                       bool has_error_code, u32 error_code)
1375 {
1376         if (!is_nested(svm))
1377                 return 0;
1378
1379         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1380         svm->vmcb->control.exit_code_hi = 0;
1381         svm->vmcb->control.exit_info_1 = error_code;
1382         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1383
1384         return nested_svm_exit_handled(svm);
1385 }
1386
1387 static inline int nested_svm_intr(struct vcpu_svm *svm)
1388 {
1389         if (!is_nested(svm))
1390                 return 0;
1391
1392         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1393                 return 0;
1394
1395         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1396                 return 0;
1397
1398         svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1399
1400         if (svm->nested.intercept & 1ULL) {
1401                 /*
1402                  * The #vmexit can't be emulated here directly because this
1403                  * code path runs with irqs and preemtion disabled. A
1404                  * #vmexit emulation might sleep. Only signal request for
1405                  * the #vmexit here.
1406                  */
1407                 svm->nested.exit_required = true;
1408                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1409                 return 1;
1410         }
1411
1412         return 0;
1413 }
1414
1415 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
1416 {
1417         struct page *page;
1418
1419         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1420         if (is_error_page(page))
1421                 goto error;
1422
1423         return kmap_atomic(page, idx);
1424
1425 error:
1426         kvm_release_page_clean(page);
1427         kvm_inject_gp(&svm->vcpu, 0);
1428
1429         return NULL;
1430 }
1431
1432 static void nested_svm_unmap(void *addr, enum km_type idx)
1433 {
1434         struct page *page;
1435
1436         if (!addr)
1437                 return;
1438
1439         page = kmap_atomic_to_page(addr);
1440
1441         kunmap_atomic(addr, idx);
1442         kvm_release_page_dirty(page);
1443 }
1444
1445 static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1446 {
1447         u32 param = svm->vmcb->control.exit_info_1 & 1;
1448         u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1449         bool ret = false;
1450         u32 t0, t1;
1451         u8 *msrpm;
1452
1453         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1454                 return false;
1455
1456         msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1457
1458         if (!msrpm)
1459                 goto out;
1460
1461         switch (msr) {
1462         case 0 ... 0x1fff:
1463                 t0 = (msr * 2) % 8;
1464                 t1 = msr / 8;
1465                 break;
1466         case 0xc0000000 ... 0xc0001fff:
1467                 t0 = (8192 + msr - 0xc0000000) * 2;
1468                 t1 = (t0 / 8);
1469                 t0 %= 8;
1470                 break;
1471         case 0xc0010000 ... 0xc0011fff:
1472                 t0 = (16384 + msr - 0xc0010000) * 2;
1473                 t1 = (t0 / 8);
1474                 t0 %= 8;
1475                 break;
1476         default:
1477                 ret = true;
1478                 goto out;
1479         }
1480
1481         ret = msrpm[t1] & ((1 << param) << t0);
1482
1483 out:
1484         nested_svm_unmap(msrpm, KM_USER0);
1485
1486         return ret;
1487 }
1488
1489 static int nested_svm_exit_special(struct vcpu_svm *svm)
1490 {
1491         u32 exit_code = svm->vmcb->control.exit_code;
1492
1493         switch (exit_code) {
1494         case SVM_EXIT_INTR:
1495         case SVM_EXIT_NMI:
1496                 return NESTED_EXIT_HOST;
1497                 /* For now we are always handling NPFs when using them */
1498         case SVM_EXIT_NPF:
1499                 if (npt_enabled)
1500                         return NESTED_EXIT_HOST;
1501                 break;
1502         /* When we're shadowing, trap PFs */
1503         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1504                 if (!npt_enabled)
1505                         return NESTED_EXIT_HOST;
1506                 break;
1507         default:
1508                 break;
1509         }
1510
1511         return NESTED_EXIT_CONTINUE;
1512 }
1513
1514 /*
1515  * If this function returns true, this #vmexit was already handled
1516  */
1517 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1518 {
1519         u32 exit_code = svm->vmcb->control.exit_code;
1520         int vmexit = NESTED_EXIT_HOST;
1521
1522         switch (exit_code) {
1523         case SVM_EXIT_MSR:
1524                 vmexit = nested_svm_exit_handled_msr(svm);
1525                 break;
1526         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1527                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1528                 if (svm->nested.intercept_cr_read & cr_bits)
1529                         vmexit = NESTED_EXIT_DONE;
1530                 break;
1531         }
1532         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1533                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1534                 if (svm->nested.intercept_cr_write & cr_bits)
1535                         vmexit = NESTED_EXIT_DONE;
1536                 break;
1537         }
1538         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1539                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1540                 if (svm->nested.intercept_dr_read & dr_bits)
1541                         vmexit = NESTED_EXIT_DONE;
1542                 break;
1543         }
1544         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1545                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1546                 if (svm->nested.intercept_dr_write & dr_bits)
1547                         vmexit = NESTED_EXIT_DONE;
1548                 break;
1549         }
1550         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1551                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1552                 if (svm->nested.intercept_exceptions & excp_bits)
1553                         vmexit = NESTED_EXIT_DONE;
1554                 break;
1555         }
1556         default: {
1557                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1558                 if (svm->nested.intercept & exit_bits)
1559                         vmexit = NESTED_EXIT_DONE;
1560         }
1561         }
1562
1563         if (vmexit == NESTED_EXIT_DONE) {
1564                 nested_svm_vmexit(svm);
1565         }
1566
1567         return vmexit;
1568 }
1569
1570 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1571 {
1572         struct vmcb_control_area *dst  = &dst_vmcb->control;
1573         struct vmcb_control_area *from = &from_vmcb->control;
1574
1575         dst->intercept_cr_read    = from->intercept_cr_read;
1576         dst->intercept_cr_write   = from->intercept_cr_write;
1577         dst->intercept_dr_read    = from->intercept_dr_read;
1578         dst->intercept_dr_write   = from->intercept_dr_write;
1579         dst->intercept_exceptions = from->intercept_exceptions;
1580         dst->intercept            = from->intercept;
1581         dst->iopm_base_pa         = from->iopm_base_pa;
1582         dst->msrpm_base_pa        = from->msrpm_base_pa;
1583         dst->tsc_offset           = from->tsc_offset;
1584         dst->asid                 = from->asid;
1585         dst->tlb_ctl              = from->tlb_ctl;
1586         dst->int_ctl              = from->int_ctl;
1587         dst->int_vector           = from->int_vector;
1588         dst->int_state            = from->int_state;
1589         dst->exit_code            = from->exit_code;
1590         dst->exit_code_hi         = from->exit_code_hi;
1591         dst->exit_info_1          = from->exit_info_1;
1592         dst->exit_info_2          = from->exit_info_2;
1593         dst->exit_int_info        = from->exit_int_info;
1594         dst->exit_int_info_err    = from->exit_int_info_err;
1595         dst->nested_ctl           = from->nested_ctl;
1596         dst->event_inj            = from->event_inj;
1597         dst->event_inj_err        = from->event_inj_err;
1598         dst->nested_cr3           = from->nested_cr3;
1599         dst->lbr_ctl              = from->lbr_ctl;
1600 }
1601
1602 static int nested_svm_vmexit(struct vcpu_svm *svm)
1603 {
1604         struct vmcb *nested_vmcb;
1605         struct vmcb *hsave = svm->nested.hsave;
1606         struct vmcb *vmcb = svm->vmcb;
1607
1608         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1609                                        vmcb->control.exit_info_1,
1610                                        vmcb->control.exit_info_2,
1611                                        vmcb->control.exit_int_info,
1612                                        vmcb->control.exit_int_info_err);
1613
1614         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
1615         if (!nested_vmcb)
1616                 return 1;
1617
1618         /* Give the current vmcb to the guest */
1619         disable_gif(svm);
1620
1621         nested_vmcb->save.es     = vmcb->save.es;
1622         nested_vmcb->save.cs     = vmcb->save.cs;
1623         nested_vmcb->save.ss     = vmcb->save.ss;
1624         nested_vmcb->save.ds     = vmcb->save.ds;
1625         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
1626         nested_vmcb->save.idtr   = vmcb->save.idtr;
1627         if (npt_enabled)
1628                 nested_vmcb->save.cr3    = vmcb->save.cr3;
1629         nested_vmcb->save.cr2    = vmcb->save.cr2;
1630         nested_vmcb->save.rflags = vmcb->save.rflags;
1631         nested_vmcb->save.rip    = vmcb->save.rip;
1632         nested_vmcb->save.rsp    = vmcb->save.rsp;
1633         nested_vmcb->save.rax    = vmcb->save.rax;
1634         nested_vmcb->save.dr7    = vmcb->save.dr7;
1635         nested_vmcb->save.dr6    = vmcb->save.dr6;
1636         nested_vmcb->save.cpl    = vmcb->save.cpl;
1637
1638         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
1639         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
1640         nested_vmcb->control.int_state         = vmcb->control.int_state;
1641         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
1642         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
1643         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
1644         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
1645         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
1646         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1647
1648         /*
1649          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1650          * to make sure that we do not lose injected events. So check event_inj
1651          * here and copy it to exit_int_info if it is valid.
1652          * Exit_int_info and event_inj can't be both valid because the case
1653          * below only happens on a VMRUN instruction intercept which has
1654          * no valid exit_int_info set.
1655          */
1656         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1657                 struct vmcb_control_area *nc = &nested_vmcb->control;
1658
1659                 nc->exit_int_info     = vmcb->control.event_inj;
1660                 nc->exit_int_info_err = vmcb->control.event_inj_err;
1661         }
1662
1663         nested_vmcb->control.tlb_ctl           = 0;
1664         nested_vmcb->control.event_inj         = 0;
1665         nested_vmcb->control.event_inj_err     = 0;
1666
1667         /* We always set V_INTR_MASKING and remember the old value in hflags */
1668         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1669                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1670
1671         /* Restore the original control entries */
1672         copy_vmcb_control_area(vmcb, hsave);
1673
1674         kvm_clear_exception_queue(&svm->vcpu);
1675         kvm_clear_interrupt_queue(&svm->vcpu);
1676
1677         /* Restore selected save entries */
1678         svm->vmcb->save.es = hsave->save.es;
1679         svm->vmcb->save.cs = hsave->save.cs;
1680         svm->vmcb->save.ss = hsave->save.ss;
1681         svm->vmcb->save.ds = hsave->save.ds;
1682         svm->vmcb->save.gdtr = hsave->save.gdtr;
1683         svm->vmcb->save.idtr = hsave->save.idtr;
1684         svm->vmcb->save.rflags = hsave->save.rflags;
1685         svm_set_efer(&svm->vcpu, hsave->save.efer);
1686         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1687         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1688         if (npt_enabled) {
1689                 svm->vmcb->save.cr3 = hsave->save.cr3;
1690                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1691         } else {
1692                 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1693         }
1694         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1695         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1696         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1697         svm->vmcb->save.dr7 = 0;
1698         svm->vmcb->save.cpl = 0;
1699         svm->vmcb->control.exit_int_info = 0;
1700
1701         /* Exit nested SVM mode */
1702         svm->nested.vmcb = 0;
1703
1704         nested_svm_unmap(nested_vmcb, KM_USER0);
1705
1706         kvm_mmu_reset_context(&svm->vcpu);
1707         kvm_mmu_load(&svm->vcpu);
1708
1709         return 0;
1710 }
1711
1712 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1713 {
1714         u32 *nested_msrpm;
1715         int i;
1716
1717         nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1718         if (!nested_msrpm)
1719                 return false;
1720
1721         for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1722                 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1723
1724         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
1725
1726         nested_svm_unmap(nested_msrpm, KM_USER0);
1727
1728         return true;
1729 }
1730
1731 static bool nested_svm_vmrun(struct vcpu_svm *svm)
1732 {
1733         struct vmcb *nested_vmcb;
1734         struct vmcb *hsave = svm->nested.hsave;
1735         struct vmcb *vmcb = svm->vmcb;
1736
1737         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1738         if (!nested_vmcb)
1739                 return false;
1740
1741         /* nested_vmcb is our indicator if nested SVM is activated */
1742         svm->nested.vmcb = svm->vmcb->save.rax;
1743
1744         trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, svm->nested.vmcb,
1745                                nested_vmcb->save.rip,
1746                                nested_vmcb->control.int_ctl,
1747                                nested_vmcb->control.event_inj,
1748                                nested_vmcb->control.nested_ctl);
1749
1750         /* Clear internal status */
1751         kvm_clear_exception_queue(&svm->vcpu);
1752         kvm_clear_interrupt_queue(&svm->vcpu);
1753
1754         /* Save the old vmcb, so we don't need to pick what we save, but
1755            can restore everything when a VMEXIT occurs */
1756         hsave->save.es     = vmcb->save.es;
1757         hsave->save.cs     = vmcb->save.cs;
1758         hsave->save.ss     = vmcb->save.ss;
1759         hsave->save.ds     = vmcb->save.ds;
1760         hsave->save.gdtr   = vmcb->save.gdtr;
1761         hsave->save.idtr   = vmcb->save.idtr;
1762         hsave->save.efer   = svm->vcpu.arch.shadow_efer;
1763         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
1764         hsave->save.cr4    = svm->vcpu.arch.cr4;
1765         hsave->save.rflags = vmcb->save.rflags;
1766         hsave->save.rip    = svm->next_rip;
1767         hsave->save.rsp    = vmcb->save.rsp;
1768         hsave->save.rax    = vmcb->save.rax;
1769         if (npt_enabled)
1770                 hsave->save.cr3    = vmcb->save.cr3;
1771         else
1772                 hsave->save.cr3    = svm->vcpu.arch.cr3;
1773
1774         copy_vmcb_control_area(hsave, vmcb);
1775
1776         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1777                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1778         else
1779                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1780
1781         /* Load the nested guest state */
1782         svm->vmcb->save.es = nested_vmcb->save.es;
1783         svm->vmcb->save.cs = nested_vmcb->save.cs;
1784         svm->vmcb->save.ss = nested_vmcb->save.ss;
1785         svm->vmcb->save.ds = nested_vmcb->save.ds;
1786         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1787         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1788         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1789         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1790         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1791         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1792         if (npt_enabled) {
1793                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1794                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1795         } else {
1796                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1797                 kvm_mmu_reset_context(&svm->vcpu);
1798         }
1799         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
1800         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1801         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1802         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1803         /* In case we don't even reach vcpu_run, the fields are not updated */
1804         svm->vmcb->save.rax = nested_vmcb->save.rax;
1805         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1806         svm->vmcb->save.rip = nested_vmcb->save.rip;
1807         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1808         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1809         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1810
1811         /* We don't want a nested guest to be more powerful than the guest,
1812            so all intercepts are ORed */
1813         svm->vmcb->control.intercept_cr_read |=
1814                 nested_vmcb->control.intercept_cr_read;
1815         svm->vmcb->control.intercept_cr_write |=
1816                 nested_vmcb->control.intercept_cr_write;
1817         svm->vmcb->control.intercept_dr_read |=
1818                 nested_vmcb->control.intercept_dr_read;
1819         svm->vmcb->control.intercept_dr_write |=
1820                 nested_vmcb->control.intercept_dr_write;
1821         svm->vmcb->control.intercept_exceptions |=
1822                 nested_vmcb->control.intercept_exceptions;
1823
1824         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1825
1826         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1827
1828         /* cache intercepts */
1829         svm->nested.intercept_cr_read    = nested_vmcb->control.intercept_cr_read;
1830         svm->nested.intercept_cr_write   = nested_vmcb->control.intercept_cr_write;
1831         svm->nested.intercept_dr_read    = nested_vmcb->control.intercept_dr_read;
1832         svm->nested.intercept_dr_write   = nested_vmcb->control.intercept_dr_write;
1833         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1834         svm->nested.intercept            = nested_vmcb->control.intercept;
1835
1836         force_new_asid(&svm->vcpu);
1837         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1838         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1839                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1840         else
1841                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1842
1843         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1844         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1845         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1846         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1847         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1848
1849         nested_svm_unmap(nested_vmcb, KM_USER0);
1850
1851         enable_gif(svm);
1852
1853         return true;
1854 }
1855
1856 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1857 {
1858         to_vmcb->save.fs = from_vmcb->save.fs;
1859         to_vmcb->save.gs = from_vmcb->save.gs;
1860         to_vmcb->save.tr = from_vmcb->save.tr;
1861         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1862         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1863         to_vmcb->save.star = from_vmcb->save.star;
1864         to_vmcb->save.lstar = from_vmcb->save.lstar;
1865         to_vmcb->save.cstar = from_vmcb->save.cstar;
1866         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1867         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1868         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1869         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1870 }
1871
1872 static int vmload_interception(struct vcpu_svm *svm)
1873 {
1874         struct vmcb *nested_vmcb;
1875
1876         if (nested_svm_check_permissions(svm))
1877                 return 1;
1878
1879         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1880         skip_emulated_instruction(&svm->vcpu);
1881
1882         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1883         if (!nested_vmcb)
1884                 return 1;
1885
1886         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1887         nested_svm_unmap(nested_vmcb, KM_USER0);
1888
1889         return 1;
1890 }
1891
1892 static int vmsave_interception(struct vcpu_svm *svm)
1893 {
1894         struct vmcb *nested_vmcb;
1895
1896         if (nested_svm_check_permissions(svm))
1897                 return 1;
1898
1899         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1900         skip_emulated_instruction(&svm->vcpu);
1901
1902         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1903         if (!nested_vmcb)
1904                 return 1;
1905
1906         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1907         nested_svm_unmap(nested_vmcb, KM_USER0);
1908
1909         return 1;
1910 }
1911
1912 static int vmrun_interception(struct vcpu_svm *svm)
1913 {
1914         if (nested_svm_check_permissions(svm))
1915                 return 1;
1916
1917         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1918         skip_emulated_instruction(&svm->vcpu);
1919
1920         if (!nested_svm_vmrun(svm))
1921                 return 1;
1922
1923         if (!nested_svm_vmrun_msrpm(svm))
1924                 goto failed;
1925
1926         return 1;
1927
1928 failed:
1929
1930         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
1931         svm->vmcb->control.exit_code_hi = 0;
1932         svm->vmcb->control.exit_info_1  = 0;
1933         svm->vmcb->control.exit_info_2  = 0;
1934
1935         nested_svm_vmexit(svm);
1936
1937         return 1;
1938 }
1939
1940 static int stgi_interception(struct vcpu_svm *svm)
1941 {
1942         if (nested_svm_check_permissions(svm))
1943                 return 1;
1944
1945         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1946         skip_emulated_instruction(&svm->vcpu);
1947
1948         enable_gif(svm);
1949
1950         return 1;
1951 }
1952
1953 static int clgi_interception(struct vcpu_svm *svm)
1954 {
1955         if (nested_svm_check_permissions(svm))
1956                 return 1;
1957
1958         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1959         skip_emulated_instruction(&svm->vcpu);
1960
1961         disable_gif(svm);
1962
1963         /* After a CLGI no interrupts should come */
1964         svm_clear_vintr(svm);
1965         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1966
1967         return 1;
1968 }
1969
1970 static int invlpga_interception(struct vcpu_svm *svm)
1971 {
1972         struct kvm_vcpu *vcpu = &svm->vcpu;
1973
1974         trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
1975                           vcpu->arch.regs[VCPU_REGS_RAX]);
1976
1977         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1978         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1979
1980         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1981         skip_emulated_instruction(&svm->vcpu);
1982         return 1;
1983 }
1984
1985 static int skinit_interception(struct vcpu_svm *svm)
1986 {
1987         trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
1988
1989         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1990         return 1;
1991 }
1992
1993 static int invalid_op_interception(struct vcpu_svm *svm)
1994 {
1995         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1996         return 1;
1997 }
1998
1999 static int task_switch_interception(struct vcpu_svm *svm)
2000 {
2001         u16 tss_selector;
2002         int reason;
2003         int int_type = svm->vmcb->control.exit_int_info &
2004                 SVM_EXITINTINFO_TYPE_MASK;
2005         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2006         uint32_t type =
2007                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2008         uint32_t idt_v =
2009                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2010
2011         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2012
2013         if (svm->vmcb->control.exit_info_2 &
2014             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2015                 reason = TASK_SWITCH_IRET;
2016         else if (svm->vmcb->control.exit_info_2 &
2017                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2018                 reason = TASK_SWITCH_JMP;
2019         else if (idt_v)
2020                 reason = TASK_SWITCH_GATE;
2021         else
2022                 reason = TASK_SWITCH_CALL;
2023
2024         if (reason == TASK_SWITCH_GATE) {
2025                 switch (type) {
2026                 case SVM_EXITINTINFO_TYPE_NMI:
2027                         svm->vcpu.arch.nmi_injected = false;
2028                         break;
2029                 case SVM_EXITINTINFO_TYPE_EXEPT:
2030                         kvm_clear_exception_queue(&svm->vcpu);
2031                         break;
2032                 case SVM_EXITINTINFO_TYPE_INTR:
2033                         kvm_clear_interrupt_queue(&svm->vcpu);
2034                         break;
2035                 default:
2036                         break;
2037                 }
2038         }
2039
2040         if (reason != TASK_SWITCH_GATE ||
2041             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2042             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2043              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2044                 skip_emulated_instruction(&svm->vcpu);
2045
2046         return kvm_task_switch(&svm->vcpu, tss_selector, reason);
2047 }
2048
2049 static int cpuid_interception(struct vcpu_svm *svm)
2050 {
2051         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2052         kvm_emulate_cpuid(&svm->vcpu);
2053         return 1;
2054 }
2055
2056 static int iret_interception(struct vcpu_svm *svm)
2057 {
2058         ++svm->vcpu.stat.nmi_window_exits;
2059         svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2060         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2061         return 1;
2062 }
2063
2064 static int invlpg_interception(struct vcpu_svm *svm)
2065 {
2066         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2067                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2068         return 1;
2069 }
2070
2071 static int emulate_on_interception(struct vcpu_svm *svm)
2072 {
2073         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2074                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2075         return 1;
2076 }
2077
2078 static int cr8_write_interception(struct vcpu_svm *svm)
2079 {
2080         struct kvm_run *kvm_run = svm->vcpu.run;
2081
2082         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2083         /* instruction emulation calls kvm_set_cr8() */
2084         emulate_instruction(&svm->vcpu, 0, 0, 0);
2085         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2086                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2087                 return 1;
2088         }
2089         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2090                 return 1;
2091         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2092         return 0;
2093 }
2094
2095 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2096 {
2097         struct vcpu_svm *svm = to_svm(vcpu);
2098
2099         switch (ecx) {
2100         case MSR_IA32_TSC: {
2101                 u64 tsc_offset;
2102
2103                 if (is_nested(svm))
2104                         tsc_offset = svm->nested.hsave->control.tsc_offset;
2105                 else
2106                         tsc_offset = svm->vmcb->control.tsc_offset;
2107
2108                 *data = tsc_offset + native_read_tsc();
2109                 break;
2110         }
2111         case MSR_K6_STAR:
2112                 *data = svm->vmcb->save.star;
2113                 break;
2114 #ifdef CONFIG_X86_64
2115         case MSR_LSTAR:
2116                 *data = svm->vmcb->save.lstar;
2117                 break;
2118         case MSR_CSTAR:
2119                 *data = svm->vmcb->save.cstar;
2120                 break;
2121         case MSR_KERNEL_GS_BASE:
2122                 *data = svm->vmcb->save.kernel_gs_base;
2123                 break;
2124         case MSR_SYSCALL_MASK:
2125                 *data = svm->vmcb->save.sfmask;
2126                 break;
2127 #endif
2128         case MSR_IA32_SYSENTER_CS:
2129                 *data = svm->vmcb->save.sysenter_cs;
2130                 break;
2131         case MSR_IA32_SYSENTER_EIP:
2132                 *data = svm->sysenter_eip;
2133                 break;
2134         case MSR_IA32_SYSENTER_ESP:
2135                 *data = svm->sysenter_esp;
2136                 break;
2137         /* Nobody will change the following 5 values in the VMCB so
2138            we can safely return them on rdmsr. They will always be 0
2139            until LBRV is implemented. */
2140         case MSR_IA32_DEBUGCTLMSR:
2141                 *data = svm->vmcb->save.dbgctl;
2142                 break;
2143         case MSR_IA32_LASTBRANCHFROMIP:
2144                 *data = svm->vmcb->save.br_from;
2145                 break;
2146         case MSR_IA32_LASTBRANCHTOIP:
2147                 *data = svm->vmcb->save.br_to;
2148                 break;
2149         case MSR_IA32_LASTINTFROMIP:
2150                 *data = svm->vmcb->save.last_excp_from;
2151                 break;
2152         case MSR_IA32_LASTINTTOIP:
2153                 *data = svm->vmcb->save.last_excp_to;
2154                 break;
2155         case MSR_VM_HSAVE_PA:
2156                 *data = svm->nested.hsave_msr;
2157                 break;
2158         case MSR_VM_CR:
2159                 *data = 0;
2160                 break;
2161         case MSR_IA32_UCODE_REV:
2162                 *data = 0x01000065;
2163                 break;
2164         default:
2165                 return kvm_get_msr_common(vcpu, ecx, data);
2166         }
2167         return 0;
2168 }
2169
2170 static int rdmsr_interception(struct vcpu_svm *svm)
2171 {
2172         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2173         u64 data;
2174
2175         if (svm_get_msr(&svm->vcpu, ecx, &data))
2176                 kvm_inject_gp(&svm->vcpu, 0);
2177         else {
2178                 trace_kvm_msr_read(ecx, data);
2179
2180                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2181                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2182                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2183                 skip_emulated_instruction(&svm->vcpu);
2184         }
2185         return 1;
2186 }
2187
2188 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2189 {
2190         struct vcpu_svm *svm = to_svm(vcpu);
2191
2192         switch (ecx) {
2193         case MSR_IA32_TSC: {
2194                 u64 tsc_offset = data - native_read_tsc();
2195                 u64 g_tsc_offset = 0;
2196
2197                 if (is_nested(svm)) {
2198                         g_tsc_offset = svm->vmcb->control.tsc_offset -
2199                                        svm->nested.hsave->control.tsc_offset;
2200                         svm->nested.hsave->control.tsc_offset = tsc_offset;
2201                 }
2202
2203                 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2204
2205                 break;
2206         }
2207         case MSR_K6_STAR:
2208                 svm->vmcb->save.star = data;
2209                 break;
2210 #ifdef CONFIG_X86_64
2211         case MSR_LSTAR:
2212                 svm->vmcb->save.lstar = data;
2213                 break;
2214         case MSR_CSTAR:
2215                 svm->vmcb->save.cstar = data;
2216                 break;
2217         case MSR_KERNEL_GS_BASE:
2218                 svm->vmcb->save.kernel_gs_base = data;
2219                 break;
2220         case MSR_SYSCALL_MASK:
2221                 svm->vmcb->save.sfmask = data;
2222                 break;
2223 #endif
2224         case MSR_IA32_SYSENTER_CS:
2225                 svm->vmcb->save.sysenter_cs = data;
2226                 break;
2227         case MSR_IA32_SYSENTER_EIP:
2228                 svm->sysenter_eip = data;
2229                 svm->vmcb->save.sysenter_eip = data;
2230                 break;
2231         case MSR_IA32_SYSENTER_ESP:
2232                 svm->sysenter_esp = data;
2233                 svm->vmcb->save.sysenter_esp = data;
2234                 break;
2235         case MSR_IA32_DEBUGCTLMSR:
2236                 if (!svm_has(SVM_FEATURE_LBRV)) {
2237                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2238                                         __func__, data);
2239                         break;
2240                 }
2241                 if (data & DEBUGCTL_RESERVED_BITS)
2242                         return 1;
2243
2244                 svm->vmcb->save.dbgctl = data;
2245                 if (data & (1ULL<<0))
2246                         svm_enable_lbrv(svm);
2247                 else
2248                         svm_disable_lbrv(svm);
2249                 break;
2250         case MSR_VM_HSAVE_PA:
2251                 svm->nested.hsave_msr = data;
2252                 break;
2253         case MSR_VM_CR:
2254         case MSR_VM_IGNNE:
2255                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2256                 break;
2257         default:
2258                 return kvm_set_msr_common(vcpu, ecx, data);
2259         }
2260         return 0;
2261 }
2262
2263 static int wrmsr_interception(struct vcpu_svm *svm)
2264 {
2265         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2266         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2267                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2268
2269         trace_kvm_msr_write(ecx, data);
2270
2271         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2272         if (svm_set_msr(&svm->vcpu, ecx, data))
2273                 kvm_inject_gp(&svm->vcpu, 0);
2274         else
2275                 skip_emulated_instruction(&svm->vcpu);
2276         return 1;
2277 }
2278
2279 static int msr_interception(struct vcpu_svm *svm)
2280 {
2281         if (svm->vmcb->control.exit_info_1)
2282                 return wrmsr_interception(svm);
2283         else
2284                 return rdmsr_interception(svm);
2285 }
2286
2287 static int interrupt_window_interception(struct vcpu_svm *svm)
2288 {
2289         struct kvm_run *kvm_run = svm->vcpu.run;
2290
2291         svm_clear_vintr(svm);
2292         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2293         /*
2294          * If the user space waits to inject interrupts, exit as soon as
2295          * possible
2296          */
2297         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2298             kvm_run->request_interrupt_window &&
2299             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2300                 ++svm->vcpu.stat.irq_window_exits;
2301                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2302                 return 0;
2303         }
2304
2305         return 1;
2306 }
2307
2308 static int pause_interception(struct vcpu_svm *svm)
2309 {
2310         kvm_vcpu_on_spin(&(svm->vcpu));
2311         return 1;
2312 }
2313
2314 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2315         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2316         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2317         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2318         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2319         [SVM_EXIT_CR0_SEL_WRITE]                = emulate_on_interception,
2320         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2321         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2322         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2323         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2324         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2325         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2326         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2327         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2328         [SVM_EXIT_READ_DR4]                     = emulate_on_interception,
2329         [SVM_EXIT_READ_DR5]                     = emulate_on_interception,
2330         [SVM_EXIT_READ_DR6]                     = emulate_on_interception,
2331         [SVM_EXIT_READ_DR7]                     = emulate_on_interception,
2332         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2333         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2334         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2335         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2336         [SVM_EXIT_WRITE_DR4]                    = emulate_on_interception,
2337         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2338         [SVM_EXIT_WRITE_DR6]                    = emulate_on_interception,
2339         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2340         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2341         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2342         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2343         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2344         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2345         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2346         [SVM_EXIT_INTR]                         = intr_interception,
2347         [SVM_EXIT_NMI]                          = nmi_interception,
2348         [SVM_EXIT_SMI]                          = nop_on_interception,
2349         [SVM_EXIT_INIT]                         = nop_on_interception,
2350         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2351         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
2352         [SVM_EXIT_CPUID]                        = cpuid_interception,
2353         [SVM_EXIT_IRET]                         = iret_interception,
2354         [SVM_EXIT_INVD]                         = emulate_on_interception,
2355         [SVM_EXIT_PAUSE]                        = pause_interception,
2356         [SVM_EXIT_HLT]                          = halt_interception,
2357         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2358         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2359         [SVM_EXIT_IOIO]                         = io_interception,
2360         [SVM_EXIT_MSR]                          = msr_interception,
2361         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2362         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2363         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2364         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2365         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2366         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2367         [SVM_EXIT_STGI]                         = stgi_interception,
2368         [SVM_EXIT_CLGI]                         = clgi_interception,
2369         [SVM_EXIT_SKINIT]                       = skinit_interception,
2370         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2371         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2372         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2373         [SVM_EXIT_NPF]                          = pf_interception,
2374 };
2375
2376 static int handle_exit(struct kvm_vcpu *vcpu)
2377 {
2378         struct vcpu_svm *svm = to_svm(vcpu);
2379         struct kvm_run *kvm_run = vcpu->run;
2380         u32 exit_code = svm->vmcb->control.exit_code;
2381
2382         trace_kvm_exit(exit_code, svm->vmcb->save.rip);
2383
2384         if (unlikely(svm->nested.exit_required)) {
2385                 nested_svm_vmexit(svm);
2386                 svm->nested.exit_required = false;
2387
2388                 return 1;
2389         }
2390
2391         if (is_nested(svm)) {
2392                 int vmexit;
2393
2394                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2395                                         svm->vmcb->control.exit_info_1,
2396                                         svm->vmcb->control.exit_info_2,
2397                                         svm->vmcb->control.exit_int_info,
2398                                         svm->vmcb->control.exit_int_info_err);
2399
2400                 vmexit = nested_svm_exit_special(svm);
2401
2402                 if (vmexit == NESTED_EXIT_CONTINUE)
2403                         vmexit = nested_svm_exit_handled(svm);
2404
2405                 if (vmexit == NESTED_EXIT_DONE)
2406                         return 1;
2407         }
2408
2409         svm_complete_interrupts(svm);
2410
2411         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2412                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2413         if (npt_enabled)
2414                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2415
2416         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2417                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2418                 kvm_run->fail_entry.hardware_entry_failure_reason
2419                         = svm->vmcb->control.exit_code;
2420                 return 0;
2421         }
2422
2423         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2424             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2425             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2426                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2427                        "exit_code 0x%x\n",
2428                        __func__, svm->vmcb->control.exit_int_info,
2429                        exit_code);
2430
2431         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2432             || !svm_exit_handlers[exit_code]) {
2433                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2434                 kvm_run->hw.hardware_exit_reason = exit_code;
2435                 return 0;
2436         }
2437
2438         return svm_exit_handlers[exit_code](svm);
2439 }
2440
2441 static void reload_tss(struct kvm_vcpu *vcpu)
2442 {
2443         int cpu = raw_smp_processor_id();
2444
2445         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2446         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
2447         load_TR_desc();
2448 }
2449
2450 static void pre_svm_run(struct vcpu_svm *svm)
2451 {
2452         int cpu = raw_smp_processor_id();
2453
2454         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2455
2456         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2457         /* FIXME: handle wraparound of asid_generation */
2458         if (svm->asid_generation != sd->asid_generation)
2459                 new_asid(svm, sd);
2460 }
2461
2462 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2463 {
2464         struct vcpu_svm *svm = to_svm(vcpu);
2465
2466         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2467         vcpu->arch.hflags |= HF_NMI_MASK;
2468         svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2469         ++vcpu->stat.nmi_injections;
2470 }
2471
2472 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2473 {
2474         struct vmcb_control_area *control;
2475
2476         trace_kvm_inj_virq(irq);
2477
2478         ++svm->vcpu.stat.irq_injections;
2479         control = &svm->vmcb->control;
2480         control->int_vector = irq;
2481         control->int_ctl &= ~V_INTR_PRIO_MASK;
2482         control->int_ctl |= V_IRQ_MASK |
2483                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2484 }
2485
2486 static void svm_set_irq(struct kvm_vcpu *vcpu)
2487 {
2488         struct vcpu_svm *svm = to_svm(vcpu);
2489
2490         BUG_ON(!(gif_set(svm)));
2491
2492         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2493                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2494 }
2495
2496 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2497 {
2498         struct vcpu_svm *svm = to_svm(vcpu);
2499
2500         if (irr == -1)
2501                 return;
2502
2503         if (tpr >= irr)
2504                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2505 }
2506
2507 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2508 {
2509         struct vcpu_svm *svm = to_svm(vcpu);
2510         struct vmcb *vmcb = svm->vmcb;
2511         return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2512                 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2513 }
2514
2515 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2516 {
2517         struct vcpu_svm *svm = to_svm(vcpu);
2518
2519         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2520 }
2521
2522 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2523 {
2524         struct vcpu_svm *svm = to_svm(vcpu);
2525
2526         if (masked) {
2527                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2528                 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2529         } else {
2530                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2531                 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2532         }
2533 }
2534
2535 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2536 {
2537         struct vcpu_svm *svm = to_svm(vcpu);
2538         struct vmcb *vmcb = svm->vmcb;
2539         int ret;
2540
2541         if (!gif_set(svm) ||
2542              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2543                 return 0;
2544
2545         ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2546
2547         if (is_nested(svm))
2548                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2549
2550         return ret;
2551 }
2552
2553 static void enable_irq_window(struct kvm_vcpu *vcpu)
2554 {
2555         struct vcpu_svm *svm = to_svm(vcpu);
2556
2557         nested_svm_intr(svm);
2558
2559         /* In case GIF=0 we can't rely on the CPU to tell us when
2560          * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2561          * The next time we get that intercept, this function will be
2562          * called again though and we'll get the vintr intercept. */
2563         if (gif_set(svm)) {
2564                 svm_set_vintr(svm);
2565                 svm_inject_irq(svm, 0x0);
2566         }
2567 }
2568
2569 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2570 {
2571         struct vcpu_svm *svm = to_svm(vcpu);
2572
2573         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2574             == HF_NMI_MASK)
2575                 return; /* IRET will cause a vm exit */
2576
2577         /* Something prevents NMI from been injected. Single step over
2578            possible problem (IRET or exception injection or interrupt
2579            shadow) */
2580         svm->nmi_singlestep = true;
2581         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2582         update_db_intercept(vcpu);
2583 }
2584
2585 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2586 {
2587         return 0;
2588 }
2589
2590 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2591 {
2592         force_new_asid(vcpu);
2593 }
2594
2595 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2596 {
2597 }
2598
2599 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2600 {
2601         struct vcpu_svm *svm = to_svm(vcpu);
2602
2603         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2604                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2605                 kvm_set_cr8(vcpu, cr8);
2606         }
2607 }
2608
2609 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2610 {
2611         struct vcpu_svm *svm = to_svm(vcpu);
2612         u64 cr8;
2613
2614         cr8 = kvm_get_cr8(vcpu);
2615         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2616         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2617 }
2618
2619 static void svm_complete_interrupts(struct vcpu_svm *svm)
2620 {
2621         u8 vector;
2622         int type;
2623         u32 exitintinfo = svm->vmcb->control.exit_int_info;
2624
2625         if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2626                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2627
2628         svm->vcpu.arch.nmi_injected = false;
2629         kvm_clear_exception_queue(&svm->vcpu);
2630         kvm_clear_interrupt_queue(&svm->vcpu);
2631
2632         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2633                 return;
2634
2635         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2636         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2637
2638         switch (type) {
2639         case SVM_EXITINTINFO_TYPE_NMI:
2640                 svm->vcpu.arch.nmi_injected = true;
2641                 break;
2642         case SVM_EXITINTINFO_TYPE_EXEPT:
2643                 /* In case of software exception do not reinject an exception
2644                    vector, but re-execute and instruction instead */
2645                 if (is_nested(svm))
2646                         break;
2647                 if (kvm_exception_is_soft(vector))
2648                         break;
2649                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2650                         u32 err = svm->vmcb->control.exit_int_info_err;
2651                         kvm_queue_exception_e(&svm->vcpu, vector, err);
2652
2653                 } else
2654                         kvm_queue_exception(&svm->vcpu, vector);
2655                 break;
2656         case SVM_EXITINTINFO_TYPE_INTR:
2657                 kvm_queue_interrupt(&svm->vcpu, vector, false);
2658                 break;
2659         default:
2660                 break;
2661         }
2662 }
2663
2664 #ifdef CONFIG_X86_64
2665 #define R "r"
2666 #else
2667 #define R "e"
2668 #endif
2669
2670 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
2671 {
2672         struct vcpu_svm *svm = to_svm(vcpu);
2673         u16 fs_selector;
2674         u16 gs_selector;
2675         u16 ldt_selector;
2676
2677         /*
2678          * A vmexit emulation is required before the vcpu can be executed
2679          * again.
2680          */
2681         if (unlikely(svm->nested.exit_required))
2682                 return;
2683
2684         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2685         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2686         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2687
2688         pre_svm_run(svm);
2689
2690         sync_lapic_to_cr8(vcpu);
2691
2692         save_host_msrs(vcpu);
2693         fs_selector = kvm_read_fs();
2694         gs_selector = kvm_read_gs();
2695         ldt_selector = kvm_read_ldt();
2696         svm->vmcb->save.cr2 = vcpu->arch.cr2;
2697         /* required for live migration with NPT */
2698         if (npt_enabled)
2699                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2700
2701         clgi();
2702
2703         local_irq_enable();
2704
2705         asm volatile (
2706                 "push %%"R"bp; \n\t"
2707                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2708                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2709                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2710                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2711                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2712                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2713 #ifdef CONFIG_X86_64
2714                 "mov %c[r8](%[svm]),  %%r8  \n\t"
2715                 "mov %c[r9](%[svm]),  %%r9  \n\t"
2716                 "mov %c[r10](%[svm]), %%r10 \n\t"
2717                 "mov %c[r11](%[svm]), %%r11 \n\t"
2718                 "mov %c[r12](%[svm]), %%r12 \n\t"
2719                 "mov %c[r13](%[svm]), %%r13 \n\t"
2720                 "mov %c[r14](%[svm]), %%r14 \n\t"
2721                 "mov %c[r15](%[svm]), %%r15 \n\t"
2722 #endif
2723
2724                 /* Enter guest mode */
2725                 "push %%"R"ax \n\t"
2726                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2727                 __ex(SVM_VMLOAD) "\n\t"
2728                 __ex(SVM_VMRUN) "\n\t"
2729                 __ex(SVM_VMSAVE) "\n\t"
2730                 "pop %%"R"ax \n\t"
2731
2732                 /* Save guest registers, load host registers */
2733                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2734                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2735                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2736                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2737                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2738                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2739 #ifdef CONFIG_X86_64
2740                 "mov %%r8,  %c[r8](%[svm]) \n\t"
2741                 "mov %%r9,  %c[r9](%[svm]) \n\t"
2742                 "mov %%r10, %c[r10](%[svm]) \n\t"
2743                 "mov %%r11, %c[r11](%[svm]) \n\t"
2744                 "mov %%r12, %c[r12](%[svm]) \n\t"
2745                 "mov %%r13, %c[r13](%[svm]) \n\t"
2746                 "mov %%r14, %c[r14](%[svm]) \n\t"
2747                 "mov %%r15, %c[r15](%[svm]) \n\t"
2748 #endif
2749                 "pop %%"R"bp"
2750                 :
2751                 : [svm]"a"(svm),
2752                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2753                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2754                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2755                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2756                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2757                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2758                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2759 #ifdef CONFIG_X86_64
2760                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2761                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2762                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2763                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2764                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2765                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2766                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2767                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2768 #endif
2769                 : "cc", "memory"
2770                 , R"bx", R"cx", R"dx", R"si", R"di"
2771 #ifdef CONFIG_X86_64
2772                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2773 #endif
2774                 );
2775
2776         vcpu->arch.cr2 = svm->vmcb->save.cr2;
2777         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2778         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2779         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2780
2781         kvm_load_fs(fs_selector);
2782         kvm_load_gs(gs_selector);
2783         kvm_load_ldt(ldt_selector);
2784         load_host_msrs(vcpu);
2785
2786         reload_tss(vcpu);
2787
2788         local_irq_disable();
2789
2790         stgi();
2791
2792         sync_cr8_to_lapic(vcpu);
2793
2794         svm->next_rip = 0;
2795
2796         if (npt_enabled) {
2797                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2798                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2799         }
2800 }
2801
2802 #undef R
2803
2804 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2805 {
2806         struct vcpu_svm *svm = to_svm(vcpu);
2807
2808         if (npt_enabled) {
2809                 svm->vmcb->control.nested_cr3 = root;
2810                 force_new_asid(vcpu);
2811                 return;
2812         }
2813
2814         svm->vmcb->save.cr3 = root;
2815         force_new_asid(vcpu);
2816 }
2817
2818 static int is_disabled(void)
2819 {
2820         u64 vm_cr;
2821
2822         rdmsrl(MSR_VM_CR, vm_cr);
2823         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2824                 return 1;
2825
2826         return 0;
2827 }
2828
2829 static void
2830 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2831 {
2832         /*
2833          * Patch in the VMMCALL instruction:
2834          */
2835         hypercall[0] = 0x0f;
2836         hypercall[1] = 0x01;
2837         hypercall[2] = 0xd9;
2838 }
2839
2840 static void svm_check_processor_compat(void *rtn)
2841 {
2842         *(int *)rtn = 0;
2843 }
2844
2845 static bool svm_cpu_has_accelerated_tpr(void)
2846 {
2847         return false;
2848 }
2849
2850 static int get_npt_level(void)
2851 {
2852 #ifdef CONFIG_X86_64
2853         return PT64_ROOT_LEVEL;
2854 #else
2855         return PT32E_ROOT_LEVEL;
2856 #endif
2857 }
2858
2859 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
2860 {
2861         return 0;
2862 }
2863
2864 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
2865 {
2866 }
2867
2868 static const struct trace_print_flags svm_exit_reasons_str[] = {
2869         { SVM_EXIT_READ_CR0,                    "read_cr0" },
2870         { SVM_EXIT_READ_CR3,                    "read_cr3" },
2871         { SVM_EXIT_READ_CR4,                    "read_cr4" },
2872         { SVM_EXIT_READ_CR8,                    "read_cr8" },
2873         { SVM_EXIT_WRITE_CR0,                   "write_cr0" },
2874         { SVM_EXIT_WRITE_CR3,                   "write_cr3" },
2875         { SVM_EXIT_WRITE_CR4,                   "write_cr4" },
2876         { SVM_EXIT_WRITE_CR8,                   "write_cr8" },
2877         { SVM_EXIT_READ_DR0,                    "read_dr0" },
2878         { SVM_EXIT_READ_DR1,                    "read_dr1" },
2879         { SVM_EXIT_READ_DR2,                    "read_dr2" },
2880         { SVM_EXIT_READ_DR3,                    "read_dr3" },
2881         { SVM_EXIT_WRITE_DR0,                   "write_dr0" },
2882         { SVM_EXIT_WRITE_DR1,                   "write_dr1" },
2883         { SVM_EXIT_WRITE_DR2,                   "write_dr2" },
2884         { SVM_EXIT_WRITE_DR3,                   "write_dr3" },
2885         { SVM_EXIT_WRITE_DR5,                   "write_dr5" },
2886         { SVM_EXIT_WRITE_DR7,                   "write_dr7" },
2887         { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" },
2888         { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" },
2889         { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" },
2890         { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" },
2891         { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" },
2892         { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" },
2893         { SVM_EXIT_INTR,                        "interrupt" },
2894         { SVM_EXIT_NMI,                         "nmi" },
2895         { SVM_EXIT_SMI,                         "smi" },
2896         { SVM_EXIT_INIT,                        "init" },
2897         { SVM_EXIT_VINTR,                       "vintr" },
2898         { SVM_EXIT_CPUID,                       "cpuid" },
2899         { SVM_EXIT_INVD,                        "invd" },
2900         { SVM_EXIT_HLT,                         "hlt" },
2901         { SVM_EXIT_INVLPG,                      "invlpg" },
2902         { SVM_EXIT_INVLPGA,                     "invlpga" },
2903         { SVM_EXIT_IOIO,                        "io" },
2904         { SVM_EXIT_MSR,                         "msr" },
2905         { SVM_EXIT_TASK_SWITCH,                 "task_switch" },
2906         { SVM_EXIT_SHUTDOWN,                    "shutdown" },
2907         { SVM_EXIT_VMRUN,                       "vmrun" },
2908         { SVM_EXIT_VMMCALL,                     "hypercall" },
2909         { SVM_EXIT_VMLOAD,                      "vmload" },
2910         { SVM_EXIT_VMSAVE,                      "vmsave" },
2911         { SVM_EXIT_STGI,                        "stgi" },
2912         { SVM_EXIT_CLGI,                        "clgi" },
2913         { SVM_EXIT_SKINIT,                      "skinit" },
2914         { SVM_EXIT_WBINVD,                      "wbinvd" },
2915         { SVM_EXIT_MONITOR,                     "monitor" },
2916         { SVM_EXIT_MWAIT,                       "mwait" },
2917         { SVM_EXIT_NPF,                         "npf" },
2918         { -1, NULL }
2919 };
2920
2921 static int svm_get_lpage_level(void)
2922 {
2923         return PT_PDPE_LEVEL;
2924 }
2925
2926 static bool svm_rdtscp_supported(void)
2927 {
2928         return false;
2929 }
2930
2931 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
2932 {
2933         struct vcpu_svm *svm = to_svm(vcpu);
2934
2935         update_cr0_intercept(svm);
2936         svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
2937 }
2938
2939 static struct kvm_x86_ops svm_x86_ops = {
2940         .cpu_has_kvm_support = has_svm,
2941         .disabled_by_bios = is_disabled,
2942         .hardware_setup = svm_hardware_setup,
2943         .hardware_unsetup = svm_hardware_unsetup,
2944         .check_processor_compatibility = svm_check_processor_compat,
2945         .hardware_enable = svm_hardware_enable,
2946         .hardware_disable = svm_hardware_disable,
2947         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2948
2949         .vcpu_create = svm_create_vcpu,
2950         .vcpu_free = svm_free_vcpu,
2951         .vcpu_reset = svm_vcpu_reset,
2952
2953         .prepare_guest_switch = svm_prepare_guest_switch,
2954         .vcpu_load = svm_vcpu_load,
2955         .vcpu_put = svm_vcpu_put,
2956
2957         .set_guest_debug = svm_guest_debug,
2958         .get_msr = svm_get_msr,
2959         .set_msr = svm_set_msr,
2960         .get_segment_base = svm_get_segment_base,
2961         .get_segment = svm_get_segment,
2962         .set_segment = svm_set_segment,
2963         .get_cpl = svm_get_cpl,
2964         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2965         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
2966         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2967         .set_cr0 = svm_set_cr0,
2968         .set_cr3 = svm_set_cr3,
2969         .set_cr4 = svm_set_cr4,
2970         .set_efer = svm_set_efer,
2971         .get_idt = svm_get_idt,
2972         .set_idt = svm_set_idt,
2973         .get_gdt = svm_get_gdt,
2974         .set_gdt = svm_set_gdt,
2975         .get_dr = svm_get_dr,
2976         .set_dr = svm_set_dr,
2977         .cache_reg = svm_cache_reg,
2978         .get_rflags = svm_get_rflags,
2979         .set_rflags = svm_set_rflags,
2980         .fpu_deactivate = svm_fpu_deactivate,
2981
2982         .tlb_flush = svm_flush_tlb,
2983
2984         .run = svm_vcpu_run,
2985         .handle_exit = handle_exit,
2986         .skip_emulated_instruction = skip_emulated_instruction,
2987         .set_interrupt_shadow = svm_set_interrupt_shadow,
2988         .get_interrupt_shadow = svm_get_interrupt_shadow,
2989         .patch_hypercall = svm_patch_hypercall,
2990         .set_irq = svm_set_irq,
2991         .set_nmi = svm_inject_nmi,
2992         .queue_exception = svm_queue_exception,
2993         .interrupt_allowed = svm_interrupt_allowed,
2994         .nmi_allowed = svm_nmi_allowed,
2995         .get_nmi_mask = svm_get_nmi_mask,
2996         .set_nmi_mask = svm_set_nmi_mask,
2997         .enable_nmi_window = enable_nmi_window,
2998         .enable_irq_window = enable_irq_window,
2999         .update_cr8_intercept = update_cr8_intercept,
3000
3001         .set_tss_addr = svm_set_tss_addr,
3002         .get_tdp_level = get_npt_level,
3003         .get_mt_mask = svm_get_mt_mask,
3004
3005         .exit_reasons_str = svm_exit_reasons_str,
3006         .get_lpage_level = svm_get_lpage_level,
3007
3008         .cpuid_update = svm_cpuid_update,
3009
3010         .rdtscp_supported = svm_rdtscp_supported,
3011 };
3012
3013 static int __init svm_init(void)
3014 {
3015         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3016                               THIS_MODULE);
3017 }
3018
3019 static void __exit svm_exit(void)
3020 {
3021         kvm_exit();
3022 }
3023
3024 module_init(svm_init)
3025 module_exit(svm_exit)