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   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20 #include "kvm_cache_regs.h"
  21 #include "x86.h"
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/ftrace_event.h>
  29
  30 #include <asm/desc.h>
  31
  32 #include <asm/virtext.h>
  33 #include "trace.h"
  34
  35 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  36
  37 MODULE_AUTHOR("Qumranet");
  38 MODULE_LICENSE("GPL");
  39
  40 #define IOPM_ALLOC_ORDER 2
  41 #define MSRPM_ALLOC_ORDER 1
  42
  43 #define SEG_TYPE_LDT 2
  44 #define SEG_TYPE_BUSY_TSS16 3
  45
  46 #define SVM_FEATURE_NPT  (1 << 0)
  47 #define SVM_FEATURE_LBRV (1 << 1)
  48 #define SVM_FEATURE_SVML (1 << 2)
  49 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
  50
  51 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  52 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  53 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  54
  55 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  56
  57 static const u32 host_save_user_msrs[] = {
  58 #ifdef CONFIG_X86_64
  59         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  60         MSR_FS_BASE,
  61 #endif
  62         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  63 };
  64
  65 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  66
  67 struct kvm_vcpu;
  68
  69 struct nested_state {
  70         struct vmcb *hsave;
  71         u64 hsave_msr;
  72         u64 vmcb;
  73
  74         /* These are the merged vectors */
  75         u32 *msrpm;
  76
  77         /* gpa pointers to the real vectors */
  78         u64 vmcb_msrpm;
  79
  80         /* A VMEXIT is required but not yet emulated */
  81         bool exit_required;
  82
  83         /* cache for intercepts of the guest */
  84         u16 intercept_cr_read;
  85         u16 intercept_cr_write;
  86         u16 intercept_dr_read;
  87         u16 intercept_dr_write;
  88         u32 intercept_exceptions;
  89         u64 intercept;
  90
  91 };
  92
  93 struct vcpu_svm {
  94         struct kvm_vcpu vcpu;
  95         struct vmcb *vmcb;
  96         unsigned long vmcb_pa;
  97         struct svm_cpu_data *svm_data;
  98         uint64_t asid_generation;
  99         uint64_t sysenter_esp;
 100         uint64_t sysenter_eip;
 101
 102         u64 next_rip;
 103
 104         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 105         u64 host_gs_base;
 106
 107         u32 *msrpm;
 108
 109         struct nested_state nested;
 110
 111         bool nmi_singlestep;
 112 };
 113
 114 /* enable NPT for AMD64 and X86 with PAE */
 115 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 116 static bool npt_enabled = true;
 117 #else
 118 static bool npt_enabled = false;
 119 #endif
 120 static int npt = 1;
 121
 122 module_param(npt, int, S_IRUGO);
 123
 124 static int nested = 1;
 125 module_param(nested, int, S_IRUGO);
 126
 127 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 128 static void svm_complete_interrupts(struct vcpu_svm *svm);
 129
 130 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 131 static int nested_svm_vmexit(struct vcpu_svm *svm);
 132 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 133                                       bool has_error_code, u32 error_code);
 134
 135 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 136 {
 137         return container_of(vcpu, struct vcpu_svm, vcpu);
 138 }
 139
 140 static inline bool is_nested(struct vcpu_svm *svm)
 141 {
 142         return svm->nested.vmcb;
 143 }
 144
 145 static inline void enable_gif(struct vcpu_svm *svm)
 146 {
 147         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 148 }
 149
 150 static inline void disable_gif(struct vcpu_svm *svm)
 151 {
 152         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 153 }
 154
 155 static inline bool gif_set(struct vcpu_svm *svm)
 156 {
 157         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 158 }
 159
 160 static unsigned long iopm_base;
 161
 162 struct kvm_ldttss_desc {
 163         u16 limit0;
 164         u16 base0;
 165         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
 166         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
 167         u32 base3;
 168         u32 zero1;
 169 } __attribute__((packed));
 170
 171 struct svm_cpu_data {
 172         int cpu;
 173
 174         u64 asid_generation;
 175         u32 max_asid;
 176         u32 next_asid;
 177         struct kvm_ldttss_desc *tss_desc;
 178
 179         struct page *save_area;
 180 };
 181
 182 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 183 static uint32_t svm_features;
 184
 185 struct svm_init_data {
 186         int cpu;
 187         int r;
 188 };
 189
 190 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 191
 192 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 193 #define MSRS_RANGE_SIZE 2048
 194 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 195
 196 #define MAX_INST_SIZE 15
 197
 198 static inline u32 svm_has(u32 feat)
 199 {
 200         return svm_features & feat;
 201 }
 202
 203 static inline void clgi(void)
 204 {
 205         asm volatile (__ex(SVM_CLGI));
 206 }
 207
 208 static inline void stgi(void)
 209 {
 210         asm volatile (__ex(SVM_STGI));
 211 }
 212
 213 static inline void invlpga(unsigned long addr, u32 asid)
 214 {
 215         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 216 }
 217
 218 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 219 {
 220         to_svm(vcpu)->asid_generation--;
 221 }
 222
 223 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 224 {
 225         force_new_asid(vcpu);
 226 }
 227
 228 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 229 {
 230         if (!npt_enabled && !(efer & EFER_LMA))
 231                 efer &= ~EFER_LME;
 232
 233         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 234         vcpu->arch.shadow_efer = efer;
 235 }
 236
 237 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 238                                 bool has_error_code, u32 error_code)
 239 {
 240         struct vcpu_svm *svm = to_svm(vcpu);
 241
 242         /* If we are within a nested VM we'd better #VMEXIT and let the
 243            guest handle the exception */
 244         if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
 245                 return;
 246
 247         svm->vmcb->control.event_inj = nr
 248                 | SVM_EVTINJ_VALID
 249                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 250                 | SVM_EVTINJ_TYPE_EXEPT;
 251         svm->vmcb->control.event_inj_err = error_code;
 252 }
 253
 254 static int is_external_interrupt(u32 info)
 255 {
 256         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 257         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 258 }
 259
 260 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 261 {
 262         struct vcpu_svm *svm = to_svm(vcpu);
 263         u32 ret = 0;
 264
 265         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 266                 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
 267         return ret & mask;
 268 }
 269
 270 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 271 {
 272         struct vcpu_svm *svm = to_svm(vcpu);
 273
 274         if (mask == 0)
 275                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 276         else
 277                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 278
 279 }
 280
 281 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 282 {
 283         struct vcpu_svm *svm = to_svm(vcpu);
 284
 285         if (!svm->next_rip) {
 286                 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
 287                                 EMULATE_DONE)
 288                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 289                 return;
 290         }
 291         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 292                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 293                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 294
 295         kvm_rip_write(vcpu, svm->next_rip);
 296         svm_set_interrupt_shadow(vcpu, 0);
 297 }
 298
 299 static int has_svm(void)
 300 {
 301         const char *msg;
 302
 303         if (!cpu_has_svm(&msg)) {
 304                 printk(KERN_INFO "has_svm: %s\n", msg);
 305                 return 0;
 306         }
 307
 308         return 1;
 309 }
 310
 311 static void svm_hardware_disable(void *garbage)
 312 {
 313         cpu_svm_disable();
 314 }
 315
 316 static int svm_hardware_enable(void *garbage)
 317 {
 318
 319         struct svm_cpu_data *sd;
 320         uint64_t efer;
 321         struct descriptor_table gdt_descr;
 322         struct desc_struct *gdt;
 323         int me = raw_smp_processor_id();
 324
 325         rdmsrl(MSR_EFER, efer);
 326         if (efer & EFER_SVME)
 327                 return -EBUSY;
 328
 329         if (!has_svm()) {
 330                 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
 331                        me);
 332                 return -EINVAL;
 333         }
 334         sd = per_cpu(svm_data, me);
 335
 336         if (!sd) {
 337                 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
 338                        me);
 339                 return -EINVAL;
 340         }
 341
 342         sd->asid_generation = 1;
 343         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 344         sd->next_asid = sd->max_asid + 1;
 345
 346         kvm_get_gdt(&gdt_descr);
 347         gdt = (struct desc_struct *)gdt_descr.base;
 348         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 349
 350         wrmsrl(MSR_EFER, efer | EFER_SVME);
 351
 352         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 353
 354         return 0;
 355 }
 356
 357 static void svm_cpu_uninit(int cpu)
 358 {
 359         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 360
 361         if (!sd)
 362                 return;
 363
 364         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 365         __free_page(sd->save_area);
 366         kfree(sd);
 367 }
 368
 369 static int svm_cpu_init(int cpu)
 370 {
 371         struct svm_cpu_data *sd;
 372         int r;
 373
 374         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 375         if (!sd)
 376                 return -ENOMEM;
 377         sd->cpu = cpu;
 378         sd->save_area = alloc_page(GFP_KERNEL);
 379         r = -ENOMEM;
 380         if (!sd->save_area)
 381                 goto err_1;
 382
 383         per_cpu(svm_data, cpu) = sd;
 384
 385         return 0;
 386
 387 err_1:
 388         kfree(sd);
 389         return r;
 390
 391 }
 392
 393 static void set_msr_interception(u32 *msrpm, unsigned msr,
 394                                  int read, int write)
 395 {
 396         int i;
 397
 398         for (i = 0; i < NUM_MSR_MAPS; i++) {
 399                 if (msr >= msrpm_ranges[i] &&
 400                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 401                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 402                                           msrpm_ranges[i]) * 2;
 403
 404                         u32 *base = msrpm + (msr_offset / 32);
 405                         u32 msr_shift = msr_offset % 32;
 406                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 407                         *base = (*base & ~(0x3 << msr_shift)) |
 408                                 (mask << msr_shift);
 409                         return;
 410                 }
 411         }
 412         BUG();
 413 }
 414
 415 static void svm_vcpu_init_msrpm(u32 *msrpm)
 416 {
 417         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 418
 419 #ifdef CONFIG_X86_64
 420         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 421         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 422         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 423         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 424         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 425         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 426 #endif
 427         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 428         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 429 }
 430
 431 static void svm_enable_lbrv(struct vcpu_svm *svm)
 432 {
 433         u32 *msrpm = svm->msrpm;
 434
 435         svm->vmcb->control.lbr_ctl = 1;
 436         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 437         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 438         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 439         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 440 }
 441
 442 static void svm_disable_lbrv(struct vcpu_svm *svm)
 443 {
 444         u32 *msrpm = svm->msrpm;
 445
 446         svm->vmcb->control.lbr_ctl = 0;
 447         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 448         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 449         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 450         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 451 }
 452
 453 static __init int svm_hardware_setup(void)
 454 {
 455         int cpu;
 456         struct page *iopm_pages;
 457         void *iopm_va;
 458         int r;
 459
 460         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 461
 462         if (!iopm_pages)
 463                 return -ENOMEM;
 464
 465         iopm_va = page_address(iopm_pages);
 466         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 467         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 468
 469         if (boot_cpu_has(X86_FEATURE_NX))
 470                 kvm_enable_efer_bits(EFER_NX);
 471
 472         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 473                 kvm_enable_efer_bits(EFER_FFXSR);
 474
 475         if (nested) {
 476                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 477                 kvm_enable_efer_bits(EFER_SVME);
 478         }
 479
 480         for_each_possible_cpu(cpu) {
 481                 r = svm_cpu_init(cpu);
 482                 if (r)
 483                         goto err;
 484         }
 485
 486         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 487
 488         if (!svm_has(SVM_FEATURE_NPT))
 489                 npt_enabled = false;
 490
 491         if (npt_enabled && !npt) {
 492                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 493                 npt_enabled = false;
 494         }
 495
 496         if (npt_enabled) {
 497                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 498                 kvm_enable_tdp();
 499         } else
 500                 kvm_disable_tdp();
 501
 502         return 0;
 503
 504 err:
 505         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 506         iopm_base = 0;
 507         return r;
 508 }
 509
 510 static __exit void svm_hardware_unsetup(void)
 511 {
 512         int cpu;
 513
 514         for_each_possible_cpu(cpu)
 515                 svm_cpu_uninit(cpu);
 516
 517         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 518         iopm_base = 0;
 519 }
 520
 521 static void init_seg(struct vmcb_seg *seg)
 522 {
 523         seg->selector = 0;
 524         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 525                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 526         seg->limit = 0xffff;
 527         seg->base = 0;
 528 }
 529
 530 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 531 {
 532         seg->selector = 0;
 533         seg->attrib = SVM_SELECTOR_P_MASK | type;
 534         seg->limit = 0xffff;
 535         seg->base = 0;
 536 }
 537
 538 static void init_vmcb(struct vcpu_svm *svm)
 539 {
 540         struct vmcb_control_area *control = &svm->vmcb->control;
 541         struct vmcb_save_area *save = &svm->vmcb->save;
 542
 543         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 544                                         INTERCEPT_CR3_MASK |
 545                                         INTERCEPT_CR4_MASK;
 546
 547         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 548                                         INTERCEPT_CR3_MASK |
 549                                         INTERCEPT_CR4_MASK |
 550                                         INTERCEPT_CR8_MASK;
 551
 552         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 553                                         INTERCEPT_DR1_MASK |
 554                                         INTERCEPT_DR2_MASK |
 555                                         INTERCEPT_DR3_MASK;
 556
 557         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 558                                         INTERCEPT_DR1_MASK |
 559                                         INTERCEPT_DR2_MASK |
 560                                         INTERCEPT_DR3_MASK |
 561                                         INTERCEPT_DR5_MASK |
 562                                         INTERCEPT_DR7_MASK;
 563
 564         control->intercept_exceptions = (1 << PF_VECTOR) |
 565                                         (1 << UD_VECTOR) |
 566                                         (1 << MC_VECTOR);
 567
 568
 569         control->intercept =    (1ULL << INTERCEPT_INTR) |
 570                                 (1ULL << INTERCEPT_NMI) |
 571                                 (1ULL << INTERCEPT_SMI) |
 572                                 (1ULL << INTERCEPT_CPUID) |
 573                                 (1ULL << INTERCEPT_INVD) |
 574                                 (1ULL << INTERCEPT_HLT) |
 575                                 (1ULL << INTERCEPT_INVLPG) |
 576                                 (1ULL << INTERCEPT_INVLPGA) |
 577                                 (1ULL << INTERCEPT_IOIO_PROT) |
 578                                 (1ULL << INTERCEPT_MSR_PROT) |
 579                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 580                                 (1ULL << INTERCEPT_SHUTDOWN) |
 581                                 (1ULL << INTERCEPT_VMRUN) |
 582                                 (1ULL << INTERCEPT_VMMCALL) |
 583                                 (1ULL << INTERCEPT_VMLOAD) |
 584                                 (1ULL << INTERCEPT_VMSAVE) |
 585                                 (1ULL << INTERCEPT_STGI) |
 586                                 (1ULL << INTERCEPT_CLGI) |
 587                                 (1ULL << INTERCEPT_SKINIT) |
 588                                 (1ULL << INTERCEPT_WBINVD) |
 589                                 (1ULL << INTERCEPT_MONITOR) |
 590                                 (1ULL << INTERCEPT_MWAIT);
 591
 592         control->iopm_base_pa = iopm_base;
 593         control->msrpm_base_pa = __pa(svm->msrpm);
 594         control->tsc_offset = 0;
 595         control->int_ctl = V_INTR_MASKING_MASK;
 596
 597         init_seg(&save->es);
 598         init_seg(&save->ss);
 599         init_seg(&save->ds);
 600         init_seg(&save->fs);
 601         init_seg(&save->gs);
 602
 603         save->cs.selector = 0xf000;
 604         /* Executable/Readable Code Segment */
 605         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 606                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 607         save->cs.limit = 0xffff;
 608         /*
 609          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 610          * be consistent with it.
 611          *
 612          * Replace when we have real mode working for vmx.
 613          */
 614         save->cs.base = 0xf0000;
 615
 616         save->gdtr.limit = 0xffff;
 617         save->idtr.limit = 0xffff;
 618
 619         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 620         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 621
 622         save->efer = EFER_SVME;
 623         save->dr6 = 0xffff0ff0;
 624         save->dr7 = 0x400;
 625         save->rflags = 2;
 626         save->rip = 0x0000fff0;
 627         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 628
 629         /* This is the guest-visible cr0 value.
 630          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
 631          */
 632         svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
 633         kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
 634
 635         save->cr4 = X86_CR4_PAE;
 636         /* rdx = ?? */
 637
 638         if (npt_enabled) {
 639                 /* Setup VMCB for Nested Paging */
 640                 control->nested_ctl = 1;
 641                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 642                                         (1ULL << INTERCEPT_INVLPG));
 643                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 644                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 645                                                 INTERCEPT_CR3_MASK);
 646                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 647                                                  INTERCEPT_CR3_MASK);
 648                 save->g_pat = 0x0007040600070406ULL;
 649                 save->cr3 = 0;
 650                 save->cr4 = 0;
 651         }
 652         force_new_asid(&svm->vcpu);
 653
 654         svm->nested.vmcb = 0;
 655         svm->vcpu.arch.hflags = 0;
 656
 657         if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
 658                 control->pause_filter_count = 3000;
 659                 control->intercept |= (1ULL << INTERCEPT_PAUSE);
 660         }
 661
 662         enable_gif(svm);
 663 }
 664
 665 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 666 {
 667         struct vcpu_svm *svm = to_svm(vcpu);
 668
 669         init_vmcb(svm);
 670
 671         if (!kvm_vcpu_is_bsp(vcpu)) {
 672                 kvm_rip_write(vcpu, 0);
 673                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 674                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 675         }
 676         vcpu->arch.regs_avail = ~0;
 677         vcpu->arch.regs_dirty = ~0;
 678
 679         return 0;
 680 }
 681
 682 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 683 {
 684         struct vcpu_svm *svm;
 685         struct page *page;
 686         struct page *msrpm_pages;
 687         struct page *hsave_page;
 688         struct page *nested_msrpm_pages;
 689         int err;
 690
 691         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 692         if (!svm) {
 693                 err = -ENOMEM;
 694                 goto out;
 695         }
 696
 697         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 698         if (err)
 699                 goto free_svm;
 700
 701         page = alloc_page(GFP_KERNEL);
 702         if (!page) {
 703                 err = -ENOMEM;
 704                 goto uninit;
 705         }
 706
 707         err = -ENOMEM;
 708         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 709         if (!msrpm_pages)
 710                 goto uninit;
 711
 712         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 713         if (!nested_msrpm_pages)
 714                 goto uninit;
 715
 716         svm->msrpm = page_address(msrpm_pages);
 717         svm_vcpu_init_msrpm(svm->msrpm);
 718
 719         hsave_page = alloc_page(GFP_KERNEL);
 720         if (!hsave_page)
 721                 goto uninit;
 722         svm->nested.hsave = page_address(hsave_page);
 723
 724         svm->nested.msrpm = page_address(nested_msrpm_pages);
 725
 726         svm->vmcb = page_address(page);
 727         clear_page(svm->vmcb);
 728         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 729         svm->asid_generation = 0;
 730         init_vmcb(svm);
 731
 732         fx_init(&svm->vcpu);
 733         svm->vcpu.fpu_active = 1;
 734         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 735         if (kvm_vcpu_is_bsp(&svm->vcpu))
 736                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 737
 738         return &svm->vcpu;
 739
 740 uninit:
 741         kvm_vcpu_uninit(&svm->vcpu);
 742 free_svm:
 743         kmem_cache_free(kvm_vcpu_cache, svm);
 744 out:
 745         return ERR_PTR(err);
 746 }
 747
 748 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 749 {
 750         struct vcpu_svm *svm = to_svm(vcpu);
 751
 752         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 753         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 754         __free_page(virt_to_page(svm->nested.hsave));
 755         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
 756         kvm_vcpu_uninit(vcpu);
 757         kmem_cache_free(kvm_vcpu_cache, svm);
 758 }
 759
 760 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 761 {
 762         struct vcpu_svm *svm = to_svm(vcpu);
 763         int i;
 764
 765         if (unlikely(cpu != vcpu->cpu)) {
 766                 u64 delta;
 767
 768                 if (check_tsc_unstable()) {
 769                         /*
 770                          * Make sure that the guest sees a monotonically
 771                          * increasing TSC.
 772                          */
 773                         delta = vcpu->arch.host_tsc - native_read_tsc();
 774                         svm->vmcb->control.tsc_offset += delta;
 775                         if (is_nested(svm))
 776                                 svm->nested.hsave->control.tsc_offset += delta;
 777                 }
 778                 vcpu->cpu = cpu;
 779                 kvm_migrate_timers(vcpu);
 780                 svm->asid_generation = 0;
 781         }
 782
 783         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 784                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 785 }
 786
 787 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 788 {
 789         struct vcpu_svm *svm = to_svm(vcpu);
 790         int i;
 791
 792         ++vcpu->stat.host_state_reload;
 793         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 794                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 795
 796         vcpu->arch.host_tsc = native_read_tsc();
 797 }
 798
 799 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 800 {
 801         return to_svm(vcpu)->vmcb->save.rflags;
 802 }
 803
 804 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 805 {
 806         to_svm(vcpu)->vmcb->save.rflags = rflags;
 807 }
 808
 809 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
 810 {
 811         switch (reg) {
 812         case VCPU_EXREG_PDPTR:
 813                 BUG_ON(!npt_enabled);
 814                 load_pdptrs(vcpu, vcpu->arch.cr3);
 815                 break;
 816         default:
 817                 BUG();
 818         }
 819 }
 820
 821 static void svm_set_vintr(struct vcpu_svm *svm)
 822 {
 823         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 824 }
 825
 826 static void svm_clear_vintr(struct vcpu_svm *svm)
 827 {
 828         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 829 }
 830
 831 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 832 {
 833         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 834
 835         switch (seg) {
 836         case VCPU_SREG_CS: return &save->cs;
 837         case VCPU_SREG_DS: return &save->ds;
 838         case VCPU_SREG_ES: return &save->es;
 839         case VCPU_SREG_FS: return &save->fs;
 840         case VCPU_SREG_GS: return &save->gs;
 841         case VCPU_SREG_SS: return &save->ss;
 842         case VCPU_SREG_TR: return &save->tr;
 843         case VCPU_SREG_LDTR: return &save->ldtr;
 844         }
 845         BUG();
 846         return NULL;
 847 }
 848
 849 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 850 {
 851         struct vmcb_seg *s = svm_seg(vcpu, seg);
 852
 853         return s->base;
 854 }
 855
 856 static void svm_get_segment(struct kvm_vcpu *vcpu,
 857                             struct kvm_segment *var, int seg)
 858 {
 859         struct vmcb_seg *s = svm_seg(vcpu, seg);
 860
 861         var->base = s->base;
 862         var->limit = s->limit;
 863         var->selector = s->selector;
 864         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 865         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 866         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 867         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 868         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 869         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 870         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 871         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 872
 873         /* AMD's VMCB does not have an explicit unusable field, so emulate it
 874          * for cross vendor migration purposes by "not present"
 875          */
 876         var->unusable = !var->present || (var->type == 0);
 877
 878         switch (seg) {
 879         case VCPU_SREG_CS:
 880                 /*
 881                  * SVM always stores 0 for the 'G' bit in the CS selector in
 882                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 883                  * Intel's VMENTRY has a check on the 'G' bit.
 884                  */
 885                 var->g = s->limit > 0xfffff;
 886                 break;
 887         case VCPU_SREG_TR:
 888                 /*
 889                  * Work around a bug where the busy flag in the tr selector
 890                  * isn't exposed
 891                  */
 892                 var->type |= 0x2;
 893                 break;
 894         case VCPU_SREG_DS:
 895         case VCPU_SREG_ES:
 896         case VCPU_SREG_FS:
 897         case VCPU_SREG_GS:
 898                 /*
 899                  * The accessed bit must always be set in the segment
 900                  * descriptor cache, although it can be cleared in the
 901                  * descriptor, the cached bit always remains at 1. Since
 902                  * Intel has a check on this, set it here to support
 903                  * cross-vendor migration.
 904                  */
 905                 if (!var->unusable)
 906                         var->type |= 0x1;
 907                 break;
 908         case VCPU_SREG_SS:
 909                 /* On AMD CPUs sometimes the DB bit in the segment
 910                  * descriptor is left as 1, although the whole segment has
 911                  * been made unusable. Clear it here to pass an Intel VMX
 912                  * entry check when cross vendor migrating.
 913                  */
 914                 if (var->unusable)
 915                         var->db = 0;
 916                 break;
 917         }
 918 }
 919
 920 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 921 {
 922         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 923
 924         return save->cpl;
 925 }
 926
 927 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 928 {
 929         struct vcpu_svm *svm = to_svm(vcpu);
 930
 931         dt->limit = svm->vmcb->save.idtr.limit;
 932         dt->base = svm->vmcb->save.idtr.base;
 933 }
 934
 935 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 936 {
 937         struct vcpu_svm *svm = to_svm(vcpu);
 938
 939         svm->vmcb->save.idtr.limit = dt->limit;
 940         svm->vmcb->save.idtr.base = dt->base ;
 941 }
 942
 943 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 944 {
 945         struct vcpu_svm *svm = to_svm(vcpu);
 946
 947         dt->limit = svm->vmcb->save.gdtr.limit;
 948         dt->base = svm->vmcb->save.gdtr.base;
 949 }
 950
 951 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 952 {
 953         struct vcpu_svm *svm = to_svm(vcpu);
 954
 955         svm->vmcb->save.gdtr.limit = dt->limit;
 956         svm->vmcb->save.gdtr.base = dt->base ;
 957 }
 958
 959 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
 960 {
 961 }
 962
 963 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 964 {
 965 }
 966
 967 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 968 {
 969         struct vcpu_svm *svm = to_svm(vcpu);
 970
 971 #ifdef CONFIG_X86_64
 972         if (vcpu->arch.shadow_efer & EFER_LME) {
 973                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 974                         vcpu->arch.shadow_efer |= EFER_LMA;
 975                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 976                 }
 977
 978                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 979                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 980                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 981                 }
 982         }
 983 #endif
 984         if (npt_enabled)
 985                 goto set;
 986
 987         vcpu->arch.cr0 = cr0;
 988         cr0 |= X86_CR0_PG | X86_CR0_WP;
 989
 990         if (!vcpu->fpu_active)
 991                 cr0 |= X86_CR0_TS;
 992 set:
 993         /*
 994          * re-enable caching here because the QEMU bios
 995          * does not do it - this results in some delay at
 996          * reboot
 997          */
 998         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 999         svm->vmcb->save.cr0 = cr0;
1000 }
1001
1002 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1003 {
1004         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1005         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1006
1007         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1008                 force_new_asid(vcpu);
1009
1010         vcpu->arch.cr4 = cr4;
1011         if (!npt_enabled)
1012                 cr4 |= X86_CR4_PAE;
1013         cr4 |= host_cr4_mce;
1014         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1015 }
1016
1017 static void svm_set_segment(struct kvm_vcpu *vcpu,
1018                             struct kvm_segment *var, int seg)
1019 {
1020         struct vcpu_svm *svm = to_svm(vcpu);
1021         struct vmcb_seg *s = svm_seg(vcpu, seg);
1022
1023         s->base = var->base;
1024         s->limit = var->limit;
1025         s->selector = var->selector;
1026         if (var->unusable)
1027                 s->attrib = 0;
1028         else {
1029                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1030                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1031                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1032                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1033                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1034                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1035                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1036                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1037         }
1038         if (seg == VCPU_SREG_CS)
1039                 svm->vmcb->save.cpl
1040                         = (svm->vmcb->save.cs.attrib
1041                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1042
1043 }
1044
1045 static void update_db_intercept(struct kvm_vcpu *vcpu)
1046 {
1047         struct vcpu_svm *svm = to_svm(vcpu);
1048
1049         svm->vmcb->control.intercept_exceptions &=
1050                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1051
1052         if (svm->nmi_singlestep)
1053                 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1054
1055         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1056                 if (vcpu->guest_debug &
1057                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1058                         svm->vmcb->control.intercept_exceptions |=
1059                                 1 << DB_VECTOR;
1060                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1061                         svm->vmcb->control.intercept_exceptions |=
1062                                 1 << BP_VECTOR;
1063         } else
1064                 vcpu->guest_debug = 0;
1065 }
1066
1067 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1068 {
1069         struct vcpu_svm *svm = to_svm(vcpu);
1070
1071         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1072                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1073         else
1074                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1075
1076         update_db_intercept(vcpu);
1077 }
1078
1079 static void load_host_msrs(struct kvm_vcpu *vcpu)
1080 {
1081 #ifdef CONFIG_X86_64
1082         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1083 #endif
1084 }
1085
1086 static void save_host_msrs(struct kvm_vcpu *vcpu)
1087 {
1088 #ifdef CONFIG_X86_64
1089         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1090 #endif
1091 }
1092
1093 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1094 {
1095         if (sd->next_asid > sd->max_asid) {
1096                 ++sd->asid_generation;
1097                 sd->next_asid = 1;
1098                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1099         }
1100
1101         svm->asid_generation = sd->asid_generation;
1102         svm->vmcb->control.asid = sd->next_asid++;
1103 }
1104
1105 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1106 {
1107         struct vcpu_svm *svm = to_svm(vcpu);
1108         unsigned long val;
1109
1110         switch (dr) {
1111         case 0 ... 3:
1112                 val = vcpu->arch.db[dr];
1113                 break;
1114         case 6:
1115                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1116                         val = vcpu->arch.dr6;
1117                 else
1118                         val = svm->vmcb->save.dr6;
1119                 break;
1120         case 7:
1121                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1122                         val = vcpu->arch.dr7;
1123                 else
1124                         val = svm->vmcb->save.dr7;
1125                 break;
1126         default:
1127                 val = 0;
1128         }
1129
1130         return val;
1131 }
1132
1133 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1134                        int *exception)
1135 {
1136         struct vcpu_svm *svm = to_svm(vcpu);
1137
1138         *exception = 0;
1139
1140         switch (dr) {
1141         case 0 ... 3:
1142                 vcpu->arch.db[dr] = value;
1143                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1144                         vcpu->arch.eff_db[dr] = value;
1145                 return;
1146         case 4 ... 5:
1147                 if (vcpu->arch.cr4 & X86_CR4_DE)
1148                         *exception = UD_VECTOR;
1149                 return;
1150         case 6:
1151                 if (value & 0xffffffff00000000ULL) {
1152                         *exception = GP_VECTOR;
1153                         return;
1154                 }
1155                 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1156                 return;
1157         case 7:
1158                 if (value & 0xffffffff00000000ULL) {
1159                         *exception = GP_VECTOR;
1160                         return;
1161                 }
1162                 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1163                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1164                         svm->vmcb->save.dr7 = vcpu->arch.dr7;
1165                         vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1166                 }
1167                 return;
1168         default:
1169                 /* FIXME: Possible case? */
1170                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1171                        __func__, dr);
1172                 *exception = UD_VECTOR;
1173                 return;
1174         }
1175 }
1176
1177 static int pf_interception(struct vcpu_svm *svm)
1178 {
1179         u64 fault_address;
1180         u32 error_code;
1181
1182         fault_address  = svm->vmcb->control.exit_info_2;
1183         error_code = svm->vmcb->control.exit_info_1;
1184
1185         trace_kvm_page_fault(fault_address, error_code);
1186         if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1187                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1188         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1189 }
1190
1191 static int db_interception(struct vcpu_svm *svm)
1192 {
1193         struct kvm_run *kvm_run = svm->vcpu.run;
1194
1195         if (!(svm->vcpu.guest_debug &
1196               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1197                 !svm->nmi_singlestep) {
1198                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1199                 return 1;
1200         }
1201
1202         if (svm->nmi_singlestep) {
1203                 svm->nmi_singlestep = false;
1204                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1205                         svm->vmcb->save.rflags &=
1206                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1207                 update_db_intercept(&svm->vcpu);
1208         }
1209
1210         if (svm->vcpu.guest_debug &
1211             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1212                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1213                 kvm_run->debug.arch.pc =
1214                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1215                 kvm_run->debug.arch.exception = DB_VECTOR;
1216                 return 0;
1217         }
1218
1219         return 1;
1220 }
1221
1222 static int bp_interception(struct vcpu_svm *svm)
1223 {
1224         struct kvm_run *kvm_run = svm->vcpu.run;
1225
1226         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1227         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1228         kvm_run->debug.arch.exception = BP_VECTOR;
1229         return 0;
1230 }
1231
1232 static int ud_interception(struct vcpu_svm *svm)
1233 {
1234         int er;
1235
1236         er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1237         if (er != EMULATE_DONE)
1238                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1239         return 1;
1240 }
1241
1242 static int nm_interception(struct vcpu_svm *svm)
1243 {
1244         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1245         if (!kvm_read_cr0_bits(&svm->vcpu, X86_CR0_TS))
1246                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1247         else
1248                 svm->vmcb->save.cr0 |= X86_CR0_TS;
1249         svm->vcpu.fpu_active = 1;
1250
1251         return 1;
1252 }
1253
1254 static int mc_interception(struct vcpu_svm *svm)
1255 {
1256         /*
1257          * On an #MC intercept the MCE handler is not called automatically in
1258          * the host. So do it by hand here.
1259          */
1260         asm volatile (
1261                 "int $0x12\n");
1262         /* not sure if we ever come back to this point */
1263
1264         return 1;
1265 }
1266
1267 static int shutdown_interception(struct vcpu_svm *svm)
1268 {
1269         struct kvm_run *kvm_run = svm->vcpu.run;
1270
1271         /*
1272          * VMCB is undefined after a SHUTDOWN intercept
1273          * so reinitialize it.
1274          */
1275         clear_page(svm->vmcb);
1276         init_vmcb(svm);
1277
1278         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1279         return 0;
1280 }
1281
1282 static int io_interception(struct vcpu_svm *svm)
1283 {
1284         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1285         int size, in, string;
1286         unsigned port;
1287
1288         ++svm->vcpu.stat.io_exits;
1289
1290         svm->next_rip = svm->vmcb->control.exit_info_2;
1291
1292         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1293
1294         if (string) {
1295                 if (emulate_instruction(&svm->vcpu,
1296                                         0, 0, 0) == EMULATE_DO_MMIO)
1297                         return 0;
1298                 return 1;
1299         }
1300
1301         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1302         port = io_info >> 16;
1303         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1304
1305         skip_emulated_instruction(&svm->vcpu);
1306         return kvm_emulate_pio(&svm->vcpu, in, size, port);
1307 }
1308
1309 static int nmi_interception(struct vcpu_svm *svm)
1310 {
1311         return 1;
1312 }
1313
1314 static int intr_interception(struct vcpu_svm *svm)
1315 {
1316         ++svm->vcpu.stat.irq_exits;
1317         return 1;
1318 }
1319
1320 static int nop_on_interception(struct vcpu_svm *svm)
1321 {
1322         return 1;
1323 }
1324
1325 static int halt_interception(struct vcpu_svm *svm)
1326 {
1327         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1328         skip_emulated_instruction(&svm->vcpu);
1329         return kvm_emulate_halt(&svm->vcpu);
1330 }
1331
1332 static int vmmcall_interception(struct vcpu_svm *svm)
1333 {
1334         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1335         skip_emulated_instruction(&svm->vcpu);
1336         kvm_emulate_hypercall(&svm->vcpu);
1337         return 1;
1338 }
1339
1340 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1341 {
1342         if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1343             || !is_paging(&svm->vcpu)) {
1344                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1345                 return 1;
1346         }
1347
1348         if (svm->vmcb->save.cpl) {
1349                 kvm_inject_gp(&svm->vcpu, 0);
1350                 return 1;
1351         }
1352
1353        return 0;
1354 }
1355
1356 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1357                                       bool has_error_code, u32 error_code)
1358 {
1359         if (!is_nested(svm))
1360                 return 0;
1361
1362         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1363         svm->vmcb->control.exit_code_hi = 0;
1364         svm->vmcb->control.exit_info_1 = error_code;
1365         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1366
1367         return nested_svm_exit_handled(svm);
1368 }
1369
1370 static inline int nested_svm_intr(struct vcpu_svm *svm)
1371 {
1372         if (!is_nested(svm))
1373                 return 0;
1374
1375         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1376                 return 0;
1377
1378         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1379                 return 0;
1380
1381         svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1382
1383         if (svm->nested.intercept & 1ULL) {
1384                 /*
1385                  * The #vmexit can't be emulated here directly because this
1386                  * code path runs with irqs and preemtion disabled. A
1387                  * #vmexit emulation might sleep. Only signal request for
1388                  * the #vmexit here.
1389                  */
1390                 svm->nested.exit_required = true;
1391                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1392                 return 1;
1393         }
1394
1395         return 0;
1396 }
1397
1398 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
1399 {
1400         struct page *page;
1401
1402         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1403         if (is_error_page(page))
1404                 goto error;
1405
1406         return kmap_atomic(page, idx);
1407
1408 error:
1409         kvm_release_page_clean(page);
1410         kvm_inject_gp(&svm->vcpu, 0);
1411
1412         return NULL;
1413 }
1414
1415 static void nested_svm_unmap(void *addr, enum km_type idx)
1416 {
1417         struct page *page;
1418
1419         if (!addr)
1420                 return;
1421
1422         page = kmap_atomic_to_page(addr);
1423
1424         kunmap_atomic(addr, idx);
1425         kvm_release_page_dirty(page);
1426 }
1427
1428 static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1429 {
1430         u32 param = svm->vmcb->control.exit_info_1 & 1;
1431         u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1432         bool ret = false;
1433         u32 t0, t1;
1434         u8 *msrpm;
1435
1436         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1437                 return false;
1438
1439         msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1440
1441         if (!msrpm)
1442                 goto out;
1443
1444         switch (msr) {
1445         case 0 ... 0x1fff:
1446                 t0 = (msr * 2) % 8;
1447                 t1 = msr / 8;
1448                 break;
1449         case 0xc0000000 ... 0xc0001fff:
1450                 t0 = (8192 + msr - 0xc0000000) * 2;
1451                 t1 = (t0 / 8);
1452                 t0 %= 8;
1453                 break;
1454         case 0xc0010000 ... 0xc0011fff:
1455                 t0 = (16384 + msr - 0xc0010000) * 2;
1456                 t1 = (t0 / 8);
1457                 t0 %= 8;
1458                 break;
1459         default:
1460                 ret = true;
1461                 goto out;
1462         }
1463
1464         ret = msrpm[t1] & ((1 << param) << t0);
1465
1466 out:
1467         nested_svm_unmap(msrpm, KM_USER0);
1468
1469         return ret;
1470 }
1471
1472 static int nested_svm_exit_special(struct vcpu_svm *svm)
1473 {
1474         u32 exit_code = svm->vmcb->control.exit_code;
1475
1476         switch (exit_code) {
1477         case SVM_EXIT_INTR:
1478         case SVM_EXIT_NMI:
1479                 return NESTED_EXIT_HOST;
1480                 /* For now we are always handling NPFs when using them */
1481         case SVM_EXIT_NPF:
1482                 if (npt_enabled)
1483                         return NESTED_EXIT_HOST;
1484                 break;
1485         /* When we're shadowing, trap PFs */
1486         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1487                 if (!npt_enabled)
1488                         return NESTED_EXIT_HOST;
1489                 break;
1490         default:
1491                 break;
1492         }
1493
1494         return NESTED_EXIT_CONTINUE;
1495 }
1496
1497 /*
1498  * If this function returns true, this #vmexit was already handled
1499  */
1500 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1501 {
1502         u32 exit_code = svm->vmcb->control.exit_code;
1503         int vmexit = NESTED_EXIT_HOST;
1504
1505         switch (exit_code) {
1506         case SVM_EXIT_MSR:
1507                 vmexit = nested_svm_exit_handled_msr(svm);
1508                 break;
1509         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1510                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1511                 if (svm->nested.intercept_cr_read & cr_bits)
1512                         vmexit = NESTED_EXIT_DONE;
1513                 break;
1514         }
1515         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1516                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1517                 if (svm->nested.intercept_cr_write & cr_bits)
1518                         vmexit = NESTED_EXIT_DONE;
1519                 break;
1520         }
1521         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1522                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1523                 if (svm->nested.intercept_dr_read & dr_bits)
1524                         vmexit = NESTED_EXIT_DONE;
1525                 break;
1526         }
1527         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1528                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1529                 if (svm->nested.intercept_dr_write & dr_bits)
1530                         vmexit = NESTED_EXIT_DONE;
1531                 break;
1532         }
1533         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1534                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1535                 if (svm->nested.intercept_exceptions & excp_bits)
1536                         vmexit = NESTED_EXIT_DONE;
1537                 break;
1538         }
1539         default: {
1540                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1541                 if (svm->nested.intercept & exit_bits)
1542                         vmexit = NESTED_EXIT_DONE;
1543         }
1544         }
1545
1546         if (vmexit == NESTED_EXIT_DONE) {
1547                 nested_svm_vmexit(svm);
1548         }
1549
1550         return vmexit;
1551 }
1552
1553 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1554 {
1555         struct vmcb_control_area *dst  = &dst_vmcb->control;
1556         struct vmcb_control_area *from = &from_vmcb->control;
1557
1558         dst->intercept_cr_read    = from->intercept_cr_read;
1559         dst->intercept_cr_write   = from->intercept_cr_write;
1560         dst->intercept_dr_read    = from->intercept_dr_read;
1561         dst->intercept_dr_write   = from->intercept_dr_write;
1562         dst->intercept_exceptions = from->intercept_exceptions;
1563         dst->intercept            = from->intercept;
1564         dst->iopm_base_pa         = from->iopm_base_pa;
1565         dst->msrpm_base_pa        = from->msrpm_base_pa;
1566         dst->tsc_offset           = from->tsc_offset;
1567         dst->asid                 = from->asid;
1568         dst->tlb_ctl              = from->tlb_ctl;
1569         dst->int_ctl              = from->int_ctl;
1570         dst->int_vector           = from->int_vector;
1571         dst->int_state            = from->int_state;
1572         dst->exit_code            = from->exit_code;
1573         dst->exit_code_hi         = from->exit_code_hi;
1574         dst->exit_info_1          = from->exit_info_1;
1575         dst->exit_info_2          = from->exit_info_2;
1576         dst->exit_int_info        = from->exit_int_info;
1577         dst->exit_int_info_err    = from->exit_int_info_err;
1578         dst->nested_ctl           = from->nested_ctl;
1579         dst->event_inj            = from->event_inj;
1580         dst->event_inj_err        = from->event_inj_err;
1581         dst->nested_cr3           = from->nested_cr3;
1582         dst->lbr_ctl              = from->lbr_ctl;
1583 }
1584
1585 static int nested_svm_vmexit(struct vcpu_svm *svm)
1586 {
1587         struct vmcb *nested_vmcb;
1588         struct vmcb *hsave = svm->nested.hsave;
1589         struct vmcb *vmcb = svm->vmcb;
1590
1591         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1592                                        vmcb->control.exit_info_1,
1593                                        vmcb->control.exit_info_2,
1594                                        vmcb->control.exit_int_info,
1595                                        vmcb->control.exit_int_info_err);
1596
1597         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
1598         if (!nested_vmcb)
1599                 return 1;
1600
1601         /* Give the current vmcb to the guest */
1602         disable_gif(svm);
1603
1604         nested_vmcb->save.es     = vmcb->save.es;
1605         nested_vmcb->save.cs     = vmcb->save.cs;
1606         nested_vmcb->save.ss     = vmcb->save.ss;
1607         nested_vmcb->save.ds     = vmcb->save.ds;
1608         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
1609         nested_vmcb->save.idtr   = vmcb->save.idtr;
1610         if (npt_enabled)
1611                 nested_vmcb->save.cr3    = vmcb->save.cr3;
1612         nested_vmcb->save.cr2    = vmcb->save.cr2;
1613         nested_vmcb->save.rflags = vmcb->save.rflags;
1614         nested_vmcb->save.rip    = vmcb->save.rip;
1615         nested_vmcb->save.rsp    = vmcb->save.rsp;
1616         nested_vmcb->save.rax    = vmcb->save.rax;
1617         nested_vmcb->save.dr7    = vmcb->save.dr7;
1618         nested_vmcb->save.dr6    = vmcb->save.dr6;
1619         nested_vmcb->save.cpl    = vmcb->save.cpl;
1620
1621         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
1622         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
1623         nested_vmcb->control.int_state         = vmcb->control.int_state;
1624         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
1625         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
1626         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
1627         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
1628         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
1629         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1630
1631         /*
1632          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1633          * to make sure that we do not lose injected events. So check event_inj
1634          * here and copy it to exit_int_info if it is valid.
1635          * Exit_int_info and event_inj can't be both valid because the case
1636          * below only happens on a VMRUN instruction intercept which has
1637          * no valid exit_int_info set.
1638          */
1639         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1640                 struct vmcb_control_area *nc = &nested_vmcb->control;
1641
1642                 nc->exit_int_info     = vmcb->control.event_inj;
1643                 nc->exit_int_info_err = vmcb->control.event_inj_err;
1644         }
1645
1646         nested_vmcb->control.tlb_ctl           = 0;
1647         nested_vmcb->control.event_inj         = 0;
1648         nested_vmcb->control.event_inj_err     = 0;
1649
1650         /* We always set V_INTR_MASKING and remember the old value in hflags */
1651         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1652                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1653
1654         /* Restore the original control entries */
1655         copy_vmcb_control_area(vmcb, hsave);
1656
1657         kvm_clear_exception_queue(&svm->vcpu);
1658         kvm_clear_interrupt_queue(&svm->vcpu);
1659
1660         /* Restore selected save entries */
1661         svm->vmcb->save.es = hsave->save.es;
1662         svm->vmcb->save.cs = hsave->save.cs;
1663         svm->vmcb->save.ss = hsave->save.ss;
1664         svm->vmcb->save.ds = hsave->save.ds;
1665         svm->vmcb->save.gdtr = hsave->save.gdtr;
1666         svm->vmcb->save.idtr = hsave->save.idtr;
1667         svm->vmcb->save.rflags = hsave->save.rflags;
1668         svm_set_efer(&svm->vcpu, hsave->save.efer);
1669         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1670         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1671         if (npt_enabled) {
1672                 svm->vmcb->save.cr3 = hsave->save.cr3;
1673                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1674         } else {
1675                 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1676         }
1677         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1678         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1679         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1680         svm->vmcb->save.dr7 = 0;
1681         svm->vmcb->save.cpl = 0;
1682         svm->vmcb->control.exit_int_info = 0;
1683
1684         /* Exit nested SVM mode */
1685         svm->nested.vmcb = 0;
1686
1687         nested_svm_unmap(nested_vmcb, KM_USER0);
1688
1689         kvm_mmu_reset_context(&svm->vcpu);
1690         kvm_mmu_load(&svm->vcpu);
1691
1692         return 0;
1693 }
1694
1695 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1696 {
1697         u32 *nested_msrpm;
1698         int i;
1699
1700         nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1701         if (!nested_msrpm)
1702                 return false;
1703
1704         for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1705                 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1706
1707         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
1708
1709         nested_svm_unmap(nested_msrpm, KM_USER0);
1710
1711         return true;
1712 }
1713
1714 static bool nested_svm_vmrun(struct vcpu_svm *svm)
1715 {
1716         struct vmcb *nested_vmcb;
1717         struct vmcb *hsave = svm->nested.hsave;
1718         struct vmcb *vmcb = svm->vmcb;
1719
1720         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1721         if (!nested_vmcb)
1722                 return false;
1723
1724         /* nested_vmcb is our indicator if nested SVM is activated */
1725         svm->nested.vmcb = svm->vmcb->save.rax;
1726
1727         trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, svm->nested.vmcb,
1728                                nested_vmcb->save.rip,
1729                                nested_vmcb->control.int_ctl,
1730                                nested_vmcb->control.event_inj,
1731                                nested_vmcb->control.nested_ctl);
1732
1733         /* Clear internal status */
1734         kvm_clear_exception_queue(&svm->vcpu);
1735         kvm_clear_interrupt_queue(&svm->vcpu);
1736
1737         /* Save the old vmcb, so we don't need to pick what we save, but
1738            can restore everything when a VMEXIT occurs */
1739         hsave->save.es     = vmcb->save.es;
1740         hsave->save.cs     = vmcb->save.cs;
1741         hsave->save.ss     = vmcb->save.ss;
1742         hsave->save.ds     = vmcb->save.ds;
1743         hsave->save.gdtr   = vmcb->save.gdtr;
1744         hsave->save.idtr   = vmcb->save.idtr;
1745         hsave->save.efer   = svm->vcpu.arch.shadow_efer;
1746         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
1747         hsave->save.cr4    = svm->vcpu.arch.cr4;
1748         hsave->save.rflags = vmcb->save.rflags;
1749         hsave->save.rip    = svm->next_rip;
1750         hsave->save.rsp    = vmcb->save.rsp;
1751         hsave->save.rax    = vmcb->save.rax;
1752         if (npt_enabled)
1753                 hsave->save.cr3    = vmcb->save.cr3;
1754         else
1755                 hsave->save.cr3    = svm->vcpu.arch.cr3;
1756
1757         copy_vmcb_control_area(hsave, vmcb);
1758
1759         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1760                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1761         else
1762                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1763
1764         /* Load the nested guest state */
1765         svm->vmcb->save.es = nested_vmcb->save.es;
1766         svm->vmcb->save.cs = nested_vmcb->save.cs;
1767         svm->vmcb->save.ss = nested_vmcb->save.ss;
1768         svm->vmcb->save.ds = nested_vmcb->save.ds;
1769         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1770         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1771         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1772         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1773         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1774         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1775         if (npt_enabled) {
1776                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1777                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1778         } else {
1779                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1780                 kvm_mmu_reset_context(&svm->vcpu);
1781         }
1782         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
1783         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1784         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1785         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1786         /* In case we don't even reach vcpu_run, the fields are not updated */
1787         svm->vmcb->save.rax = nested_vmcb->save.rax;
1788         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1789         svm->vmcb->save.rip = nested_vmcb->save.rip;
1790         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1791         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1792         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1793
1794         /* We don't want a nested guest to be more powerful than the guest,
1795            so all intercepts are ORed */
1796         svm->vmcb->control.intercept_cr_read |=
1797                 nested_vmcb->control.intercept_cr_read;
1798         svm->vmcb->control.intercept_cr_write |=
1799                 nested_vmcb->control.intercept_cr_write;
1800         svm->vmcb->control.intercept_dr_read |=
1801                 nested_vmcb->control.intercept_dr_read;
1802         svm->vmcb->control.intercept_dr_write |=
1803                 nested_vmcb->control.intercept_dr_write;
1804         svm->vmcb->control.intercept_exceptions |=
1805                 nested_vmcb->control.intercept_exceptions;
1806
1807         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1808
1809         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1810
1811         /* cache intercepts */
1812         svm->nested.intercept_cr_read    = nested_vmcb->control.intercept_cr_read;
1813         svm->nested.intercept_cr_write   = nested_vmcb->control.intercept_cr_write;
1814         svm->nested.intercept_dr_read    = nested_vmcb->control.intercept_dr_read;
1815         svm->nested.intercept_dr_write   = nested_vmcb->control.intercept_dr_write;
1816         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1817         svm->nested.intercept            = nested_vmcb->control.intercept;
1818
1819         force_new_asid(&svm->vcpu);
1820         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1821         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1822                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1823         else
1824                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1825
1826         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1827         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1828         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1829         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1830         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1831
1832         nested_svm_unmap(nested_vmcb, KM_USER0);
1833
1834         enable_gif(svm);
1835
1836         return true;
1837 }
1838
1839 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1840 {
1841         to_vmcb->save.fs = from_vmcb->save.fs;
1842         to_vmcb->save.gs = from_vmcb->save.gs;
1843         to_vmcb->save.tr = from_vmcb->save.tr;
1844         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1845         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1846         to_vmcb->save.star = from_vmcb->save.star;
1847         to_vmcb->save.lstar = from_vmcb->save.lstar;
1848         to_vmcb->save.cstar = from_vmcb->save.cstar;
1849         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1850         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1851         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1852         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1853 }
1854
1855 static int vmload_interception(struct vcpu_svm *svm)
1856 {
1857         struct vmcb *nested_vmcb;
1858
1859         if (nested_svm_check_permissions(svm))
1860                 return 1;
1861
1862         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1863         skip_emulated_instruction(&svm->vcpu);
1864
1865         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1866         if (!nested_vmcb)
1867                 return 1;
1868
1869         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1870         nested_svm_unmap(nested_vmcb, KM_USER0);
1871
1872         return 1;
1873 }
1874
1875 static int vmsave_interception(struct vcpu_svm *svm)
1876 {
1877         struct vmcb *nested_vmcb;
1878
1879         if (nested_svm_check_permissions(svm))
1880                 return 1;
1881
1882         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1883         skip_emulated_instruction(&svm->vcpu);
1884
1885         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1886         if (!nested_vmcb)
1887                 return 1;
1888
1889         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1890         nested_svm_unmap(nested_vmcb, KM_USER0);
1891
1892         return 1;
1893 }
1894
1895 static int vmrun_interception(struct vcpu_svm *svm)
1896 {
1897         if (nested_svm_check_permissions(svm))
1898                 return 1;
1899
1900         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1901         skip_emulated_instruction(&svm->vcpu);
1902
1903         if (!nested_svm_vmrun(svm))
1904                 return 1;
1905
1906         if (!nested_svm_vmrun_msrpm(svm))
1907                 goto failed;
1908
1909         return 1;
1910
1911 failed:
1912
1913         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
1914         svm->vmcb->control.exit_code_hi = 0;
1915         svm->vmcb->control.exit_info_1  = 0;
1916         svm->vmcb->control.exit_info_2  = 0;
1917
1918         nested_svm_vmexit(svm);
1919
1920         return 1;
1921 }
1922
1923 static int stgi_interception(struct vcpu_svm *svm)
1924 {
1925         if (nested_svm_check_permissions(svm))
1926                 return 1;
1927
1928         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1929         skip_emulated_instruction(&svm->vcpu);
1930
1931         enable_gif(svm);
1932
1933         return 1;
1934 }
1935
1936 static int clgi_interception(struct vcpu_svm *svm)
1937 {
1938         if (nested_svm_check_permissions(svm))
1939                 return 1;
1940
1941         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1942         skip_emulated_instruction(&svm->vcpu);
1943
1944         disable_gif(svm);
1945
1946         /* After a CLGI no interrupts should come */
1947         svm_clear_vintr(svm);
1948         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1949
1950         return 1;
1951 }
1952
1953 static int invlpga_interception(struct vcpu_svm *svm)
1954 {
1955         struct kvm_vcpu *vcpu = &svm->vcpu;
1956
1957         trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
1958                           vcpu->arch.regs[VCPU_REGS_RAX]);
1959
1960         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1961         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1962
1963         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1964         skip_emulated_instruction(&svm->vcpu);
1965         return 1;
1966 }
1967
1968 static int skinit_interception(struct vcpu_svm *svm)
1969 {
1970         trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
1971
1972         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1973         return 1;
1974 }
1975
1976 static int invalid_op_interception(struct vcpu_svm *svm)
1977 {
1978         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1979         return 1;
1980 }
1981
1982 static int task_switch_interception(struct vcpu_svm *svm)
1983 {
1984         u16 tss_selector;
1985         int reason;
1986         int int_type = svm->vmcb->control.exit_int_info &
1987                 SVM_EXITINTINFO_TYPE_MASK;
1988         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
1989         uint32_t type =
1990                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
1991         uint32_t idt_v =
1992                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
1993
1994         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1995
1996         if (svm->vmcb->control.exit_info_2 &
1997             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1998                 reason = TASK_SWITCH_IRET;
1999         else if (svm->vmcb->control.exit_info_2 &
2000                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2001                 reason = TASK_SWITCH_JMP;
2002         else if (idt_v)
2003                 reason = TASK_SWITCH_GATE;
2004         else
2005                 reason = TASK_SWITCH_CALL;
2006
2007         if (reason == TASK_SWITCH_GATE) {
2008                 switch (type) {
2009                 case SVM_EXITINTINFO_TYPE_NMI:
2010                         svm->vcpu.arch.nmi_injected = false;
2011                         break;
2012                 case SVM_EXITINTINFO_TYPE_EXEPT:
2013                         kvm_clear_exception_queue(&svm->vcpu);
2014                         break;
2015                 case SVM_EXITINTINFO_TYPE_INTR:
2016                         kvm_clear_interrupt_queue(&svm->vcpu);
2017                         break;
2018                 default:
2019                         break;
2020                 }
2021         }
2022
2023         if (reason != TASK_SWITCH_GATE ||
2024             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2025             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2026              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2027                 skip_emulated_instruction(&svm->vcpu);
2028
2029         return kvm_task_switch(&svm->vcpu, tss_selector, reason);
2030 }
2031
2032 static int cpuid_interception(struct vcpu_svm *svm)
2033 {
2034         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2035         kvm_emulate_cpuid(&svm->vcpu);
2036         return 1;
2037 }
2038
2039 static int iret_interception(struct vcpu_svm *svm)
2040 {
2041         ++svm->vcpu.stat.nmi_window_exits;
2042         svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2043         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2044         return 1;
2045 }
2046
2047 static int invlpg_interception(struct vcpu_svm *svm)
2048 {
2049         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2050                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2051         return 1;
2052 }
2053
2054 static int emulate_on_interception(struct vcpu_svm *svm)
2055 {
2056         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2057                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2058         return 1;
2059 }
2060
2061 static int cr8_write_interception(struct vcpu_svm *svm)
2062 {
2063         struct kvm_run *kvm_run = svm->vcpu.run;
2064
2065         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2066         /* instruction emulation calls kvm_set_cr8() */
2067         emulate_instruction(&svm->vcpu, 0, 0, 0);
2068         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2069                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2070                 return 1;
2071         }
2072         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2073                 return 1;
2074         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2075         return 0;
2076 }
2077
2078 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2079 {
2080         struct vcpu_svm *svm = to_svm(vcpu);
2081
2082         switch (ecx) {
2083         case MSR_IA32_TSC: {
2084                 u64 tsc_offset;
2085
2086                 if (is_nested(svm))
2087                         tsc_offset = svm->nested.hsave->control.tsc_offset;
2088                 else
2089                         tsc_offset = svm->vmcb->control.tsc_offset;
2090
2091                 *data = tsc_offset + native_read_tsc();
2092                 break;
2093         }
2094         case MSR_K6_STAR:
2095                 *data = svm->vmcb->save.star;
2096                 break;
2097 #ifdef CONFIG_X86_64
2098         case MSR_LSTAR:
2099                 *data = svm->vmcb->save.lstar;
2100                 break;
2101         case MSR_CSTAR:
2102                 *data = svm->vmcb->save.cstar;
2103                 break;
2104         case MSR_KERNEL_GS_BASE:
2105                 *data = svm->vmcb->save.kernel_gs_base;
2106                 break;
2107         case MSR_SYSCALL_MASK:
2108                 *data = svm->vmcb->save.sfmask;
2109                 break;
2110 #endif
2111         case MSR_IA32_SYSENTER_CS:
2112                 *data = svm->vmcb->save.sysenter_cs;
2113                 break;
2114         case MSR_IA32_SYSENTER_EIP:
2115                 *data = svm->sysenter_eip;
2116                 break;
2117         case MSR_IA32_SYSENTER_ESP:
2118                 *data = svm->sysenter_esp;
2119                 break;
2120         /* Nobody will change the following 5 values in the VMCB so
2121            we can safely return them on rdmsr. They will always be 0
2122            until LBRV is implemented. */
2123         case MSR_IA32_DEBUGCTLMSR:
2124                 *data = svm->vmcb->save.dbgctl;
2125                 break;
2126         case MSR_IA32_LASTBRANCHFROMIP:
2127                 *data = svm->vmcb->save.br_from;
2128                 break;
2129         case MSR_IA32_LASTBRANCHTOIP:
2130                 *data = svm->vmcb->save.br_to;
2131                 break;
2132         case MSR_IA32_LASTINTFROMIP:
2133                 *data = svm->vmcb->save.last_excp_from;
2134                 break;
2135         case MSR_IA32_LASTINTTOIP:
2136                 *data = svm->vmcb->save.last_excp_to;
2137                 break;
2138         case MSR_VM_HSAVE_PA:
2139                 *data = svm->nested.hsave_msr;
2140                 break;
2141         case MSR_VM_CR:
2142                 *data = 0;
2143                 break;
2144         case MSR_IA32_UCODE_REV:
2145                 *data = 0x01000065;
2146                 break;
2147         default:
2148                 return kvm_get_msr_common(vcpu, ecx, data);
2149         }
2150         return 0;
2151 }
2152
2153 static int rdmsr_interception(struct vcpu_svm *svm)
2154 {
2155         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2156         u64 data;
2157
2158         if (svm_get_msr(&svm->vcpu, ecx, &data))
2159                 kvm_inject_gp(&svm->vcpu, 0);
2160         else {
2161                 trace_kvm_msr_read(ecx, data);
2162
2163                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2164                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2165                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2166                 skip_emulated_instruction(&svm->vcpu);
2167         }
2168         return 1;
2169 }
2170
2171 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2172 {
2173         struct vcpu_svm *svm = to_svm(vcpu);
2174
2175         switch (ecx) {
2176         case MSR_IA32_TSC: {
2177                 u64 tsc_offset = data - native_read_tsc();
2178                 u64 g_tsc_offset = 0;
2179
2180                 if (is_nested(svm)) {
2181                         g_tsc_offset = svm->vmcb->control.tsc_offset -
2182                                        svm->nested.hsave->control.tsc_offset;
2183                         svm->nested.hsave->control.tsc_offset = tsc_offset;
2184                 }
2185
2186                 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2187
2188                 break;
2189         }
2190         case MSR_K6_STAR:
2191                 svm->vmcb->save.star = data;
2192                 break;
2193 #ifdef CONFIG_X86_64
2194         case MSR_LSTAR:
2195                 svm->vmcb->save.lstar = data;
2196                 break;
2197         case MSR_CSTAR:
2198                 svm->vmcb->save.cstar = data;
2199                 break;
2200         case MSR_KERNEL_GS_BASE:
2201                 svm->vmcb->save.kernel_gs_base = data;
2202                 break;
2203         case MSR_SYSCALL_MASK:
2204                 svm->vmcb->save.sfmask = data;
2205                 break;
2206 #endif
2207         case MSR_IA32_SYSENTER_CS:
2208                 svm->vmcb->save.sysenter_cs = data;
2209                 break;
2210         case MSR_IA32_SYSENTER_EIP:
2211                 svm->sysenter_eip = data;
2212                 svm->vmcb->save.sysenter_eip = data;
2213                 break;
2214         case MSR_IA32_SYSENTER_ESP:
2215                 svm->sysenter_esp = data;
2216                 svm->vmcb->save.sysenter_esp = data;
2217                 break;
2218         case MSR_IA32_DEBUGCTLMSR:
2219                 if (!svm_has(SVM_FEATURE_LBRV)) {
2220                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2221                                         __func__, data);
2222                         break;
2223                 }
2224                 if (data & DEBUGCTL_RESERVED_BITS)
2225                         return 1;
2226
2227                 svm->vmcb->save.dbgctl = data;
2228                 if (data & (1ULL<<0))
2229                         svm_enable_lbrv(svm);
2230                 else
2231                         svm_disable_lbrv(svm);
2232                 break;
2233         case MSR_VM_HSAVE_PA:
2234                 svm->nested.hsave_msr = data;
2235                 break;
2236         case MSR_VM_CR:
2237         case MSR_VM_IGNNE:
2238                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2239                 break;
2240         default:
2241                 return kvm_set_msr_common(vcpu, ecx, data);
2242         }
2243         return 0;
2244 }
2245
2246 static int wrmsr_interception(struct vcpu_svm *svm)
2247 {
2248         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2249         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2250                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2251
2252         trace_kvm_msr_write(ecx, data);
2253
2254         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2255         if (svm_set_msr(&svm->vcpu, ecx, data))
2256                 kvm_inject_gp(&svm->vcpu, 0);
2257         else
2258                 skip_emulated_instruction(&svm->vcpu);
2259         return 1;
2260 }
2261
2262 static int msr_interception(struct vcpu_svm *svm)
2263 {
2264         if (svm->vmcb->control.exit_info_1)
2265                 return wrmsr_interception(svm);
2266         else
2267                 return rdmsr_interception(svm);
2268 }
2269
2270 static int interrupt_window_interception(struct vcpu_svm *svm)
2271 {
2272         struct kvm_run *kvm_run = svm->vcpu.run;
2273
2274         svm_clear_vintr(svm);
2275         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2276         /*
2277          * If the user space waits to inject interrupts, exit as soon as
2278          * possible
2279          */
2280         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2281             kvm_run->request_interrupt_window &&
2282             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2283                 ++svm->vcpu.stat.irq_window_exits;
2284                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2285                 return 0;
2286         }
2287
2288         return 1;
2289 }
2290
2291 static int pause_interception(struct vcpu_svm *svm)
2292 {
2293         kvm_vcpu_on_spin(&(svm->vcpu));
2294         return 1;
2295 }
2296
2297 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2298         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2299         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2300         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2301         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2302         /* for now: */
2303         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2304         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2305         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2306         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2307         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2308         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2309         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2310         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2311         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2312         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2313         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2314         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2315         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2316         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2317         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2318         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2319         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2320         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2321         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2322         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2323         [SVM_EXIT_INTR]                         = intr_interception,
2324         [SVM_EXIT_NMI]                          = nmi_interception,
2325         [SVM_EXIT_SMI]                          = nop_on_interception,
2326         [SVM_EXIT_INIT]                         = nop_on_interception,
2327         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2328         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
2329         [SVM_EXIT_CPUID]                        = cpuid_interception,
2330         [SVM_EXIT_IRET]                         = iret_interception,
2331         [SVM_EXIT_INVD]                         = emulate_on_interception,
2332         [SVM_EXIT_PAUSE]                        = pause_interception,
2333         [SVM_EXIT_HLT]                          = halt_interception,
2334         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2335         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2336         [SVM_EXIT_IOIO]                         = io_interception,
2337         [SVM_EXIT_MSR]                          = msr_interception,
2338         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2339         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2340         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2341         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2342         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2343         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2344         [SVM_EXIT_STGI]                         = stgi_interception,
2345         [SVM_EXIT_CLGI]                         = clgi_interception,
2346         [SVM_EXIT_SKINIT]                       = skinit_interception,
2347         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2348         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2349         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2350         [SVM_EXIT_NPF]                          = pf_interception,
2351 };
2352
2353 static int handle_exit(struct kvm_vcpu *vcpu)
2354 {
2355         struct vcpu_svm *svm = to_svm(vcpu);
2356         struct kvm_run *kvm_run = vcpu->run;
2357         u32 exit_code = svm->vmcb->control.exit_code;
2358
2359         trace_kvm_exit(exit_code, svm->vmcb->save.rip);
2360
2361         if (unlikely(svm->nested.exit_required)) {
2362                 nested_svm_vmexit(svm);
2363                 svm->nested.exit_required = false;
2364
2365                 return 1;
2366         }
2367
2368         if (is_nested(svm)) {
2369                 int vmexit;
2370
2371                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2372                                         svm->vmcb->control.exit_info_1,
2373                                         svm->vmcb->control.exit_info_2,
2374                                         svm->vmcb->control.exit_int_info,
2375                                         svm->vmcb->control.exit_int_info_err);
2376
2377                 vmexit = nested_svm_exit_special(svm);
2378
2379                 if (vmexit == NESTED_EXIT_CONTINUE)
2380                         vmexit = nested_svm_exit_handled(svm);
2381
2382                 if (vmexit == NESTED_EXIT_DONE)
2383                         return 1;
2384         }
2385
2386         svm_complete_interrupts(svm);
2387
2388         if (npt_enabled) {
2389                 int mmu_reload = 0;
2390                 if ((kvm_read_cr0_bits(vcpu, X86_CR0_PG) ^ svm->vmcb->save.cr0)
2391                     & X86_CR0_PG) {
2392                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2393                         mmu_reload = 1;
2394                 }
2395                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2396                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2397                 if (mmu_reload) {
2398                         kvm_mmu_reset_context(vcpu);
2399                         kvm_mmu_load(vcpu);
2400                 }
2401         }
2402
2403
2404         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2405                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2406                 kvm_run->fail_entry.hardware_entry_failure_reason
2407                         = svm->vmcb->control.exit_code;
2408                 return 0;
2409         }
2410
2411         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2412             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2413             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2414                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2415                        "exit_code 0x%x\n",
2416                        __func__, svm->vmcb->control.exit_int_info,
2417                        exit_code);
2418
2419         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2420             || !svm_exit_handlers[exit_code]) {
2421                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2422                 kvm_run->hw.hardware_exit_reason = exit_code;
2423                 return 0;
2424         }
2425
2426         return svm_exit_handlers[exit_code](svm);
2427 }
2428
2429 static void reload_tss(struct kvm_vcpu *vcpu)
2430 {
2431         int cpu = raw_smp_processor_id();
2432
2433         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2434         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
2435         load_TR_desc();
2436 }
2437
2438 static void pre_svm_run(struct vcpu_svm *svm)
2439 {
2440         int cpu = raw_smp_processor_id();
2441
2442         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2443
2444         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2445         /* FIXME: handle wraparound of asid_generation */
2446         if (svm->asid_generation != sd->asid_generation)
2447                 new_asid(svm, sd);
2448 }
2449
2450 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2451 {
2452         struct vcpu_svm *svm = to_svm(vcpu);
2453
2454         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2455         vcpu->arch.hflags |= HF_NMI_MASK;
2456         svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2457         ++vcpu->stat.nmi_injections;
2458 }
2459
2460 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2461 {
2462         struct vmcb_control_area *control;
2463
2464         trace_kvm_inj_virq(irq);
2465
2466         ++svm->vcpu.stat.irq_injections;
2467         control = &svm->vmcb->control;
2468         control->int_vector = irq;
2469         control->int_ctl &= ~V_INTR_PRIO_MASK;
2470         control->int_ctl |= V_IRQ_MASK |
2471                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2472 }
2473
2474 static void svm_set_irq(struct kvm_vcpu *vcpu)
2475 {
2476         struct vcpu_svm *svm = to_svm(vcpu);
2477
2478         BUG_ON(!(gif_set(svm)));
2479
2480         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2481                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2482 }
2483
2484 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2485 {
2486         struct vcpu_svm *svm = to_svm(vcpu);
2487
2488         if (irr == -1)
2489                 return;
2490
2491         if (tpr >= irr)
2492                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2493 }
2494
2495 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2496 {
2497         struct vcpu_svm *svm = to_svm(vcpu);
2498         struct vmcb *vmcb = svm->vmcb;
2499         return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2500                 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2501 }
2502
2503 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2504 {
2505         struct vcpu_svm *svm = to_svm(vcpu);
2506
2507         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2508 }
2509
2510 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2511 {
2512         struct vcpu_svm *svm = to_svm(vcpu);
2513
2514         if (masked) {
2515                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2516                 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2517         } else {
2518                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2519                 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2520         }
2521 }
2522
2523 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2524 {
2525         struct vcpu_svm *svm = to_svm(vcpu);
2526         struct vmcb *vmcb = svm->vmcb;
2527         int ret;
2528
2529         if (!gif_set(svm) ||
2530              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2531                 return 0;
2532
2533         ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2534
2535         if (is_nested(svm))
2536                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2537
2538         return ret;
2539 }
2540
2541 static void enable_irq_window(struct kvm_vcpu *vcpu)
2542 {
2543         struct vcpu_svm *svm = to_svm(vcpu);
2544
2545         nested_svm_intr(svm);
2546
2547         /* In case GIF=0 we can't rely on the CPU to tell us when
2548          * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2549          * The next time we get that intercept, this function will be
2550          * called again though and we'll get the vintr intercept. */
2551         if (gif_set(svm)) {
2552                 svm_set_vintr(svm);
2553                 svm_inject_irq(svm, 0x0);
2554         }
2555 }
2556
2557 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2558 {
2559         struct vcpu_svm *svm = to_svm(vcpu);
2560
2561         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2562             == HF_NMI_MASK)
2563                 return; /* IRET will cause a vm exit */
2564
2565         /* Something prevents NMI from been injected. Single step over
2566            possible problem (IRET or exception injection or interrupt
2567            shadow) */
2568         svm->nmi_singlestep = true;
2569         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2570         update_db_intercept(vcpu);
2571 }
2572
2573 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2574 {
2575         return 0;
2576 }
2577
2578 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2579 {
2580         force_new_asid(vcpu);
2581 }
2582
2583 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2584 {
2585         if (npt_enabled)
2586                 vcpu->fpu_active = 1;
2587 }
2588
2589 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2590 {
2591         struct vcpu_svm *svm = to_svm(vcpu);
2592
2593         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2594                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2595                 kvm_set_cr8(vcpu, cr8);
2596         }
2597 }
2598
2599 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2600 {
2601         struct vcpu_svm *svm = to_svm(vcpu);
2602         u64 cr8;
2603
2604         cr8 = kvm_get_cr8(vcpu);
2605         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2606         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2607 }
2608
2609 static void svm_complete_interrupts(struct vcpu_svm *svm)
2610 {
2611         u8 vector;
2612         int type;
2613         u32 exitintinfo = svm->vmcb->control.exit_int_info;
2614
2615         if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2616                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2617
2618         svm->vcpu.arch.nmi_injected = false;
2619         kvm_clear_exception_queue(&svm->vcpu);
2620         kvm_clear_interrupt_queue(&svm->vcpu);
2621
2622         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2623                 return;
2624
2625         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2626         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2627
2628         switch (type) {
2629         case SVM_EXITINTINFO_TYPE_NMI:
2630                 svm->vcpu.arch.nmi_injected = true;
2631                 break;
2632         case SVM_EXITINTINFO_TYPE_EXEPT:
2633                 /* In case of software exception do not reinject an exception
2634                    vector, but re-execute and instruction instead */
2635                 if (is_nested(svm))
2636                         break;
2637                 if (kvm_exception_is_soft(vector))
2638                         break;
2639                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2640                         u32 err = svm->vmcb->control.exit_int_info_err;
2641                         kvm_queue_exception_e(&svm->vcpu, vector, err);
2642
2643                 } else
2644                         kvm_queue_exception(&svm->vcpu, vector);
2645                 break;
2646         case SVM_EXITINTINFO_TYPE_INTR:
2647                 kvm_queue_interrupt(&svm->vcpu, vector, false);
2648                 break;
2649         default:
2650                 break;
2651         }
2652 }
2653
2654 #ifdef CONFIG_X86_64
2655 #define R "r"
2656 #else
2657 #define R "e"
2658 #endif
2659
2660 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
2661 {
2662         struct vcpu_svm *svm = to_svm(vcpu);
2663         u16 fs_selector;
2664         u16 gs_selector;
2665         u16 ldt_selector;
2666
2667         /*
2668          * A vmexit emulation is required before the vcpu can be executed
2669          * again.
2670          */
2671         if (unlikely(svm->nested.exit_required))
2672                 return;
2673
2674         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2675         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2676         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2677
2678         pre_svm_run(svm);
2679
2680         sync_lapic_to_cr8(vcpu);
2681
2682         save_host_msrs(vcpu);
2683         fs_selector = kvm_read_fs();
2684         gs_selector = kvm_read_gs();
2685         ldt_selector = kvm_read_ldt();
2686         svm->vmcb->save.cr2 = vcpu->arch.cr2;
2687         /* required for live migration with NPT */
2688         if (npt_enabled)
2689                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2690
2691         clgi();
2692
2693         local_irq_enable();
2694
2695         asm volatile (
2696                 "push %%"R"bp; \n\t"
2697                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2698                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2699                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2700                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2701                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2702                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2703 #ifdef CONFIG_X86_64
2704                 "mov %c[r8](%[svm]),  %%r8  \n\t"
2705                 "mov %c[r9](%[svm]),  %%r9  \n\t"
2706                 "mov %c[r10](%[svm]), %%r10 \n\t"
2707                 "mov %c[r11](%[svm]), %%r11 \n\t"
2708                 "mov %c[r12](%[svm]), %%r12 \n\t"
2709                 "mov %c[r13](%[svm]), %%r13 \n\t"
2710                 "mov %c[r14](%[svm]), %%r14 \n\t"
2711                 "mov %c[r15](%[svm]), %%r15 \n\t"
2712 #endif
2713
2714                 /* Enter guest mode */
2715                 "push %%"R"ax \n\t"
2716                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2717                 __ex(SVM_VMLOAD) "\n\t"
2718                 __ex(SVM_VMRUN) "\n\t"
2719                 __ex(SVM_VMSAVE) "\n\t"
2720                 "pop %%"R"ax \n\t"
2721
2722                 /* Save guest registers, load host registers */
2723                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2724                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2725                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2726                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2727                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2728                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2729 #ifdef CONFIG_X86_64
2730                 "mov %%r8,  %c[r8](%[svm]) \n\t"
2731                 "mov %%r9,  %c[r9](%[svm]) \n\t"
2732                 "mov %%r10, %c[r10](%[svm]) \n\t"
2733                 "mov %%r11, %c[r11](%[svm]) \n\t"
2734                 "mov %%r12, %c[r12](%[svm]) \n\t"
2735                 "mov %%r13, %c[r13](%[svm]) \n\t"
2736                 "mov %%r14, %c[r14](%[svm]) \n\t"
2737                 "mov %%r15, %c[r15](%[svm]) \n\t"
2738 #endif
2739                 "pop %%"R"bp"
2740                 :
2741                 : [svm]"a"(svm),
2742                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2743                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2744                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2745                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2746                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2747                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2748                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2749 #ifdef CONFIG_X86_64
2750                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2751                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2752                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2753                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2754                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2755                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2756                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2757                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2758 #endif
2759                 : "cc", "memory"
2760                 , R"bx", R"cx", R"dx", R"si", R"di"
2761 #ifdef CONFIG_X86_64
2762                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2763 #endif
2764                 );
2765
2766         vcpu->arch.cr2 = svm->vmcb->save.cr2;
2767         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2768         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2769         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2770
2771         kvm_load_fs(fs_selector);
2772         kvm_load_gs(gs_selector);
2773         kvm_load_ldt(ldt_selector);
2774         load_host_msrs(vcpu);
2775
2776         reload_tss(vcpu);
2777
2778         local_irq_disable();
2779
2780         stgi();
2781
2782         sync_cr8_to_lapic(vcpu);
2783
2784         svm->next_rip = 0;
2785
2786         if (npt_enabled) {
2787                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2788                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2789         }
2790 }
2791
2792 #undef R
2793
2794 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2795 {
2796         struct vcpu_svm *svm = to_svm(vcpu);
2797
2798         if (npt_enabled) {
2799                 svm->vmcb->control.nested_cr3 = root;
2800                 force_new_asid(vcpu);
2801                 return;
2802         }
2803
2804         svm->vmcb->save.cr3 = root;
2805         force_new_asid(vcpu);
2806 }
2807
2808 static int is_disabled(void)
2809 {
2810         u64 vm_cr;
2811
2812         rdmsrl(MSR_VM_CR, vm_cr);
2813         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2814                 return 1;
2815
2816         return 0;
2817 }
2818
2819 static void
2820 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2821 {
2822         /*
2823          * Patch in the VMMCALL instruction:
2824          */
2825         hypercall[0] = 0x0f;
2826         hypercall[1] = 0x01;
2827         hypercall[2] = 0xd9;
2828 }
2829
2830 static void svm_check_processor_compat(void *rtn)
2831 {
2832         *(int *)rtn = 0;
2833 }
2834
2835 static bool svm_cpu_has_accelerated_tpr(void)
2836 {
2837         return false;
2838 }
2839
2840 static int get_npt_level(void)
2841 {
2842 #ifdef CONFIG_X86_64
2843         return PT64_ROOT_LEVEL;
2844 #else
2845         return PT32E_ROOT_LEVEL;
2846 #endif
2847 }
2848
2849 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
2850 {
2851         return 0;
2852 }
2853
2854 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
2855 {
2856 }
2857
2858 static const struct trace_print_flags svm_exit_reasons_str[] = {
2859         { SVM_EXIT_READ_CR0,                    "read_cr0" },
2860         { SVM_EXIT_READ_CR3,                    "read_cr3" },
2861         { SVM_EXIT_READ_CR4,                    "read_cr4" },
2862         { SVM_EXIT_READ_CR8,                    "read_cr8" },
2863         { SVM_EXIT_WRITE_CR0,                   "write_cr0" },
2864         { SVM_EXIT_WRITE_CR3,                   "write_cr3" },
2865         { SVM_EXIT_WRITE_CR4,                   "write_cr4" },
2866         { SVM_EXIT_WRITE_CR8,                   "write_cr8" },
2867         { SVM_EXIT_READ_DR0,                    "read_dr0" },
2868         { SVM_EXIT_READ_DR1,                    "read_dr1" },
2869         { SVM_EXIT_READ_DR2,                    "read_dr2" },
2870         { SVM_EXIT_READ_DR3,                    "read_dr3" },
2871         { SVM_EXIT_WRITE_DR0,                   "write_dr0" },
2872         { SVM_EXIT_WRITE_DR1,                   "write_dr1" },
2873         { SVM_EXIT_WRITE_DR2,                   "write_dr2" },
2874         { SVM_EXIT_WRITE_DR3,                   "write_dr3" },
2875         { SVM_EXIT_WRITE_DR5,                   "write_dr5" },
2876         { SVM_EXIT_WRITE_DR7,                   "write_dr7" },
2877         { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" },
2878         { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" },
2879         { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" },
2880         { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" },
2881         { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" },
2882         { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" },
2883         { SVM_EXIT_INTR,                        "interrupt" },
2884         { SVM_EXIT_NMI,                         "nmi" },
2885         { SVM_EXIT_SMI,                         "smi" },
2886         { SVM_EXIT_INIT,                        "init" },
2887         { SVM_EXIT_VINTR,                       "vintr" },
2888         { SVM_EXIT_CPUID,                       "cpuid" },
2889         { SVM_EXIT_INVD,                        "invd" },
2890         { SVM_EXIT_HLT,                         "hlt" },
2891         { SVM_EXIT_INVLPG,                      "invlpg" },
2892         { SVM_EXIT_INVLPGA,                     "invlpga" },
2893         { SVM_EXIT_IOIO,                        "io" },
2894         { SVM_EXIT_MSR,                         "msr" },
2895         { SVM_EXIT_TASK_SWITCH,                 "task_switch" },
2896         { SVM_EXIT_SHUTDOWN,                    "shutdown" },
2897         { SVM_EXIT_VMRUN,                       "vmrun" },
2898         { SVM_EXIT_VMMCALL,                     "hypercall" },
2899         { SVM_EXIT_VMLOAD,                      "vmload" },
2900         { SVM_EXIT_VMSAVE,                      "vmsave" },
2901         { SVM_EXIT_STGI,                        "stgi" },
2902         { SVM_EXIT_CLGI,                        "clgi" },
2903         { SVM_EXIT_SKINIT,                      "skinit" },
2904         { SVM_EXIT_WBINVD,                      "wbinvd" },
2905         { SVM_EXIT_MONITOR,                     "monitor" },
2906         { SVM_EXIT_MWAIT,                       "mwait" },
2907         { SVM_EXIT_NPF,                         "npf" },
2908         { -1, NULL }
2909 };
2910
2911 static int svm_get_lpage_level(void)
2912 {
2913         return PT_PDPE_LEVEL;
2914 }
2915
2916 static bool svm_rdtscp_supported(void)
2917 {
2918         return false;
2919 }
2920
2921 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
2922 {
2923         struct vcpu_svm *svm = to_svm(vcpu);
2924
2925         if (npt_enabled) {
2926                 /* hack: npt requires active fpu at this time */
2927                 vcpu->fpu_active = 1;
2928                 return;
2929         }
2930
2931         svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
2932         svm->vmcb->save.cr0 |= X86_CR0_TS;
2933 }
2934
2935 static struct kvm_x86_ops svm_x86_ops = {
2936         .cpu_has_kvm_support = has_svm,
2937         .disabled_by_bios = is_disabled,
2938         .hardware_setup = svm_hardware_setup,
2939         .hardware_unsetup = svm_hardware_unsetup,
2940         .check_processor_compatibility = svm_check_processor_compat,
2941         .hardware_enable = svm_hardware_enable,
2942         .hardware_disable = svm_hardware_disable,
2943         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2944
2945         .vcpu_create = svm_create_vcpu,
2946         .vcpu_free = svm_free_vcpu,
2947         .vcpu_reset = svm_vcpu_reset,
2948
2949         .prepare_guest_switch = svm_prepare_guest_switch,
2950         .vcpu_load = svm_vcpu_load,
2951         .vcpu_put = svm_vcpu_put,
2952
2953         .set_guest_debug = svm_guest_debug,
2954         .get_msr = svm_get_msr,
2955         .set_msr = svm_set_msr,
2956         .get_segment_base = svm_get_segment_base,
2957         .get_segment = svm_get_segment,
2958         .set_segment = svm_set_segment,
2959         .get_cpl = svm_get_cpl,
2960         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2961         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
2962         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2963         .set_cr0 = svm_set_cr0,
2964         .set_cr3 = svm_set_cr3,
2965         .set_cr4 = svm_set_cr4,
2966         .set_efer = svm_set_efer,
2967         .get_idt = svm_get_idt,
2968         .set_idt = svm_set_idt,
2969         .get_gdt = svm_get_gdt,
2970         .set_gdt = svm_set_gdt,
2971         .get_dr = svm_get_dr,
2972         .set_dr = svm_set_dr,
2973         .cache_reg = svm_cache_reg,
2974         .get_rflags = svm_get_rflags,
2975         .set_rflags = svm_set_rflags,
2976         .fpu_deactivate = svm_fpu_deactivate,
2977
2978         .tlb_flush = svm_flush_tlb,
2979
2980         .run = svm_vcpu_run,
2981         .handle_exit = handle_exit,
2982         .skip_emulated_instruction = skip_emulated_instruction,
2983         .set_interrupt_shadow = svm_set_interrupt_shadow,
2984         .get_interrupt_shadow = svm_get_interrupt_shadow,
2985         .patch_hypercall = svm_patch_hypercall,
2986         .set_irq = svm_set_irq,
2987         .set_nmi = svm_inject_nmi,
2988         .queue_exception = svm_queue_exception,
2989         .interrupt_allowed = svm_interrupt_allowed,
2990         .nmi_allowed = svm_nmi_allowed,
2991         .get_nmi_mask = svm_get_nmi_mask,
2992         .set_nmi_mask = svm_set_nmi_mask,
2993         .enable_nmi_window = enable_nmi_window,
2994         .enable_irq_window = enable_irq_window,
2995         .update_cr8_intercept = update_cr8_intercept,
2996
2997         .set_tss_addr = svm_set_tss_addr,
2998         .get_tdp_level = get_npt_level,
2999         .get_mt_mask = svm_get_mt_mask,
3000
3001         .exit_reasons_str = svm_exit_reasons_str,
3002         .get_lpage_level = svm_get_lpage_level,
3003
3004         .cpuid_update = svm_cpuid_update,
3005
3006         .rdtscp_supported = svm_rdtscp_supported,
3007 };
3008
3009 static int __init svm_init(void)
3010 {
3011         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3012                               THIS_MODULE);
3013 }
3014
3015 static void __exit svm_exit(void)
3016 {
3017         kvm_exit();
3018 }
3019
3020 module_init(svm_init)
3021 module_exit(svm_exit)