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   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20 #include "kvm_cache_regs.h"
  21 #include "x86.h"
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/ftrace_event.h>
  29
  30 #include <asm/desc.h>
  31
  32 #include <asm/virtext.h>
  33 #include "trace.h"
  34
  35 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  36
  37 MODULE_AUTHOR("Qumranet");
  38 MODULE_LICENSE("GPL");
  39
  40 #define IOPM_ALLOC_ORDER 2
  41 #define MSRPM_ALLOC_ORDER 1
  42
  43 #define SEG_TYPE_LDT 2
  44 #define SEG_TYPE_BUSY_TSS16 3
  45
  46 #define SVM_FEATURE_NPT  (1 << 0)
  47 #define SVM_FEATURE_LBRV (1 << 1)
  48 #define SVM_FEATURE_SVML (1 << 2)
  49 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
  50
  51 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  52 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  53 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  54
  55 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  56
  57 static const u32 host_save_user_msrs[] = {
  58 #ifdef CONFIG_X86_64
  59         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  60         MSR_FS_BASE,
  61 #endif
  62         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  63 };
  64
  65 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  66
  67 struct kvm_vcpu;
  68
  69 struct nested_state {
  70         struct vmcb *hsave;
  71         u64 hsave_msr;
  72         u64 vmcb;
  73
  74         /* These are the merged vectors */
  75         u32 *msrpm;
  76
  77         /* gpa pointers to the real vectors */
  78         u64 vmcb_msrpm;
  79
  80         /* A VMEXIT is required but not yet emulated */
  81         bool exit_required;
  82
  83         /* cache for intercepts of the guest */
  84         u16 intercept_cr_read;
  85         u16 intercept_cr_write;
  86         u16 intercept_dr_read;
  87         u16 intercept_dr_write;
  88         u32 intercept_exceptions;
  89         u64 intercept;
  90
  91 };
  92
  93 struct vcpu_svm {
  94         struct kvm_vcpu vcpu;
  95         struct vmcb *vmcb;
  96         unsigned long vmcb_pa;
  97         struct svm_cpu_data *svm_data;
  98         uint64_t asid_generation;
  99         uint64_t sysenter_esp;
 100         uint64_t sysenter_eip;
 101
 102         u64 next_rip;
 103
 104         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 105         u64 host_gs_base;
 106
 107         u32 *msrpm;
 108
 109         struct nested_state nested;
 110
 111         bool nmi_singlestep;
 112 };
 113
 114 /* enable NPT for AMD64 and X86 with PAE */
 115 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 116 static bool npt_enabled = true;
 117 #else
 118 static bool npt_enabled = false;
 119 #endif
 120 static int npt = 1;
 121
 122 module_param(npt, int, S_IRUGO);
 123
 124 static int nested = 1;
 125 module_param(nested, int, S_IRUGO);
 126
 127 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 128 static void svm_complete_interrupts(struct vcpu_svm *svm);
 129
 130 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 131 static int nested_svm_vmexit(struct vcpu_svm *svm);
 132 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 133                                       bool has_error_code, u32 error_code);
 134
 135 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 136 {
 137         return container_of(vcpu, struct vcpu_svm, vcpu);
 138 }
 139
 140 static inline bool is_nested(struct vcpu_svm *svm)
 141 {
 142         return svm->nested.vmcb;
 143 }
 144
 145 static inline void enable_gif(struct vcpu_svm *svm)
 146 {
 147         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 148 }
 149
 150 static inline void disable_gif(struct vcpu_svm *svm)
 151 {
 152         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 153 }
 154
 155 static inline bool gif_set(struct vcpu_svm *svm)
 156 {
 157         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 158 }
 159
 160 static unsigned long iopm_base;
 161
 162 struct kvm_ldttss_desc {
 163         u16 limit0;
 164         u16 base0;
 165         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
 166         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
 167         u32 base3;
 168         u32 zero1;
 169 } __attribute__((packed));
 170
 171 struct svm_cpu_data {
 172         int cpu;
 173
 174         u64 asid_generation;
 175         u32 max_asid;
 176         u32 next_asid;
 177         struct kvm_ldttss_desc *tss_desc;
 178
 179         struct page *save_area;
 180 };
 181
 182 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 183 static uint32_t svm_features;
 184
 185 struct svm_init_data {
 186         int cpu;
 187         int r;
 188 };
 189
 190 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 191
 192 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 193 #define MSRS_RANGE_SIZE 2048
 194 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 195
 196 #define MAX_INST_SIZE 15
 197
 198 static inline u32 svm_has(u32 feat)
 199 {
 200         return svm_features & feat;
 201 }
 202
 203 static inline void clgi(void)
 204 {
 205         asm volatile (__ex(SVM_CLGI));
 206 }
 207
 208 static inline void stgi(void)
 209 {
 210         asm volatile (__ex(SVM_STGI));
 211 }
 212
 213 static inline void invlpga(unsigned long addr, u32 asid)
 214 {
 215         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 216 }
 217
 218 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 219 {
 220         to_svm(vcpu)->asid_generation--;
 221 }
 222
 223 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 224 {
 225         force_new_asid(vcpu);
 226 }
 227
 228 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 229 {
 230         if (!npt_enabled && !(efer & EFER_LMA))
 231                 efer &= ~EFER_LME;
 232
 233         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 234         vcpu->arch.efer = efer;
 235 }
 236
 237 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 238                                 bool has_error_code, u32 error_code)
 239 {
 240         struct vcpu_svm *svm = to_svm(vcpu);
 241
 242         /* If we are within a nested VM we'd better #VMEXIT and let the
 243            guest handle the exception */
 244         if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
 245                 return;
 246
 247         svm->vmcb->control.event_inj = nr
 248                 | SVM_EVTINJ_VALID
 249                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 250                 | SVM_EVTINJ_TYPE_EXEPT;
 251         svm->vmcb->control.event_inj_err = error_code;
 252 }
 253
 254 static int is_external_interrupt(u32 info)
 255 {
 256         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 257         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 258 }
 259
 260 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 261 {
 262         struct vcpu_svm *svm = to_svm(vcpu);
 263         u32 ret = 0;
 264
 265         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 266                 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
 267         return ret & mask;
 268 }
 269
 270 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 271 {
 272         struct vcpu_svm *svm = to_svm(vcpu);
 273
 274         if (mask == 0)
 275                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 276         else
 277                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 278
 279 }
 280
 281 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 282 {
 283         struct vcpu_svm *svm = to_svm(vcpu);
 284
 285         if (!svm->next_rip) {
 286                 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
 287                                 EMULATE_DONE)
 288                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 289                 return;
 290         }
 291         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 292                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 293                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 294
 295         kvm_rip_write(vcpu, svm->next_rip);
 296         svm_set_interrupt_shadow(vcpu, 0);
 297 }
 298
 299 static int has_svm(void)
 300 {
 301         const char *msg;
 302
 303         if (!cpu_has_svm(&msg)) {
 304                 printk(KERN_INFO "has_svm: %s\n", msg);
 305                 return 0;
 306         }
 307
 308         return 1;
 309 }
 310
 311 static void svm_hardware_disable(void *garbage)
 312 {
 313         cpu_svm_disable();
 314 }
 315
 316 static int svm_hardware_enable(void *garbage)
 317 {
 318
 319         struct svm_cpu_data *sd;
 320         uint64_t efer;
 321         struct descriptor_table gdt_descr;
 322         struct desc_struct *gdt;
 323         int me = raw_smp_processor_id();
 324
 325         rdmsrl(MSR_EFER, efer);
 326         if (efer & EFER_SVME)
 327                 return -EBUSY;
 328
 329         if (!has_svm()) {
 330                 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
 331                        me);
 332                 return -EINVAL;
 333         }
 334         sd = per_cpu(svm_data, me);
 335
 336         if (!sd) {
 337                 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
 338                        me);
 339                 return -EINVAL;
 340         }
 341
 342         sd->asid_generation = 1;
 343         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 344         sd->next_asid = sd->max_asid + 1;
 345
 346         kvm_get_gdt(&gdt_descr);
 347         gdt = (struct desc_struct *)gdt_descr.base;
 348         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 349
 350         wrmsrl(MSR_EFER, efer | EFER_SVME);
 351
 352         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 353
 354         return 0;
 355 }
 356
 357 static void svm_cpu_uninit(int cpu)
 358 {
 359         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 360
 361         if (!sd)
 362                 return;
 363
 364         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 365         __free_page(sd->save_area);
 366         kfree(sd);
 367 }
 368
 369 static int svm_cpu_init(int cpu)
 370 {
 371         struct svm_cpu_data *sd;
 372         int r;
 373
 374         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 375         if (!sd)
 376                 return -ENOMEM;
 377         sd->cpu = cpu;
 378         sd->save_area = alloc_page(GFP_KERNEL);
 379         r = -ENOMEM;
 380         if (!sd->save_area)
 381                 goto err_1;
 382
 383         per_cpu(svm_data, cpu) = sd;
 384
 385         return 0;
 386
 387 err_1:
 388         kfree(sd);
 389         return r;
 390
 391 }
 392
 393 static void set_msr_interception(u32 *msrpm, unsigned msr,
 394                                  int read, int write)
 395 {
 396         int i;
 397
 398         for (i = 0; i < NUM_MSR_MAPS; i++) {
 399                 if (msr >= msrpm_ranges[i] &&
 400                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 401                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 402                                           msrpm_ranges[i]) * 2;
 403
 404                         u32 *base = msrpm + (msr_offset / 32);
 405                         u32 msr_shift = msr_offset % 32;
 406                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 407                         *base = (*base & ~(0x3 << msr_shift)) |
 408                                 (mask << msr_shift);
 409                         return;
 410                 }
 411         }
 412         BUG();
 413 }
 414
 415 static void svm_vcpu_init_msrpm(u32 *msrpm)
 416 {
 417         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 418
 419 #ifdef CONFIG_X86_64
 420         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 421         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 422         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 423         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 424         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 425         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 426 #endif
 427         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 428         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 429 }
 430
 431 static void svm_enable_lbrv(struct vcpu_svm *svm)
 432 {
 433         u32 *msrpm = svm->msrpm;
 434
 435         svm->vmcb->control.lbr_ctl = 1;
 436         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 437         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 438         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 439         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 440 }
 441
 442 static void svm_disable_lbrv(struct vcpu_svm *svm)
 443 {
 444         u32 *msrpm = svm->msrpm;
 445
 446         svm->vmcb->control.lbr_ctl = 0;
 447         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 448         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 449         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 450         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 451 }
 452
 453 static __init int svm_hardware_setup(void)
 454 {
 455         int cpu;
 456         struct page *iopm_pages;
 457         void *iopm_va;
 458         int r;
 459
 460         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 461
 462         if (!iopm_pages)
 463                 return -ENOMEM;
 464
 465         iopm_va = page_address(iopm_pages);
 466         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 467         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 468
 469         if (boot_cpu_has(X86_FEATURE_NX))
 470                 kvm_enable_efer_bits(EFER_NX);
 471
 472         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 473                 kvm_enable_efer_bits(EFER_FFXSR);
 474
 475         if (nested) {
 476                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 477                 kvm_enable_efer_bits(EFER_SVME);
 478         }
 479
 480         for_each_possible_cpu(cpu) {
 481                 r = svm_cpu_init(cpu);
 482                 if (r)
 483                         goto err;
 484         }
 485
 486         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 487
 488         if (!svm_has(SVM_FEATURE_NPT))
 489                 npt_enabled = false;
 490
 491         if (npt_enabled && !npt) {
 492                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 493                 npt_enabled = false;
 494         }
 495
 496         if (npt_enabled) {
 497                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 498                 kvm_enable_tdp();
 499         } else
 500                 kvm_disable_tdp();
 501
 502         return 0;
 503
 504 err:
 505         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 506         iopm_base = 0;
 507         return r;
 508 }
 509
 510 static __exit void svm_hardware_unsetup(void)
 511 {
 512         int cpu;
 513
 514         for_each_possible_cpu(cpu)
 515                 svm_cpu_uninit(cpu);
 516
 517         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 518         iopm_base = 0;
 519 }
 520
 521 static void init_seg(struct vmcb_seg *seg)
 522 {
 523         seg->selector = 0;
 524         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 525                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 526         seg->limit = 0xffff;
 527         seg->base = 0;
 528 }
 529
 530 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 531 {
 532         seg->selector = 0;
 533         seg->attrib = SVM_SELECTOR_P_MASK | type;
 534         seg->limit = 0xffff;
 535         seg->base = 0;
 536 }
 537
 538 static void init_vmcb(struct vcpu_svm *svm)
 539 {
 540         struct vmcb_control_area *control = &svm->vmcb->control;
 541         struct vmcb_save_area *save = &svm->vmcb->save;
 542
 543         svm->vcpu.fpu_active = 1;
 544
 545         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 546                                         INTERCEPT_CR3_MASK |
 547                                         INTERCEPT_CR4_MASK;
 548
 549         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 550                                         INTERCEPT_CR3_MASK |
 551                                         INTERCEPT_CR4_MASK |
 552                                         INTERCEPT_CR8_MASK;
 553
 554         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 555                                         INTERCEPT_DR1_MASK |
 556                                         INTERCEPT_DR2_MASK |
 557                                         INTERCEPT_DR3_MASK |
 558                                         INTERCEPT_DR4_MASK |
 559                                         INTERCEPT_DR5_MASK |
 560                                         INTERCEPT_DR6_MASK |
 561                                         INTERCEPT_DR7_MASK;
 562
 563         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 564                                         INTERCEPT_DR1_MASK |
 565                                         INTERCEPT_DR2_MASK |
 566                                         INTERCEPT_DR3_MASK |
 567                                         INTERCEPT_DR4_MASK |
 568                                         INTERCEPT_DR5_MASK |
 569                                         INTERCEPT_DR6_MASK |
 570                                         INTERCEPT_DR7_MASK;
 571
 572         control->intercept_exceptions = (1 << PF_VECTOR) |
 573                                         (1 << UD_VECTOR) |
 574                                         (1 << MC_VECTOR);
 575
 576
 577         control->intercept =    (1ULL << INTERCEPT_INTR) |
 578                                 (1ULL << INTERCEPT_NMI) |
 579                                 (1ULL << INTERCEPT_SMI) |
 580                                 (1ULL << INTERCEPT_SELECTIVE_CR0) |
 581                                 (1ULL << INTERCEPT_CPUID) |
 582                                 (1ULL << INTERCEPT_INVD) |
 583                                 (1ULL << INTERCEPT_HLT) |
 584                                 (1ULL << INTERCEPT_INVLPG) |
 585                                 (1ULL << INTERCEPT_INVLPGA) |
 586                                 (1ULL << INTERCEPT_IOIO_PROT) |
 587                                 (1ULL << INTERCEPT_MSR_PROT) |
 588                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 589                                 (1ULL << INTERCEPT_SHUTDOWN) |
 590                                 (1ULL << INTERCEPT_VMRUN) |
 591                                 (1ULL << INTERCEPT_VMMCALL) |
 592                                 (1ULL << INTERCEPT_VMLOAD) |
 593                                 (1ULL << INTERCEPT_VMSAVE) |
 594                                 (1ULL << INTERCEPT_STGI) |
 595                                 (1ULL << INTERCEPT_CLGI) |
 596                                 (1ULL << INTERCEPT_SKINIT) |
 597                                 (1ULL << INTERCEPT_WBINVD) |
 598                                 (1ULL << INTERCEPT_MONITOR) |
 599                                 (1ULL << INTERCEPT_MWAIT);
 600
 601         control->iopm_base_pa = iopm_base;
 602         control->msrpm_base_pa = __pa(svm->msrpm);
 603         control->tsc_offset = 0;
 604         control->int_ctl = V_INTR_MASKING_MASK;
 605
 606         init_seg(&save->es);
 607         init_seg(&save->ss);
 608         init_seg(&save->ds);
 609         init_seg(&save->fs);
 610         init_seg(&save->gs);
 611
 612         save->cs.selector = 0xf000;
 613         /* Executable/Readable Code Segment */
 614         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 615                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 616         save->cs.limit = 0xffff;
 617         /*
 618          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 619          * be consistent with it.
 620          *
 621          * Replace when we have real mode working for vmx.
 622          */
 623         save->cs.base = 0xf0000;
 624
 625         save->gdtr.limit = 0xffff;
 626         save->idtr.limit = 0xffff;
 627
 628         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 629         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 630
 631         save->efer = EFER_SVME;
 632         save->dr6 = 0xffff0ff0;
 633         save->dr7 = 0x400;
 634         save->rflags = 2;
 635         save->rip = 0x0000fff0;
 636         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 637
 638         /* This is the guest-visible cr0 value.
 639          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
 640          */
 641         svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
 642         kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
 643
 644         save->cr4 = X86_CR4_PAE;
 645         /* rdx = ?? */
 646
 647         if (npt_enabled) {
 648                 /* Setup VMCB for Nested Paging */
 649                 control->nested_ctl = 1;
 650                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 651                                         (1ULL << INTERCEPT_INVLPG));
 652                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 653                 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
 654                 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
 655                 save->g_pat = 0x0007040600070406ULL;
 656                 save->cr3 = 0;
 657                 save->cr4 = 0;
 658         }
 659         force_new_asid(&svm->vcpu);
 660
 661         svm->nested.vmcb = 0;
 662         svm->vcpu.arch.hflags = 0;
 663
 664         if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
 665                 control->pause_filter_count = 3000;
 666                 control->intercept |= (1ULL << INTERCEPT_PAUSE);
 667         }
 668
 669         enable_gif(svm);
 670 }
 671
 672 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 673 {
 674         struct vcpu_svm *svm = to_svm(vcpu);
 675
 676         init_vmcb(svm);
 677
 678         if (!kvm_vcpu_is_bsp(vcpu)) {
 679                 kvm_rip_write(vcpu, 0);
 680                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 681                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 682         }
 683         vcpu->arch.regs_avail = ~0;
 684         vcpu->arch.regs_dirty = ~0;
 685
 686         return 0;
 687 }
 688
 689 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 690 {
 691         struct vcpu_svm *svm;
 692         struct page *page;
 693         struct page *msrpm_pages;
 694         struct page *hsave_page;
 695         struct page *nested_msrpm_pages;
 696         int err;
 697
 698         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 699         if (!svm) {
 700                 err = -ENOMEM;
 701                 goto out;
 702         }
 703
 704         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 705         if (err)
 706                 goto free_svm;
 707
 708         page = alloc_page(GFP_KERNEL);
 709         if (!page) {
 710                 err = -ENOMEM;
 711                 goto uninit;
 712         }
 713
 714         err = -ENOMEM;
 715         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 716         if (!msrpm_pages)
 717                 goto uninit;
 718
 719         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 720         if (!nested_msrpm_pages)
 721                 goto uninit;
 722
 723         svm->msrpm = page_address(msrpm_pages);
 724         svm_vcpu_init_msrpm(svm->msrpm);
 725
 726         hsave_page = alloc_page(GFP_KERNEL);
 727         if (!hsave_page)
 728                 goto uninit;
 729         svm->nested.hsave = page_address(hsave_page);
 730
 731         svm->nested.msrpm = page_address(nested_msrpm_pages);
 732
 733         svm->vmcb = page_address(page);
 734         clear_page(svm->vmcb);
 735         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 736         svm->asid_generation = 0;
 737         init_vmcb(svm);
 738
 739         fx_init(&svm->vcpu);
 740         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 741         if (kvm_vcpu_is_bsp(&svm->vcpu))
 742                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 743
 744         return &svm->vcpu;
 745
 746 uninit:
 747         kvm_vcpu_uninit(&svm->vcpu);
 748 free_svm:
 749         kmem_cache_free(kvm_vcpu_cache, svm);
 750 out:
 751         return ERR_PTR(err);
 752 }
 753
 754 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 755 {
 756         struct vcpu_svm *svm = to_svm(vcpu);
 757
 758         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 759         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 760         __free_page(virt_to_page(svm->nested.hsave));
 761         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
 762         kvm_vcpu_uninit(vcpu);
 763         kmem_cache_free(kvm_vcpu_cache, svm);
 764 }
 765
 766 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 767 {
 768         struct vcpu_svm *svm = to_svm(vcpu);
 769         int i;
 770
 771         if (unlikely(cpu != vcpu->cpu)) {
 772                 u64 delta;
 773
 774                 if (check_tsc_unstable()) {
 775                         /*
 776                          * Make sure that the guest sees a monotonically
 777                          * increasing TSC.
 778                          */
 779                         delta = vcpu->arch.host_tsc - native_read_tsc();
 780                         svm->vmcb->control.tsc_offset += delta;
 781                         if (is_nested(svm))
 782                                 svm->nested.hsave->control.tsc_offset += delta;
 783                 }
 784                 vcpu->cpu = cpu;
 785                 kvm_migrate_timers(vcpu);
 786                 svm->asid_generation = 0;
 787         }
 788
 789         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 790                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 791 }
 792
 793 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 794 {
 795         struct vcpu_svm *svm = to_svm(vcpu);
 796         int i;
 797
 798         ++vcpu->stat.host_state_reload;
 799         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 800                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 801
 802         vcpu->arch.host_tsc = native_read_tsc();
 803 }
 804
 805 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 806 {
 807         return to_svm(vcpu)->vmcb->save.rflags;
 808 }
 809
 810 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 811 {
 812         to_svm(vcpu)->vmcb->save.rflags = rflags;
 813 }
 814
 815 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
 816 {
 817         switch (reg) {
 818         case VCPU_EXREG_PDPTR:
 819                 BUG_ON(!npt_enabled);
 820                 load_pdptrs(vcpu, vcpu->arch.cr3);
 821                 break;
 822         default:
 823                 BUG();
 824         }
 825 }
 826
 827 static void svm_set_vintr(struct vcpu_svm *svm)
 828 {
 829         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 830 }
 831
 832 static void svm_clear_vintr(struct vcpu_svm *svm)
 833 {
 834         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 835 }
 836
 837 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 838 {
 839         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 840
 841         switch (seg) {
 842         case VCPU_SREG_CS: return &save->cs;
 843         case VCPU_SREG_DS: return &save->ds;
 844         case VCPU_SREG_ES: return &save->es;
 845         case VCPU_SREG_FS: return &save->fs;
 846         case VCPU_SREG_GS: return &save->gs;
 847         case VCPU_SREG_SS: return &save->ss;
 848         case VCPU_SREG_TR: return &save->tr;
 849         case VCPU_SREG_LDTR: return &save->ldtr;
 850         }
 851         BUG();
 852         return NULL;
 853 }
 854
 855 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 856 {
 857         struct vmcb_seg *s = svm_seg(vcpu, seg);
 858
 859         return s->base;
 860 }
 861
 862 static void svm_get_segment(struct kvm_vcpu *vcpu,
 863                             struct kvm_segment *var, int seg)
 864 {
 865         struct vmcb_seg *s = svm_seg(vcpu, seg);
 866
 867         var->base = s->base;
 868         var->limit = s->limit;
 869         var->selector = s->selector;
 870         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 871         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 872         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 873         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 874         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 875         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 876         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 877         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 878
 879         /* AMD's VMCB does not have an explicit unusable field, so emulate it
 880          * for cross vendor migration purposes by "not present"
 881          */
 882         var->unusable = !var->present || (var->type == 0);
 883
 884         switch (seg) {
 885         case VCPU_SREG_CS:
 886                 /*
 887                  * SVM always stores 0 for the 'G' bit in the CS selector in
 888                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 889                  * Intel's VMENTRY has a check on the 'G' bit.
 890                  */
 891                 var->g = s->limit > 0xfffff;
 892                 break;
 893         case VCPU_SREG_TR:
 894                 /*
 895                  * Work around a bug where the busy flag in the tr selector
 896                  * isn't exposed
 897                  */
 898                 var->type |= 0x2;
 899                 break;
 900         case VCPU_SREG_DS:
 901         case VCPU_SREG_ES:
 902         case VCPU_SREG_FS:
 903         case VCPU_SREG_GS:
 904                 /*
 905                  * The accessed bit must always be set in the segment
 906                  * descriptor cache, although it can be cleared in the
 907                  * descriptor, the cached bit always remains at 1. Since
 908                  * Intel has a check on this, set it here to support
 909                  * cross-vendor migration.
 910                  */
 911                 if (!var->unusable)
 912                         var->type |= 0x1;
 913                 break;
 914         case VCPU_SREG_SS:
 915                 /* On AMD CPUs sometimes the DB bit in the segment
 916                  * descriptor is left as 1, although the whole segment has
 917                  * been made unusable. Clear it here to pass an Intel VMX
 918                  * entry check when cross vendor migrating.
 919                  */
 920                 if (var->unusable)
 921                         var->db = 0;
 922                 break;
 923         }
 924 }
 925
 926 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 927 {
 928         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 929
 930         return save->cpl;
 931 }
 932
 933 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 934 {
 935         struct vcpu_svm *svm = to_svm(vcpu);
 936
 937         dt->limit = svm->vmcb->save.idtr.limit;
 938         dt->base = svm->vmcb->save.idtr.base;
 939 }
 940
 941 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 942 {
 943         struct vcpu_svm *svm = to_svm(vcpu);
 944
 945         svm->vmcb->save.idtr.limit = dt->limit;
 946         svm->vmcb->save.idtr.base = dt->base ;
 947 }
 948
 949 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 950 {
 951         struct vcpu_svm *svm = to_svm(vcpu);
 952
 953         dt->limit = svm->vmcb->save.gdtr.limit;
 954         dt->base = svm->vmcb->save.gdtr.base;
 955 }
 956
 957 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 958 {
 959         struct vcpu_svm *svm = to_svm(vcpu);
 960
 961         svm->vmcb->save.gdtr.limit = dt->limit;
 962         svm->vmcb->save.gdtr.base = dt->base ;
 963 }
 964
 965 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
 966 {
 967 }
 968
 969 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 970 {
 971 }
 972
 973 static void update_cr0_intercept(struct vcpu_svm *svm)
 974 {
 975         ulong gcr0 = svm->vcpu.arch.cr0;
 976         u64 *hcr0 = &svm->vmcb->save.cr0;
 977
 978         if (!svm->vcpu.fpu_active)
 979                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
 980         else
 981                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
 982                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
 983
 984
 985         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
 986                 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
 987                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
 988         } else {
 989                 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
 990                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
 991         }
 992 }
 993
 994 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 995 {
 996         struct vcpu_svm *svm = to_svm(vcpu);
 997
 998 #ifdef CONFIG_X86_64
 999         if (vcpu->arch.efer & EFER_LME) {
1000                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1001                         vcpu->arch.efer |= EFER_LMA;
1002                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1003                 }
1004
1005                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1006                         vcpu->arch.efer &= ~EFER_LMA;
1007                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1008                 }
1009         }
1010 #endif
1011         vcpu->arch.cr0 = cr0;
1012
1013         if (!npt_enabled)
1014                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1015
1016         if (!vcpu->fpu_active)
1017                 cr0 |= X86_CR0_TS;
1018         /*
1019          * re-enable caching here because the QEMU bios
1020          * does not do it - this results in some delay at
1021          * reboot
1022          */
1023         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1024         svm->vmcb->save.cr0 = cr0;
1025         update_cr0_intercept(svm);
1026 }
1027
1028 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1029 {
1030         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1031         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1032
1033         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1034                 force_new_asid(vcpu);
1035
1036         vcpu->arch.cr4 = cr4;
1037         if (!npt_enabled)
1038                 cr4 |= X86_CR4_PAE;
1039         cr4 |= host_cr4_mce;
1040         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1041 }
1042
1043 static void svm_set_segment(struct kvm_vcpu *vcpu,
1044                             struct kvm_segment *var, int seg)
1045 {
1046         struct vcpu_svm *svm = to_svm(vcpu);
1047         struct vmcb_seg *s = svm_seg(vcpu, seg);
1048
1049         s->base = var->base;
1050         s->limit = var->limit;
1051         s->selector = var->selector;
1052         if (var->unusable)
1053                 s->attrib = 0;
1054         else {
1055                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1056                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1057                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1058                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1059                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1060                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1061                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1062                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1063         }
1064         if (seg == VCPU_SREG_CS)
1065                 svm->vmcb->save.cpl
1066                         = (svm->vmcb->save.cs.attrib
1067                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1068
1069 }
1070
1071 static void update_db_intercept(struct kvm_vcpu *vcpu)
1072 {
1073         struct vcpu_svm *svm = to_svm(vcpu);
1074
1075         svm->vmcb->control.intercept_exceptions &=
1076                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1077
1078         if (svm->nmi_singlestep)
1079                 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1080
1081         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1082                 if (vcpu->guest_debug &
1083                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1084                         svm->vmcb->control.intercept_exceptions |=
1085                                 1 << DB_VECTOR;
1086                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1087                         svm->vmcb->control.intercept_exceptions |=
1088                                 1 << BP_VECTOR;
1089         } else
1090                 vcpu->guest_debug = 0;
1091 }
1092
1093 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1094 {
1095         struct vcpu_svm *svm = to_svm(vcpu);
1096
1097         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1098                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1099         else
1100                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1101
1102         update_db_intercept(vcpu);
1103 }
1104
1105 static void load_host_msrs(struct kvm_vcpu *vcpu)
1106 {
1107 #ifdef CONFIG_X86_64
1108         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1109 #endif
1110 }
1111
1112 static void save_host_msrs(struct kvm_vcpu *vcpu)
1113 {
1114 #ifdef CONFIG_X86_64
1115         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1116 #endif
1117 }
1118
1119 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1120 {
1121         if (sd->next_asid > sd->max_asid) {
1122                 ++sd->asid_generation;
1123                 sd->next_asid = 1;
1124                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1125         }
1126
1127         svm->asid_generation = sd->asid_generation;
1128         svm->vmcb->control.asid = sd->next_asid++;
1129 }
1130
1131 static int svm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *dest)
1132 {
1133         struct vcpu_svm *svm = to_svm(vcpu);
1134
1135         switch (dr) {
1136         case 0 ... 3:
1137                 *dest = vcpu->arch.db[dr];
1138                 break;
1139         case 4:
1140                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1141                         return EMULATE_FAIL; /* will re-inject UD */
1142                 /* fall through */
1143         case 6:
1144                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1145                         *dest = vcpu->arch.dr6;
1146                 else
1147                         *dest = svm->vmcb->save.dr6;
1148                 break;
1149         case 5:
1150                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1151                         return EMULATE_FAIL; /* will re-inject UD */
1152                 /* fall through */
1153         case 7:
1154                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1155                         *dest = vcpu->arch.dr7;
1156                 else
1157                         *dest = svm->vmcb->save.dr7;
1158                 break;
1159         }
1160
1161         return EMULATE_DONE;
1162 }
1163
1164 static int svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value)
1165 {
1166         struct vcpu_svm *svm = to_svm(vcpu);
1167
1168         switch (dr) {
1169         case 0 ... 3:
1170                 vcpu->arch.db[dr] = value;
1171                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1172                         vcpu->arch.eff_db[dr] = value;
1173                 break;
1174         case 4:
1175                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1176                         return EMULATE_FAIL; /* will re-inject UD */
1177                 /* fall through */
1178         case 6:
1179                 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1180                 break;
1181         case 5:
1182                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1183                         return EMULATE_FAIL; /* will re-inject UD */
1184                 /* fall through */
1185         case 7:
1186                 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1187                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1188                         svm->vmcb->save.dr7 = vcpu->arch.dr7;
1189                         vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1190                 }
1191                 break;
1192         }
1193
1194         return EMULATE_DONE;
1195 }
1196
1197 static int pf_interception(struct vcpu_svm *svm)
1198 {
1199         u64 fault_address;
1200         u32 error_code;
1201
1202         fault_address  = svm->vmcb->control.exit_info_2;
1203         error_code = svm->vmcb->control.exit_info_1;
1204
1205         trace_kvm_page_fault(fault_address, error_code);
1206         if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1207                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1208         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1209 }
1210
1211 static int db_interception(struct vcpu_svm *svm)
1212 {
1213         struct kvm_run *kvm_run = svm->vcpu.run;
1214
1215         if (!(svm->vcpu.guest_debug &
1216               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1217                 !svm->nmi_singlestep) {
1218                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1219                 return 1;
1220         }
1221
1222         if (svm->nmi_singlestep) {
1223                 svm->nmi_singlestep = false;
1224                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1225                         svm->vmcb->save.rflags &=
1226                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1227                 update_db_intercept(&svm->vcpu);
1228         }
1229
1230         if (svm->vcpu.guest_debug &
1231             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1232                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1233                 kvm_run->debug.arch.pc =
1234                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1235                 kvm_run->debug.arch.exception = DB_VECTOR;
1236                 return 0;
1237         }
1238
1239         return 1;
1240 }
1241
1242 static int bp_interception(struct vcpu_svm *svm)
1243 {
1244         struct kvm_run *kvm_run = svm->vcpu.run;
1245
1246         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1247         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1248         kvm_run->debug.arch.exception = BP_VECTOR;
1249         return 0;
1250 }
1251
1252 static int ud_interception(struct vcpu_svm *svm)
1253 {
1254         int er;
1255
1256         er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1257         if (er != EMULATE_DONE)
1258                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1259         return 1;
1260 }
1261
1262 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1263 {
1264         struct vcpu_svm *svm = to_svm(vcpu);
1265         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1266         svm->vcpu.fpu_active = 1;
1267         update_cr0_intercept(svm);
1268 }
1269
1270 static int nm_interception(struct vcpu_svm *svm)
1271 {
1272         svm_fpu_activate(&svm->vcpu);
1273         return 1;
1274 }
1275
1276 static int mc_interception(struct vcpu_svm *svm)
1277 {
1278         /*
1279          * On an #MC intercept the MCE handler is not called automatically in
1280          * the host. So do it by hand here.
1281          */
1282         asm volatile (
1283                 "int $0x12\n");
1284         /* not sure if we ever come back to this point */
1285
1286         return 1;
1287 }
1288
1289 static int shutdown_interception(struct vcpu_svm *svm)
1290 {
1291         struct kvm_run *kvm_run = svm->vcpu.run;
1292
1293         /*
1294          * VMCB is undefined after a SHUTDOWN intercept
1295          * so reinitialize it.
1296          */
1297         clear_page(svm->vmcb);
1298         init_vmcb(svm);
1299
1300         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1301         return 0;
1302 }
1303
1304 static int io_interception(struct vcpu_svm *svm)
1305 {
1306         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1307         int size, in, string;
1308         unsigned port;
1309
1310         ++svm->vcpu.stat.io_exits;
1311
1312         svm->next_rip = svm->vmcb->control.exit_info_2;
1313
1314         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1315
1316         if (string) {
1317                 if (emulate_instruction(&svm->vcpu,
1318                                         0, 0, 0) == EMULATE_DO_MMIO)
1319                         return 0;
1320                 return 1;
1321         }
1322
1323         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1324         port = io_info >> 16;
1325         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1326
1327         skip_emulated_instruction(&svm->vcpu);
1328         return kvm_emulate_pio(&svm->vcpu, in, size, port);
1329 }
1330
1331 static int nmi_interception(struct vcpu_svm *svm)
1332 {
1333         return 1;
1334 }
1335
1336 static int intr_interception(struct vcpu_svm *svm)
1337 {
1338         ++svm->vcpu.stat.irq_exits;
1339         return 1;
1340 }
1341
1342 static int nop_on_interception(struct vcpu_svm *svm)
1343 {
1344         return 1;
1345 }
1346
1347 static int halt_interception(struct vcpu_svm *svm)
1348 {
1349         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1350         skip_emulated_instruction(&svm->vcpu);
1351         return kvm_emulate_halt(&svm->vcpu);
1352 }
1353
1354 static int vmmcall_interception(struct vcpu_svm *svm)
1355 {
1356         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1357         skip_emulated_instruction(&svm->vcpu);
1358         kvm_emulate_hypercall(&svm->vcpu);
1359         return 1;
1360 }
1361
1362 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1363 {
1364         if (!(svm->vcpu.arch.efer & EFER_SVME)
1365             || !is_paging(&svm->vcpu)) {
1366                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1367                 return 1;
1368         }
1369
1370         if (svm->vmcb->save.cpl) {
1371                 kvm_inject_gp(&svm->vcpu, 0);
1372                 return 1;
1373         }
1374
1375        return 0;
1376 }
1377
1378 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1379                                       bool has_error_code, u32 error_code)
1380 {
1381         if (!is_nested(svm))
1382                 return 0;
1383
1384         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1385         svm->vmcb->control.exit_code_hi = 0;
1386         svm->vmcb->control.exit_info_1 = error_code;
1387         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1388
1389         return nested_svm_exit_handled(svm);
1390 }
1391
1392 static inline int nested_svm_intr(struct vcpu_svm *svm)
1393 {
1394         if (!is_nested(svm))
1395                 return 0;
1396
1397         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1398                 return 0;
1399
1400         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1401                 return 0;
1402
1403         svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1404
1405         if (svm->nested.intercept & 1ULL) {
1406                 /*
1407                  * The #vmexit can't be emulated here directly because this
1408                  * code path runs with irqs and preemtion disabled. A
1409                  * #vmexit emulation might sleep. Only signal request for
1410                  * the #vmexit here.
1411                  */
1412                 svm->nested.exit_required = true;
1413                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1414                 return 1;
1415         }
1416
1417         return 0;
1418 }
1419
1420 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
1421 {
1422         struct page *page;
1423
1424         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1425         if (is_error_page(page))
1426                 goto error;
1427
1428         return kmap_atomic(page, idx);
1429
1430 error:
1431         kvm_release_page_clean(page);
1432         kvm_inject_gp(&svm->vcpu, 0);
1433
1434         return NULL;
1435 }
1436
1437 static void nested_svm_unmap(void *addr, enum km_type idx)
1438 {
1439         struct page *page;
1440
1441         if (!addr)
1442                 return;
1443
1444         page = kmap_atomic_to_page(addr);
1445
1446         kunmap_atomic(addr, idx);
1447         kvm_release_page_dirty(page);
1448 }
1449
1450 static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1451 {
1452         u32 param = svm->vmcb->control.exit_info_1 & 1;
1453         u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1454         bool ret = false;
1455         u32 t0, t1;
1456         u8 *msrpm;
1457
1458         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1459                 return false;
1460
1461         msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1462
1463         if (!msrpm)
1464                 goto out;
1465
1466         switch (msr) {
1467         case 0 ... 0x1fff:
1468                 t0 = (msr * 2) % 8;
1469                 t1 = msr / 8;
1470                 break;
1471         case 0xc0000000 ... 0xc0001fff:
1472                 t0 = (8192 + msr - 0xc0000000) * 2;
1473                 t1 = (t0 / 8);
1474                 t0 %= 8;
1475                 break;
1476         case 0xc0010000 ... 0xc0011fff:
1477                 t0 = (16384 + msr - 0xc0010000) * 2;
1478                 t1 = (t0 / 8);
1479                 t0 %= 8;
1480                 break;
1481         default:
1482                 ret = true;
1483                 goto out;
1484         }
1485
1486         ret = msrpm[t1] & ((1 << param) << t0);
1487
1488 out:
1489         nested_svm_unmap(msrpm, KM_USER0);
1490
1491         return ret;
1492 }
1493
1494 static int nested_svm_exit_special(struct vcpu_svm *svm)
1495 {
1496         u32 exit_code = svm->vmcb->control.exit_code;
1497
1498         switch (exit_code) {
1499         case SVM_EXIT_INTR:
1500         case SVM_EXIT_NMI:
1501                 return NESTED_EXIT_HOST;
1502                 /* For now we are always handling NPFs when using them */
1503         case SVM_EXIT_NPF:
1504                 if (npt_enabled)
1505                         return NESTED_EXIT_HOST;
1506                 break;
1507         /* When we're shadowing, trap PFs */
1508         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1509                 if (!npt_enabled)
1510                         return NESTED_EXIT_HOST;
1511                 break;
1512         default:
1513                 break;
1514         }
1515
1516         return NESTED_EXIT_CONTINUE;
1517 }
1518
1519 /*
1520  * If this function returns true, this #vmexit was already handled
1521  */
1522 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1523 {
1524         u32 exit_code = svm->vmcb->control.exit_code;
1525         int vmexit = NESTED_EXIT_HOST;
1526
1527         switch (exit_code) {
1528         case SVM_EXIT_MSR:
1529                 vmexit = nested_svm_exit_handled_msr(svm);
1530                 break;
1531         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1532                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1533                 if (svm->nested.intercept_cr_read & cr_bits)
1534                         vmexit = NESTED_EXIT_DONE;
1535                 break;
1536         }
1537         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1538                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1539                 if (svm->nested.intercept_cr_write & cr_bits)
1540                         vmexit = NESTED_EXIT_DONE;
1541                 break;
1542         }
1543         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1544                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1545                 if (svm->nested.intercept_dr_read & dr_bits)
1546                         vmexit = NESTED_EXIT_DONE;
1547                 break;
1548         }
1549         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1550                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1551                 if (svm->nested.intercept_dr_write & dr_bits)
1552                         vmexit = NESTED_EXIT_DONE;
1553                 break;
1554         }
1555         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1556                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1557                 if (svm->nested.intercept_exceptions & excp_bits)
1558                         vmexit = NESTED_EXIT_DONE;
1559                 break;
1560         }
1561         default: {
1562                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1563                 if (svm->nested.intercept & exit_bits)
1564                         vmexit = NESTED_EXIT_DONE;
1565         }
1566         }
1567
1568         if (vmexit == NESTED_EXIT_DONE) {
1569                 nested_svm_vmexit(svm);
1570         }
1571
1572         return vmexit;
1573 }
1574
1575 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1576 {
1577         struct vmcb_control_area *dst  = &dst_vmcb->control;
1578         struct vmcb_control_area *from = &from_vmcb->control;
1579
1580         dst->intercept_cr_read    = from->intercept_cr_read;
1581         dst->intercept_cr_write   = from->intercept_cr_write;
1582         dst->intercept_dr_read    = from->intercept_dr_read;
1583         dst->intercept_dr_write   = from->intercept_dr_write;
1584         dst->intercept_exceptions = from->intercept_exceptions;
1585         dst->intercept            = from->intercept;
1586         dst->iopm_base_pa         = from->iopm_base_pa;
1587         dst->msrpm_base_pa        = from->msrpm_base_pa;
1588         dst->tsc_offset           = from->tsc_offset;
1589         dst->asid                 = from->asid;
1590         dst->tlb_ctl              = from->tlb_ctl;
1591         dst->int_ctl              = from->int_ctl;
1592         dst->int_vector           = from->int_vector;
1593         dst->int_state            = from->int_state;
1594         dst->exit_code            = from->exit_code;
1595         dst->exit_code_hi         = from->exit_code_hi;
1596         dst->exit_info_1          = from->exit_info_1;
1597         dst->exit_info_2          = from->exit_info_2;
1598         dst->exit_int_info        = from->exit_int_info;
1599         dst->exit_int_info_err    = from->exit_int_info_err;
1600         dst->nested_ctl           = from->nested_ctl;
1601         dst->event_inj            = from->event_inj;
1602         dst->event_inj_err        = from->event_inj_err;
1603         dst->nested_cr3           = from->nested_cr3;
1604         dst->lbr_ctl              = from->lbr_ctl;
1605 }
1606
1607 static int nested_svm_vmexit(struct vcpu_svm *svm)
1608 {
1609         struct vmcb *nested_vmcb;
1610         struct vmcb *hsave = svm->nested.hsave;
1611         struct vmcb *vmcb = svm->vmcb;
1612
1613         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1614                                        vmcb->control.exit_info_1,
1615                                        vmcb->control.exit_info_2,
1616                                        vmcb->control.exit_int_info,
1617                                        vmcb->control.exit_int_info_err);
1618
1619         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
1620         if (!nested_vmcb)
1621                 return 1;
1622
1623         /* Give the current vmcb to the guest */
1624         disable_gif(svm);
1625
1626         nested_vmcb->save.es     = vmcb->save.es;
1627         nested_vmcb->save.cs     = vmcb->save.cs;
1628         nested_vmcb->save.ss     = vmcb->save.ss;
1629         nested_vmcb->save.ds     = vmcb->save.ds;
1630         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
1631         nested_vmcb->save.idtr   = vmcb->save.idtr;
1632         if (npt_enabled)
1633                 nested_vmcb->save.cr3    = vmcb->save.cr3;
1634         nested_vmcb->save.cr2    = vmcb->save.cr2;
1635         nested_vmcb->save.rflags = vmcb->save.rflags;
1636         nested_vmcb->save.rip    = vmcb->save.rip;
1637         nested_vmcb->save.rsp    = vmcb->save.rsp;
1638         nested_vmcb->save.rax    = vmcb->save.rax;
1639         nested_vmcb->save.dr7    = vmcb->save.dr7;
1640         nested_vmcb->save.dr6    = vmcb->save.dr6;
1641         nested_vmcb->save.cpl    = vmcb->save.cpl;
1642
1643         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
1644         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
1645         nested_vmcb->control.int_state         = vmcb->control.int_state;
1646         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
1647         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
1648         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
1649         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
1650         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
1651         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1652
1653         /*
1654          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1655          * to make sure that we do not lose injected events. So check event_inj
1656          * here and copy it to exit_int_info if it is valid.
1657          * Exit_int_info and event_inj can't be both valid because the case
1658          * below only happens on a VMRUN instruction intercept which has
1659          * no valid exit_int_info set.
1660          */
1661         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1662                 struct vmcb_control_area *nc = &nested_vmcb->control;
1663
1664                 nc->exit_int_info     = vmcb->control.event_inj;
1665                 nc->exit_int_info_err = vmcb->control.event_inj_err;
1666         }
1667
1668         nested_vmcb->control.tlb_ctl           = 0;
1669         nested_vmcb->control.event_inj         = 0;
1670         nested_vmcb->control.event_inj_err     = 0;
1671
1672         /* We always set V_INTR_MASKING and remember the old value in hflags */
1673         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1674                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1675
1676         /* Restore the original control entries */
1677         copy_vmcb_control_area(vmcb, hsave);
1678
1679         kvm_clear_exception_queue(&svm->vcpu);
1680         kvm_clear_interrupt_queue(&svm->vcpu);
1681
1682         /* Restore selected save entries */
1683         svm->vmcb->save.es = hsave->save.es;
1684         svm->vmcb->save.cs = hsave->save.cs;
1685         svm->vmcb->save.ss = hsave->save.ss;
1686         svm->vmcb->save.ds = hsave->save.ds;
1687         svm->vmcb->save.gdtr = hsave->save.gdtr;
1688         svm->vmcb->save.idtr = hsave->save.idtr;
1689         svm->vmcb->save.rflags = hsave->save.rflags;
1690         svm_set_efer(&svm->vcpu, hsave->save.efer);
1691         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1692         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1693         if (npt_enabled) {
1694                 svm->vmcb->save.cr3 = hsave->save.cr3;
1695                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1696         } else {
1697                 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1698         }
1699         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1700         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1701         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1702         svm->vmcb->save.dr7 = 0;
1703         svm->vmcb->save.cpl = 0;
1704         svm->vmcb->control.exit_int_info = 0;
1705
1706         /* Exit nested SVM mode */
1707         svm->nested.vmcb = 0;
1708
1709         nested_svm_unmap(nested_vmcb, KM_USER0);
1710
1711         kvm_mmu_reset_context(&svm->vcpu);
1712         kvm_mmu_load(&svm->vcpu);
1713
1714         return 0;
1715 }
1716
1717 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1718 {
1719         u32 *nested_msrpm;
1720         int i;
1721
1722         nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1723         if (!nested_msrpm)
1724                 return false;
1725
1726         for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1727                 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1728
1729         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
1730
1731         nested_svm_unmap(nested_msrpm, KM_USER0);
1732
1733         return true;
1734 }
1735
1736 static bool nested_svm_vmrun(struct vcpu_svm *svm)
1737 {
1738         struct vmcb *nested_vmcb;
1739         struct vmcb *hsave = svm->nested.hsave;
1740         struct vmcb *vmcb = svm->vmcb;
1741
1742         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1743         if (!nested_vmcb)
1744                 return false;
1745
1746         /* nested_vmcb is our indicator if nested SVM is activated */
1747         svm->nested.vmcb = svm->vmcb->save.rax;
1748
1749         trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, svm->nested.vmcb,
1750                                nested_vmcb->save.rip,
1751                                nested_vmcb->control.int_ctl,
1752                                nested_vmcb->control.event_inj,
1753                                nested_vmcb->control.nested_ctl);
1754
1755         /* Clear internal status */
1756         kvm_clear_exception_queue(&svm->vcpu);
1757         kvm_clear_interrupt_queue(&svm->vcpu);
1758
1759         /* Save the old vmcb, so we don't need to pick what we save, but
1760            can restore everything when a VMEXIT occurs */
1761         hsave->save.es     = vmcb->save.es;
1762         hsave->save.cs     = vmcb->save.cs;
1763         hsave->save.ss     = vmcb->save.ss;
1764         hsave->save.ds     = vmcb->save.ds;
1765         hsave->save.gdtr   = vmcb->save.gdtr;
1766         hsave->save.idtr   = vmcb->save.idtr;
1767         hsave->save.efer   = svm->vcpu.arch.efer;
1768         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
1769         hsave->save.cr4    = svm->vcpu.arch.cr4;
1770         hsave->save.rflags = vmcb->save.rflags;
1771         hsave->save.rip    = svm->next_rip;
1772         hsave->save.rsp    = vmcb->save.rsp;
1773         hsave->save.rax    = vmcb->save.rax;
1774         if (npt_enabled)
1775                 hsave->save.cr3    = vmcb->save.cr3;
1776         else
1777                 hsave->save.cr3    = svm->vcpu.arch.cr3;
1778
1779         copy_vmcb_control_area(hsave, vmcb);
1780
1781         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1782                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1783         else
1784                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1785
1786         /* Load the nested guest state */
1787         svm->vmcb->save.es = nested_vmcb->save.es;
1788         svm->vmcb->save.cs = nested_vmcb->save.cs;
1789         svm->vmcb->save.ss = nested_vmcb->save.ss;
1790         svm->vmcb->save.ds = nested_vmcb->save.ds;
1791         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1792         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1793         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1794         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1795         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1796         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1797         if (npt_enabled) {
1798                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1799                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1800         } else {
1801                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1802                 kvm_mmu_reset_context(&svm->vcpu);
1803         }
1804         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
1805         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1806         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1807         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1808         /* In case we don't even reach vcpu_run, the fields are not updated */
1809         svm->vmcb->save.rax = nested_vmcb->save.rax;
1810         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1811         svm->vmcb->save.rip = nested_vmcb->save.rip;
1812         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1813         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1814         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1815
1816         /* We don't want a nested guest to be more powerful than the guest,
1817            so all intercepts are ORed */
1818         svm->vmcb->control.intercept_cr_read |=
1819                 nested_vmcb->control.intercept_cr_read;
1820         svm->vmcb->control.intercept_cr_write |=
1821                 nested_vmcb->control.intercept_cr_write;
1822         svm->vmcb->control.intercept_dr_read |=
1823                 nested_vmcb->control.intercept_dr_read;
1824         svm->vmcb->control.intercept_dr_write |=
1825                 nested_vmcb->control.intercept_dr_write;
1826         svm->vmcb->control.intercept_exceptions |=
1827                 nested_vmcb->control.intercept_exceptions;
1828
1829         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1830
1831         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1832
1833         /* cache intercepts */
1834         svm->nested.intercept_cr_read    = nested_vmcb->control.intercept_cr_read;
1835         svm->nested.intercept_cr_write   = nested_vmcb->control.intercept_cr_write;
1836         svm->nested.intercept_dr_read    = nested_vmcb->control.intercept_dr_read;
1837         svm->nested.intercept_dr_write   = nested_vmcb->control.intercept_dr_write;
1838         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1839         svm->nested.intercept            = nested_vmcb->control.intercept;
1840
1841         force_new_asid(&svm->vcpu);
1842         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1843         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1844                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1845         else
1846                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1847
1848         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1849         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1850         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1851         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1852         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1853
1854         nested_svm_unmap(nested_vmcb, KM_USER0);
1855
1856         enable_gif(svm);
1857
1858         return true;
1859 }
1860
1861 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1862 {
1863         to_vmcb->save.fs = from_vmcb->save.fs;
1864         to_vmcb->save.gs = from_vmcb->save.gs;
1865         to_vmcb->save.tr = from_vmcb->save.tr;
1866         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1867         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1868         to_vmcb->save.star = from_vmcb->save.star;
1869         to_vmcb->save.lstar = from_vmcb->save.lstar;
1870         to_vmcb->save.cstar = from_vmcb->save.cstar;
1871         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1872         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1873         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1874         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1875 }
1876
1877 static int vmload_interception(struct vcpu_svm *svm)
1878 {
1879         struct vmcb *nested_vmcb;
1880
1881         if (nested_svm_check_permissions(svm))
1882                 return 1;
1883
1884         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1885         skip_emulated_instruction(&svm->vcpu);
1886
1887         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1888         if (!nested_vmcb)
1889                 return 1;
1890
1891         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1892         nested_svm_unmap(nested_vmcb, KM_USER0);
1893
1894         return 1;
1895 }
1896
1897 static int vmsave_interception(struct vcpu_svm *svm)
1898 {
1899         struct vmcb *nested_vmcb;
1900
1901         if (nested_svm_check_permissions(svm))
1902                 return 1;
1903
1904         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1905         skip_emulated_instruction(&svm->vcpu);
1906
1907         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1908         if (!nested_vmcb)
1909                 return 1;
1910
1911         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1912         nested_svm_unmap(nested_vmcb, KM_USER0);
1913
1914         return 1;
1915 }
1916
1917 static int vmrun_interception(struct vcpu_svm *svm)
1918 {
1919         if (nested_svm_check_permissions(svm))
1920                 return 1;
1921
1922         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1923         skip_emulated_instruction(&svm->vcpu);
1924
1925         if (!nested_svm_vmrun(svm))
1926                 return 1;
1927
1928         if (!nested_svm_vmrun_msrpm(svm))
1929                 goto failed;
1930
1931         return 1;
1932
1933 failed:
1934
1935         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
1936         svm->vmcb->control.exit_code_hi = 0;
1937         svm->vmcb->control.exit_info_1  = 0;
1938         svm->vmcb->control.exit_info_2  = 0;
1939
1940         nested_svm_vmexit(svm);
1941
1942         return 1;
1943 }
1944
1945 static int stgi_interception(struct vcpu_svm *svm)
1946 {
1947         if (nested_svm_check_permissions(svm))
1948                 return 1;
1949
1950         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1951         skip_emulated_instruction(&svm->vcpu);
1952
1953         enable_gif(svm);
1954
1955         return 1;
1956 }
1957
1958 static int clgi_interception(struct vcpu_svm *svm)
1959 {
1960         if (nested_svm_check_permissions(svm))
1961                 return 1;
1962
1963         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1964         skip_emulated_instruction(&svm->vcpu);
1965
1966         disable_gif(svm);
1967
1968         /* After a CLGI no interrupts should come */
1969         svm_clear_vintr(svm);
1970         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1971
1972         return 1;
1973 }
1974
1975 static int invlpga_interception(struct vcpu_svm *svm)
1976 {
1977         struct kvm_vcpu *vcpu = &svm->vcpu;
1978
1979         trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
1980                           vcpu->arch.regs[VCPU_REGS_RAX]);
1981
1982         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1983         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1984
1985         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1986         skip_emulated_instruction(&svm->vcpu);
1987         return 1;
1988 }
1989
1990 static int skinit_interception(struct vcpu_svm *svm)
1991 {
1992         trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
1993
1994         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1995         return 1;
1996 }
1997
1998 static int invalid_op_interception(struct vcpu_svm *svm)
1999 {
2000         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2001         return 1;
2002 }
2003
2004 static int task_switch_interception(struct vcpu_svm *svm)
2005 {
2006         u16 tss_selector;
2007         int reason;
2008         int int_type = svm->vmcb->control.exit_int_info &
2009                 SVM_EXITINTINFO_TYPE_MASK;
2010         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2011         uint32_t type =
2012                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2013         uint32_t idt_v =
2014                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2015
2016         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2017
2018         if (svm->vmcb->control.exit_info_2 &
2019             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2020                 reason = TASK_SWITCH_IRET;
2021         else if (svm->vmcb->control.exit_info_2 &
2022                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2023                 reason = TASK_SWITCH_JMP;
2024         else if (idt_v)
2025                 reason = TASK_SWITCH_GATE;
2026         else
2027                 reason = TASK_SWITCH_CALL;
2028
2029         if (reason == TASK_SWITCH_GATE) {
2030                 switch (type) {
2031                 case SVM_EXITINTINFO_TYPE_NMI:
2032                         svm->vcpu.arch.nmi_injected = false;
2033                         break;
2034                 case SVM_EXITINTINFO_TYPE_EXEPT:
2035                         kvm_clear_exception_queue(&svm->vcpu);
2036                         break;
2037                 case SVM_EXITINTINFO_TYPE_INTR:
2038                         kvm_clear_interrupt_queue(&svm->vcpu);
2039                         break;
2040                 default:
2041                         break;
2042                 }
2043         }
2044
2045         if (reason != TASK_SWITCH_GATE ||
2046             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2047             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2048              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2049                 skip_emulated_instruction(&svm->vcpu);
2050
2051         return kvm_task_switch(&svm->vcpu, tss_selector, reason);
2052 }
2053
2054 static int cpuid_interception(struct vcpu_svm *svm)
2055 {
2056         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2057         kvm_emulate_cpuid(&svm->vcpu);
2058         return 1;
2059 }
2060
2061 static int iret_interception(struct vcpu_svm *svm)
2062 {
2063         ++svm->vcpu.stat.nmi_window_exits;
2064         svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2065         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2066         return 1;
2067 }
2068
2069 static int invlpg_interception(struct vcpu_svm *svm)
2070 {
2071         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2072                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2073         return 1;
2074 }
2075
2076 static int emulate_on_interception(struct vcpu_svm *svm)
2077 {
2078         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2079                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2080         return 1;
2081 }
2082
2083 static int cr8_write_interception(struct vcpu_svm *svm)
2084 {
2085         struct kvm_run *kvm_run = svm->vcpu.run;
2086
2087         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2088         /* instruction emulation calls kvm_set_cr8() */
2089         emulate_instruction(&svm->vcpu, 0, 0, 0);
2090         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2091                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2092                 return 1;
2093         }
2094         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2095                 return 1;
2096         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2097         return 0;
2098 }
2099
2100 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2101 {
2102         struct vcpu_svm *svm = to_svm(vcpu);
2103
2104         switch (ecx) {
2105         case MSR_IA32_TSC: {
2106                 u64 tsc_offset;
2107
2108                 if (is_nested(svm))
2109                         tsc_offset = svm->nested.hsave->control.tsc_offset;
2110                 else
2111                         tsc_offset = svm->vmcb->control.tsc_offset;
2112
2113                 *data = tsc_offset + native_read_tsc();
2114                 break;
2115         }
2116         case MSR_K6_STAR:
2117                 *data = svm->vmcb->save.star;
2118                 break;
2119 #ifdef CONFIG_X86_64
2120         case MSR_LSTAR:
2121                 *data = svm->vmcb->save.lstar;
2122                 break;
2123         case MSR_CSTAR:
2124                 *data = svm->vmcb->save.cstar;
2125                 break;
2126         case MSR_KERNEL_GS_BASE:
2127                 *data = svm->vmcb->save.kernel_gs_base;
2128                 break;
2129         case MSR_SYSCALL_MASK:
2130                 *data = svm->vmcb->save.sfmask;
2131                 break;
2132 #endif
2133         case MSR_IA32_SYSENTER_CS:
2134                 *data = svm->vmcb->save.sysenter_cs;
2135                 break;
2136         case MSR_IA32_SYSENTER_EIP:
2137                 *data = svm->sysenter_eip;
2138                 break;
2139         case MSR_IA32_SYSENTER_ESP:
2140                 *data = svm->sysenter_esp;
2141                 break;
2142         /* Nobody will change the following 5 values in the VMCB so
2143            we can safely return them on rdmsr. They will always be 0
2144            until LBRV is implemented. */
2145         case MSR_IA32_DEBUGCTLMSR:
2146                 *data = svm->vmcb->save.dbgctl;
2147                 break;
2148         case MSR_IA32_LASTBRANCHFROMIP:
2149                 *data = svm->vmcb->save.br_from;
2150                 break;
2151         case MSR_IA32_LASTBRANCHTOIP:
2152                 *data = svm->vmcb->save.br_to;
2153                 break;
2154         case MSR_IA32_LASTINTFROMIP:
2155                 *data = svm->vmcb->save.last_excp_from;
2156                 break;
2157         case MSR_IA32_LASTINTTOIP:
2158                 *data = svm->vmcb->save.last_excp_to;
2159                 break;
2160         case MSR_VM_HSAVE_PA:
2161                 *data = svm->nested.hsave_msr;
2162                 break;
2163         case MSR_VM_CR:
2164                 *data = 0;
2165                 break;
2166         case MSR_IA32_UCODE_REV:
2167                 *data = 0x01000065;
2168                 break;
2169         default:
2170                 return kvm_get_msr_common(vcpu, ecx, data);
2171         }
2172         return 0;
2173 }
2174
2175 static int rdmsr_interception(struct vcpu_svm *svm)
2176 {
2177         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2178         u64 data;
2179
2180         if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2181                 trace_kvm_msr_read_ex(ecx);
2182                 kvm_inject_gp(&svm->vcpu, 0);
2183         } else {
2184                 trace_kvm_msr_read(ecx, data);
2185
2186                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2187                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2188                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2189                 skip_emulated_instruction(&svm->vcpu);
2190         }
2191         return 1;
2192 }
2193
2194 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2195 {
2196         struct vcpu_svm *svm = to_svm(vcpu);
2197
2198         switch (ecx) {
2199         case MSR_IA32_TSC: {
2200                 u64 tsc_offset = data - native_read_tsc();
2201                 u64 g_tsc_offset = 0;
2202
2203                 if (is_nested(svm)) {
2204                         g_tsc_offset = svm->vmcb->control.tsc_offset -
2205                                        svm->nested.hsave->control.tsc_offset;
2206                         svm->nested.hsave->control.tsc_offset = tsc_offset;
2207                 }
2208
2209                 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2210
2211                 break;
2212         }
2213         case MSR_K6_STAR:
2214                 svm->vmcb->save.star = data;
2215                 break;
2216 #ifdef CONFIG_X86_64
2217         case MSR_LSTAR:
2218                 svm->vmcb->save.lstar = data;
2219                 break;
2220         case MSR_CSTAR:
2221                 svm->vmcb->save.cstar = data;
2222                 break;
2223         case MSR_KERNEL_GS_BASE:
2224                 svm->vmcb->save.kernel_gs_base = data;
2225                 break;
2226         case MSR_SYSCALL_MASK:
2227                 svm->vmcb->save.sfmask = data;
2228                 break;
2229 #endif
2230         case MSR_IA32_SYSENTER_CS:
2231                 svm->vmcb->save.sysenter_cs = data;
2232                 break;
2233         case MSR_IA32_SYSENTER_EIP:
2234                 svm->sysenter_eip = data;
2235                 svm->vmcb->save.sysenter_eip = data;
2236                 break;
2237         case MSR_IA32_SYSENTER_ESP:
2238                 svm->sysenter_esp = data;
2239                 svm->vmcb->save.sysenter_esp = data;
2240                 break;
2241         case MSR_IA32_DEBUGCTLMSR:
2242                 if (!svm_has(SVM_FEATURE_LBRV)) {
2243                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2244                                         __func__, data);
2245                         break;
2246                 }
2247                 if (data & DEBUGCTL_RESERVED_BITS)
2248                         return 1;
2249
2250                 svm->vmcb->save.dbgctl = data;
2251                 if (data & (1ULL<<0))
2252                         svm_enable_lbrv(svm);
2253                 else
2254                         svm_disable_lbrv(svm);
2255                 break;
2256         case MSR_VM_HSAVE_PA:
2257                 svm->nested.hsave_msr = data;
2258                 break;
2259         case MSR_VM_CR:
2260         case MSR_VM_IGNNE:
2261                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2262                 break;
2263         default:
2264                 return kvm_set_msr_common(vcpu, ecx, data);
2265         }
2266         return 0;
2267 }
2268
2269 static int wrmsr_interception(struct vcpu_svm *svm)
2270 {
2271         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2272         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2273                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2274
2275
2276         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2277         if (svm_set_msr(&svm->vcpu, ecx, data)) {
2278                 trace_kvm_msr_write_ex(ecx, data);
2279                 kvm_inject_gp(&svm->vcpu, 0);
2280         } else {
2281                 trace_kvm_msr_write(ecx, data);
2282                 skip_emulated_instruction(&svm->vcpu);
2283         }
2284         return 1;
2285 }
2286
2287 static int msr_interception(struct vcpu_svm *svm)
2288 {
2289         if (svm->vmcb->control.exit_info_1)
2290                 return wrmsr_interception(svm);
2291         else
2292                 return rdmsr_interception(svm);
2293 }
2294
2295 static int interrupt_window_interception(struct vcpu_svm *svm)
2296 {
2297         struct kvm_run *kvm_run = svm->vcpu.run;
2298
2299         svm_clear_vintr(svm);
2300         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2301         /*
2302          * If the user space waits to inject interrupts, exit as soon as
2303          * possible
2304          */
2305         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2306             kvm_run->request_interrupt_window &&
2307             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2308                 ++svm->vcpu.stat.irq_window_exits;
2309                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2310                 return 0;
2311         }
2312
2313         return 1;
2314 }
2315
2316 static int pause_interception(struct vcpu_svm *svm)
2317 {
2318         kvm_vcpu_on_spin(&(svm->vcpu));
2319         return 1;
2320 }
2321
2322 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2323         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2324         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2325         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2326         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2327         [SVM_EXIT_CR0_SEL_WRITE]                = emulate_on_interception,
2328         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2329         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2330         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2331         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2332         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2333         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2334         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2335         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2336         [SVM_EXIT_READ_DR4]                     = emulate_on_interception,
2337         [SVM_EXIT_READ_DR5]                     = emulate_on_interception,
2338         [SVM_EXIT_READ_DR6]                     = emulate_on_interception,
2339         [SVM_EXIT_READ_DR7]                     = emulate_on_interception,
2340         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2341         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2342         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2343         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2344         [SVM_EXIT_WRITE_DR4]                    = emulate_on_interception,
2345         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2346         [SVM_EXIT_WRITE_DR6]                    = emulate_on_interception,
2347         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2348         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2349         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2350         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2351         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2352         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2353         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2354         [SVM_EXIT_INTR]                         = intr_interception,
2355         [SVM_EXIT_NMI]                          = nmi_interception,
2356         [SVM_EXIT_SMI]                          = nop_on_interception,
2357         [SVM_EXIT_INIT]                         = nop_on_interception,
2358         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2359         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
2360         [SVM_EXIT_CPUID]                        = cpuid_interception,
2361         [SVM_EXIT_IRET]                         = iret_interception,
2362         [SVM_EXIT_INVD]                         = emulate_on_interception,
2363         [SVM_EXIT_PAUSE]                        = pause_interception,
2364         [SVM_EXIT_HLT]                          = halt_interception,
2365         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2366         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2367         [SVM_EXIT_IOIO]                         = io_interception,
2368         [SVM_EXIT_MSR]                          = msr_interception,
2369         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2370         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2371         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2372         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2373         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2374         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2375         [SVM_EXIT_STGI]                         = stgi_interception,
2376         [SVM_EXIT_CLGI]                         = clgi_interception,
2377         [SVM_EXIT_SKINIT]                       = skinit_interception,
2378         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2379         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2380         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2381         [SVM_EXIT_NPF]                          = pf_interception,
2382 };
2383
2384 static int handle_exit(struct kvm_vcpu *vcpu)
2385 {
2386         struct vcpu_svm *svm = to_svm(vcpu);
2387         struct kvm_run *kvm_run = vcpu->run;
2388         u32 exit_code = svm->vmcb->control.exit_code;
2389
2390         trace_kvm_exit(exit_code, svm->vmcb->save.rip);
2391
2392         if (unlikely(svm->nested.exit_required)) {
2393                 nested_svm_vmexit(svm);
2394                 svm->nested.exit_required = false;
2395
2396                 return 1;
2397         }
2398
2399         if (is_nested(svm)) {
2400                 int vmexit;
2401
2402                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2403                                         svm->vmcb->control.exit_info_1,
2404                                         svm->vmcb->control.exit_info_2,
2405                                         svm->vmcb->control.exit_int_info,
2406                                         svm->vmcb->control.exit_int_info_err);
2407
2408                 vmexit = nested_svm_exit_special(svm);
2409
2410                 if (vmexit == NESTED_EXIT_CONTINUE)
2411                         vmexit = nested_svm_exit_handled(svm);
2412
2413                 if (vmexit == NESTED_EXIT_DONE)
2414                         return 1;
2415         }
2416
2417         svm_complete_interrupts(svm);
2418
2419         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2420                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2421         if (npt_enabled)
2422                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2423
2424         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2425                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2426                 kvm_run->fail_entry.hardware_entry_failure_reason
2427                         = svm->vmcb->control.exit_code;
2428                 return 0;
2429         }
2430
2431         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2432             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2433             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2434                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2435                        "exit_code 0x%x\n",
2436                        __func__, svm->vmcb->control.exit_int_info,
2437                        exit_code);
2438
2439         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2440             || !svm_exit_handlers[exit_code]) {
2441                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2442                 kvm_run->hw.hardware_exit_reason = exit_code;
2443                 return 0;
2444         }
2445
2446         return svm_exit_handlers[exit_code](svm);
2447 }
2448
2449 static void reload_tss(struct kvm_vcpu *vcpu)
2450 {
2451         int cpu = raw_smp_processor_id();
2452
2453         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2454         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
2455         load_TR_desc();
2456 }
2457
2458 static void pre_svm_run(struct vcpu_svm *svm)
2459 {
2460         int cpu = raw_smp_processor_id();
2461
2462         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2463
2464         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2465         /* FIXME: handle wraparound of asid_generation */
2466         if (svm->asid_generation != sd->asid_generation)
2467                 new_asid(svm, sd);
2468 }
2469
2470 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2471 {
2472         struct vcpu_svm *svm = to_svm(vcpu);
2473
2474         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2475         vcpu->arch.hflags |= HF_NMI_MASK;
2476         svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2477         ++vcpu->stat.nmi_injections;
2478 }
2479
2480 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2481 {
2482         struct vmcb_control_area *control;
2483
2484         trace_kvm_inj_virq(irq);
2485
2486         ++svm->vcpu.stat.irq_injections;
2487         control = &svm->vmcb->control;
2488         control->int_vector = irq;
2489         control->int_ctl &= ~V_INTR_PRIO_MASK;
2490         control->int_ctl |= V_IRQ_MASK |
2491                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2492 }
2493
2494 static void svm_set_irq(struct kvm_vcpu *vcpu)
2495 {
2496         struct vcpu_svm *svm = to_svm(vcpu);
2497
2498         BUG_ON(!(gif_set(svm)));
2499
2500         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2501                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2502 }
2503
2504 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2505 {
2506         struct vcpu_svm *svm = to_svm(vcpu);
2507
2508         if (irr == -1)
2509                 return;
2510
2511         if (tpr >= irr)
2512                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2513 }
2514
2515 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2516 {
2517         struct vcpu_svm *svm = to_svm(vcpu);
2518         struct vmcb *vmcb = svm->vmcb;
2519         return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2520                 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2521 }
2522
2523 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2524 {
2525         struct vcpu_svm *svm = to_svm(vcpu);
2526
2527         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2528 }
2529
2530 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2531 {
2532         struct vcpu_svm *svm = to_svm(vcpu);
2533
2534         if (masked) {
2535                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2536                 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2537         } else {
2538                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2539                 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2540         }
2541 }
2542
2543 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2544 {
2545         struct vcpu_svm *svm = to_svm(vcpu);
2546         struct vmcb *vmcb = svm->vmcb;
2547         int ret;
2548
2549         if (!gif_set(svm) ||
2550              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2551                 return 0;
2552
2553         ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2554
2555         if (is_nested(svm))
2556                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2557
2558         return ret;
2559 }
2560
2561 static void enable_irq_window(struct kvm_vcpu *vcpu)
2562 {
2563         struct vcpu_svm *svm = to_svm(vcpu);
2564
2565         nested_svm_intr(svm);
2566
2567         /* In case GIF=0 we can't rely on the CPU to tell us when
2568          * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2569          * The next time we get that intercept, this function will be
2570          * called again though and we'll get the vintr intercept. */
2571         if (gif_set(svm)) {
2572                 svm_set_vintr(svm);
2573                 svm_inject_irq(svm, 0x0);
2574         }
2575 }
2576
2577 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2578 {
2579         struct vcpu_svm *svm = to_svm(vcpu);
2580
2581         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2582             == HF_NMI_MASK)
2583                 return; /* IRET will cause a vm exit */
2584
2585         /* Something prevents NMI from been injected. Single step over
2586            possible problem (IRET or exception injection or interrupt
2587            shadow) */
2588         svm->nmi_singlestep = true;
2589         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2590         update_db_intercept(vcpu);
2591 }
2592
2593 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2594 {
2595         return 0;
2596 }
2597
2598 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2599 {
2600         force_new_asid(vcpu);
2601 }
2602
2603 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2604 {
2605 }
2606
2607 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2608 {
2609         struct vcpu_svm *svm = to_svm(vcpu);
2610
2611         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2612                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2613                 kvm_set_cr8(vcpu, cr8);
2614         }
2615 }
2616
2617 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2618 {
2619         struct vcpu_svm *svm = to_svm(vcpu);
2620         u64 cr8;
2621
2622         cr8 = kvm_get_cr8(vcpu);
2623         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2624         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2625 }
2626
2627 static void svm_complete_interrupts(struct vcpu_svm *svm)
2628 {
2629         u8 vector;
2630         int type;
2631         u32 exitintinfo = svm->vmcb->control.exit_int_info;
2632
2633         if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2634                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2635
2636         svm->vcpu.arch.nmi_injected = false;
2637         kvm_clear_exception_queue(&svm->vcpu);
2638         kvm_clear_interrupt_queue(&svm->vcpu);
2639
2640         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2641                 return;
2642
2643         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2644         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2645
2646         switch (type) {
2647         case SVM_EXITINTINFO_TYPE_NMI:
2648                 svm->vcpu.arch.nmi_injected = true;
2649                 break;
2650         case SVM_EXITINTINFO_TYPE_EXEPT:
2651                 /* In case of software exception do not reinject an exception
2652                    vector, but re-execute and instruction instead */
2653                 if (is_nested(svm))
2654                         break;
2655                 if (kvm_exception_is_soft(vector))
2656                         break;
2657                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2658                         u32 err = svm->vmcb->control.exit_int_info_err;
2659                         kvm_queue_exception_e(&svm->vcpu, vector, err);
2660
2661                 } else
2662                         kvm_queue_exception(&svm->vcpu, vector);
2663                 break;
2664         case SVM_EXITINTINFO_TYPE_INTR:
2665                 kvm_queue_interrupt(&svm->vcpu, vector, false);
2666                 break;
2667         default:
2668                 break;
2669         }
2670 }
2671
2672 #ifdef CONFIG_X86_64
2673 #define R "r"
2674 #else
2675 #define R "e"
2676 #endif
2677
2678 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
2679 {
2680         struct vcpu_svm *svm = to_svm(vcpu);
2681         u16 fs_selector;
2682         u16 gs_selector;
2683         u16 ldt_selector;
2684
2685         /*
2686          * A vmexit emulation is required before the vcpu can be executed
2687          * again.
2688          */
2689         if (unlikely(svm->nested.exit_required))
2690                 return;
2691
2692         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2693         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2694         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2695
2696         pre_svm_run(svm);
2697
2698         sync_lapic_to_cr8(vcpu);
2699
2700         save_host_msrs(vcpu);
2701         fs_selector = kvm_read_fs();
2702         gs_selector = kvm_read_gs();
2703         ldt_selector = kvm_read_ldt();
2704         svm->vmcb->save.cr2 = vcpu->arch.cr2;
2705         /* required for live migration with NPT */
2706         if (npt_enabled)
2707                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2708
2709         clgi();
2710
2711         local_irq_enable();
2712
2713         asm volatile (
2714                 "push %%"R"bp; \n\t"
2715                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2716                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2717                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2718                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2719                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2720                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2721 #ifdef CONFIG_X86_64
2722                 "mov %c[r8](%[svm]),  %%r8  \n\t"
2723                 "mov %c[r9](%[svm]),  %%r9  \n\t"
2724                 "mov %c[r10](%[svm]), %%r10 \n\t"
2725                 "mov %c[r11](%[svm]), %%r11 \n\t"
2726                 "mov %c[r12](%[svm]), %%r12 \n\t"
2727                 "mov %c[r13](%[svm]), %%r13 \n\t"
2728                 "mov %c[r14](%[svm]), %%r14 \n\t"
2729                 "mov %c[r15](%[svm]), %%r15 \n\t"
2730 #endif
2731
2732                 /* Enter guest mode */
2733                 "push %%"R"ax \n\t"
2734                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2735                 __ex(SVM_VMLOAD) "\n\t"
2736                 __ex(SVM_VMRUN) "\n\t"
2737                 __ex(SVM_VMSAVE) "\n\t"
2738                 "pop %%"R"ax \n\t"
2739
2740                 /* Save guest registers, load host registers */
2741                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2742                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2743                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2744                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2745                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2746                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2747 #ifdef CONFIG_X86_64
2748                 "mov %%r8,  %c[r8](%[svm]) \n\t"
2749                 "mov %%r9,  %c[r9](%[svm]) \n\t"
2750                 "mov %%r10, %c[r10](%[svm]) \n\t"
2751                 "mov %%r11, %c[r11](%[svm]) \n\t"
2752                 "mov %%r12, %c[r12](%[svm]) \n\t"
2753                 "mov %%r13, %c[r13](%[svm]) \n\t"
2754                 "mov %%r14, %c[r14](%[svm]) \n\t"
2755                 "mov %%r15, %c[r15](%[svm]) \n\t"
2756 #endif
2757                 "pop %%"R"bp"
2758                 :
2759                 : [svm]"a"(svm),
2760                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2761                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2762                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2763                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2764                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2765                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2766                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2767 #ifdef CONFIG_X86_64
2768                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2769                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2770                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2771                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2772                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2773                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2774                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2775                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2776 #endif
2777                 : "cc", "memory"
2778                 , R"bx", R"cx", R"dx", R"si", R"di"
2779 #ifdef CONFIG_X86_64
2780                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2781 #endif
2782                 );
2783
2784         vcpu->arch.cr2 = svm->vmcb->save.cr2;
2785         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2786         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2787         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2788
2789         kvm_load_fs(fs_selector);
2790         kvm_load_gs(gs_selector);
2791         kvm_load_ldt(ldt_selector);
2792         load_host_msrs(vcpu);
2793
2794         reload_tss(vcpu);
2795
2796         local_irq_disable();
2797
2798         stgi();
2799
2800         sync_cr8_to_lapic(vcpu);
2801
2802         svm->next_rip = 0;
2803
2804         if (npt_enabled) {
2805                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2806                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2807         }
2808 }
2809
2810 #undef R
2811
2812 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2813 {
2814         struct vcpu_svm *svm = to_svm(vcpu);
2815
2816         if (npt_enabled) {
2817                 svm->vmcb->control.nested_cr3 = root;
2818                 force_new_asid(vcpu);
2819                 return;
2820         }
2821
2822         svm->vmcb->save.cr3 = root;
2823         force_new_asid(vcpu);
2824 }
2825
2826 static int is_disabled(void)
2827 {
2828         u64 vm_cr;
2829
2830         rdmsrl(MSR_VM_CR, vm_cr);
2831         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2832                 return 1;
2833
2834         return 0;
2835 }
2836
2837 static void
2838 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2839 {
2840         /*
2841          * Patch in the VMMCALL instruction:
2842          */
2843         hypercall[0] = 0x0f;
2844         hypercall[1] = 0x01;
2845         hypercall[2] = 0xd9;
2846 }
2847
2848 static void svm_check_processor_compat(void *rtn)
2849 {
2850         *(int *)rtn = 0;
2851 }
2852
2853 static bool svm_cpu_has_accelerated_tpr(void)
2854 {
2855         return false;
2856 }
2857
2858 static int get_npt_level(void)
2859 {
2860 #ifdef CONFIG_X86_64
2861         return PT64_ROOT_LEVEL;
2862 #else
2863         return PT32E_ROOT_LEVEL;
2864 #endif
2865 }
2866
2867 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
2868 {
2869         return 0;
2870 }
2871
2872 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
2873 {
2874 }
2875
2876 static const struct trace_print_flags svm_exit_reasons_str[] = {
2877         { SVM_EXIT_READ_CR0,                    "read_cr0" },
2878         { SVM_EXIT_READ_CR3,                    "read_cr3" },
2879         { SVM_EXIT_READ_CR4,                    "read_cr4" },
2880         { SVM_EXIT_READ_CR8,                    "read_cr8" },
2881         { SVM_EXIT_WRITE_CR0,                   "write_cr0" },
2882         { SVM_EXIT_WRITE_CR3,                   "write_cr3" },
2883         { SVM_EXIT_WRITE_CR4,                   "write_cr4" },
2884         { SVM_EXIT_WRITE_CR8,                   "write_cr8" },
2885         { SVM_EXIT_READ_DR0,                    "read_dr0" },
2886         { SVM_EXIT_READ_DR1,                    "read_dr1" },
2887         { SVM_EXIT_READ_DR2,                    "read_dr2" },
2888         { SVM_EXIT_READ_DR3,                    "read_dr3" },
2889         { SVM_EXIT_WRITE_DR0,                   "write_dr0" },
2890         { SVM_EXIT_WRITE_DR1,                   "write_dr1" },
2891         { SVM_EXIT_WRITE_DR2,                   "write_dr2" },
2892         { SVM_EXIT_WRITE_DR3,                   "write_dr3" },
2893         { SVM_EXIT_WRITE_DR5,                   "write_dr5" },
2894         { SVM_EXIT_WRITE_DR7,                   "write_dr7" },
2895         { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" },
2896         { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" },
2897         { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" },
2898         { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" },
2899         { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" },
2900         { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" },
2901         { SVM_EXIT_INTR,                        "interrupt" },
2902         { SVM_EXIT_NMI,                         "nmi" },
2903         { SVM_EXIT_SMI,                         "smi" },
2904         { SVM_EXIT_INIT,                        "init" },
2905         { SVM_EXIT_VINTR,                       "vintr" },
2906         { SVM_EXIT_CPUID,                       "cpuid" },
2907         { SVM_EXIT_INVD,                        "invd" },
2908         { SVM_EXIT_HLT,                         "hlt" },
2909         { SVM_EXIT_INVLPG,                      "invlpg" },
2910         { SVM_EXIT_INVLPGA,                     "invlpga" },
2911         { SVM_EXIT_IOIO,                        "io" },
2912         { SVM_EXIT_MSR,                         "msr" },
2913         { SVM_EXIT_TASK_SWITCH,                 "task_switch" },
2914         { SVM_EXIT_SHUTDOWN,                    "shutdown" },
2915         { SVM_EXIT_VMRUN,                       "vmrun" },
2916         { SVM_EXIT_VMMCALL,                     "hypercall" },
2917         { SVM_EXIT_VMLOAD,                      "vmload" },
2918         { SVM_EXIT_VMSAVE,                      "vmsave" },
2919         { SVM_EXIT_STGI,                        "stgi" },
2920         { SVM_EXIT_CLGI,                        "clgi" },
2921         { SVM_EXIT_SKINIT,                      "skinit" },
2922         { SVM_EXIT_WBINVD,                      "wbinvd" },
2923         { SVM_EXIT_MONITOR,                     "monitor" },
2924         { SVM_EXIT_MWAIT,                       "mwait" },
2925         { SVM_EXIT_NPF,                         "npf" },
2926         { -1, NULL }
2927 };
2928
2929 static int svm_get_lpage_level(void)
2930 {
2931         return PT_PDPE_LEVEL;
2932 }
2933
2934 static bool svm_rdtscp_supported(void)
2935 {
2936         return false;
2937 }
2938
2939 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
2940 {
2941         struct vcpu_svm *svm = to_svm(vcpu);
2942
2943         update_cr0_intercept(svm);
2944         svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
2945 }
2946
2947 static struct kvm_x86_ops svm_x86_ops = {
2948         .cpu_has_kvm_support = has_svm,
2949         .disabled_by_bios = is_disabled,
2950         .hardware_setup = svm_hardware_setup,
2951         .hardware_unsetup = svm_hardware_unsetup,
2952         .check_processor_compatibility = svm_check_processor_compat,
2953         .hardware_enable = svm_hardware_enable,
2954         .hardware_disable = svm_hardware_disable,
2955         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2956
2957         .vcpu_create = svm_create_vcpu,
2958         .vcpu_free = svm_free_vcpu,
2959         .vcpu_reset = svm_vcpu_reset,
2960
2961         .prepare_guest_switch = svm_prepare_guest_switch,
2962         .vcpu_load = svm_vcpu_load,
2963         .vcpu_put = svm_vcpu_put,
2964
2965         .set_guest_debug = svm_guest_debug,
2966         .get_msr = svm_get_msr,
2967         .set_msr = svm_set_msr,
2968         .get_segment_base = svm_get_segment_base,
2969         .get_segment = svm_get_segment,
2970         .set_segment = svm_set_segment,
2971         .get_cpl = svm_get_cpl,
2972         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2973         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
2974         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2975         .set_cr0 = svm_set_cr0,
2976         .set_cr3 = svm_set_cr3,
2977         .set_cr4 = svm_set_cr4,
2978         .set_efer = svm_set_efer,
2979         .get_idt = svm_get_idt,
2980         .set_idt = svm_set_idt,
2981         .get_gdt = svm_get_gdt,
2982         .set_gdt = svm_set_gdt,
2983         .get_dr = svm_get_dr,
2984         .set_dr = svm_set_dr,
2985         .cache_reg = svm_cache_reg,
2986         .get_rflags = svm_get_rflags,
2987         .set_rflags = svm_set_rflags,
2988         .fpu_activate = svm_fpu_activate,
2989         .fpu_deactivate = svm_fpu_deactivate,
2990
2991         .tlb_flush = svm_flush_tlb,
2992
2993         .run = svm_vcpu_run,
2994         .handle_exit = handle_exit,
2995         .skip_emulated_instruction = skip_emulated_instruction,
2996         .set_interrupt_shadow = svm_set_interrupt_shadow,
2997         .get_interrupt_shadow = svm_get_interrupt_shadow,
2998         .patch_hypercall = svm_patch_hypercall,
2999         .set_irq = svm_set_irq,
3000         .set_nmi = svm_inject_nmi,
3001         .queue_exception = svm_queue_exception,
3002         .interrupt_allowed = svm_interrupt_allowed,
3003         .nmi_allowed = svm_nmi_allowed,
3004         .get_nmi_mask = svm_get_nmi_mask,
3005         .set_nmi_mask = svm_set_nmi_mask,
3006         .enable_nmi_window = enable_nmi_window,
3007         .enable_irq_window = enable_irq_window,
3008         .update_cr8_intercept = update_cr8_intercept,
3009
3010         .set_tss_addr = svm_set_tss_addr,
3011         .get_tdp_level = get_npt_level,
3012         .get_mt_mask = svm_get_mt_mask,
3013
3014         .exit_reasons_str = svm_exit_reasons_str,
3015         .get_lpage_level = svm_get_lpage_level,
3016
3017         .cpuid_update = svm_cpuid_update,
3018
3019         .rdtscp_supported = svm_rdtscp_supported,
3020 };
3021
3022 static int __init svm_init(void)
3023 {
3024         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3025                               THIS_MODULE);
3026 }
3027
3028 static void __exit svm_exit(void)
3029 {
3030         kvm_exit();
3031 }
3032
3033 module_init(svm_init)
3034 module_exit(svm_exit)