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   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20 #include "kvm_cache_regs.h"
  21 #include "x86.h"
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/ftrace_event.h>
  29
  30 #include <asm/desc.h>
  31
  32 #include <asm/virtext.h>
  33 #include "trace.h"
  34
  35 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  36
  37 MODULE_AUTHOR("Qumranet");
  38 MODULE_LICENSE("GPL");
  39
  40 #define IOPM_ALLOC_ORDER 2
  41 #define MSRPM_ALLOC_ORDER 1
  42
  43 #define SEG_TYPE_LDT 2
  44 #define SEG_TYPE_BUSY_TSS16 3
  45
  46 #define SVM_FEATURE_NPT  (1 << 0)
  47 #define SVM_FEATURE_LBRV (1 << 1)
  48 #define SVM_FEATURE_SVML (1 << 2)
  49 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
  50
  51 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  52 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  53 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  54
  55 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  56
  57 static const u32 host_save_user_msrs[] = {
  58 #ifdef CONFIG_X86_64
  59         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  60         MSR_FS_BASE,
  61 #endif
  62         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  63 };
  64
  65 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  66
  67 struct kvm_vcpu;
  68
  69 struct nested_state {
  70         struct vmcb *hsave;
  71         u64 hsave_msr;
  72         u64 vmcb;
  73
  74         /* These are the merged vectors */
  75         u32 *msrpm;
  76
  77         /* gpa pointers to the real vectors */
  78         u64 vmcb_msrpm;
  79
  80         /* A VMEXIT is required but not yet emulated */
  81         bool exit_required;
  82
  83         /* cache for intercepts of the guest */
  84         u16 intercept_cr_read;
  85         u16 intercept_cr_write;
  86         u16 intercept_dr_read;
  87         u16 intercept_dr_write;
  88         u32 intercept_exceptions;
  89         u64 intercept;
  90
  91 };
  92
  93 struct vcpu_svm {
  94         struct kvm_vcpu vcpu;
  95         struct vmcb *vmcb;
  96         unsigned long vmcb_pa;
  97         struct svm_cpu_data *svm_data;
  98         uint64_t asid_generation;
  99         uint64_t sysenter_esp;
 100         uint64_t sysenter_eip;
 101
 102         u64 next_rip;
 103
 104         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 105         u64 host_gs_base;
 106
 107         u32 *msrpm;
 108
 109         struct nested_state nested;
 110 };
 111
 112 /* enable NPT for AMD64 and X86 with PAE */
 113 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 114 static bool npt_enabled = true;
 115 #else
 116 static bool npt_enabled = false;
 117 #endif
 118 static int npt = 1;
 119
 120 module_param(npt, int, S_IRUGO);
 121
 122 static int nested = 1;
 123 module_param(nested, int, S_IRUGO);
 124
 125 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 126 static void svm_complete_interrupts(struct vcpu_svm *svm);
 127
 128 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 129 static int nested_svm_vmexit(struct vcpu_svm *svm);
 130 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 131                                       bool has_error_code, u32 error_code);
 132
 133 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 134 {
 135         return container_of(vcpu, struct vcpu_svm, vcpu);
 136 }
 137
 138 static inline bool is_nested(struct vcpu_svm *svm)
 139 {
 140         return svm->nested.vmcb;
 141 }
 142
 143 static inline void enable_gif(struct vcpu_svm *svm)
 144 {
 145         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 146 }
 147
 148 static inline void disable_gif(struct vcpu_svm *svm)
 149 {
 150         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 151 }
 152
 153 static inline bool gif_set(struct vcpu_svm *svm)
 154 {
 155         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 156 }
 157
 158 static unsigned long iopm_base;
 159
 160 struct kvm_ldttss_desc {
 161         u16 limit0;
 162         u16 base0;
 163         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
 164         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
 165         u32 base3;
 166         u32 zero1;
 167 } __attribute__((packed));
 168
 169 struct svm_cpu_data {
 170         int cpu;
 171
 172         u64 asid_generation;
 173         u32 max_asid;
 174         u32 next_asid;
 175         struct kvm_ldttss_desc *tss_desc;
 176
 177         struct page *save_area;
 178 };
 179
 180 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 181 static uint32_t svm_features;
 182
 183 struct svm_init_data {
 184         int cpu;
 185         int r;
 186 };
 187
 188 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 189
 190 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 191 #define MSRS_RANGE_SIZE 2048
 192 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 193
 194 #define MAX_INST_SIZE 15
 195
 196 static inline u32 svm_has(u32 feat)
 197 {
 198         return svm_features & feat;
 199 }
 200
 201 static inline void clgi(void)
 202 {
 203         asm volatile (__ex(SVM_CLGI));
 204 }
 205
 206 static inline void stgi(void)
 207 {
 208         asm volatile (__ex(SVM_STGI));
 209 }
 210
 211 static inline void invlpga(unsigned long addr, u32 asid)
 212 {
 213         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 214 }
 215
 216 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 217 {
 218         to_svm(vcpu)->asid_generation--;
 219 }
 220
 221 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 222 {
 223         force_new_asid(vcpu);
 224 }
 225
 226 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 227 {
 228         if (!npt_enabled && !(efer & EFER_LMA))
 229                 efer &= ~EFER_LME;
 230
 231         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 232         vcpu->arch.shadow_efer = efer;
 233 }
 234
 235 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 236                                 bool has_error_code, u32 error_code)
 237 {
 238         struct vcpu_svm *svm = to_svm(vcpu);
 239
 240         /* If we are within a nested VM we'd better #VMEXIT and let the
 241            guest handle the exception */
 242         if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
 243                 return;
 244
 245         svm->vmcb->control.event_inj = nr
 246                 | SVM_EVTINJ_VALID
 247                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 248                 | SVM_EVTINJ_TYPE_EXEPT;
 249         svm->vmcb->control.event_inj_err = error_code;
 250 }
 251
 252 static int is_external_interrupt(u32 info)
 253 {
 254         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 255         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 256 }
 257
 258 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 259 {
 260         struct vcpu_svm *svm = to_svm(vcpu);
 261         u32 ret = 0;
 262
 263         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 264                 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
 265         return ret & mask;
 266 }
 267
 268 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 269 {
 270         struct vcpu_svm *svm = to_svm(vcpu);
 271
 272         if (mask == 0)
 273                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 274         else
 275                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 276
 277 }
 278
 279 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 280 {
 281         struct vcpu_svm *svm = to_svm(vcpu);
 282
 283         if (!svm->next_rip) {
 284                 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
 285                                 EMULATE_DONE)
 286                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 287                 return;
 288         }
 289         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 290                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 291                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 292
 293         kvm_rip_write(vcpu, svm->next_rip);
 294         svm_set_interrupt_shadow(vcpu, 0);
 295 }
 296
 297 static int has_svm(void)
 298 {
 299         const char *msg;
 300
 301         if (!cpu_has_svm(&msg)) {
 302                 printk(KERN_INFO "has_svm: %s\n", msg);
 303                 return 0;
 304         }
 305
 306         return 1;
 307 }
 308
 309 static void svm_hardware_disable(void *garbage)
 310 {
 311         cpu_svm_disable();
 312 }
 313
 314 static int svm_hardware_enable(void *garbage)
 315 {
 316
 317         struct svm_cpu_data *svm_data;
 318         uint64_t efer;
 319         struct descriptor_table gdt_descr;
 320         struct desc_struct *gdt;
 321         int me = raw_smp_processor_id();
 322
 323         rdmsrl(MSR_EFER, efer);
 324         if (efer & EFER_SVME)
 325                 return -EBUSY;
 326
 327         if (!has_svm()) {
 328                 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
 329                        me);
 330                 return -EINVAL;
 331         }
 332         svm_data = per_cpu(svm_data, me);
 333
 334         if (!svm_data) {
 335                 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
 336                        me);
 337                 return -EINVAL;
 338         }
 339
 340         svm_data->asid_generation = 1;
 341         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 342         svm_data->next_asid = svm_data->max_asid + 1;
 343
 344         kvm_get_gdt(&gdt_descr);
 345         gdt = (struct desc_struct *)gdt_descr.base;
 346         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 347
 348         wrmsrl(MSR_EFER, efer | EFER_SVME);
 349
 350         wrmsrl(MSR_VM_HSAVE_PA,
 351                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 352
 353         return 0;
 354 }
 355
 356 static void svm_cpu_uninit(int cpu)
 357 {
 358         struct svm_cpu_data *svm_data
 359                 = per_cpu(svm_data, raw_smp_processor_id());
 360
 361         if (!svm_data)
 362                 return;
 363
 364         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 365         __free_page(svm_data->save_area);
 366         kfree(svm_data);
 367 }
 368
 369 static int svm_cpu_init(int cpu)
 370 {
 371         struct svm_cpu_data *svm_data;
 372         int r;
 373
 374         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 375         if (!svm_data)
 376                 return -ENOMEM;
 377         svm_data->cpu = cpu;
 378         svm_data->save_area = alloc_page(GFP_KERNEL);
 379         r = -ENOMEM;
 380         if (!svm_data->save_area)
 381                 goto err_1;
 382
 383         per_cpu(svm_data, cpu) = svm_data;
 384
 385         return 0;
 386
 387 err_1:
 388         kfree(svm_data);
 389         return r;
 390
 391 }
 392
 393 static void set_msr_interception(u32 *msrpm, unsigned msr,
 394                                  int read, int write)
 395 {
 396         int i;
 397
 398         for (i = 0; i < NUM_MSR_MAPS; i++) {
 399                 if (msr >= msrpm_ranges[i] &&
 400                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 401                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 402                                           msrpm_ranges[i]) * 2;
 403
 404                         u32 *base = msrpm + (msr_offset / 32);
 405                         u32 msr_shift = msr_offset % 32;
 406                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 407                         *base = (*base & ~(0x3 << msr_shift)) |
 408                                 (mask << msr_shift);
 409                         return;
 410                 }
 411         }
 412         BUG();
 413 }
 414
 415 static void svm_vcpu_init_msrpm(u32 *msrpm)
 416 {
 417         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 418
 419 #ifdef CONFIG_X86_64
 420         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 421         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 422         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 423         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 424         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 425         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 426 #endif
 427         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 428         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 429 }
 430
 431 static void svm_enable_lbrv(struct vcpu_svm *svm)
 432 {
 433         u32 *msrpm = svm->msrpm;
 434
 435         svm->vmcb->control.lbr_ctl = 1;
 436         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 437         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 438         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 439         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 440 }
 441
 442 static void svm_disable_lbrv(struct vcpu_svm *svm)
 443 {
 444         u32 *msrpm = svm->msrpm;
 445
 446         svm->vmcb->control.lbr_ctl = 0;
 447         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 448         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 449         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 450         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 451 }
 452
 453 static __init int svm_hardware_setup(void)
 454 {
 455         int cpu;
 456         struct page *iopm_pages;
 457         void *iopm_va;
 458         int r;
 459
 460         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 461
 462         if (!iopm_pages)
 463                 return -ENOMEM;
 464
 465         iopm_va = page_address(iopm_pages);
 466         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 467         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 468
 469         if (boot_cpu_has(X86_FEATURE_NX))
 470                 kvm_enable_efer_bits(EFER_NX);
 471
 472         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 473                 kvm_enable_efer_bits(EFER_FFXSR);
 474
 475         if (nested) {
 476                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 477                 kvm_enable_efer_bits(EFER_SVME);
 478         }
 479
 480         for_each_possible_cpu(cpu) {
 481                 r = svm_cpu_init(cpu);
 482                 if (r)
 483                         goto err;
 484         }
 485
 486         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 487
 488         if (!svm_has(SVM_FEATURE_NPT))
 489                 npt_enabled = false;
 490
 491         if (npt_enabled && !npt) {
 492                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 493                 npt_enabled = false;
 494         }
 495
 496         if (npt_enabled) {
 497                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 498                 kvm_enable_tdp();
 499         } else
 500                 kvm_disable_tdp();
 501
 502         return 0;
 503
 504 err:
 505         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 506         iopm_base = 0;
 507         return r;
 508 }
 509
 510 static __exit void svm_hardware_unsetup(void)
 511 {
 512         int cpu;
 513
 514         for_each_possible_cpu(cpu)
 515                 svm_cpu_uninit(cpu);
 516
 517         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 518         iopm_base = 0;
 519 }
 520
 521 static void init_seg(struct vmcb_seg *seg)
 522 {
 523         seg->selector = 0;
 524         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 525                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 526         seg->limit = 0xffff;
 527         seg->base = 0;
 528 }
 529
 530 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 531 {
 532         seg->selector = 0;
 533         seg->attrib = SVM_SELECTOR_P_MASK | type;
 534         seg->limit = 0xffff;
 535         seg->base = 0;
 536 }
 537
 538 static void init_vmcb(struct vcpu_svm *svm)
 539 {
 540         struct vmcb_control_area *control = &svm->vmcb->control;
 541         struct vmcb_save_area *save = &svm->vmcb->save;
 542
 543         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 544                                         INTERCEPT_CR3_MASK |
 545                                         INTERCEPT_CR4_MASK;
 546
 547         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 548                                         INTERCEPT_CR3_MASK |
 549                                         INTERCEPT_CR4_MASK |
 550                                         INTERCEPT_CR8_MASK;
 551
 552         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 553                                         INTERCEPT_DR1_MASK |
 554                                         INTERCEPT_DR2_MASK |
 555                                         INTERCEPT_DR3_MASK;
 556
 557         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 558                                         INTERCEPT_DR1_MASK |
 559                                         INTERCEPT_DR2_MASK |
 560                                         INTERCEPT_DR3_MASK |
 561                                         INTERCEPT_DR5_MASK |
 562                                         INTERCEPT_DR7_MASK;
 563
 564         control->intercept_exceptions = (1 << PF_VECTOR) |
 565                                         (1 << UD_VECTOR) |
 566                                         (1 << MC_VECTOR);
 567
 568
 569         control->intercept =    (1ULL << INTERCEPT_INTR) |
 570                                 (1ULL << INTERCEPT_NMI) |
 571                                 (1ULL << INTERCEPT_SMI) |
 572                                 (1ULL << INTERCEPT_CPUID) |
 573                                 (1ULL << INTERCEPT_INVD) |
 574                                 (1ULL << INTERCEPT_HLT) |
 575                                 (1ULL << INTERCEPT_INVLPG) |
 576                                 (1ULL << INTERCEPT_INVLPGA) |
 577                                 (1ULL << INTERCEPT_IOIO_PROT) |
 578                                 (1ULL << INTERCEPT_MSR_PROT) |
 579                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 580                                 (1ULL << INTERCEPT_SHUTDOWN) |
 581                                 (1ULL << INTERCEPT_VMRUN) |
 582                                 (1ULL << INTERCEPT_VMMCALL) |
 583                                 (1ULL << INTERCEPT_VMLOAD) |
 584                                 (1ULL << INTERCEPT_VMSAVE) |
 585                                 (1ULL << INTERCEPT_STGI) |
 586                                 (1ULL << INTERCEPT_CLGI) |
 587                                 (1ULL << INTERCEPT_SKINIT) |
 588                                 (1ULL << INTERCEPT_WBINVD) |
 589                                 (1ULL << INTERCEPT_MONITOR) |
 590                                 (1ULL << INTERCEPT_MWAIT);
 591
 592         control->iopm_base_pa = iopm_base;
 593         control->msrpm_base_pa = __pa(svm->msrpm);
 594         control->tsc_offset = 0;
 595         control->int_ctl = V_INTR_MASKING_MASK;
 596
 597         init_seg(&save->es);
 598         init_seg(&save->ss);
 599         init_seg(&save->ds);
 600         init_seg(&save->fs);
 601         init_seg(&save->gs);
 602
 603         save->cs.selector = 0xf000;
 604         /* Executable/Readable Code Segment */
 605         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 606                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 607         save->cs.limit = 0xffff;
 608         /*
 609          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 610          * be consistent with it.
 611          *
 612          * Replace when we have real mode working for vmx.
 613          */
 614         save->cs.base = 0xf0000;
 615
 616         save->gdtr.limit = 0xffff;
 617         save->idtr.limit = 0xffff;
 618
 619         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 620         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 621
 622         save->efer = EFER_SVME;
 623         save->dr6 = 0xffff0ff0;
 624         save->dr7 = 0x400;
 625         save->rflags = 2;
 626         save->rip = 0x0000fff0;
 627         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 628
 629         /*
 630          * cr0 val on cpu init should be 0x60000010, we enable cpu
 631          * cache by default. the orderly way is to enable cache in bios.
 632          */
 633         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 634         save->cr4 = X86_CR4_PAE;
 635         /* rdx = ?? */
 636
 637         if (npt_enabled) {
 638                 /* Setup VMCB for Nested Paging */
 639                 control->nested_ctl = 1;
 640                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 641                                         (1ULL << INTERCEPT_INVLPG));
 642                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 643                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 644                                                 INTERCEPT_CR3_MASK);
 645                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 646                                                  INTERCEPT_CR3_MASK);
 647                 save->g_pat = 0x0007040600070406ULL;
 648                 /* enable caching because the QEMU Bios doesn't enable it */
 649                 save->cr0 = X86_CR0_ET;
 650                 save->cr3 = 0;
 651                 save->cr4 = 0;
 652         }
 653         force_new_asid(&svm->vcpu);
 654
 655         svm->nested.vmcb = 0;
 656         svm->vcpu.arch.hflags = 0;
 657
 658         if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
 659                 control->pause_filter_count = 3000;
 660                 control->intercept |= (1ULL << INTERCEPT_PAUSE);
 661         }
 662
 663         enable_gif(svm);
 664 }
 665
 666 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 667 {
 668         struct vcpu_svm *svm = to_svm(vcpu);
 669
 670         init_vmcb(svm);
 671
 672         if (!kvm_vcpu_is_bsp(vcpu)) {
 673                 kvm_rip_write(vcpu, 0);
 674                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 675                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 676         }
 677         vcpu->arch.regs_avail = ~0;
 678         vcpu->arch.regs_dirty = ~0;
 679
 680         return 0;
 681 }
 682
 683 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 684 {
 685         struct vcpu_svm *svm;
 686         struct page *page;
 687         struct page *msrpm_pages;
 688         struct page *hsave_page;
 689         struct page *nested_msrpm_pages;
 690         int err;
 691
 692         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 693         if (!svm) {
 694                 err = -ENOMEM;
 695                 goto out;
 696         }
 697
 698         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 699         if (err)
 700                 goto free_svm;
 701
 702         page = alloc_page(GFP_KERNEL);
 703         if (!page) {
 704                 err = -ENOMEM;
 705                 goto uninit;
 706         }
 707
 708         err = -ENOMEM;
 709         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 710         if (!msrpm_pages)
 711                 goto uninit;
 712
 713         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 714         if (!nested_msrpm_pages)
 715                 goto uninit;
 716
 717         svm->msrpm = page_address(msrpm_pages);
 718         svm_vcpu_init_msrpm(svm->msrpm);
 719
 720         hsave_page = alloc_page(GFP_KERNEL);
 721         if (!hsave_page)
 722                 goto uninit;
 723         svm->nested.hsave = page_address(hsave_page);
 724
 725         svm->nested.msrpm = page_address(nested_msrpm_pages);
 726
 727         svm->vmcb = page_address(page);
 728         clear_page(svm->vmcb);
 729         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 730         svm->asid_generation = 0;
 731         init_vmcb(svm);
 732
 733         fx_init(&svm->vcpu);
 734         svm->vcpu.fpu_active = 1;
 735         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 736         if (kvm_vcpu_is_bsp(&svm->vcpu))
 737                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 738
 739         return &svm->vcpu;
 740
 741 uninit:
 742         kvm_vcpu_uninit(&svm->vcpu);
 743 free_svm:
 744         kmem_cache_free(kvm_vcpu_cache, svm);
 745 out:
 746         return ERR_PTR(err);
 747 }
 748
 749 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 750 {
 751         struct vcpu_svm *svm = to_svm(vcpu);
 752
 753         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 754         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 755         __free_page(virt_to_page(svm->nested.hsave));
 756         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
 757         kvm_vcpu_uninit(vcpu);
 758         kmem_cache_free(kvm_vcpu_cache, svm);
 759 }
 760
 761 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 762 {
 763         struct vcpu_svm *svm = to_svm(vcpu);
 764         int i;
 765
 766         if (unlikely(cpu != vcpu->cpu)) {
 767                 u64 delta;
 768
 769                 /*
 770                  * Make sure that the guest sees a monotonically
 771                  * increasing TSC.
 772                  */
 773                 delta = vcpu->arch.host_tsc - native_read_tsc();
 774                 svm->vmcb->control.tsc_offset += delta;
 775                 if (is_nested(svm))
 776                         svm->nested.hsave->control.tsc_offset += delta;
 777                 vcpu->cpu = cpu;
 778                 kvm_migrate_timers(vcpu);
 779                 svm->asid_generation = 0;
 780         }
 781
 782         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 783                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 784 }
 785
 786 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 787 {
 788         struct vcpu_svm *svm = to_svm(vcpu);
 789         int i;
 790
 791         ++vcpu->stat.host_state_reload;
 792         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 793                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 794
 795         vcpu->arch.host_tsc = native_read_tsc();
 796 }
 797
 798 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 799 {
 800         return to_svm(vcpu)->vmcb->save.rflags;
 801 }
 802
 803 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 804 {
 805         to_svm(vcpu)->vmcb->save.rflags = rflags;
 806 }
 807
 808 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
 809 {
 810         switch (reg) {
 811         case VCPU_EXREG_PDPTR:
 812                 BUG_ON(!npt_enabled);
 813                 load_pdptrs(vcpu, vcpu->arch.cr3);
 814                 break;
 815         default:
 816                 BUG();
 817         }
 818 }
 819
 820 static void svm_set_vintr(struct vcpu_svm *svm)
 821 {
 822         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 823 }
 824
 825 static void svm_clear_vintr(struct vcpu_svm *svm)
 826 {
 827         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 828 }
 829
 830 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 831 {
 832         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 833
 834         switch (seg) {
 835         case VCPU_SREG_CS: return &save->cs;
 836         case VCPU_SREG_DS: return &save->ds;
 837         case VCPU_SREG_ES: return &save->es;
 838         case VCPU_SREG_FS: return &save->fs;
 839         case VCPU_SREG_GS: return &save->gs;
 840         case VCPU_SREG_SS: return &save->ss;
 841         case VCPU_SREG_TR: return &save->tr;
 842         case VCPU_SREG_LDTR: return &save->ldtr;
 843         }
 844         BUG();
 845         return NULL;
 846 }
 847
 848 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 849 {
 850         struct vmcb_seg *s = svm_seg(vcpu, seg);
 851
 852         return s->base;
 853 }
 854
 855 static void svm_get_segment(struct kvm_vcpu *vcpu,
 856                             struct kvm_segment *var, int seg)
 857 {
 858         struct vmcb_seg *s = svm_seg(vcpu, seg);
 859
 860         var->base = s->base;
 861         var->limit = s->limit;
 862         var->selector = s->selector;
 863         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 864         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 865         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 866         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 867         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 868         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 869         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 870         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 871
 872         /* AMD's VMCB does not have an explicit unusable field, so emulate it
 873          * for cross vendor migration purposes by "not present"
 874          */
 875         var->unusable = !var->present || (var->type == 0);
 876
 877         switch (seg) {
 878         case VCPU_SREG_CS:
 879                 /*
 880                  * SVM always stores 0 for the 'G' bit in the CS selector in
 881                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 882                  * Intel's VMENTRY has a check on the 'G' bit.
 883                  */
 884                 var->g = s->limit > 0xfffff;
 885                 break;
 886         case VCPU_SREG_TR:
 887                 /*
 888                  * Work around a bug where the busy flag in the tr selector
 889                  * isn't exposed
 890                  */
 891                 var->type |= 0x2;
 892                 break;
 893         case VCPU_SREG_DS:
 894         case VCPU_SREG_ES:
 895         case VCPU_SREG_FS:
 896         case VCPU_SREG_GS:
 897                 /*
 898                  * The accessed bit must always be set in the segment
 899                  * descriptor cache, although it can be cleared in the
 900                  * descriptor, the cached bit always remains at 1. Since
 901                  * Intel has a check on this, set it here to support
 902                  * cross-vendor migration.
 903                  */
 904                 if (!var->unusable)
 905                         var->type |= 0x1;
 906                 break;
 907         case VCPU_SREG_SS:
 908                 /* On AMD CPUs sometimes the DB bit in the segment
 909                  * descriptor is left as 1, although the whole segment has
 910                  * been made unusable. Clear it here to pass an Intel VMX
 911                  * entry check when cross vendor migrating.
 912                  */
 913                 if (var->unusable)
 914                         var->db = 0;
 915                 break;
 916         }
 917 }
 918
 919 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 920 {
 921         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 922
 923         return save->cpl;
 924 }
 925
 926 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 927 {
 928         struct vcpu_svm *svm = to_svm(vcpu);
 929
 930         dt->limit = svm->vmcb->save.idtr.limit;
 931         dt->base = svm->vmcb->save.idtr.base;
 932 }
 933
 934 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 935 {
 936         struct vcpu_svm *svm = to_svm(vcpu);
 937
 938         svm->vmcb->save.idtr.limit = dt->limit;
 939         svm->vmcb->save.idtr.base = dt->base ;
 940 }
 941
 942 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 943 {
 944         struct vcpu_svm *svm = to_svm(vcpu);
 945
 946         dt->limit = svm->vmcb->save.gdtr.limit;
 947         dt->base = svm->vmcb->save.gdtr.base;
 948 }
 949
 950 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 951 {
 952         struct vcpu_svm *svm = to_svm(vcpu);
 953
 954         svm->vmcb->save.gdtr.limit = dt->limit;
 955         svm->vmcb->save.gdtr.base = dt->base ;
 956 }
 957
 958 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 959 {
 960 }
 961
 962 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 963 {
 964         struct vcpu_svm *svm = to_svm(vcpu);
 965
 966 #ifdef CONFIG_X86_64
 967         if (vcpu->arch.shadow_efer & EFER_LME) {
 968                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 969                         vcpu->arch.shadow_efer |= EFER_LMA;
 970                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 971                 }
 972
 973                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 974                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 975                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 976                 }
 977         }
 978 #endif
 979         if (npt_enabled)
 980                 goto set;
 981
 982         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 983                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 984                 vcpu->fpu_active = 1;
 985         }
 986
 987         vcpu->arch.cr0 = cr0;
 988         cr0 |= X86_CR0_PG | X86_CR0_WP;
 989         if (!vcpu->fpu_active) {
 990                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 991                 cr0 |= X86_CR0_TS;
 992         }
 993 set:
 994         /*
 995          * re-enable caching here because the QEMU bios
 996          * does not do it - this results in some delay at
 997          * reboot
 998          */
 999         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1000         svm->vmcb->save.cr0 = cr0;
1001 }
1002
1003 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1004 {
1005         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1006         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1007
1008         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1009                 force_new_asid(vcpu);
1010
1011         vcpu->arch.cr4 = cr4;
1012         if (!npt_enabled)
1013                 cr4 |= X86_CR4_PAE;
1014         cr4 |= host_cr4_mce;
1015         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1016 }
1017
1018 static void svm_set_segment(struct kvm_vcpu *vcpu,
1019                             struct kvm_segment *var, int seg)
1020 {
1021         struct vcpu_svm *svm = to_svm(vcpu);
1022         struct vmcb_seg *s = svm_seg(vcpu, seg);
1023
1024         s->base = var->base;
1025         s->limit = var->limit;
1026         s->selector = var->selector;
1027         if (var->unusable)
1028                 s->attrib = 0;
1029         else {
1030                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1031                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1032                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1033                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1034                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1035                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1036                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1037                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1038         }
1039         if (seg == VCPU_SREG_CS)
1040                 svm->vmcb->save.cpl
1041                         = (svm->vmcb->save.cs.attrib
1042                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1043
1044 }
1045
1046 static void update_db_intercept(struct kvm_vcpu *vcpu)
1047 {
1048         struct vcpu_svm *svm = to_svm(vcpu);
1049
1050         svm->vmcb->control.intercept_exceptions &=
1051                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1052
1053         if (vcpu->arch.singlestep)
1054                 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1055
1056         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1057                 if (vcpu->guest_debug &
1058                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1059                         svm->vmcb->control.intercept_exceptions |=
1060                                 1 << DB_VECTOR;
1061                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1062                         svm->vmcb->control.intercept_exceptions |=
1063                                 1 << BP_VECTOR;
1064         } else
1065                 vcpu->guest_debug = 0;
1066 }
1067
1068 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1069 {
1070         struct vcpu_svm *svm = to_svm(vcpu);
1071
1072         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1073                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1074         else
1075                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1076
1077         update_db_intercept(vcpu);
1078 }
1079
1080 static void load_host_msrs(struct kvm_vcpu *vcpu)
1081 {
1082 #ifdef CONFIG_X86_64
1083         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1084 #endif
1085 }
1086
1087 static void save_host_msrs(struct kvm_vcpu *vcpu)
1088 {
1089 #ifdef CONFIG_X86_64
1090         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1091 #endif
1092 }
1093
1094 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
1095 {
1096         if (svm_data->next_asid > svm_data->max_asid) {
1097                 ++svm_data->asid_generation;
1098                 svm_data->next_asid = 1;
1099                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1100         }
1101
1102         svm->asid_generation = svm_data->asid_generation;
1103         svm->vmcb->control.asid = svm_data->next_asid++;
1104 }
1105
1106 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1107 {
1108         struct vcpu_svm *svm = to_svm(vcpu);
1109         unsigned long val;
1110
1111         switch (dr) {
1112         case 0 ... 3:
1113                 val = vcpu->arch.db[dr];
1114                 break;
1115         case 6:
1116                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1117                         val = vcpu->arch.dr6;
1118                 else
1119                         val = svm->vmcb->save.dr6;
1120                 break;
1121         case 7:
1122                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1123                         val = vcpu->arch.dr7;
1124                 else
1125                         val = svm->vmcb->save.dr7;
1126                 break;
1127         default:
1128                 val = 0;
1129         }
1130
1131         return val;
1132 }
1133
1134 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1135                        int *exception)
1136 {
1137         struct vcpu_svm *svm = to_svm(vcpu);
1138
1139         *exception = 0;
1140
1141         switch (dr) {
1142         case 0 ... 3:
1143                 vcpu->arch.db[dr] = value;
1144                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1145                         vcpu->arch.eff_db[dr] = value;
1146                 return;
1147         case 4 ... 5:
1148                 if (vcpu->arch.cr4 & X86_CR4_DE)
1149                         *exception = UD_VECTOR;
1150                 return;
1151         case 6:
1152                 if (value & 0xffffffff00000000ULL) {
1153                         *exception = GP_VECTOR;
1154                         return;
1155                 }
1156                 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1157                 return;
1158         case 7:
1159                 if (value & 0xffffffff00000000ULL) {
1160                         *exception = GP_VECTOR;
1161                         return;
1162                 }
1163                 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1164                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1165                         svm->vmcb->save.dr7 = vcpu->arch.dr7;
1166                         vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1167                 }
1168                 return;
1169         default:
1170                 /* FIXME: Possible case? */
1171                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1172                        __func__, dr);
1173                 *exception = UD_VECTOR;
1174                 return;
1175         }
1176 }
1177
1178 static int pf_interception(struct vcpu_svm *svm)
1179 {
1180         u64 fault_address;
1181         u32 error_code;
1182
1183         fault_address  = svm->vmcb->control.exit_info_2;
1184         error_code = svm->vmcb->control.exit_info_1;
1185
1186         trace_kvm_page_fault(fault_address, error_code);
1187         if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1188                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1189         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1190 }
1191
1192 static int db_interception(struct vcpu_svm *svm)
1193 {
1194         struct kvm_run *kvm_run = svm->vcpu.run;
1195
1196         if (!(svm->vcpu.guest_debug &
1197               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1198                 !svm->vcpu.arch.singlestep) {
1199                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1200                 return 1;
1201         }
1202
1203         if (svm->vcpu.arch.singlestep) {
1204                 svm->vcpu.arch.singlestep = false;
1205                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1206                         svm->vmcb->save.rflags &=
1207                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1208                 update_db_intercept(&svm->vcpu);
1209         }
1210
1211         if (svm->vcpu.guest_debug &
1212             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1213                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1214                 kvm_run->debug.arch.pc =
1215                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1216                 kvm_run->debug.arch.exception = DB_VECTOR;
1217                 return 0;
1218         }
1219
1220         return 1;
1221 }
1222
1223 static int bp_interception(struct vcpu_svm *svm)
1224 {
1225         struct kvm_run *kvm_run = svm->vcpu.run;
1226
1227         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1228         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1229         kvm_run->debug.arch.exception = BP_VECTOR;
1230         return 0;
1231 }
1232
1233 static int ud_interception(struct vcpu_svm *svm)
1234 {
1235         int er;
1236
1237         er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1238         if (er != EMULATE_DONE)
1239                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1240         return 1;
1241 }
1242
1243 static int nm_interception(struct vcpu_svm *svm)
1244 {
1245         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1246         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1247                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1248         svm->vcpu.fpu_active = 1;
1249
1250         return 1;
1251 }
1252
1253 static int mc_interception(struct vcpu_svm *svm)
1254 {
1255         /*
1256          * On an #MC intercept the MCE handler is not called automatically in
1257          * the host. So do it by hand here.
1258          */
1259         asm volatile (
1260                 "int $0x12\n");
1261         /* not sure if we ever come back to this point */
1262
1263         return 1;
1264 }
1265
1266 static int shutdown_interception(struct vcpu_svm *svm)
1267 {
1268         struct kvm_run *kvm_run = svm->vcpu.run;
1269
1270         /*
1271          * VMCB is undefined after a SHUTDOWN intercept
1272          * so reinitialize it.
1273          */
1274         clear_page(svm->vmcb);
1275         init_vmcb(svm);
1276
1277         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1278         return 0;
1279 }
1280
1281 static int io_interception(struct vcpu_svm *svm)
1282 {
1283         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1284         int size, in, string;
1285         unsigned port;
1286
1287         ++svm->vcpu.stat.io_exits;
1288
1289         svm->next_rip = svm->vmcb->control.exit_info_2;
1290
1291         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1292
1293         if (string) {
1294                 if (emulate_instruction(&svm->vcpu,
1295                                         0, 0, 0) == EMULATE_DO_MMIO)
1296                         return 0;
1297                 return 1;
1298         }
1299
1300         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1301         port = io_info >> 16;
1302         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1303
1304         skip_emulated_instruction(&svm->vcpu);
1305         return kvm_emulate_pio(&svm->vcpu, in, size, port);
1306 }
1307
1308 static int nmi_interception(struct vcpu_svm *svm)
1309 {
1310         return 1;
1311 }
1312
1313 static int intr_interception(struct vcpu_svm *svm)
1314 {
1315         ++svm->vcpu.stat.irq_exits;
1316         return 1;
1317 }
1318
1319 static int nop_on_interception(struct vcpu_svm *svm)
1320 {
1321         return 1;
1322 }
1323
1324 static int halt_interception(struct vcpu_svm *svm)
1325 {
1326         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1327         skip_emulated_instruction(&svm->vcpu);
1328         return kvm_emulate_halt(&svm->vcpu);
1329 }
1330
1331 static int vmmcall_interception(struct vcpu_svm *svm)
1332 {
1333         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1334         skip_emulated_instruction(&svm->vcpu);
1335         kvm_emulate_hypercall(&svm->vcpu);
1336         return 1;
1337 }
1338
1339 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1340 {
1341         if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1342             || !is_paging(&svm->vcpu)) {
1343                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1344                 return 1;
1345         }
1346
1347         if (svm->vmcb->save.cpl) {
1348                 kvm_inject_gp(&svm->vcpu, 0);
1349                 return 1;
1350         }
1351
1352        return 0;
1353 }
1354
1355 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1356                                       bool has_error_code, u32 error_code)
1357 {
1358         if (!is_nested(svm))
1359                 return 0;
1360
1361         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1362         svm->vmcb->control.exit_code_hi = 0;
1363         svm->vmcb->control.exit_info_1 = error_code;
1364         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1365
1366         return nested_svm_exit_handled(svm);
1367 }
1368
1369 static inline int nested_svm_intr(struct vcpu_svm *svm)
1370 {
1371         if (!is_nested(svm))
1372                 return 0;
1373
1374         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1375                 return 0;
1376
1377         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1378                 return 0;
1379
1380         svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1381
1382         if (svm->nested.intercept & 1ULL) {
1383                 /*
1384                  * The #vmexit can't be emulated here directly because this
1385                  * code path runs with irqs and preemtion disabled. A
1386                  * #vmexit emulation might sleep. Only signal request for
1387                  * the #vmexit here.
1388                  */
1389                 svm->nested.exit_required = true;
1390                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1391                 return 1;
1392         }
1393
1394         return 0;
1395 }
1396
1397 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
1398 {
1399         struct page *page;
1400
1401         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1402         if (is_error_page(page))
1403                 goto error;
1404
1405         return kmap_atomic(page, idx);
1406
1407 error:
1408         kvm_release_page_clean(page);
1409         kvm_inject_gp(&svm->vcpu, 0);
1410
1411         return NULL;
1412 }
1413
1414 static void nested_svm_unmap(void *addr, enum km_type idx)
1415 {
1416         struct page *page;
1417
1418         if (!addr)
1419                 return;
1420
1421         page = kmap_atomic_to_page(addr);
1422
1423         kunmap_atomic(addr, idx);
1424         kvm_release_page_dirty(page);
1425 }
1426
1427 static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1428 {
1429         u32 param = svm->vmcb->control.exit_info_1 & 1;
1430         u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1431         bool ret = false;
1432         u32 t0, t1;
1433         u8 *msrpm;
1434
1435         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1436                 return false;
1437
1438         msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1439
1440         if (!msrpm)
1441                 goto out;
1442
1443         switch (msr) {
1444         case 0 ... 0x1fff:
1445                 t0 = (msr * 2) % 8;
1446                 t1 = msr / 8;
1447                 break;
1448         case 0xc0000000 ... 0xc0001fff:
1449                 t0 = (8192 + msr - 0xc0000000) * 2;
1450                 t1 = (t0 / 8);
1451                 t0 %= 8;
1452                 break;
1453         case 0xc0010000 ... 0xc0011fff:
1454                 t0 = (16384 + msr - 0xc0010000) * 2;
1455                 t1 = (t0 / 8);
1456                 t0 %= 8;
1457                 break;
1458         default:
1459                 ret = true;
1460                 goto out;
1461         }
1462
1463         ret = msrpm[t1] & ((1 << param) << t0);
1464
1465 out:
1466         nested_svm_unmap(msrpm, KM_USER0);
1467
1468         return ret;
1469 }
1470
1471 static int nested_svm_exit_special(struct vcpu_svm *svm)
1472 {
1473         u32 exit_code = svm->vmcb->control.exit_code;
1474
1475         switch (exit_code) {
1476         case SVM_EXIT_INTR:
1477         case SVM_EXIT_NMI:
1478                 return NESTED_EXIT_HOST;
1479                 /* For now we are always handling NPFs when using them */
1480         case SVM_EXIT_NPF:
1481                 if (npt_enabled)
1482                         return NESTED_EXIT_HOST;
1483                 break;
1484         /* When we're shadowing, trap PFs */
1485         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1486                 if (!npt_enabled)
1487                         return NESTED_EXIT_HOST;
1488                 break;
1489         default:
1490                 break;
1491         }
1492
1493         return NESTED_EXIT_CONTINUE;
1494 }
1495
1496 /*
1497  * If this function returns true, this #vmexit was already handled
1498  */
1499 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1500 {
1501         u32 exit_code = svm->vmcb->control.exit_code;
1502         int vmexit = NESTED_EXIT_HOST;
1503
1504         switch (exit_code) {
1505         case SVM_EXIT_MSR:
1506                 vmexit = nested_svm_exit_handled_msr(svm);
1507                 break;
1508         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1509                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1510                 if (svm->nested.intercept_cr_read & cr_bits)
1511                         vmexit = NESTED_EXIT_DONE;
1512                 break;
1513         }
1514         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1515                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1516                 if (svm->nested.intercept_cr_write & cr_bits)
1517                         vmexit = NESTED_EXIT_DONE;
1518                 break;
1519         }
1520         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1521                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1522                 if (svm->nested.intercept_dr_read & dr_bits)
1523                         vmexit = NESTED_EXIT_DONE;
1524                 break;
1525         }
1526         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1527                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1528                 if (svm->nested.intercept_dr_write & dr_bits)
1529                         vmexit = NESTED_EXIT_DONE;
1530                 break;
1531         }
1532         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1533                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1534                 if (svm->nested.intercept_exceptions & excp_bits)
1535                         vmexit = NESTED_EXIT_DONE;
1536                 break;
1537         }
1538         default: {
1539                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1540                 if (svm->nested.intercept & exit_bits)
1541                         vmexit = NESTED_EXIT_DONE;
1542         }
1543         }
1544
1545         if (vmexit == NESTED_EXIT_DONE) {
1546                 nested_svm_vmexit(svm);
1547         }
1548
1549         return vmexit;
1550 }
1551
1552 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1553 {
1554         struct vmcb_control_area *dst  = &dst_vmcb->control;
1555         struct vmcb_control_area *from = &from_vmcb->control;
1556
1557         dst->intercept_cr_read    = from->intercept_cr_read;
1558         dst->intercept_cr_write   = from->intercept_cr_write;
1559         dst->intercept_dr_read    = from->intercept_dr_read;
1560         dst->intercept_dr_write   = from->intercept_dr_write;
1561         dst->intercept_exceptions = from->intercept_exceptions;
1562         dst->intercept            = from->intercept;
1563         dst->iopm_base_pa         = from->iopm_base_pa;
1564         dst->msrpm_base_pa        = from->msrpm_base_pa;
1565         dst->tsc_offset           = from->tsc_offset;
1566         dst->asid                 = from->asid;
1567         dst->tlb_ctl              = from->tlb_ctl;
1568         dst->int_ctl              = from->int_ctl;
1569         dst->int_vector           = from->int_vector;
1570         dst->int_state            = from->int_state;
1571         dst->exit_code            = from->exit_code;
1572         dst->exit_code_hi         = from->exit_code_hi;
1573         dst->exit_info_1          = from->exit_info_1;
1574         dst->exit_info_2          = from->exit_info_2;
1575         dst->exit_int_info        = from->exit_int_info;
1576         dst->exit_int_info_err    = from->exit_int_info_err;
1577         dst->nested_ctl           = from->nested_ctl;
1578         dst->event_inj            = from->event_inj;
1579         dst->event_inj_err        = from->event_inj_err;
1580         dst->nested_cr3           = from->nested_cr3;
1581         dst->lbr_ctl              = from->lbr_ctl;
1582 }
1583
1584 static int nested_svm_vmexit(struct vcpu_svm *svm)
1585 {
1586         struct vmcb *nested_vmcb;
1587         struct vmcb *hsave = svm->nested.hsave;
1588         struct vmcb *vmcb = svm->vmcb;
1589
1590         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1591                                        vmcb->control.exit_info_1,
1592                                        vmcb->control.exit_info_2,
1593                                        vmcb->control.exit_int_info,
1594                                        vmcb->control.exit_int_info_err);
1595
1596         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
1597         if (!nested_vmcb)
1598                 return 1;
1599
1600         /* Give the current vmcb to the guest */
1601         disable_gif(svm);
1602
1603         nested_vmcb->save.es     = vmcb->save.es;
1604         nested_vmcb->save.cs     = vmcb->save.cs;
1605         nested_vmcb->save.ss     = vmcb->save.ss;
1606         nested_vmcb->save.ds     = vmcb->save.ds;
1607         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
1608         nested_vmcb->save.idtr   = vmcb->save.idtr;
1609         if (npt_enabled)
1610                 nested_vmcb->save.cr3    = vmcb->save.cr3;
1611         nested_vmcb->save.cr2    = vmcb->save.cr2;
1612         nested_vmcb->save.rflags = vmcb->save.rflags;
1613         nested_vmcb->save.rip    = vmcb->save.rip;
1614         nested_vmcb->save.rsp    = vmcb->save.rsp;
1615         nested_vmcb->save.rax    = vmcb->save.rax;
1616         nested_vmcb->save.dr7    = vmcb->save.dr7;
1617         nested_vmcb->save.dr6    = vmcb->save.dr6;
1618         nested_vmcb->save.cpl    = vmcb->save.cpl;
1619
1620         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
1621         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
1622         nested_vmcb->control.int_state         = vmcb->control.int_state;
1623         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
1624         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
1625         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
1626         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
1627         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
1628         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1629
1630         /*
1631          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1632          * to make sure that we do not lose injected events. So check event_inj
1633          * here and copy it to exit_int_info if it is valid.
1634          * Exit_int_info and event_inj can't be both valid because the case
1635          * below only happens on a VMRUN instruction intercept which has
1636          * no valid exit_int_info set.
1637          */
1638         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1639                 struct vmcb_control_area *nc = &nested_vmcb->control;
1640
1641                 nc->exit_int_info     = vmcb->control.event_inj;
1642                 nc->exit_int_info_err = vmcb->control.event_inj_err;
1643         }
1644
1645         nested_vmcb->control.tlb_ctl           = 0;
1646         nested_vmcb->control.event_inj         = 0;
1647         nested_vmcb->control.event_inj_err     = 0;
1648
1649         /* We always set V_INTR_MASKING and remember the old value in hflags */
1650         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1651                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1652
1653         /* Restore the original control entries */
1654         copy_vmcb_control_area(vmcb, hsave);
1655
1656         kvm_clear_exception_queue(&svm->vcpu);
1657         kvm_clear_interrupt_queue(&svm->vcpu);
1658
1659         /* Restore selected save entries */
1660         svm->vmcb->save.es = hsave->save.es;
1661         svm->vmcb->save.cs = hsave->save.cs;
1662         svm->vmcb->save.ss = hsave->save.ss;
1663         svm->vmcb->save.ds = hsave->save.ds;
1664         svm->vmcb->save.gdtr = hsave->save.gdtr;
1665         svm->vmcb->save.idtr = hsave->save.idtr;
1666         svm->vmcb->save.rflags = hsave->save.rflags;
1667         svm_set_efer(&svm->vcpu, hsave->save.efer);
1668         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1669         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1670         if (npt_enabled) {
1671                 svm->vmcb->save.cr3 = hsave->save.cr3;
1672                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1673         } else {
1674                 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1675         }
1676         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1677         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1678         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1679         svm->vmcb->save.dr7 = 0;
1680         svm->vmcb->save.cpl = 0;
1681         svm->vmcb->control.exit_int_info = 0;
1682
1683         /* Exit nested SVM mode */
1684         svm->nested.vmcb = 0;
1685
1686         nested_svm_unmap(nested_vmcb, KM_USER0);
1687
1688         kvm_mmu_reset_context(&svm->vcpu);
1689         kvm_mmu_load(&svm->vcpu);
1690
1691         return 0;
1692 }
1693
1694 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1695 {
1696         u32 *nested_msrpm;
1697         int i;
1698
1699         nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1700         if (!nested_msrpm)
1701                 return false;
1702
1703         for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1704                 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1705
1706         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
1707
1708         nested_svm_unmap(nested_msrpm, KM_USER0);
1709
1710         return true;
1711 }
1712
1713 static bool nested_svm_vmrun(struct vcpu_svm *svm)
1714 {
1715         struct vmcb *nested_vmcb;
1716         struct vmcb *hsave = svm->nested.hsave;
1717         struct vmcb *vmcb = svm->vmcb;
1718
1719         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1720         if (!nested_vmcb)
1721                 return false;
1722
1723         /* nested_vmcb is our indicator if nested SVM is activated */
1724         svm->nested.vmcb = svm->vmcb->save.rax;
1725
1726         trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, svm->nested.vmcb,
1727                                nested_vmcb->save.rip,
1728                                nested_vmcb->control.int_ctl,
1729                                nested_vmcb->control.event_inj,
1730                                nested_vmcb->control.nested_ctl);
1731
1732         /* Clear internal status */
1733         kvm_clear_exception_queue(&svm->vcpu);
1734         kvm_clear_interrupt_queue(&svm->vcpu);
1735
1736         /* Save the old vmcb, so we don't need to pick what we save, but
1737            can restore everything when a VMEXIT occurs */
1738         hsave->save.es     = vmcb->save.es;
1739         hsave->save.cs     = vmcb->save.cs;
1740         hsave->save.ss     = vmcb->save.ss;
1741         hsave->save.ds     = vmcb->save.ds;
1742         hsave->save.gdtr   = vmcb->save.gdtr;
1743         hsave->save.idtr   = vmcb->save.idtr;
1744         hsave->save.efer   = svm->vcpu.arch.shadow_efer;
1745         hsave->save.cr0    = svm->vcpu.arch.cr0;
1746         hsave->save.cr4    = svm->vcpu.arch.cr4;
1747         hsave->save.rflags = vmcb->save.rflags;
1748         hsave->save.rip    = svm->next_rip;
1749         hsave->save.rsp    = vmcb->save.rsp;
1750         hsave->save.rax    = vmcb->save.rax;
1751         if (npt_enabled)
1752                 hsave->save.cr3    = vmcb->save.cr3;
1753         else
1754                 hsave->save.cr3    = svm->vcpu.arch.cr3;
1755
1756         copy_vmcb_control_area(hsave, vmcb);
1757
1758         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1759                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1760         else
1761                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1762
1763         /* Load the nested guest state */
1764         svm->vmcb->save.es = nested_vmcb->save.es;
1765         svm->vmcb->save.cs = nested_vmcb->save.cs;
1766         svm->vmcb->save.ss = nested_vmcb->save.ss;
1767         svm->vmcb->save.ds = nested_vmcb->save.ds;
1768         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1769         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1770         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1771         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1772         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1773         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1774         if (npt_enabled) {
1775                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1776                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1777         } else {
1778                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1779                 kvm_mmu_reset_context(&svm->vcpu);
1780         }
1781         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
1782         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1783         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1784         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1785         /* In case we don't even reach vcpu_run, the fields are not updated */
1786         svm->vmcb->save.rax = nested_vmcb->save.rax;
1787         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1788         svm->vmcb->save.rip = nested_vmcb->save.rip;
1789         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1790         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1791         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1792
1793         /* We don't want a nested guest to be more powerful than the guest,
1794            so all intercepts are ORed */
1795         svm->vmcb->control.intercept_cr_read |=
1796                 nested_vmcb->control.intercept_cr_read;
1797         svm->vmcb->control.intercept_cr_write |=
1798                 nested_vmcb->control.intercept_cr_write;
1799         svm->vmcb->control.intercept_dr_read |=
1800                 nested_vmcb->control.intercept_dr_read;
1801         svm->vmcb->control.intercept_dr_write |=
1802                 nested_vmcb->control.intercept_dr_write;
1803         svm->vmcb->control.intercept_exceptions |=
1804                 nested_vmcb->control.intercept_exceptions;
1805
1806         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1807
1808         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1809
1810         /* cache intercepts */
1811         svm->nested.intercept_cr_read    = nested_vmcb->control.intercept_cr_read;
1812         svm->nested.intercept_cr_write   = nested_vmcb->control.intercept_cr_write;
1813         svm->nested.intercept_dr_read    = nested_vmcb->control.intercept_dr_read;
1814         svm->nested.intercept_dr_write   = nested_vmcb->control.intercept_dr_write;
1815         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1816         svm->nested.intercept            = nested_vmcb->control.intercept;
1817
1818         force_new_asid(&svm->vcpu);
1819         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1820         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1821                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1822         else
1823                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1824
1825         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1826         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1827         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1828         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1829         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1830
1831         nested_svm_unmap(nested_vmcb, KM_USER0);
1832
1833         enable_gif(svm);
1834
1835         return true;
1836 }
1837
1838 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1839 {
1840         to_vmcb->save.fs = from_vmcb->save.fs;
1841         to_vmcb->save.gs = from_vmcb->save.gs;
1842         to_vmcb->save.tr = from_vmcb->save.tr;
1843         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1844         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1845         to_vmcb->save.star = from_vmcb->save.star;
1846         to_vmcb->save.lstar = from_vmcb->save.lstar;
1847         to_vmcb->save.cstar = from_vmcb->save.cstar;
1848         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1849         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1850         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1851         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1852 }
1853
1854 static int vmload_interception(struct vcpu_svm *svm)
1855 {
1856         struct vmcb *nested_vmcb;
1857
1858         if (nested_svm_check_permissions(svm))
1859                 return 1;
1860
1861         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1862         skip_emulated_instruction(&svm->vcpu);
1863
1864         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1865         if (!nested_vmcb)
1866                 return 1;
1867
1868         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1869         nested_svm_unmap(nested_vmcb, KM_USER0);
1870
1871         return 1;
1872 }
1873
1874 static int vmsave_interception(struct vcpu_svm *svm)
1875 {
1876         struct vmcb *nested_vmcb;
1877
1878         if (nested_svm_check_permissions(svm))
1879                 return 1;
1880
1881         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1882         skip_emulated_instruction(&svm->vcpu);
1883
1884         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1885         if (!nested_vmcb)
1886                 return 1;
1887
1888         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1889         nested_svm_unmap(nested_vmcb, KM_USER0);
1890
1891         return 1;
1892 }
1893
1894 static int vmrun_interception(struct vcpu_svm *svm)
1895 {
1896         if (nested_svm_check_permissions(svm))
1897                 return 1;
1898
1899         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1900         skip_emulated_instruction(&svm->vcpu);
1901
1902         if (!nested_svm_vmrun(svm))
1903                 return 1;
1904
1905         if (!nested_svm_vmrun_msrpm(svm))
1906                 goto failed;
1907
1908         return 1;
1909
1910 failed:
1911
1912         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
1913         svm->vmcb->control.exit_code_hi = 0;
1914         svm->vmcb->control.exit_info_1  = 0;
1915         svm->vmcb->control.exit_info_2  = 0;
1916
1917         nested_svm_vmexit(svm);
1918
1919         return 1;
1920 }
1921
1922 static int stgi_interception(struct vcpu_svm *svm)
1923 {
1924         if (nested_svm_check_permissions(svm))
1925                 return 1;
1926
1927         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1928         skip_emulated_instruction(&svm->vcpu);
1929
1930         enable_gif(svm);
1931
1932         return 1;
1933 }
1934
1935 static int clgi_interception(struct vcpu_svm *svm)
1936 {
1937         if (nested_svm_check_permissions(svm))
1938                 return 1;
1939
1940         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1941         skip_emulated_instruction(&svm->vcpu);
1942
1943         disable_gif(svm);
1944
1945         /* After a CLGI no interrupts should come */
1946         svm_clear_vintr(svm);
1947         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1948
1949         return 1;
1950 }
1951
1952 static int invlpga_interception(struct vcpu_svm *svm)
1953 {
1954         struct kvm_vcpu *vcpu = &svm->vcpu;
1955
1956         trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
1957                           vcpu->arch.regs[VCPU_REGS_RAX]);
1958
1959         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1960         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1961
1962         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1963         skip_emulated_instruction(&svm->vcpu);
1964         return 1;
1965 }
1966
1967 static int skinit_interception(struct vcpu_svm *svm)
1968 {
1969         trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
1970
1971         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1972         return 1;
1973 }
1974
1975 static int invalid_op_interception(struct vcpu_svm *svm)
1976 {
1977         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1978         return 1;
1979 }
1980
1981 static int task_switch_interception(struct vcpu_svm *svm)
1982 {
1983         u16 tss_selector;
1984         int reason;
1985         int int_type = svm->vmcb->control.exit_int_info &
1986                 SVM_EXITINTINFO_TYPE_MASK;
1987         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
1988         uint32_t type =
1989                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
1990         uint32_t idt_v =
1991                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
1992
1993         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1994
1995         if (svm->vmcb->control.exit_info_2 &
1996             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1997                 reason = TASK_SWITCH_IRET;
1998         else if (svm->vmcb->control.exit_info_2 &
1999                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2000                 reason = TASK_SWITCH_JMP;
2001         else if (idt_v)
2002                 reason = TASK_SWITCH_GATE;
2003         else
2004                 reason = TASK_SWITCH_CALL;
2005
2006         if (reason == TASK_SWITCH_GATE) {
2007                 switch (type) {
2008                 case SVM_EXITINTINFO_TYPE_NMI:
2009                         svm->vcpu.arch.nmi_injected = false;
2010                         break;
2011                 case SVM_EXITINTINFO_TYPE_EXEPT:
2012                         kvm_clear_exception_queue(&svm->vcpu);
2013                         break;
2014                 case SVM_EXITINTINFO_TYPE_INTR:
2015                         kvm_clear_interrupt_queue(&svm->vcpu);
2016                         break;
2017                 default:
2018                         break;
2019                 }
2020         }
2021
2022         if (reason != TASK_SWITCH_GATE ||
2023             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2024             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2025              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2026                 skip_emulated_instruction(&svm->vcpu);
2027
2028         return kvm_task_switch(&svm->vcpu, tss_selector, reason);
2029 }
2030
2031 static int cpuid_interception(struct vcpu_svm *svm)
2032 {
2033         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2034         kvm_emulate_cpuid(&svm->vcpu);
2035         return 1;
2036 }
2037
2038 static int iret_interception(struct vcpu_svm *svm)
2039 {
2040         ++svm->vcpu.stat.nmi_window_exits;
2041         svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2042         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2043         return 1;
2044 }
2045
2046 static int invlpg_interception(struct vcpu_svm *svm)
2047 {
2048         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2049                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2050         return 1;
2051 }
2052
2053 static int emulate_on_interception(struct vcpu_svm *svm)
2054 {
2055         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2056                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2057         return 1;
2058 }
2059
2060 static int cr8_write_interception(struct vcpu_svm *svm)
2061 {
2062         struct kvm_run *kvm_run = svm->vcpu.run;
2063
2064         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2065         /* instruction emulation calls kvm_set_cr8() */
2066         emulate_instruction(&svm->vcpu, 0, 0, 0);
2067         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2068                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2069                 return 1;
2070         }
2071         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2072                 return 1;
2073         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2074         return 0;
2075 }
2076
2077 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2078 {
2079         struct vcpu_svm *svm = to_svm(vcpu);
2080
2081         switch (ecx) {
2082         case MSR_IA32_TSC: {
2083                 u64 tsc_offset;
2084
2085                 if (is_nested(svm))
2086                         tsc_offset = svm->nested.hsave->control.tsc_offset;
2087                 else
2088                         tsc_offset = svm->vmcb->control.tsc_offset;
2089
2090                 *data = tsc_offset + native_read_tsc();
2091                 break;
2092         }
2093         case MSR_K6_STAR:
2094                 *data = svm->vmcb->save.star;
2095                 break;
2096 #ifdef CONFIG_X86_64
2097         case MSR_LSTAR:
2098                 *data = svm->vmcb->save.lstar;
2099                 break;
2100         case MSR_CSTAR:
2101                 *data = svm->vmcb->save.cstar;
2102                 break;
2103         case MSR_KERNEL_GS_BASE:
2104                 *data = svm->vmcb->save.kernel_gs_base;
2105                 break;
2106         case MSR_SYSCALL_MASK:
2107                 *data = svm->vmcb->save.sfmask;
2108                 break;
2109 #endif
2110         case MSR_IA32_SYSENTER_CS:
2111                 *data = svm->vmcb->save.sysenter_cs;
2112                 break;
2113         case MSR_IA32_SYSENTER_EIP:
2114                 *data = svm->sysenter_eip;
2115                 break;
2116         case MSR_IA32_SYSENTER_ESP:
2117                 *data = svm->sysenter_esp;
2118                 break;
2119         /* Nobody will change the following 5 values in the VMCB so
2120            we can safely return them on rdmsr. They will always be 0
2121            until LBRV is implemented. */
2122         case MSR_IA32_DEBUGCTLMSR:
2123                 *data = svm->vmcb->save.dbgctl;
2124                 break;
2125         case MSR_IA32_LASTBRANCHFROMIP:
2126                 *data = svm->vmcb->save.br_from;
2127                 break;
2128         case MSR_IA32_LASTBRANCHTOIP:
2129                 *data = svm->vmcb->save.br_to;
2130                 break;
2131         case MSR_IA32_LASTINTFROMIP:
2132                 *data = svm->vmcb->save.last_excp_from;
2133                 break;
2134         case MSR_IA32_LASTINTTOIP:
2135                 *data = svm->vmcb->save.last_excp_to;
2136                 break;
2137         case MSR_VM_HSAVE_PA:
2138                 *data = svm->nested.hsave_msr;
2139                 break;
2140         case MSR_VM_CR:
2141                 *data = 0;
2142                 break;
2143         case MSR_IA32_UCODE_REV:
2144                 *data = 0x01000065;
2145                 break;
2146         default:
2147                 return kvm_get_msr_common(vcpu, ecx, data);
2148         }
2149         return 0;
2150 }
2151
2152 static int rdmsr_interception(struct vcpu_svm *svm)
2153 {
2154         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2155         u64 data;
2156
2157         if (svm_get_msr(&svm->vcpu, ecx, &data))
2158                 kvm_inject_gp(&svm->vcpu, 0);
2159         else {
2160                 trace_kvm_msr_read(ecx, data);
2161
2162                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2163                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2164                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2165                 skip_emulated_instruction(&svm->vcpu);
2166         }
2167         return 1;
2168 }
2169
2170 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2171 {
2172         struct vcpu_svm *svm = to_svm(vcpu);
2173
2174         switch (ecx) {
2175         case MSR_IA32_TSC: {
2176                 u64 tsc_offset = data - native_read_tsc();
2177                 u64 g_tsc_offset = 0;
2178
2179                 if (is_nested(svm)) {
2180                         g_tsc_offset = svm->vmcb->control.tsc_offset -
2181                                        svm->nested.hsave->control.tsc_offset;
2182                         svm->nested.hsave->control.tsc_offset = tsc_offset;
2183                 }
2184
2185                 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2186
2187                 break;
2188         }
2189         case MSR_K6_STAR:
2190                 svm->vmcb->save.star = data;
2191                 break;
2192 #ifdef CONFIG_X86_64
2193         case MSR_LSTAR:
2194                 svm->vmcb->save.lstar = data;
2195                 break;
2196         case MSR_CSTAR:
2197                 svm->vmcb->save.cstar = data;
2198                 break;
2199         case MSR_KERNEL_GS_BASE:
2200                 svm->vmcb->save.kernel_gs_base = data;
2201                 break;
2202         case MSR_SYSCALL_MASK:
2203                 svm->vmcb->save.sfmask = data;
2204                 break;
2205 #endif
2206         case MSR_IA32_SYSENTER_CS:
2207                 svm->vmcb->save.sysenter_cs = data;
2208                 break;
2209         case MSR_IA32_SYSENTER_EIP:
2210                 svm->sysenter_eip = data;
2211                 svm->vmcb->save.sysenter_eip = data;
2212                 break;
2213         case MSR_IA32_SYSENTER_ESP:
2214                 svm->sysenter_esp = data;
2215                 svm->vmcb->save.sysenter_esp = data;
2216                 break;
2217         case MSR_IA32_DEBUGCTLMSR:
2218                 if (!svm_has(SVM_FEATURE_LBRV)) {
2219                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2220                                         __func__, data);
2221                         break;
2222                 }
2223                 if (data & DEBUGCTL_RESERVED_BITS)
2224                         return 1;
2225
2226                 svm->vmcb->save.dbgctl = data;
2227                 if (data & (1ULL<<0))
2228                         svm_enable_lbrv(svm);
2229                 else
2230                         svm_disable_lbrv(svm);
2231                 break;
2232         case MSR_VM_HSAVE_PA:
2233                 svm->nested.hsave_msr = data;
2234                 break;
2235         case MSR_VM_CR:
2236         case MSR_VM_IGNNE:
2237                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2238                 break;
2239         default:
2240                 return kvm_set_msr_common(vcpu, ecx, data);
2241         }
2242         return 0;
2243 }
2244
2245 static int wrmsr_interception(struct vcpu_svm *svm)
2246 {
2247         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2248         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2249                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2250
2251         trace_kvm_msr_write(ecx, data);
2252
2253         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2254         if (svm_set_msr(&svm->vcpu, ecx, data))
2255                 kvm_inject_gp(&svm->vcpu, 0);
2256         else
2257                 skip_emulated_instruction(&svm->vcpu);
2258         return 1;
2259 }
2260
2261 static int msr_interception(struct vcpu_svm *svm)
2262 {
2263         if (svm->vmcb->control.exit_info_1)
2264                 return wrmsr_interception(svm);
2265         else
2266                 return rdmsr_interception(svm);
2267 }
2268
2269 static int interrupt_window_interception(struct vcpu_svm *svm)
2270 {
2271         struct kvm_run *kvm_run = svm->vcpu.run;
2272
2273         svm_clear_vintr(svm);
2274         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2275         /*
2276          * If the user space waits to inject interrupts, exit as soon as
2277          * possible
2278          */
2279         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2280             kvm_run->request_interrupt_window &&
2281             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2282                 ++svm->vcpu.stat.irq_window_exits;
2283                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2284                 return 0;
2285         }
2286
2287         return 1;
2288 }
2289
2290 static int pause_interception(struct vcpu_svm *svm)
2291 {
2292         kvm_vcpu_on_spin(&(svm->vcpu));
2293         return 1;
2294 }
2295
2296 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2297         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2298         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2299         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2300         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2301         /* for now: */
2302         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2303         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2304         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2305         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2306         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2307         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2308         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2309         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2310         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2311         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2312         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2313         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2314         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2315         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2316         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2317         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2318         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2319         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2320         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2321         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2322         [SVM_EXIT_INTR]                         = intr_interception,
2323         [SVM_EXIT_NMI]                          = nmi_interception,
2324         [SVM_EXIT_SMI]                          = nop_on_interception,
2325         [SVM_EXIT_INIT]                         = nop_on_interception,
2326         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2327         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
2328         [SVM_EXIT_CPUID]                        = cpuid_interception,
2329         [SVM_EXIT_IRET]                         = iret_interception,
2330         [SVM_EXIT_INVD]                         = emulate_on_interception,
2331         [SVM_EXIT_PAUSE]                        = pause_interception,
2332         [SVM_EXIT_HLT]                          = halt_interception,
2333         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2334         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2335         [SVM_EXIT_IOIO]                         = io_interception,
2336         [SVM_EXIT_MSR]                          = msr_interception,
2337         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2338         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2339         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2340         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2341         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2342         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2343         [SVM_EXIT_STGI]                         = stgi_interception,
2344         [SVM_EXIT_CLGI]                         = clgi_interception,
2345         [SVM_EXIT_SKINIT]                       = skinit_interception,
2346         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2347         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2348         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2349         [SVM_EXIT_NPF]                          = pf_interception,
2350 };
2351
2352 static int handle_exit(struct kvm_vcpu *vcpu)
2353 {
2354         struct vcpu_svm *svm = to_svm(vcpu);
2355         struct kvm_run *kvm_run = vcpu->run;
2356         u32 exit_code = svm->vmcb->control.exit_code;
2357
2358         trace_kvm_exit(exit_code, svm->vmcb->save.rip);
2359
2360         if (unlikely(svm->nested.exit_required)) {
2361                 nested_svm_vmexit(svm);
2362                 svm->nested.exit_required = false;
2363
2364                 return 1;
2365         }
2366
2367         if (is_nested(svm)) {
2368                 int vmexit;
2369
2370                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2371                                         svm->vmcb->control.exit_info_1,
2372                                         svm->vmcb->control.exit_info_2,
2373                                         svm->vmcb->control.exit_int_info,
2374                                         svm->vmcb->control.exit_int_info_err);
2375
2376                 vmexit = nested_svm_exit_special(svm);
2377
2378                 if (vmexit == NESTED_EXIT_CONTINUE)
2379                         vmexit = nested_svm_exit_handled(svm);
2380
2381                 if (vmexit == NESTED_EXIT_DONE)
2382                         return 1;
2383         }
2384
2385         svm_complete_interrupts(svm);
2386
2387         if (npt_enabled) {
2388                 int mmu_reload = 0;
2389                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2390                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2391                         mmu_reload = 1;
2392                 }
2393                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2394                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2395                 if (mmu_reload) {
2396                         kvm_mmu_reset_context(vcpu);
2397                         kvm_mmu_load(vcpu);
2398                 }
2399         }
2400
2401
2402         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2403                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2404                 kvm_run->fail_entry.hardware_entry_failure_reason
2405                         = svm->vmcb->control.exit_code;
2406                 return 0;
2407         }
2408
2409         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2410             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2411             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2412                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2413                        "exit_code 0x%x\n",
2414                        __func__, svm->vmcb->control.exit_int_info,
2415                        exit_code);
2416
2417         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2418             || !svm_exit_handlers[exit_code]) {
2419                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2420                 kvm_run->hw.hardware_exit_reason = exit_code;
2421                 return 0;
2422         }
2423
2424         return svm_exit_handlers[exit_code](svm);
2425 }
2426
2427 static void reload_tss(struct kvm_vcpu *vcpu)
2428 {
2429         int cpu = raw_smp_processor_id();
2430
2431         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2432         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
2433         load_TR_desc();
2434 }
2435
2436 static void pre_svm_run(struct vcpu_svm *svm)
2437 {
2438         int cpu = raw_smp_processor_id();
2439
2440         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2441
2442         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2443         /* FIXME: handle wraparound of asid_generation */
2444         if (svm->asid_generation != svm_data->asid_generation)
2445                 new_asid(svm, svm_data);
2446 }
2447
2448 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2449 {
2450         struct vcpu_svm *svm = to_svm(vcpu);
2451
2452         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2453         vcpu->arch.hflags |= HF_NMI_MASK;
2454         svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2455         ++vcpu->stat.nmi_injections;
2456 }
2457
2458 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2459 {
2460         struct vmcb_control_area *control;
2461
2462         trace_kvm_inj_virq(irq);
2463
2464         ++svm->vcpu.stat.irq_injections;
2465         control = &svm->vmcb->control;
2466         control->int_vector = irq;
2467         control->int_ctl &= ~V_INTR_PRIO_MASK;
2468         control->int_ctl |= V_IRQ_MASK |
2469                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2470 }
2471
2472 static void svm_set_irq(struct kvm_vcpu *vcpu)
2473 {
2474         struct vcpu_svm *svm = to_svm(vcpu);
2475
2476         BUG_ON(!(gif_set(svm)));
2477
2478         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2479                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2480 }
2481
2482 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2483 {
2484         struct vcpu_svm *svm = to_svm(vcpu);
2485
2486         if (irr == -1)
2487                 return;
2488
2489         if (tpr >= irr)
2490                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2491 }
2492
2493 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2494 {
2495         struct vcpu_svm *svm = to_svm(vcpu);
2496         struct vmcb *vmcb = svm->vmcb;
2497         return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2498                 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2499 }
2500
2501 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2502 {
2503         struct vcpu_svm *svm = to_svm(vcpu);
2504         struct vmcb *vmcb = svm->vmcb;
2505         int ret;
2506
2507         if (!gif_set(svm) ||
2508              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2509                 return 0;
2510
2511         ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2512
2513         if (is_nested(svm))
2514                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2515
2516         return ret;
2517 }
2518
2519 static void enable_irq_window(struct kvm_vcpu *vcpu)
2520 {
2521         struct vcpu_svm *svm = to_svm(vcpu);
2522
2523         nested_svm_intr(svm);
2524
2525         /* In case GIF=0 we can't rely on the CPU to tell us when
2526          * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2527          * The next time we get that intercept, this function will be
2528          * called again though and we'll get the vintr intercept. */
2529         if (gif_set(svm)) {
2530                 svm_set_vintr(svm);
2531                 svm_inject_irq(svm, 0x0);
2532         }
2533 }
2534
2535 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2536 {
2537         struct vcpu_svm *svm = to_svm(vcpu);
2538
2539         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2540             == HF_NMI_MASK)
2541                 return; /* IRET will cause a vm exit */
2542
2543         /* Something prevents NMI from been injected. Single step over
2544            possible problem (IRET or exception injection or interrupt
2545            shadow) */
2546         vcpu->arch.singlestep = true;
2547         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2548         update_db_intercept(vcpu);
2549 }
2550
2551 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2552 {
2553         return 0;
2554 }
2555
2556 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2557 {
2558         force_new_asid(vcpu);
2559 }
2560
2561 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2562 {
2563 }
2564
2565 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2566 {
2567         struct vcpu_svm *svm = to_svm(vcpu);
2568
2569         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2570                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2571                 kvm_set_cr8(vcpu, cr8);
2572         }
2573 }
2574
2575 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2576 {
2577         struct vcpu_svm *svm = to_svm(vcpu);
2578         u64 cr8;
2579
2580         cr8 = kvm_get_cr8(vcpu);
2581         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2582         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2583 }
2584
2585 static void svm_complete_interrupts(struct vcpu_svm *svm)
2586 {
2587         u8 vector;
2588         int type;
2589         u32 exitintinfo = svm->vmcb->control.exit_int_info;
2590
2591         if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2592                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2593
2594         svm->vcpu.arch.nmi_injected = false;
2595         kvm_clear_exception_queue(&svm->vcpu);
2596         kvm_clear_interrupt_queue(&svm->vcpu);
2597
2598         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2599                 return;
2600
2601         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2602         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2603
2604         switch (type) {
2605         case SVM_EXITINTINFO_TYPE_NMI:
2606                 svm->vcpu.arch.nmi_injected = true;
2607                 break;
2608         case SVM_EXITINTINFO_TYPE_EXEPT:
2609                 /* In case of software exception do not reinject an exception
2610                    vector, but re-execute and instruction instead */
2611                 if (is_nested(svm))
2612                         break;
2613                 if (kvm_exception_is_soft(vector))
2614                         break;
2615                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2616                         u32 err = svm->vmcb->control.exit_int_info_err;
2617                         kvm_queue_exception_e(&svm->vcpu, vector, err);
2618
2619                 } else
2620                         kvm_queue_exception(&svm->vcpu, vector);
2621                 break;
2622         case SVM_EXITINTINFO_TYPE_INTR:
2623                 kvm_queue_interrupt(&svm->vcpu, vector, false);
2624                 break;
2625         default:
2626                 break;
2627         }
2628 }
2629
2630 #ifdef CONFIG_X86_64
2631 #define R "r"
2632 #else
2633 #define R "e"
2634 #endif
2635
2636 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
2637 {
2638         struct vcpu_svm *svm = to_svm(vcpu);
2639         u16 fs_selector;
2640         u16 gs_selector;
2641         u16 ldt_selector;
2642
2643         /*
2644          * A vmexit emulation is required before the vcpu can be executed
2645          * again.
2646          */
2647         if (unlikely(svm->nested.exit_required))
2648                 return;
2649
2650         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2651         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2652         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2653
2654         pre_svm_run(svm);
2655
2656         sync_lapic_to_cr8(vcpu);
2657
2658         save_host_msrs(vcpu);
2659         fs_selector = kvm_read_fs();
2660         gs_selector = kvm_read_gs();
2661         ldt_selector = kvm_read_ldt();
2662         svm->vmcb->save.cr2 = vcpu->arch.cr2;
2663         /* required for live migration with NPT */
2664         if (npt_enabled)
2665                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2666
2667         clgi();
2668
2669         local_irq_enable();
2670
2671         asm volatile (
2672                 "push %%"R"bp; \n\t"
2673                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2674                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2675                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2676                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2677                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2678                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2679 #ifdef CONFIG_X86_64
2680                 "mov %c[r8](%[svm]),  %%r8  \n\t"
2681                 "mov %c[r9](%[svm]),  %%r9  \n\t"
2682                 "mov %c[r10](%[svm]), %%r10 \n\t"
2683                 "mov %c[r11](%[svm]), %%r11 \n\t"
2684                 "mov %c[r12](%[svm]), %%r12 \n\t"
2685                 "mov %c[r13](%[svm]), %%r13 \n\t"
2686                 "mov %c[r14](%[svm]), %%r14 \n\t"
2687                 "mov %c[r15](%[svm]), %%r15 \n\t"
2688 #endif
2689
2690                 /* Enter guest mode */
2691                 "push %%"R"ax \n\t"
2692                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2693                 __ex(SVM_VMLOAD) "\n\t"
2694                 __ex(SVM_VMRUN) "\n\t"
2695                 __ex(SVM_VMSAVE) "\n\t"
2696                 "pop %%"R"ax \n\t"
2697
2698                 /* Save guest registers, load host registers */
2699                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2700                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2701                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2702                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2703                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2704                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2705 #ifdef CONFIG_X86_64
2706                 "mov %%r8,  %c[r8](%[svm]) \n\t"
2707                 "mov %%r9,  %c[r9](%[svm]) \n\t"
2708                 "mov %%r10, %c[r10](%[svm]) \n\t"
2709                 "mov %%r11, %c[r11](%[svm]) \n\t"
2710                 "mov %%r12, %c[r12](%[svm]) \n\t"
2711                 "mov %%r13, %c[r13](%[svm]) \n\t"
2712                 "mov %%r14, %c[r14](%[svm]) \n\t"
2713                 "mov %%r15, %c[r15](%[svm]) \n\t"
2714 #endif
2715                 "pop %%"R"bp"
2716                 :
2717                 : [svm]"a"(svm),
2718                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2719                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2720                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2721                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2722                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2723                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2724                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2725 #ifdef CONFIG_X86_64
2726                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2727                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2728                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2729                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2730                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2731                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2732                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2733                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2734 #endif
2735                 : "cc", "memory"
2736                 , R"bx", R"cx", R"dx", R"si", R"di"
2737 #ifdef CONFIG_X86_64
2738                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2739 #endif
2740                 );
2741
2742         vcpu->arch.cr2 = svm->vmcb->save.cr2;
2743         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2744         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2745         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2746
2747         kvm_load_fs(fs_selector);
2748         kvm_load_gs(gs_selector);
2749         kvm_load_ldt(ldt_selector);
2750         load_host_msrs(vcpu);
2751
2752         reload_tss(vcpu);
2753
2754         local_irq_disable();
2755
2756         stgi();
2757
2758         sync_cr8_to_lapic(vcpu);
2759
2760         svm->next_rip = 0;
2761
2762         if (npt_enabled) {
2763                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2764                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2765         }
2766 }
2767
2768 #undef R
2769
2770 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2771 {
2772         struct vcpu_svm *svm = to_svm(vcpu);
2773
2774         if (npt_enabled) {
2775                 svm->vmcb->control.nested_cr3 = root;
2776                 force_new_asid(vcpu);
2777                 return;
2778         }
2779
2780         svm->vmcb->save.cr3 = root;
2781         force_new_asid(vcpu);
2782
2783         if (vcpu->fpu_active) {
2784                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2785                 svm->vmcb->save.cr0 |= X86_CR0_TS;
2786                 vcpu->fpu_active = 0;
2787         }
2788 }
2789
2790 static int is_disabled(void)
2791 {
2792         u64 vm_cr;
2793
2794         rdmsrl(MSR_VM_CR, vm_cr);
2795         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2796                 return 1;
2797
2798         return 0;
2799 }
2800
2801 static void
2802 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2803 {
2804         /*
2805          * Patch in the VMMCALL instruction:
2806          */
2807         hypercall[0] = 0x0f;
2808         hypercall[1] = 0x01;
2809         hypercall[2] = 0xd9;
2810 }
2811
2812 static void svm_check_processor_compat(void *rtn)
2813 {
2814         *(int *)rtn = 0;
2815 }
2816
2817 static bool svm_cpu_has_accelerated_tpr(void)
2818 {
2819         return false;
2820 }
2821
2822 static int get_npt_level(void)
2823 {
2824 #ifdef CONFIG_X86_64
2825         return PT64_ROOT_LEVEL;
2826 #else
2827         return PT32E_ROOT_LEVEL;
2828 #endif
2829 }
2830
2831 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
2832 {
2833         return 0;
2834 }
2835
2836 static const struct trace_print_flags svm_exit_reasons_str[] = {
2837         { SVM_EXIT_READ_CR0,                    "read_cr0" },
2838         { SVM_EXIT_READ_CR3,                    "read_cr3" },
2839         { SVM_EXIT_READ_CR4,                    "read_cr4" },
2840         { SVM_EXIT_READ_CR8,                    "read_cr8" },
2841         { SVM_EXIT_WRITE_CR0,                   "write_cr0" },
2842         { SVM_EXIT_WRITE_CR3,                   "write_cr3" },
2843         { SVM_EXIT_WRITE_CR4,                   "write_cr4" },
2844         { SVM_EXIT_WRITE_CR8,                   "write_cr8" },
2845         { SVM_EXIT_READ_DR0,                    "read_dr0" },
2846         { SVM_EXIT_READ_DR1,                    "read_dr1" },
2847         { SVM_EXIT_READ_DR2,                    "read_dr2" },
2848         { SVM_EXIT_READ_DR3,                    "read_dr3" },
2849         { SVM_EXIT_WRITE_DR0,                   "write_dr0" },
2850         { SVM_EXIT_WRITE_DR1,                   "write_dr1" },
2851         { SVM_EXIT_WRITE_DR2,                   "write_dr2" },
2852         { SVM_EXIT_WRITE_DR3,                   "write_dr3" },
2853         { SVM_EXIT_WRITE_DR5,                   "write_dr5" },
2854         { SVM_EXIT_WRITE_DR7,                   "write_dr7" },
2855         { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" },
2856         { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" },
2857         { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" },
2858         { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" },
2859         { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" },
2860         { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" },
2861         { SVM_EXIT_INTR,                        "interrupt" },
2862         { SVM_EXIT_NMI,                         "nmi" },
2863         { SVM_EXIT_SMI,                         "smi" },
2864         { SVM_EXIT_INIT,                        "init" },
2865         { SVM_EXIT_VINTR,                       "vintr" },
2866         { SVM_EXIT_CPUID,                       "cpuid" },
2867         { SVM_EXIT_INVD,                        "invd" },
2868         { SVM_EXIT_HLT,                         "hlt" },
2869         { SVM_EXIT_INVLPG,                      "invlpg" },
2870         { SVM_EXIT_INVLPGA,                     "invlpga" },
2871         { SVM_EXIT_IOIO,                        "io" },
2872         { SVM_EXIT_MSR,                         "msr" },
2873         { SVM_EXIT_TASK_SWITCH,                 "task_switch" },
2874         { SVM_EXIT_SHUTDOWN,                    "shutdown" },
2875         { SVM_EXIT_VMRUN,                       "vmrun" },
2876         { SVM_EXIT_VMMCALL,                     "hypercall" },
2877         { SVM_EXIT_VMLOAD,                      "vmload" },
2878         { SVM_EXIT_VMSAVE,                      "vmsave" },
2879         { SVM_EXIT_STGI,                        "stgi" },
2880         { SVM_EXIT_CLGI,                        "clgi" },
2881         { SVM_EXIT_SKINIT,                      "skinit" },
2882         { SVM_EXIT_WBINVD,                      "wbinvd" },
2883         { SVM_EXIT_MONITOR,                     "monitor" },
2884         { SVM_EXIT_MWAIT,                       "mwait" },
2885         { SVM_EXIT_NPF,                         "npf" },
2886         { -1, NULL }
2887 };
2888
2889 static bool svm_gb_page_enable(void)
2890 {
2891         return true;
2892 }
2893
2894 static struct kvm_x86_ops svm_x86_ops = {
2895         .cpu_has_kvm_support = has_svm,
2896         .disabled_by_bios = is_disabled,
2897         .hardware_setup = svm_hardware_setup,
2898         .hardware_unsetup = svm_hardware_unsetup,
2899         .check_processor_compatibility = svm_check_processor_compat,
2900         .hardware_enable = svm_hardware_enable,
2901         .hardware_disable = svm_hardware_disable,
2902         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2903
2904         .vcpu_create = svm_create_vcpu,
2905         .vcpu_free = svm_free_vcpu,
2906         .vcpu_reset = svm_vcpu_reset,
2907
2908         .prepare_guest_switch = svm_prepare_guest_switch,
2909         .vcpu_load = svm_vcpu_load,
2910         .vcpu_put = svm_vcpu_put,
2911
2912         .set_guest_debug = svm_guest_debug,
2913         .get_msr = svm_get_msr,
2914         .set_msr = svm_set_msr,
2915         .get_segment_base = svm_get_segment_base,
2916         .get_segment = svm_get_segment,
2917         .set_segment = svm_set_segment,
2918         .get_cpl = svm_get_cpl,
2919         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2920         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2921         .set_cr0 = svm_set_cr0,
2922         .set_cr3 = svm_set_cr3,
2923         .set_cr4 = svm_set_cr4,
2924         .set_efer = svm_set_efer,
2925         .get_idt = svm_get_idt,
2926         .set_idt = svm_set_idt,
2927         .get_gdt = svm_get_gdt,
2928         .set_gdt = svm_set_gdt,
2929         .get_dr = svm_get_dr,
2930         .set_dr = svm_set_dr,
2931         .cache_reg = svm_cache_reg,
2932         .get_rflags = svm_get_rflags,
2933         .set_rflags = svm_set_rflags,
2934
2935         .tlb_flush = svm_flush_tlb,
2936
2937         .run = svm_vcpu_run,
2938         .handle_exit = handle_exit,
2939         .skip_emulated_instruction = skip_emulated_instruction,
2940         .set_interrupt_shadow = svm_set_interrupt_shadow,
2941         .get_interrupt_shadow = svm_get_interrupt_shadow,
2942         .patch_hypercall = svm_patch_hypercall,
2943         .set_irq = svm_set_irq,
2944         .set_nmi = svm_inject_nmi,
2945         .queue_exception = svm_queue_exception,
2946         .interrupt_allowed = svm_interrupt_allowed,
2947         .nmi_allowed = svm_nmi_allowed,
2948         .enable_nmi_window = enable_nmi_window,
2949         .enable_irq_window = enable_irq_window,
2950         .update_cr8_intercept = update_cr8_intercept,
2951
2952         .set_tss_addr = svm_set_tss_addr,
2953         .get_tdp_level = get_npt_level,
2954         .get_mt_mask = svm_get_mt_mask,
2955
2956         .exit_reasons_str = svm_exit_reasons_str,
2957         .gb_page_enable = svm_gb_page_enable,
2958 };
2959
2960 static int __init svm_init(void)
2961 {
2962         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2963                               THIS_MODULE);
2964 }
2965
2966 static void __exit svm_exit(void)
2967 {
2968         kvm_exit();
2969 }
2970
2971 module_init(svm_init)
2972 module_exit(svm_exit)