2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Avi Kivity <avi@qumranet.com>
15 * This work is licensed under the terms of the GNU GPL, version 2. See
16 * the COPYING file in the top-level directory.
21 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
22 * so the code in this file is compiled twice, once per pte size.
26 #define pt_element_t u64
27 #define guest_walker guest_walker64
28 #define FNAME(name) paging##64_##name
29 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
30 #define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
31 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
32 #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
33 #define PT_LEVEL_BITS PT64_LEVEL_BITS
35 #define PT_MAX_FULL_LEVELS 4
36 #define CMPXCHG cmpxchg
38 #define CMPXCHG cmpxchg64
39 #define PT_MAX_FULL_LEVELS 2
42 #define pt_element_t u32
43 #define guest_walker guest_walker32
44 #define FNAME(name) paging##32_##name
45 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
46 #define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
47 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
48 #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
49 #define PT_LEVEL_BITS PT32_LEVEL_BITS
50 #define PT_MAX_FULL_LEVELS 2
51 #define CMPXCHG cmpxchg
53 #error Invalid PTTYPE value
56 #define gpte_to_gfn FNAME(gpte_to_gfn)
57 #define gpte_to_gfn_pde FNAME(gpte_to_gfn_pde)
60 * The guest_walker structure emulates the behavior of the hardware page
65 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
66 pt_element_t ptes[PT_MAX_FULL_LEVELS];
67 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
74 static gfn_t gpte_to_gfn(pt_element_t gpte)
76 return (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
79 static gfn_t gpte_to_gfn_pde(pt_element_t gpte)
81 return (gpte & PT_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
84 static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
85 gfn_t table_gfn, unsigned index,
86 pt_element_t orig_pte, pt_element_t new_pte)
92 page = gfn_to_page(kvm, table_gfn);
94 table = kmap_atomic(page, KM_USER0);
95 ret = CMPXCHG(&table[index], orig_pte, new_pte);
96 kunmap_atomic(table, KM_USER0);
98 kvm_release_page_dirty(page);
100 return (ret != orig_pte);
103 static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
107 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
110 access &= ~(gpte >> PT64_NX_SHIFT);
116 * Fetch a guest pte for a guest virtual address
118 static int FNAME(walk_addr)(struct guest_walker *walker,
119 struct kvm_vcpu *vcpu, gva_t addr,
120 int write_fault, int user_fault, int fetch_fault)
124 unsigned index, pt_access, pte_access;
127 pgprintk("%s: addr %lx\n", __func__, addr);
129 walker->level = vcpu->arch.mmu.root_level;
130 pte = vcpu->arch.cr3;
132 if (!is_long_mode(vcpu)) {
133 pte = vcpu->arch.pdptrs[(addr >> 30) & 3];
134 if (!is_present_pte(pte))
139 ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
140 (vcpu->arch.cr3 & CR3_NONPAE_RESERVED_BITS) == 0);
145 index = PT_INDEX(addr, walker->level);
147 table_gfn = gpte_to_gfn(pte);
148 pte_gpa = gfn_to_gpa(table_gfn);
149 pte_gpa += index * sizeof(pt_element_t);
150 walker->table_gfn[walker->level - 1] = table_gfn;
151 walker->pte_gpa[walker->level - 1] = pte_gpa;
152 pgprintk("%s: table_gfn[%d] %lx\n", __func__,
153 walker->level - 1, table_gfn);
155 kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
157 if (!is_present_pte(pte))
160 if (write_fault && !is_writeble_pte(pte))
161 if (user_fault || is_write_protection(vcpu))
164 if (user_fault && !(pte & PT_USER_MASK))
168 if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK))
172 if (!(pte & PT_ACCESSED_MASK)) {
173 mark_page_dirty(vcpu->kvm, table_gfn);
174 if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
175 index, pte, pte|PT_ACCESSED_MASK))
177 pte |= PT_ACCESSED_MASK;
180 pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
182 walker->ptes[walker->level - 1] = pte;
184 if (walker->level == PT_PAGE_TABLE_LEVEL) {
185 walker->gfn = gpte_to_gfn(pte);
189 if (walker->level == PT_DIRECTORY_LEVEL
190 && (pte & PT_PAGE_SIZE_MASK)
191 && (PTTYPE == 64 || is_pse(vcpu))) {
192 walker->gfn = gpte_to_gfn_pde(pte);
193 walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
194 if (PTTYPE == 32 && is_cpuid_PSE36())
195 walker->gfn += pse36_gfn_delta(pte);
199 pt_access = pte_access;
203 if (write_fault && !is_dirty_pte(pte)) {
206 mark_page_dirty(vcpu->kvm, table_gfn);
207 ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
211 pte |= PT_DIRTY_MASK;
212 walker->ptes[walker->level - 1] = pte;
215 walker->pt_access = pt_access;
216 walker->pte_access = pte_access;
217 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
218 __func__, (u64)pte, pt_access, pte_access);
222 walker->error_code = 0;
226 walker->error_code = PFERR_PRESENT_MASK;
230 walker->error_code |= PFERR_WRITE_MASK;
232 walker->error_code |= PFERR_USER_MASK;
234 walker->error_code |= PFERR_FETCH_MASK;
238 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
239 u64 *spte, const void *pte)
244 int largepage = vcpu->arch.update_pte.largepage;
246 gpte = *(const pt_element_t *)pte;
247 if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
248 if (!is_present_pte(gpte))
249 set_shadow_pte(spte, shadow_notrap_nonpresent_pte);
252 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
253 pte_access = page->role.access & FNAME(gpte_access)(vcpu, gpte);
254 if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn)
256 pfn = vcpu->arch.update_pte.pfn;
257 if (is_error_pfn(pfn))
259 if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq))
262 mmu_set_spte(vcpu, spte, page->role.access, pte_access, 0, 0,
263 gpte & PT_DIRTY_MASK, NULL, largepage,
264 gpte & PT_GLOBAL_MASK, gpte_to_gfn(gpte),
269 * Fetch a shadow pte for a specific level in the paging hierarchy.
271 static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
272 struct guest_walker *gw,
273 int user_fault, int write_fault, int largepage,
274 int *ptwrite, pfn_t pfn)
276 unsigned access = gw->pt_access;
277 struct kvm_mmu_page *shadow_page;
283 pt_element_t curr_pte;
284 struct kvm_shadow_walk_iterator iterator;
286 if (!is_present_pte(gw->ptes[gw->level - 1]))
289 for_each_shadow_entry(vcpu, addr, iterator) {
290 level = iterator.level;
291 sptep = iterator.sptep;
292 if (level == PT_PAGE_TABLE_LEVEL
293 || (largepage && level == PT_DIRECTORY_LEVEL)) {
294 mmu_set_spte(vcpu, sptep, access,
295 gw->pte_access & access,
296 user_fault, write_fault,
297 gw->ptes[gw->level-1] & PT_DIRTY_MASK,
299 gw->ptes[gw->level-1] & PT_GLOBAL_MASK,
300 gw->gfn, pfn, false);
304 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep))
307 if (is_large_pte(*sptep)) {
308 rmap_remove(vcpu->kvm, sptep);
309 set_shadow_pte(sptep, shadow_trap_nonpresent_pte);
310 kvm_flush_remote_tlbs(vcpu->kvm);
313 if (level == PT_DIRECTORY_LEVEL
314 && gw->level == PT_DIRECTORY_LEVEL) {
316 if (!is_dirty_pte(gw->ptes[level - 1]))
317 access &= ~ACC_WRITE_MASK;
318 table_gfn = gpte_to_gfn(gw->ptes[level - 1]);
321 table_gfn = gw->table_gfn[level - 2];
323 shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
324 direct, access, sptep);
326 r = kvm_read_guest_atomic(vcpu->kvm,
327 gw->pte_gpa[level - 2],
328 &curr_pte, sizeof(curr_pte));
329 if (r || curr_pte != gw->ptes[level - 2]) {
330 kvm_mmu_put_page(shadow_page, sptep);
331 kvm_release_pfn_clean(pfn);
337 spte = __pa(shadow_page->spt)
338 | PT_PRESENT_MASK | PT_ACCESSED_MASK
339 | PT_WRITABLE_MASK | PT_USER_MASK;
347 * Page fault handler. There are several causes for a page fault:
348 * - there is no shadow pte for the guest pte
349 * - write access through a shadow pte marked read only so that we can set
351 * - write access to a shadow pte marked read only so we can update the page
352 * dirty bitmap, when userspace requests it
353 * - mmio access; in this case we will never install a present shadow pte
354 * - normal guest page fault due to the guest pte marked not present, not
355 * writable, or not executable
357 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
358 * a negative value on error.
360 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
363 int write_fault = error_code & PFERR_WRITE_MASK;
364 int user_fault = error_code & PFERR_USER_MASK;
365 int fetch_fault = error_code & PFERR_FETCH_MASK;
366 struct guest_walker walker;
372 unsigned long mmu_seq;
374 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
375 kvm_mmu_audit(vcpu, "pre page fault");
377 r = mmu_topup_memory_caches(vcpu);
382 * Look up the guest pte for the faulting address.
384 r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
388 * The page is not mapped by the guest. Let the guest handle it.
391 pgprintk("%s: guest page fault\n", __func__);
392 inject_page_fault(vcpu, addr, walker.error_code);
393 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
397 if (walker.level == PT_DIRECTORY_LEVEL) {
399 large_gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE-1);
400 if (is_largepage_backed(vcpu, large_gfn)) {
401 walker.gfn = large_gfn;
405 mmu_seq = vcpu->kvm->mmu_notifier_seq;
407 pfn = gfn_to_pfn(vcpu->kvm, walker.gfn);
410 if (is_error_pfn(pfn)) {
411 pgprintk("gfn %lx is mmio\n", walker.gfn);
412 kvm_release_pfn_clean(pfn);
416 spin_lock(&vcpu->kvm->mmu_lock);
417 if (mmu_notifier_retry(vcpu, mmu_seq))
419 kvm_mmu_free_some_pages(vcpu);
420 shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
421 largepage, &write_pt, pfn);
423 pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
424 shadow_pte, *shadow_pte, write_pt);
427 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
429 ++vcpu->stat.pf_fixed;
430 kvm_mmu_audit(vcpu, "post page fault (fixed)");
431 spin_unlock(&vcpu->kvm->mmu_lock);
436 spin_unlock(&vcpu->kvm->mmu_lock);
437 kvm_release_pfn_clean(pfn);
441 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
443 struct kvm_shadow_walk_iterator iterator;
450 spin_lock(&vcpu->kvm->mmu_lock);
452 for_each_shadow_entry(vcpu, gva, iterator) {
453 level = iterator.level;
454 sptep = iterator.sptep;
456 /* FIXME: properly handle invlpg on large guest pages */
457 if (level == PT_PAGE_TABLE_LEVEL ||
458 ((level == PT_DIRECTORY_LEVEL) && is_large_pte(*sptep))) {
459 struct kvm_mmu_page *sp = page_header(__pa(sptep));
461 pte_gpa = (sp->gfn << PAGE_SHIFT);
462 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
464 if (is_shadow_present_pte(*sptep)) {
465 rmap_remove(vcpu->kvm, sptep);
466 if (is_large_pte(*sptep))
467 --vcpu->kvm->stat.lpages;
470 set_shadow_pte(sptep, shadow_trap_nonpresent_pte);
474 if (!is_shadow_present_pte(*sptep))
479 kvm_flush_remote_tlbs(vcpu->kvm);
480 spin_unlock(&vcpu->kvm->mmu_lock);
484 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
485 sizeof(pt_element_t)))
487 if (is_present_pte(gpte) && (gpte & PT_ACCESSED_MASK)) {
488 if (mmu_topup_memory_caches(vcpu))
490 kvm_mmu_pte_write(vcpu, pte_gpa, (const u8 *)&gpte,
491 sizeof(pt_element_t), 0);
495 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
497 struct guest_walker walker;
498 gpa_t gpa = UNMAPPED_GVA;
501 r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);
504 gpa = gfn_to_gpa(walker.gfn);
505 gpa |= vaddr & ~PAGE_MASK;
511 static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
512 struct kvm_mmu_page *sp)
515 pt_element_t pt[256 / sizeof(pt_element_t)];
519 || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
520 nonpaging_prefetch_page(vcpu, sp);
524 pte_gpa = gfn_to_gpa(sp->gfn);
526 offset = sp->role.quadrant << PT64_LEVEL_BITS;
527 pte_gpa += offset * sizeof(pt_element_t);
530 for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) {
531 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt);
532 pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t);
533 for (j = 0; j < ARRAY_SIZE(pt); ++j)
534 if (r || is_present_pte(pt[j]))
535 sp->spt[i+j] = shadow_trap_nonpresent_pte;
537 sp->spt[i+j] = shadow_notrap_nonpresent_pte;
542 * Using the cached information from sp->gfns is safe because:
543 * - The spte has a reference to the struct page, so the pfn for a given gfn
544 * can't change unless all sptes pointing to it are nuked first.
545 * - Alias changes zap the entire shadow cache.
547 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
549 int i, offset, nr_present;
551 offset = nr_present = 0;
554 offset = sp->role.quadrant << PT64_LEVEL_BITS;
556 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
560 gfn_t gfn = sp->gfns[i];
562 if (!is_shadow_present_pte(sp->spt[i]))
565 pte_gpa = gfn_to_gpa(sp->gfn);
566 pte_gpa += (i+offset) * sizeof(pt_element_t);
568 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
569 sizeof(pt_element_t)))
572 if (gpte_to_gfn(gpte) != gfn || !is_present_pte(gpte) ||
573 !(gpte & PT_ACCESSED_MASK)) {
576 rmap_remove(vcpu->kvm, &sp->spt[i]);
577 if (is_present_pte(gpte))
578 nonpresent = shadow_trap_nonpresent_pte;
580 nonpresent = shadow_notrap_nonpresent_pte;
581 set_shadow_pte(&sp->spt[i], nonpresent);
586 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
587 set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
588 is_dirty_pte(gpte), 0, gpte & PT_GLOBAL_MASK, gfn,
589 spte_to_pfn(sp->spt[i]), true, false);
598 #undef PT_BASE_ADDR_MASK
601 #undef PT_DIR_BASE_ADDR_MASK
603 #undef PT_MAX_FULL_LEVELS
605 #undef gpte_to_gfn_pde