2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Avi Kivity <avi@qumranet.com>
15 * This work is licensed under the terms of the GNU GPL, version 2. See
16 * the COPYING file in the top-level directory.
21 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
22 * so the code in this file is compiled twice, once per pte size.
26 #define pt_element_t u64
27 #define guest_walker guest_walker64
28 #define FNAME(name) paging##64_##name
29 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
30 #define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
31 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
32 #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
33 #define PT_LEVEL_BITS PT64_LEVEL_BITS
35 #define PT_MAX_FULL_LEVELS 4
36 #define CMPXCHG cmpxchg
38 #define CMPXCHG cmpxchg64
39 #define PT_MAX_FULL_LEVELS 2
42 #define pt_element_t u32
43 #define guest_walker guest_walker32
44 #define FNAME(name) paging##32_##name
45 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
46 #define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
47 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
48 #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
49 #define PT_LEVEL_BITS PT32_LEVEL_BITS
50 #define PT_MAX_FULL_LEVELS 2
51 #define CMPXCHG cmpxchg
53 #error Invalid PTTYPE value
56 #define gpte_to_gfn FNAME(gpte_to_gfn)
57 #define gpte_to_gfn_pde FNAME(gpte_to_gfn_pde)
60 * The guest_walker structure emulates the behavior of the hardware page
65 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
66 pt_element_t ptes[PT_MAX_FULL_LEVELS];
67 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
74 static gfn_t gpte_to_gfn(pt_element_t gpte)
76 return (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
79 static gfn_t gpte_to_gfn_pde(pt_element_t gpte)
81 return (gpte & PT_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
84 static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
85 gfn_t table_gfn, unsigned index,
86 pt_element_t orig_pte, pt_element_t new_pte)
92 page = gfn_to_page(kvm, table_gfn);
94 table = kmap_atomic(page, KM_USER0);
95 ret = CMPXCHG(&table[index], orig_pte, new_pte);
96 kunmap_atomic(table, KM_USER0);
98 kvm_release_page_dirty(page);
100 return (ret != orig_pte);
103 static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
107 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
110 access &= ~(gpte >> PT64_NX_SHIFT);
116 * Fetch a guest pte for a guest virtual address
118 static int FNAME(walk_addr)(struct guest_walker *walker,
119 struct kvm_vcpu *vcpu, gva_t addr,
120 int write_fault, int user_fault, int fetch_fault)
124 unsigned index, pt_access, pte_access;
128 trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault,
131 walker->level = vcpu->arch.mmu.root_level;
132 pte = vcpu->arch.cr3;
134 if (!is_long_mode(vcpu)) {
135 pte = kvm_pdptr_read(vcpu, (addr >> 30) & 3);
136 trace_kvm_mmu_paging_element(pte, walker->level);
137 if (!is_present_gpte(pte))
142 ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
143 (vcpu->arch.cr3 & CR3_NONPAE_RESERVED_BITS) == 0);
148 index = PT_INDEX(addr, walker->level);
150 table_gfn = gpte_to_gfn(pte);
151 pte_gpa = gfn_to_gpa(table_gfn);
152 pte_gpa += index * sizeof(pt_element_t);
153 walker->table_gfn[walker->level - 1] = table_gfn;
154 walker->pte_gpa[walker->level - 1] = pte_gpa;
156 kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
157 trace_kvm_mmu_paging_element(pte, walker->level);
159 if (!is_present_gpte(pte))
162 rsvd_fault = is_rsvd_bits_set(vcpu, pte, walker->level);
166 if (write_fault && !is_writeble_pte(pte))
167 if (user_fault || is_write_protection(vcpu))
170 if (user_fault && !(pte & PT_USER_MASK))
174 if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK))
178 if (!(pte & PT_ACCESSED_MASK)) {
179 trace_kvm_mmu_set_accessed_bit(table_gfn, index,
181 mark_page_dirty(vcpu->kvm, table_gfn);
182 if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
183 index, pte, pte|PT_ACCESSED_MASK))
185 pte |= PT_ACCESSED_MASK;
188 pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
190 walker->ptes[walker->level - 1] = pte;
192 if (walker->level == PT_PAGE_TABLE_LEVEL) {
193 walker->gfn = gpte_to_gfn(pte);
197 if (walker->level == PT_DIRECTORY_LEVEL
198 && (pte & PT_PAGE_SIZE_MASK)
199 && (PTTYPE == 64 || is_pse(vcpu))) {
200 walker->gfn = gpte_to_gfn_pde(pte);
201 walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
202 if (PTTYPE == 32 && is_cpuid_PSE36())
203 walker->gfn += pse36_gfn_delta(pte);
207 pt_access = pte_access;
211 if (write_fault && !is_dirty_gpte(pte)) {
214 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
215 mark_page_dirty(vcpu->kvm, table_gfn);
216 ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
220 pte |= PT_DIRTY_MASK;
221 walker->ptes[walker->level - 1] = pte;
224 walker->pt_access = pt_access;
225 walker->pte_access = pte_access;
226 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
227 __func__, (u64)pte, pt_access, pte_access);
231 walker->error_code = 0;
235 walker->error_code = PFERR_PRESENT_MASK;
239 walker->error_code |= PFERR_WRITE_MASK;
241 walker->error_code |= PFERR_USER_MASK;
243 walker->error_code |= PFERR_FETCH_MASK;
245 walker->error_code |= PFERR_RSVD_MASK;
246 trace_kvm_mmu_walker_error(walker->error_code);
250 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
251 u64 *spte, const void *pte)
256 int largepage = vcpu->arch.update_pte.largepage;
258 gpte = *(const pt_element_t *)pte;
259 if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
260 if (!is_present_gpte(gpte))
261 __set_spte(spte, shadow_notrap_nonpresent_pte);
264 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
265 pte_access = page->role.access & FNAME(gpte_access)(vcpu, gpte);
266 if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn)
268 pfn = vcpu->arch.update_pte.pfn;
269 if (is_error_pfn(pfn))
271 if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq))
274 mmu_set_spte(vcpu, spte, page->role.access, pte_access, 0, 0,
275 gpte & PT_DIRTY_MASK, NULL, largepage,
276 gpte_to_gfn(gpte), pfn, true);
280 * Fetch a shadow pte for a specific level in the paging hierarchy.
282 static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
283 struct guest_walker *gw,
284 int user_fault, int write_fault, int largepage,
285 int *ptwrite, pfn_t pfn)
287 unsigned access = gw->pt_access;
288 struct kvm_mmu_page *shadow_page;
289 u64 spte, *sptep = NULL;
294 pt_element_t curr_pte;
295 struct kvm_shadow_walk_iterator iterator;
297 if (!is_present_gpte(gw->ptes[gw->level - 1]))
300 for_each_shadow_entry(vcpu, addr, iterator) {
301 level = iterator.level;
302 sptep = iterator.sptep;
303 if (level == PT_PAGE_TABLE_LEVEL
304 || (largepage && level == PT_DIRECTORY_LEVEL)) {
305 mmu_set_spte(vcpu, sptep, access,
306 gw->pte_access & access,
307 user_fault, write_fault,
308 gw->ptes[gw->level-1] & PT_DIRTY_MASK,
310 gw->gfn, pfn, false);
314 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep))
317 if (is_large_pte(*sptep)) {
318 rmap_remove(vcpu->kvm, sptep);
319 __set_spte(sptep, shadow_trap_nonpresent_pte);
320 kvm_flush_remote_tlbs(vcpu->kvm);
323 if (level == PT_DIRECTORY_LEVEL
324 && gw->level == PT_DIRECTORY_LEVEL) {
326 if (!is_dirty_gpte(gw->ptes[level - 1]))
327 access &= ~ACC_WRITE_MASK;
328 table_gfn = gpte_to_gfn(gw->ptes[level - 1]);
331 table_gfn = gw->table_gfn[level - 2];
333 shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
334 direct, access, sptep);
336 r = kvm_read_guest_atomic(vcpu->kvm,
337 gw->pte_gpa[level - 2],
338 &curr_pte, sizeof(curr_pte));
339 if (r || curr_pte != gw->ptes[level - 2]) {
340 kvm_mmu_put_page(shadow_page, sptep);
341 kvm_release_pfn_clean(pfn);
347 spte = __pa(shadow_page->spt)
348 | PT_PRESENT_MASK | PT_ACCESSED_MASK
349 | PT_WRITABLE_MASK | PT_USER_MASK;
357 * Page fault handler. There are several causes for a page fault:
358 * - there is no shadow pte for the guest pte
359 * - write access through a shadow pte marked read only so that we can set
361 * - write access to a shadow pte marked read only so we can update the page
362 * dirty bitmap, when userspace requests it
363 * - mmio access; in this case we will never install a present shadow pte
364 * - normal guest page fault due to the guest pte marked not present, not
365 * writable, or not executable
367 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
368 * a negative value on error.
370 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
373 int write_fault = error_code & PFERR_WRITE_MASK;
374 int user_fault = error_code & PFERR_USER_MASK;
375 int fetch_fault = error_code & PFERR_FETCH_MASK;
376 struct guest_walker walker;
382 unsigned long mmu_seq;
384 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
385 kvm_mmu_audit(vcpu, "pre page fault");
387 r = mmu_topup_memory_caches(vcpu);
392 * Look up the guest pte for the faulting address.
394 r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
398 * The page is not mapped by the guest. Let the guest handle it.
401 pgprintk("%s: guest page fault\n", __func__);
402 inject_page_fault(vcpu, addr, walker.error_code);
403 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
407 if (walker.level == PT_DIRECTORY_LEVEL) {
409 large_gfn = walker.gfn &
410 ~(KVM_PAGES_PER_HPAGE(PT_DIRECTORY_LEVEL) - 1);
411 if (is_largepage_backed(vcpu, large_gfn)) {
412 walker.gfn = large_gfn;
416 mmu_seq = vcpu->kvm->mmu_notifier_seq;
418 pfn = gfn_to_pfn(vcpu->kvm, walker.gfn);
421 if (is_error_pfn(pfn)) {
422 pgprintk("gfn %lx is mmio\n", walker.gfn);
423 kvm_release_pfn_clean(pfn);
427 spin_lock(&vcpu->kvm->mmu_lock);
428 if (mmu_notifier_retry(vcpu, mmu_seq))
430 kvm_mmu_free_some_pages(vcpu);
431 sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
432 largepage, &write_pt, pfn);
434 pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
435 sptep, *sptep, write_pt);
438 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
440 ++vcpu->stat.pf_fixed;
441 kvm_mmu_audit(vcpu, "post page fault (fixed)");
442 spin_unlock(&vcpu->kvm->mmu_lock);
447 spin_unlock(&vcpu->kvm->mmu_lock);
448 kvm_release_pfn_clean(pfn);
452 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
454 struct kvm_shadow_walk_iterator iterator;
461 spin_lock(&vcpu->kvm->mmu_lock);
463 for_each_shadow_entry(vcpu, gva, iterator) {
464 level = iterator.level;
465 sptep = iterator.sptep;
467 /* FIXME: properly handle invlpg on large guest pages */
468 if (level == PT_PAGE_TABLE_LEVEL ||
469 ((level == PT_DIRECTORY_LEVEL) && is_large_pte(*sptep))) {
470 struct kvm_mmu_page *sp = page_header(__pa(sptep));
472 pte_gpa = (sp->gfn << PAGE_SHIFT);
473 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
475 if (is_shadow_present_pte(*sptep)) {
476 rmap_remove(vcpu->kvm, sptep);
477 if (is_large_pte(*sptep))
478 --vcpu->kvm->stat.lpages;
481 __set_spte(sptep, shadow_trap_nonpresent_pte);
485 if (!is_shadow_present_pte(*sptep))
490 kvm_flush_remote_tlbs(vcpu->kvm);
491 spin_unlock(&vcpu->kvm->mmu_lock);
495 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
496 sizeof(pt_element_t)))
498 if (is_present_gpte(gpte) && (gpte & PT_ACCESSED_MASK)) {
499 if (mmu_topup_memory_caches(vcpu))
501 kvm_mmu_pte_write(vcpu, pte_gpa, (const u8 *)&gpte,
502 sizeof(pt_element_t), 0);
506 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
508 struct guest_walker walker;
509 gpa_t gpa = UNMAPPED_GVA;
512 r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);
515 gpa = gfn_to_gpa(walker.gfn);
516 gpa |= vaddr & ~PAGE_MASK;
522 static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
523 struct kvm_mmu_page *sp)
526 pt_element_t pt[256 / sizeof(pt_element_t)];
530 || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
531 nonpaging_prefetch_page(vcpu, sp);
535 pte_gpa = gfn_to_gpa(sp->gfn);
537 offset = sp->role.quadrant << PT64_LEVEL_BITS;
538 pte_gpa += offset * sizeof(pt_element_t);
541 for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) {
542 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt);
543 pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t);
544 for (j = 0; j < ARRAY_SIZE(pt); ++j)
545 if (r || is_present_gpte(pt[j]))
546 sp->spt[i+j] = shadow_trap_nonpresent_pte;
548 sp->spt[i+j] = shadow_notrap_nonpresent_pte;
553 * Using the cached information from sp->gfns is safe because:
554 * - The spte has a reference to the struct page, so the pfn for a given gfn
555 * can't change unless all sptes pointing to it are nuked first.
556 * - Alias changes zap the entire shadow cache.
558 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
560 int i, offset, nr_present;
562 offset = nr_present = 0;
565 offset = sp->role.quadrant << PT64_LEVEL_BITS;
567 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
571 gfn_t gfn = sp->gfns[i];
573 if (!is_shadow_present_pte(sp->spt[i]))
576 pte_gpa = gfn_to_gpa(sp->gfn);
577 pte_gpa += (i+offset) * sizeof(pt_element_t);
579 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
580 sizeof(pt_element_t)))
583 if (gpte_to_gfn(gpte) != gfn || !is_present_gpte(gpte) ||
584 !(gpte & PT_ACCESSED_MASK)) {
587 rmap_remove(vcpu->kvm, &sp->spt[i]);
588 if (is_present_gpte(gpte))
589 nonpresent = shadow_trap_nonpresent_pte;
591 nonpresent = shadow_notrap_nonpresent_pte;
592 __set_spte(&sp->spt[i], nonpresent);
597 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
598 set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
599 is_dirty_gpte(gpte), 0, gfn,
600 spte_to_pfn(sp->spt[i]), true, false);
609 #undef PT_BASE_ADDR_MASK
612 #undef PT_DIR_BASE_ADDR_MASK
614 #undef PT_MAX_FULL_LEVELS
616 #undef gpte_to_gfn_pde