3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
10 * Dor Laor <dor.laor@qumranet.com>
11 * Gregory Haskins <ghaskins@novell.com>
12 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
20 #include <linux/kvm_host.h>
21 #include <linux/kvm.h>
23 #include <linux/highmem.h>
24 #include <linux/smp.h>
25 #include <linux/hrtimer.h>
27 #include <linux/module.h>
28 #include <linux/math64.h>
29 #include <asm/processor.h>
32 #include <asm/current.h>
33 #include <asm/apicdef.h>
34 #include <asm/atomic.h>
35 #include "kvm_cache_regs.h"
39 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
41 #define mod_64(x, y) ((x) % (y))
49 #define APIC_BUS_CYCLE_NS 1
51 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
52 #define apic_debug(fmt, arg...)
54 #define APIC_LVT_NUM 6
55 /* 14 is the version for Xeon and Pentium 8.4.8*/
56 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
57 #define LAPIC_MMIO_LENGTH (1 << 12)
58 /* followed define is not in apicdef.h */
59 #define APIC_SHORT_MASK 0xc0000
60 #define APIC_DEST_NOSHORT 0x0
61 #define APIC_DEST_MASK 0x800
62 #define MAX_APIC_VECTOR 256
64 #define VEC_POS(v) ((v) & (32 - 1))
65 #define REG_POS(v) (((v) >> 5) << 4)
67 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
69 return *((u32 *) (apic->regs + reg_off));
72 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
74 *((u32 *) (apic->regs + reg_off)) = val;
77 static inline int apic_test_and_set_vector(int vec, void *bitmap)
79 return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
82 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
84 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
87 static inline void apic_set_vector(int vec, void *bitmap)
89 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
92 static inline void apic_clear_vector(int vec, void *bitmap)
94 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
97 static inline int apic_hw_enabled(struct kvm_lapic *apic)
99 return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
102 static inline int apic_sw_enabled(struct kvm_lapic *apic)
104 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
107 static inline int apic_enabled(struct kvm_lapic *apic)
109 return apic_sw_enabled(apic) && apic_hw_enabled(apic);
113 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
116 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
117 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
119 static inline int kvm_apic_id(struct kvm_lapic *apic)
121 return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
124 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
126 return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
129 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
131 return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
134 static inline int apic_lvtt_period(struct kvm_lapic *apic)
136 return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
139 static inline int apic_lvt_nmi_mode(u32 lvt_val)
141 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
144 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
145 LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */
146 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
147 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
148 LINT_MASK, LINT_MASK, /* LVT0-1 */
149 LVT_MASK /* LVTERR */
152 static int find_highest_vector(void *bitmap)
155 int word_offset = MAX_APIC_VECTOR >> 5;
157 while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
160 if (likely(!word_offset && !word[0]))
163 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
166 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
168 return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
171 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
173 apic_clear_vector(vec, apic->regs + APIC_IRR);
176 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
180 result = find_highest_vector(apic->regs + APIC_IRR);
181 ASSERT(result == -1 || result >= 16);
186 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
188 struct kvm_lapic *apic = vcpu->arch.apic;
193 highest_irr = apic_find_highest_irr(apic);
197 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
199 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
200 int vector, int level, int trig_mode);
202 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, u8 vec, u8 dmode, u8 trig)
204 struct kvm_lapic *apic = vcpu->arch.apic;
208 case IOAPIC_LOWEST_PRIORITY:
209 lapic_dmode = APIC_DM_LOWEST;
212 lapic_dmode = APIC_DM_FIXED;
215 lapic_dmode = APIC_DM_NMI;
218 printk(KERN_DEBUG"Ignoring delivery mode %d\n", dmode);
222 return __apic_accept_irq(apic, lapic_dmode, vec, 1, trig);
225 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
229 result = find_highest_vector(apic->regs + APIC_ISR);
230 ASSERT(result == -1 || result >= 16);
235 static void apic_update_ppr(struct kvm_lapic *apic)
240 tpr = apic_get_reg(apic, APIC_TASKPRI);
241 isr = apic_find_highest_isr(apic);
242 isrv = (isr != -1) ? isr : 0;
244 if ((tpr & 0xf0) >= (isrv & 0xf0))
249 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
250 apic, ppr, isr, isrv);
252 apic_set_reg(apic, APIC_PROCPRI, ppr);
255 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
257 apic_set_reg(apic, APIC_TASKPRI, tpr);
258 apic_update_ppr(apic);
261 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
263 return dest == 0xff || kvm_apic_id(apic) == dest;
266 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
271 logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
273 switch (apic_get_reg(apic, APIC_DFR)) {
275 if (logical_id & mda)
278 case APIC_DFR_CLUSTER:
279 if (((logical_id >> 4) == (mda >> 0x4))
280 && (logical_id & mda & 0xf))
284 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
285 apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
292 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
293 int short_hand, int dest, int dest_mode)
296 struct kvm_lapic *target = vcpu->arch.apic;
298 apic_debug("target %p, source %p, dest 0x%x, "
299 "dest_mode 0x%x, short_hand 0x%x\n",
300 target, source, dest, dest_mode, short_hand);
303 switch (short_hand) {
304 case APIC_DEST_NOSHORT:
307 result = kvm_apic_match_physical_addr(target, dest);
310 result = kvm_apic_match_logical_addr(target, dest);
313 result = (target == source);
315 case APIC_DEST_ALLINC:
318 case APIC_DEST_ALLBUT:
319 result = (target != source);
322 printk(KERN_WARNING "Bad dest shorthand value %x\n",
331 * Add a pending IRQ into lapic.
332 * Return 1 if successfully added and 0 if discarded.
334 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
335 int vector, int level, int trig_mode)
338 struct kvm_vcpu *vcpu = apic->vcpu;
340 switch (delivery_mode) {
342 vcpu->arch.apic_arb_prio++;
344 /* FIXME add logic for vcpu on reset */
345 if (unlikely(!apic_enabled(apic)))
348 result = !apic_test_and_set_irr(vector, apic);
351 apic_debug("level trig mode repeatedly for "
352 "vector %d", vector);
357 apic_debug("level trig mode for vector %d", vector);
358 apic_set_vector(vector, apic->regs + APIC_TMR);
360 apic_clear_vector(vector, apic->regs + APIC_TMR);
365 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
369 printk(KERN_DEBUG "Ignoring guest SMI\n");
374 kvm_inject_nmi(vcpu);
381 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
383 "INIT on a runnable vcpu %d\n",
385 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
388 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
393 case APIC_DM_STARTUP:
394 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
395 vcpu->vcpu_id, vector);
396 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
398 vcpu->arch.sipi_vector = vector;
399 vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
406 * Should only be called by kvm_apic_local_deliver() with LVT0,
407 * before NMI watchdog was enabled. Already handled by
408 * kvm_apic_accept_pic_intr().
413 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
420 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
422 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
425 static void apic_set_eoi(struct kvm_lapic *apic)
427 int vector = apic_find_highest_isr(apic);
430 * Not every write EOI will has corresponding ISR,
431 * one example is when Kernel check timer on setup_IO_APIC
436 apic_clear_vector(vector, apic->regs + APIC_ISR);
437 apic_update_ppr(apic);
439 if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
440 trigger_mode = IOAPIC_LEVEL_TRIG;
442 trigger_mode = IOAPIC_EDGE_TRIG;
443 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
446 static void apic_send_ipi(struct kvm_lapic *apic)
448 u32 icr_low = apic_get_reg(apic, APIC_ICR);
449 u32 icr_high = apic_get_reg(apic, APIC_ICR2);
451 unsigned int dest = GET_APIC_DEST_FIELD(icr_high);
452 unsigned int short_hand = icr_low & APIC_SHORT_MASK;
453 unsigned int trig_mode = icr_low & APIC_INT_LEVELTRIG;
454 unsigned int level = icr_low & APIC_INT_ASSERT;
455 unsigned int dest_mode = icr_low & APIC_DEST_MASK;
456 unsigned int delivery_mode = icr_low & APIC_MODE_MASK;
457 unsigned int vector = icr_low & APIC_VECTOR_MASK;
459 DECLARE_BITMAP(deliver_bitmask, KVM_MAX_VCPUS);
462 apic_debug("icr_high 0x%x, icr_low 0x%x, "
463 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
464 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
465 icr_high, icr_low, short_hand, dest,
466 trig_mode, level, dest_mode, delivery_mode, vector);
468 kvm_get_intr_delivery_bitmask(apic->vcpu->kvm, apic, dest, dest_mode,
469 delivery_mode == APIC_DM_LOWEST, short_hand,
472 while ((i = find_first_bit(deliver_bitmask, KVM_MAX_VCPUS))
474 struct kvm_vcpu *vcpu = apic->vcpu->kvm->vcpus[i];
475 __clear_bit(i, deliver_bitmask);
477 __apic_accept_irq(vcpu->arch.apic, delivery_mode,
478 vector, level, trig_mode);
482 static u32 apic_get_tmcct(struct kvm_lapic *apic)
488 ASSERT(apic != NULL);
490 /* if initial count is 0, current count should also be 0 */
491 if (apic_get_reg(apic, APIC_TMICT) == 0)
494 remaining = hrtimer_expires_remaining(&apic->lapic_timer.timer);
495 if (ktime_to_ns(remaining) < 0)
496 remaining = ktime_set(0, 0);
498 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
499 tmcct = div64_u64(ns,
500 (APIC_BUS_CYCLE_NS * apic->divide_count));
505 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
507 struct kvm_vcpu *vcpu = apic->vcpu;
508 struct kvm_run *run = vcpu->run;
510 set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests);
511 run->tpr_access.rip = kvm_rip_read(vcpu);
512 run->tpr_access.is_write = write;
515 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
517 if (apic->vcpu->arch.tpr_access_reporting)
518 __report_tpr_access(apic, write);
521 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
525 KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
527 if (offset >= LAPIC_MMIO_LENGTH)
532 printk(KERN_WARNING "Access APIC ARBPRI register "
533 "which is for P6\n");
536 case APIC_TMCCT: /* Timer CCR */
537 val = apic_get_tmcct(apic);
541 report_tpr_access(apic, false);
544 apic_update_ppr(apic);
545 val = apic_get_reg(apic, offset);
552 static void apic_mmio_read(struct kvm_io_device *this,
553 gpa_t address, int len, void *data)
555 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
556 unsigned int offset = address - apic->base_address;
557 unsigned char alignment = offset & 0xf;
560 if ((alignment + len) > 4) {
561 printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
562 (unsigned long)address, len);
565 result = __apic_read(apic, offset & ~0xf);
571 memcpy(data, (char *)&result + alignment, len);
574 printk(KERN_ERR "Local APIC read with len = %x, "
575 "should be 1,2, or 4 instead\n", len);
580 static void update_divide_count(struct kvm_lapic *apic)
582 u32 tmp1, tmp2, tdcr;
584 tdcr = apic_get_reg(apic, APIC_TDCR);
586 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
587 apic->divide_count = 0x1 << (tmp2 & 0x7);
589 apic_debug("timer divide count is 0x%x\n",
590 apic->lapic_timer.divide_count);
593 static void start_apic_timer(struct kvm_lapic *apic)
595 ktime_t now = apic->lapic_timer.timer.base->get_time();
597 apic->lapic_timer.period = apic_get_reg(apic, APIC_TMICT) *
598 APIC_BUS_CYCLE_NS * apic->divide_count;
599 atomic_set(&apic->lapic_timer.pending, 0);
601 if (!apic->lapic_timer.period)
604 hrtimer_start(&apic->lapic_timer.timer,
605 ktime_add_ns(now, apic->lapic_timer.period),
608 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
610 "timer initial count 0x%x, period %lldns, "
611 "expire @ 0x%016" PRIx64 ".\n", __func__,
612 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
613 apic_get_reg(apic, APIC_TMICT),
614 apic->lapic_timer.period,
615 ktime_to_ns(ktime_add_ns(now,
616 apic->lapic_timer.period)));
619 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
621 int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
623 if (apic_lvt_nmi_mode(lvt0_val)) {
624 if (!nmi_wd_enabled) {
625 apic_debug("Receive NMI setting on APIC_LVT0 "
626 "for cpu %d\n", apic->vcpu->vcpu_id);
627 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
629 } else if (nmi_wd_enabled)
630 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
633 static void apic_mmio_write(struct kvm_io_device *this,
634 gpa_t address, int len, const void *data)
636 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
637 unsigned int offset = address - apic->base_address;
638 unsigned char alignment = offset & 0xf;
642 * APIC register must be aligned on 128-bits boundary.
643 * 32/64/128 bits registers must be accessed thru 32 bits.
646 if (len != 4 || alignment) {
647 /* Don't shout loud, $infamous_os would cause only noise. */
648 apic_debug("apic write: bad size=%d %lx\n",
655 /* too common printing */
656 if (offset != APIC_EOI)
657 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
658 "0x%x\n", __func__, offset, len, val);
662 KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
665 case APIC_ID: /* Local APIC ID */
666 apic_set_reg(apic, APIC_ID, val);
670 report_tpr_access(apic, true);
671 apic_set_tpr(apic, val & 0xff);
679 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
683 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
687 apic_set_reg(apic, APIC_SPIV, val & 0x3ff);
688 if (!(val & APIC_SPIV_APIC_ENABLED)) {
692 for (i = 0; i < APIC_LVT_NUM; i++) {
693 lvt_val = apic_get_reg(apic,
694 APIC_LVTT + 0x10 * i);
695 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
696 lvt_val | APIC_LVT_MASKED);
698 atomic_set(&apic->lapic_timer.pending, 0);
704 /* No delay here, so we always clear the pending bit */
705 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
710 apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
714 apic_manage_nmi_watchdog(apic, val);
720 /* TODO: Check vector */
721 if (!apic_sw_enabled(apic))
722 val |= APIC_LVT_MASKED;
724 val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
725 apic_set_reg(apic, offset, val);
730 hrtimer_cancel(&apic->lapic_timer.timer);
731 apic_set_reg(apic, APIC_TMICT, val);
732 start_apic_timer(apic);
737 printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
738 apic_set_reg(apic, APIC_TDCR, val);
739 update_divide_count(apic);
743 apic_debug("Local APIC Write to read-only register %x\n",
750 static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr,
753 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
757 if (apic_hw_enabled(apic) &&
758 (addr >= apic->base_address) &&
759 (addr < (apic->base_address + LAPIC_MMIO_LENGTH)))
765 void kvm_free_lapic(struct kvm_vcpu *vcpu)
767 if (!vcpu->arch.apic)
770 hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
772 if (vcpu->arch.apic->regs_page)
773 __free_page(vcpu->arch.apic->regs_page);
775 kfree(vcpu->arch.apic);
779 *----------------------------------------------------------------------
781 *----------------------------------------------------------------------
784 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
786 struct kvm_lapic *apic = vcpu->arch.apic;
790 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
791 | (apic_get_reg(apic, APIC_TASKPRI) & 4));
793 EXPORT_SYMBOL_GPL(kvm_lapic_set_tpr);
795 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
797 struct kvm_lapic *apic = vcpu->arch.apic;
802 tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
804 return (tpr & 0xf0) >> 4;
806 EXPORT_SYMBOL_GPL(kvm_lapic_get_cr8);
808 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
810 struct kvm_lapic *apic = vcpu->arch.apic;
813 value |= MSR_IA32_APICBASE_BSP;
814 vcpu->arch.apic_base = value;
817 if (apic->vcpu->vcpu_id)
818 value &= ~MSR_IA32_APICBASE_BSP;
820 vcpu->arch.apic_base = value;
821 apic->base_address = apic->vcpu->arch.apic_base &
822 MSR_IA32_APICBASE_BASE;
824 /* with FSB delivery interrupt, we can restart APIC functionality */
825 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
826 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
830 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu)
832 return vcpu->arch.apic_base;
834 EXPORT_SYMBOL_GPL(kvm_lapic_get_base);
836 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
838 struct kvm_lapic *apic;
841 apic_debug("%s\n", __func__);
844 apic = vcpu->arch.apic;
845 ASSERT(apic != NULL);
847 /* Stop the timer in case it's a reset to an active apic */
848 hrtimer_cancel(&apic->lapic_timer.timer);
850 apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
851 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
853 for (i = 0; i < APIC_LVT_NUM; i++)
854 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
855 apic_set_reg(apic, APIC_LVT0,
856 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
858 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
859 apic_set_reg(apic, APIC_SPIV, 0xff);
860 apic_set_reg(apic, APIC_TASKPRI, 0);
861 apic_set_reg(apic, APIC_LDR, 0);
862 apic_set_reg(apic, APIC_ESR, 0);
863 apic_set_reg(apic, APIC_ICR, 0);
864 apic_set_reg(apic, APIC_ICR2, 0);
865 apic_set_reg(apic, APIC_TDCR, 0);
866 apic_set_reg(apic, APIC_TMICT, 0);
867 for (i = 0; i < 8; i++) {
868 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
869 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
870 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
872 update_divide_count(apic);
873 atomic_set(&apic->lapic_timer.pending, 0);
874 if (vcpu->vcpu_id == 0)
875 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
876 apic_update_ppr(apic);
878 vcpu->arch.apic_arb_prio = 0;
880 apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
881 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
882 vcpu, kvm_apic_id(apic),
883 vcpu->arch.apic_base, apic->base_address);
885 EXPORT_SYMBOL_GPL(kvm_lapic_reset);
887 bool kvm_apic_present(struct kvm_vcpu *vcpu)
889 return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic);
892 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
894 return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
896 EXPORT_SYMBOL_GPL(kvm_lapic_enabled);
899 *----------------------------------------------------------------------
901 *----------------------------------------------------------------------
904 static bool lapic_is_periodic(struct kvm_timer *ktimer)
906 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic,
908 return apic_lvtt_period(apic);
911 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
913 struct kvm_lapic *lapic = vcpu->arch.apic;
915 if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
916 return atomic_read(&lapic->lapic_timer.pending);
921 static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
923 u32 reg = apic_get_reg(apic, lvt_type);
924 int vector, mode, trig_mode;
926 if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
927 vector = reg & APIC_VECTOR_MASK;
928 mode = reg & APIC_MODE_MASK;
929 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
930 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
935 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
937 struct kvm_lapic *apic = vcpu->arch.apic;
940 kvm_apic_local_deliver(apic, APIC_LVT0);
943 struct kvm_timer_ops lapic_timer_ops = {
944 .is_periodic = lapic_is_periodic,
947 int kvm_create_lapic(struct kvm_vcpu *vcpu)
949 struct kvm_lapic *apic;
951 ASSERT(vcpu != NULL);
952 apic_debug("apic_init %d\n", vcpu->vcpu_id);
954 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
958 vcpu->arch.apic = apic;
960 apic->regs_page = alloc_page(GFP_KERNEL);
961 if (apic->regs_page == NULL) {
962 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
964 goto nomem_free_apic;
966 apic->regs = page_address(apic->regs_page);
967 memset(apic->regs, 0, PAGE_SIZE);
970 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
972 apic->lapic_timer.timer.function = kvm_timer_fn;
973 apic->lapic_timer.t_ops = &lapic_timer_ops;
974 apic->lapic_timer.kvm = vcpu->kvm;
975 apic->lapic_timer.vcpu_id = vcpu->vcpu_id;
977 apic->base_address = APIC_DEFAULT_PHYS_BASE;
978 vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
980 kvm_lapic_reset(vcpu);
981 apic->dev.read = apic_mmio_read;
982 apic->dev.write = apic_mmio_write;
983 apic->dev.in_range = apic_mmio_range;
984 apic->dev.private = apic;
992 EXPORT_SYMBOL_GPL(kvm_create_lapic);
994 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
996 struct kvm_lapic *apic = vcpu->arch.apic;
999 if (!apic || !apic_enabled(apic))
1002 apic_update_ppr(apic);
1003 highest_irr = apic_find_highest_irr(apic);
1004 if ((highest_irr == -1) ||
1005 ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1010 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1012 u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1015 if (vcpu->vcpu_id == 0) {
1016 if (!apic_hw_enabled(vcpu->arch.apic))
1018 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1019 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1025 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1027 struct kvm_lapic *apic = vcpu->arch.apic;
1029 if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
1030 if (kvm_apic_local_deliver(apic, APIC_LVTT))
1031 atomic_dec(&apic->lapic_timer.pending);
1035 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1037 int vector = kvm_apic_has_interrupt(vcpu);
1038 struct kvm_lapic *apic = vcpu->arch.apic;
1043 apic_set_vector(vector, apic->regs + APIC_ISR);
1044 apic_update_ppr(apic);
1045 apic_clear_irr(vector, apic);
1049 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1051 struct kvm_lapic *apic = vcpu->arch.apic;
1053 apic->base_address = vcpu->arch.apic_base &
1054 MSR_IA32_APICBASE_BASE;
1055 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
1056 apic_update_ppr(apic);
1057 hrtimer_cancel(&apic->lapic_timer.timer);
1058 update_divide_count(apic);
1059 start_apic_timer(apic);
1062 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1064 struct kvm_lapic *apic = vcpu->arch.apic;
1065 struct hrtimer *timer;
1070 timer = &apic->lapic_timer.timer;
1071 if (hrtimer_cancel(timer))
1072 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1075 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1080 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1083 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1084 data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1085 kunmap_atomic(vapic, KM_USER0);
1087 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1090 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1093 int max_irr, max_isr;
1094 struct kvm_lapic *apic;
1097 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1100 apic = vcpu->arch.apic;
1101 tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1102 max_irr = apic_find_highest_irr(apic);
1105 max_isr = apic_find_highest_isr(apic);
1108 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1110 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1111 *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1112 kunmap_atomic(vapic, KM_USER0);
1115 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1117 if (!irqchip_in_kernel(vcpu->kvm))
1120 vcpu->arch.apic->vapic_addr = vapic_addr;